2 * PCIe host controller driver for NWL PCIe Bridge
3 * Based on pcie-xilinx.c, pci-tegra.c
5 * (C) Copyright 2014 - 2015, Xilinx, Inc.
7 * This program is free software: you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation, either version 2 of the License, or
10 * (at your option) any later version.
13 #include <linux/delay.h>
14 #include <linux/interrupt.h>
15 #include <linux/irq.h>
16 #include <linux/irqdomain.h>
17 #include <linux/kernel.h>
18 #include <linux/init.h>
19 #include <linux/msi.h>
20 #include <linux/of_address.h>
21 #include <linux/of_pci.h>
22 #include <linux/of_platform.h>
23 #include <linux/of_irq.h>
24 #include <linux/pci.h>
25 #include <linux/platform_device.h>
26 #include <linux/irqchip/chained_irq.h>
28 /* Bridge core config registers */
29 #define BRCFG_PCIE_RX0 0x00000000
30 #define BRCFG_INTERRUPT 0x00000010
31 #define BRCFG_PCIE_RX_MSG_FILTER 0x00000020
33 /* Egress - Bridge translation registers */
34 #define E_BREG_CAPABILITIES 0x00000200
35 #define E_BREG_CONTROL 0x00000208
36 #define E_BREG_BASE_LO 0x00000210
37 #define E_BREG_BASE_HI 0x00000214
38 #define E_ECAM_CAPABILITIES 0x00000220
39 #define E_ECAM_CONTROL 0x00000228
40 #define E_ECAM_BASE_LO 0x00000230
41 #define E_ECAM_BASE_HI 0x00000234
43 /* Ingress - address translations */
44 #define I_MSII_CAPABILITIES 0x00000300
45 #define I_MSII_CONTROL 0x00000308
46 #define I_MSII_BASE_LO 0x00000310
47 #define I_MSII_BASE_HI 0x00000314
49 #define I_ISUB_CONTROL 0x000003E8
50 #define SET_ISUB_CONTROL BIT(0)
51 /* Rxed msg fifo - Interrupt status registers */
52 #define MSGF_MISC_STATUS 0x00000400
53 #define MSGF_MISC_MASK 0x00000404
54 #define MSGF_LEG_STATUS 0x00000420
55 #define MSGF_LEG_MASK 0x00000424
56 #define MSGF_MSI_STATUS_LO 0x00000440
57 #define MSGF_MSI_STATUS_HI 0x00000444
58 #define MSGF_MSI_MASK_LO 0x00000448
59 #define MSGF_MSI_MASK_HI 0x0000044C
61 /* Msg filter mask bits */
62 #define CFG_ENABLE_PM_MSG_FWD BIT(1)
63 #define CFG_ENABLE_INT_MSG_FWD BIT(2)
64 #define CFG_ENABLE_ERR_MSG_FWD BIT(3)
65 #define CFG_ENABLE_MSG_FILTER_MASK (CFG_ENABLE_PM_MSG_FWD | \
66 CFG_ENABLE_INT_MSG_FWD | \
67 CFG_ENABLE_ERR_MSG_FWD)
69 /* Misc interrupt status mask bits */
70 #define MSGF_MISC_SR_RXMSG_AVAIL BIT(0)
71 #define MSGF_MISC_SR_RXMSG_OVER BIT(1)
72 #define MSGF_MISC_SR_SLAVE_ERR BIT(4)
73 #define MSGF_MISC_SR_MASTER_ERR BIT(5)
74 #define MSGF_MISC_SR_I_ADDR_ERR BIT(6)
75 #define MSGF_MISC_SR_E_ADDR_ERR BIT(7)
76 #define MSGF_MISC_SR_FATAL_AER BIT(16)
77 #define MSGF_MISC_SR_NON_FATAL_AER BIT(17)
78 #define MSGF_MISC_SR_CORR_AER BIT(18)
79 #define MSGF_MISC_SR_UR_DETECT BIT(20)
80 #define MSGF_MISC_SR_NON_FATAL_DEV BIT(22)
81 #define MSGF_MISC_SR_FATAL_DEV BIT(23)
82 #define MSGF_MISC_SR_LINK_DOWN BIT(24)
83 #define MSGF_MSIC_SR_LINK_AUTO_BWIDTH BIT(25)
84 #define MSGF_MSIC_SR_LINK_BWIDTH BIT(26)
86 #define MSGF_MISC_SR_MASKALL (MSGF_MISC_SR_RXMSG_AVAIL | \
87 MSGF_MISC_SR_RXMSG_OVER | \
88 MSGF_MISC_SR_SLAVE_ERR | \
89 MSGF_MISC_SR_MASTER_ERR | \
90 MSGF_MISC_SR_I_ADDR_ERR | \
91 MSGF_MISC_SR_E_ADDR_ERR | \
92 MSGF_MISC_SR_FATAL_AER | \
93 MSGF_MISC_SR_NON_FATAL_AER | \
94 MSGF_MISC_SR_CORR_AER | \
95 MSGF_MISC_SR_UR_DETECT | \
96 MSGF_MISC_SR_NON_FATAL_DEV | \
97 MSGF_MISC_SR_FATAL_DEV | \
98 MSGF_MISC_SR_LINK_DOWN | \
99 MSGF_MSIC_SR_LINK_AUTO_BWIDTH | \
100 MSGF_MSIC_SR_LINK_BWIDTH)
102 /* Legacy interrupt status mask bits */
103 #define MSGF_LEG_SR_INTA BIT(0)
104 #define MSGF_LEG_SR_INTB BIT(1)
105 #define MSGF_LEG_SR_INTC BIT(2)
106 #define MSGF_LEG_SR_INTD BIT(3)
107 #define MSGF_LEG_SR_MASKALL (MSGF_LEG_SR_INTA | MSGF_LEG_SR_INTB | \
108 MSGF_LEG_SR_INTC | MSGF_LEG_SR_INTD)
110 /* MSI interrupt status mask bits */
111 #define MSGF_MSI_SR_LO_MASK GENMASK(31, 0)
112 #define MSGF_MSI_SR_HI_MASK GENMASK(31, 0)
114 #define MSII_PRESENT BIT(0)
115 #define MSII_ENABLE BIT(0)
116 #define MSII_STATUS_ENABLE BIT(15)
118 /* Bridge config interrupt mask */
119 #define BRCFG_INTERRUPT_MASK BIT(0)
120 #define BREG_PRESENT BIT(0)
121 #define BREG_ENABLE BIT(0)
122 #define BREG_ENABLE_FORCE BIT(1)
124 /* E_ECAM status mask bits */
125 #define E_ECAM_PRESENT BIT(0)
126 #define E_ECAM_CR_ENABLE BIT(0)
127 #define E_ECAM_SIZE_LOC GENMASK(20, 16)
128 #define E_ECAM_SIZE_SHIFT 16
129 #define ECAM_BUS_LOC_SHIFT 20
130 #define ECAM_DEV_LOC_SHIFT 12
131 #define NWL_ECAM_VALUE_DEFAULT 12
133 #define CFG_DMA_REG_BAR GENMASK(2, 0)
135 #define INT_PCI_MSI_NR (2 * 32)
138 /* Readin the PS_LINKUP */
139 #define PS_LINKUP_OFFSET 0x00000238
140 #define PCIE_PHY_LINKUP_BIT BIT(0)
141 #define PHY_RDY_LINKUP_BIT BIT(1)
143 /* Parameters for the waiting for link up routine */
144 #define LINK_WAIT_MAX_RETRIES 10
145 #define LINK_WAIT_USLEEP_MIN 90000
146 #define LINK_WAIT_USLEEP_MAX 100000
148 struct nwl_msi { /* MSI information */
149 struct irq_domain *msi_domain;
150 unsigned long *bitmap;
151 struct irq_domain *dev_domain;
152 struct mutex lock; /* protect bitmap variable */
159 void __iomem *breg_base;
160 void __iomem *pcireg_base;
161 void __iomem *ecam_base;
162 phys_addr_t phys_breg_base; /* Physical Bridge Register Base */
163 phys_addr_t phys_pcie_reg_base; /* Physical PCIe Controller Base */
164 phys_addr_t phys_ecam_base; /* Physical Configuration Base */
174 struct irq_domain *legacy_irq_domain;
177 static inline u32 nwl_bridge_readl(struct nwl_pcie *pcie, u32 off)
179 return readl(pcie->breg_base + off);
182 static inline void nwl_bridge_writel(struct nwl_pcie *pcie, u32 val, u32 off)
184 writel(val, pcie->breg_base + off);
187 static bool nwl_pcie_link_up(struct nwl_pcie *pcie)
189 if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PCIE_PHY_LINKUP_BIT)
194 static bool nwl_phy_link_up(struct nwl_pcie *pcie)
196 if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PHY_RDY_LINKUP_BIT)
201 static int nwl_wait_for_link(struct nwl_pcie *pcie)
203 struct device *dev = pcie->dev;
206 /* check if the link is up or not */
207 for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
208 if (nwl_phy_link_up(pcie))
210 usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX);
213 dev_err(dev, "PHY link never came up\n");
217 static bool nwl_pcie_valid_device(struct pci_bus *bus, unsigned int devfn)
219 struct nwl_pcie *pcie = bus->sysdata;
221 /* Check link before accessing downstream ports */
222 if (bus->number != pcie->root_busno) {
223 if (!nwl_pcie_link_up(pcie))
227 /* Only one device down on each root port */
228 if (bus->number == pcie->root_busno && devfn > 0)
235 * nwl_pcie_map_bus - Get configuration base
237 * @bus: Bus structure of current bus
238 * @devfn: Device/function
239 * @where: Offset from base
241 * Return: Base address of the configuration space needed to be
244 static void __iomem *nwl_pcie_map_bus(struct pci_bus *bus, unsigned int devfn,
247 struct nwl_pcie *pcie = bus->sysdata;
250 if (!nwl_pcie_valid_device(bus, devfn))
253 relbus = (bus->number << ECAM_BUS_LOC_SHIFT) |
254 (devfn << ECAM_DEV_LOC_SHIFT);
256 return pcie->ecam_base + relbus + where;
259 /* PCIe operations */
260 static struct pci_ops nwl_pcie_ops = {
261 .map_bus = nwl_pcie_map_bus,
262 .read = pci_generic_config_read,
263 .write = pci_generic_config_write,
266 static irqreturn_t nwl_pcie_misc_handler(int irq, void *data)
268 struct nwl_pcie *pcie = data;
269 struct device *dev = pcie->dev;
272 /* Checking for misc interrupts */
273 misc_stat = nwl_bridge_readl(pcie, MSGF_MISC_STATUS) &
274 MSGF_MISC_SR_MASKALL;
278 if (misc_stat & MSGF_MISC_SR_RXMSG_OVER)
279 dev_err(dev, "Received Message FIFO Overflow\n");
281 if (misc_stat & MSGF_MISC_SR_SLAVE_ERR)
282 dev_err(dev, "Slave error\n");
284 if (misc_stat & MSGF_MISC_SR_MASTER_ERR)
285 dev_err(dev, "Master error\n");
287 if (misc_stat & MSGF_MISC_SR_I_ADDR_ERR)
288 dev_err(dev, "In Misc Ingress address translation error\n");
290 if (misc_stat & MSGF_MISC_SR_E_ADDR_ERR)
291 dev_err(dev, "In Misc Egress address translation error\n");
293 if (misc_stat & MSGF_MISC_SR_FATAL_AER)
294 dev_err(dev, "Fatal Error in AER Capability\n");
296 if (misc_stat & MSGF_MISC_SR_NON_FATAL_AER)
297 dev_err(dev, "Non-Fatal Error in AER Capability\n");
299 if (misc_stat & MSGF_MISC_SR_CORR_AER)
300 dev_err(dev, "Correctable Error in AER Capability\n");
302 if (misc_stat & MSGF_MISC_SR_UR_DETECT)
303 dev_err(dev, "Unsupported request Detected\n");
305 if (misc_stat & MSGF_MISC_SR_NON_FATAL_DEV)
306 dev_err(dev, "Non-Fatal Error Detected\n");
308 if (misc_stat & MSGF_MISC_SR_FATAL_DEV)
309 dev_err(dev, "Fatal Error Detected\n");
311 if (misc_stat & MSGF_MSIC_SR_LINK_AUTO_BWIDTH)
312 dev_info(dev, "Link Autonomous Bandwidth Management Status bit set\n");
314 if (misc_stat & MSGF_MSIC_SR_LINK_BWIDTH)
315 dev_info(dev, "Link Bandwidth Management Status bit set\n");
317 /* Clear misc interrupt status */
318 nwl_bridge_writel(pcie, misc_stat, MSGF_MISC_STATUS);
323 static void nwl_pcie_leg_handler(struct irq_desc *desc)
325 struct irq_chip *chip = irq_desc_get_chip(desc);
326 struct nwl_pcie *pcie;
327 unsigned long status;
331 chained_irq_enter(chip, desc);
332 pcie = irq_desc_get_handler_data(desc);
334 while ((status = nwl_bridge_readl(pcie, MSGF_LEG_STATUS) &
335 MSGF_LEG_SR_MASKALL) != 0) {
336 for_each_set_bit(bit, &status, INTX_NUM) {
337 virq = irq_find_mapping(pcie->legacy_irq_domain,
340 generic_handle_irq(virq);
344 chained_irq_exit(chip, desc);
347 static void nwl_pcie_handle_msi_irq(struct nwl_pcie *pcie, u32 status_reg)
350 unsigned long status;
356 while ((status = nwl_bridge_readl(pcie, status_reg)) != 0) {
357 for_each_set_bit(bit, &status, 32) {
358 nwl_bridge_writel(pcie, 1 << bit, status_reg);
359 virq = irq_find_mapping(msi->dev_domain, bit);
361 generic_handle_irq(virq);
366 static void nwl_pcie_msi_handler_high(struct irq_desc *desc)
368 struct irq_chip *chip = irq_desc_get_chip(desc);
369 struct nwl_pcie *pcie = irq_desc_get_handler_data(desc);
371 chained_irq_enter(chip, desc);
372 nwl_pcie_handle_msi_irq(pcie, MSGF_MSI_STATUS_HI);
373 chained_irq_exit(chip, desc);
376 static void nwl_pcie_msi_handler_low(struct irq_desc *desc)
378 struct irq_chip *chip = irq_desc_get_chip(desc);
379 struct nwl_pcie *pcie = irq_desc_get_handler_data(desc);
381 chained_irq_enter(chip, desc);
382 nwl_pcie_handle_msi_irq(pcie, MSGF_MSI_STATUS_LO);
383 chained_irq_exit(chip, desc);
386 static int nwl_legacy_map(struct irq_domain *domain, unsigned int irq,
387 irq_hw_number_t hwirq)
389 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
390 irq_set_chip_data(irq, domain->host_data);
395 static const struct irq_domain_ops legacy_domain_ops = {
396 .map = nwl_legacy_map,
399 #ifdef CONFIG_PCI_MSI
400 static struct irq_chip nwl_msi_irq_chip = {
401 .name = "nwl_pcie:msi",
402 .irq_enable = unmask_msi_irq,
403 .irq_disable = mask_msi_irq,
404 .irq_mask = mask_msi_irq,
405 .irq_unmask = unmask_msi_irq,
409 static struct msi_domain_info nwl_msi_domain_info = {
410 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
411 MSI_FLAG_MULTI_PCI_MSI),
412 .chip = &nwl_msi_irq_chip,
416 static void nwl_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
418 struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data);
419 phys_addr_t msi_addr = pcie->phys_pcie_reg_base;
421 msg->address_lo = lower_32_bits(msi_addr);
422 msg->address_hi = upper_32_bits(msi_addr);
423 msg->data = data->hwirq;
426 static int nwl_msi_set_affinity(struct irq_data *irq_data,
427 const struct cpumask *mask, bool force)
432 static struct irq_chip nwl_irq_chip = {
433 .name = "Xilinx MSI",
434 .irq_compose_msi_msg = nwl_compose_msi_msg,
435 .irq_set_affinity = nwl_msi_set_affinity,
438 static int nwl_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
439 unsigned int nr_irqs, void *args)
441 struct nwl_pcie *pcie = domain->host_data;
442 struct nwl_msi *msi = &pcie->msi;
446 mutex_lock(&msi->lock);
447 bit = bitmap_find_next_zero_area(msi->bitmap, INT_PCI_MSI_NR, 0,
449 if (bit >= INT_PCI_MSI_NR) {
450 mutex_unlock(&msi->lock);
454 bitmap_set(msi->bitmap, bit, nr_irqs);
456 for (i = 0; i < nr_irqs; i++) {
457 irq_domain_set_info(domain, virq + i, bit + i, &nwl_irq_chip,
458 domain->host_data, handle_simple_irq,
461 mutex_unlock(&msi->lock);
465 static void nwl_irq_domain_free(struct irq_domain *domain, unsigned int virq,
466 unsigned int nr_irqs)
468 struct irq_data *data = irq_domain_get_irq_data(domain, virq);
469 struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data);
470 struct nwl_msi *msi = &pcie->msi;
472 mutex_lock(&msi->lock);
473 bitmap_clear(msi->bitmap, data->hwirq, nr_irqs);
474 mutex_unlock(&msi->lock);
477 static const struct irq_domain_ops dev_msi_domain_ops = {
478 .alloc = nwl_irq_domain_alloc,
479 .free = nwl_irq_domain_free,
482 static int nwl_pcie_init_msi_irq_domain(struct nwl_pcie *pcie)
484 #ifdef CONFIG_PCI_MSI
485 struct device *dev = pcie->dev;
486 struct fwnode_handle *fwnode = of_node_to_fwnode(dev->of_node);
487 struct nwl_msi *msi = &pcie->msi;
489 msi->dev_domain = irq_domain_add_linear(NULL, INT_PCI_MSI_NR,
490 &dev_msi_domain_ops, pcie);
491 if (!msi->dev_domain) {
492 dev_err(dev, "failed to create dev IRQ domain\n");
495 msi->msi_domain = pci_msi_create_irq_domain(fwnode,
496 &nwl_msi_domain_info,
498 if (!msi->msi_domain) {
499 dev_err(dev, "failed to create msi IRQ domain\n");
500 irq_domain_remove(msi->dev_domain);
507 static int nwl_pcie_init_irq_domain(struct nwl_pcie *pcie)
509 struct device *dev = pcie->dev;
510 struct device_node *node = dev->of_node;
511 struct device_node *legacy_intc_node;
513 legacy_intc_node = of_get_next_child(node, NULL);
514 if (!legacy_intc_node) {
515 dev_err(dev, "No legacy intc node found\n");
519 pcie->legacy_irq_domain = irq_domain_add_linear(legacy_intc_node,
524 if (!pcie->legacy_irq_domain) {
525 dev_err(dev, "failed to create IRQ domain\n");
529 nwl_pcie_init_msi_irq_domain(pcie);
533 static int nwl_pcie_enable_msi(struct nwl_pcie *pcie, struct pci_bus *bus)
535 struct device *dev = pcie->dev;
536 struct platform_device *pdev = to_platform_device(dev);
537 struct nwl_msi *msi = &pcie->msi;
540 int size = BITS_TO_LONGS(INT_PCI_MSI_NR) * sizeof(long);
542 mutex_init(&msi->lock);
544 msi->bitmap = kzalloc(size, GFP_KERNEL);
548 /* Get msi_1 IRQ number */
549 msi->irq_msi1 = platform_get_irq_byname(pdev, "msi1");
550 if (msi->irq_msi1 < 0) {
551 dev_err(dev, "failed to get IRQ#%d\n", msi->irq_msi1);
556 irq_set_chained_handler_and_data(msi->irq_msi1,
557 nwl_pcie_msi_handler_high, pcie);
559 /* Get msi_0 IRQ number */
560 msi->irq_msi0 = platform_get_irq_byname(pdev, "msi0");
561 if (msi->irq_msi0 < 0) {
562 dev_err(dev, "failed to get IRQ#%d\n", msi->irq_msi0);
567 irq_set_chained_handler_and_data(msi->irq_msi0,
568 nwl_pcie_msi_handler_low, pcie);
570 /* Check for msii_present bit */
571 ret = nwl_bridge_readl(pcie, I_MSII_CAPABILITIES) & MSII_PRESENT;
573 dev_err(dev, "MSI not present\n");
579 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, I_MSII_CONTROL) |
580 MSII_ENABLE, I_MSII_CONTROL);
582 /* Enable MSII status */
583 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, I_MSII_CONTROL) |
584 MSII_STATUS_ENABLE, I_MSII_CONTROL);
586 /* setup AFI/FPCI range */
587 base = pcie->phys_pcie_reg_base;
588 nwl_bridge_writel(pcie, lower_32_bits(base), I_MSII_BASE_LO);
589 nwl_bridge_writel(pcie, upper_32_bits(base), I_MSII_BASE_HI);
592 * For high range MSI interrupts: disable, clear any pending,
595 nwl_bridge_writel(pcie, (u32)~MSGF_MSI_SR_HI_MASK, MSGF_MSI_MASK_HI);
597 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MSI_STATUS_HI) &
598 MSGF_MSI_SR_HI_MASK, MSGF_MSI_STATUS_HI);
600 nwl_bridge_writel(pcie, MSGF_MSI_SR_HI_MASK, MSGF_MSI_MASK_HI);
603 * For low range MSI interrupts: disable, clear any pending,
606 nwl_bridge_writel(pcie, (u32)~MSGF_MSI_SR_LO_MASK, MSGF_MSI_MASK_LO);
608 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MSI_STATUS_LO) &
609 MSGF_MSI_SR_LO_MASK, MSGF_MSI_STATUS_LO);
611 nwl_bridge_writel(pcie, MSGF_MSI_SR_LO_MASK, MSGF_MSI_MASK_LO);
620 static int nwl_pcie_bridge_init(struct nwl_pcie *pcie)
622 struct device *dev = pcie->dev;
623 struct platform_device *pdev = to_platform_device(dev);
624 u32 breg_val, ecam_val, first_busno = 0;
627 breg_val = nwl_bridge_readl(pcie, E_BREG_CAPABILITIES) & BREG_PRESENT;
629 dev_err(dev, "BREG is not present\n");
633 /* Write bridge_off to breg base */
634 nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_breg_base),
636 nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_breg_base),
640 nwl_bridge_writel(pcie, ~BREG_ENABLE_FORCE & BREG_ENABLE,
643 /* Disable DMA channel registers */
644 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_PCIE_RX0) |
645 CFG_DMA_REG_BAR, BRCFG_PCIE_RX0);
647 /* Enable Ingress subtractive decode translation */
648 nwl_bridge_writel(pcie, SET_ISUB_CONTROL, I_ISUB_CONTROL);
650 /* Enable msg filtering details */
651 nwl_bridge_writel(pcie, CFG_ENABLE_MSG_FILTER_MASK,
652 BRCFG_PCIE_RX_MSG_FILTER);
654 err = nwl_wait_for_link(pcie);
658 ecam_val = nwl_bridge_readl(pcie, E_ECAM_CAPABILITIES) & E_ECAM_PRESENT;
660 dev_err(dev, "ECAM is not present\n");
665 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) |
666 E_ECAM_CR_ENABLE, E_ECAM_CONTROL);
668 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) |
669 (pcie->ecam_value << E_ECAM_SIZE_SHIFT),
672 nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_ecam_base),
674 nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_ecam_base),
678 ecam_val = nwl_bridge_readl(pcie, E_ECAM_CONTROL);
679 pcie->last_busno = (ecam_val & E_ECAM_SIZE_LOC) >> E_ECAM_SIZE_SHIFT;
680 /* Write primary, secondary and subordinate bus numbers */
681 ecam_val = first_busno;
682 ecam_val |= (first_busno + 1) << 8;
683 ecam_val |= (pcie->last_busno << E_ECAM_SIZE_SHIFT);
684 writel(ecam_val, (pcie->ecam_base + PCI_PRIMARY_BUS));
686 if (nwl_pcie_link_up(pcie))
687 dev_info(dev, "Link is UP\n");
689 dev_info(dev, "Link is DOWN\n");
691 /* Get misc IRQ number */
692 pcie->irq_misc = platform_get_irq_byname(pdev, "misc");
693 if (pcie->irq_misc < 0) {
694 dev_err(dev, "failed to get misc IRQ %d\n",
699 err = devm_request_irq(dev, pcie->irq_misc,
700 nwl_pcie_misc_handler, IRQF_SHARED,
701 "nwl_pcie:misc", pcie);
703 dev_err(dev, "fail to register misc IRQ#%d\n",
708 /* Disable all misc interrupts */
709 nwl_bridge_writel(pcie, (u32)~MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK);
711 /* Clear pending misc interrupts */
712 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MISC_STATUS) &
713 MSGF_MISC_SR_MASKALL, MSGF_MISC_STATUS);
715 /* Enable all misc interrupts */
716 nwl_bridge_writel(pcie, MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK);
719 /* Disable all legacy interrupts */
720 nwl_bridge_writel(pcie, (u32)~MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK);
722 /* Clear pending legacy interrupts */
723 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_LEG_STATUS) &
724 MSGF_LEG_SR_MASKALL, MSGF_LEG_STATUS);
726 /* Enable all legacy interrupts */
727 nwl_bridge_writel(pcie, MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK);
729 /* Enable the bridge config interrupt */
730 nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_INTERRUPT) |
731 BRCFG_INTERRUPT_MASK, BRCFG_INTERRUPT);
736 static int nwl_pcie_parse_dt(struct nwl_pcie *pcie,
737 struct platform_device *pdev)
739 struct device *dev = pcie->dev;
740 struct device_node *node = dev->of_node;
741 struct resource *res;
744 /* Check for device type */
745 type = of_get_property(node, "device_type", NULL);
746 if (!type || strcmp(type, "pci")) {
747 dev_err(dev, "invalid \"device_type\" %s\n", type);
751 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "breg");
752 pcie->breg_base = devm_ioremap_resource(dev, res);
753 if (IS_ERR(pcie->breg_base))
754 return PTR_ERR(pcie->breg_base);
755 pcie->phys_breg_base = res->start;
757 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pcireg");
758 pcie->pcireg_base = devm_ioremap_resource(dev, res);
759 if (IS_ERR(pcie->pcireg_base))
760 return PTR_ERR(pcie->pcireg_base);
761 pcie->phys_pcie_reg_base = res->start;
763 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");
764 pcie->ecam_base = devm_pci_remap_cfg_resource(dev, res);
765 if (IS_ERR(pcie->ecam_base))
766 return PTR_ERR(pcie->ecam_base);
767 pcie->phys_ecam_base = res->start;
769 /* Get intx IRQ number */
770 pcie->irq_intx = platform_get_irq_byname(pdev, "intx");
771 if (pcie->irq_intx < 0) {
772 dev_err(dev, "failed to get intx IRQ %d\n", pcie->irq_intx);
776 irq_set_chained_handler_and_data(pcie->irq_intx,
777 nwl_pcie_leg_handler, pcie);
782 static const struct of_device_id nwl_pcie_of_match[] = {
783 { .compatible = "xlnx,nwl-pcie-2.11", },
787 static int nwl_pcie_probe(struct platform_device *pdev)
789 struct device *dev = &pdev->dev;
790 struct device_node *node = dev->of_node;
791 struct nwl_pcie *pcie;
793 struct pci_bus *child;
795 resource_size_t iobase = 0;
798 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
803 pcie->ecam_value = NWL_ECAM_VALUE_DEFAULT;
805 err = nwl_pcie_parse_dt(pcie, pdev);
807 dev_err(dev, "Parsing DT failed\n");
811 err = nwl_pcie_bridge_init(pcie);
813 dev_err(dev, "HW Initialization failed\n");
817 err = of_pci_get_host_bridge_resources(node, 0, 0xff, &res, &iobase);
819 dev_err(dev, "Getting bridge resources failed\n");
823 err = devm_request_pci_bus_resources(dev, &res);
827 err = nwl_pcie_init_irq_domain(pcie);
829 dev_err(dev, "Failed creating IRQ Domain\n");
833 bus = pci_create_root_bus(dev, pcie->root_busno,
834 &nwl_pcie_ops, pcie, &res);
840 if (IS_ENABLED(CONFIG_PCI_MSI)) {
841 err = nwl_pcie_enable_msi(pcie, bus);
843 dev_err(dev, "failed to enable MSI support: %d\n", err);
847 pci_scan_child_bus(bus);
848 pci_assign_unassigned_bus_resources(bus);
849 list_for_each_entry(child, &bus->children, node)
850 pcie_bus_configure_settings(child);
851 pci_bus_add_devices(bus);
855 pci_free_resource_list(&res);
859 static struct platform_driver nwl_pcie_driver = {
862 .suppress_bind_attrs = true,
863 .of_match_table = nwl_pcie_of_match,
865 .probe = nwl_pcie_probe,
867 builtin_platform_driver(nwl_pcie_driver);