2 * PCI Express PCI Hot Plug Driver
4 * Copyright (C) 1995,2001 Compaq Computer Corporation
5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
6 * Copyright (C) 2001 IBM Corp.
7 * Copyright (C) 2003-2004 Intel Corporation
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
19 * NON INFRINGEMENT. See the GNU General Public License for more
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/types.h>
33 #include <linux/signal.h>
34 #include <linux/jiffies.h>
35 #include <linux/timer.h>
36 #include <linux/pci.h>
37 #include <linux/interrupt.h>
38 #include <linux/time.h>
39 #include <linux/slab.h>
44 static inline int pciehp_readw(struct controller *ctrl, int reg, u16 *value)
46 struct pci_dev *dev = ctrl->pcie->port;
47 return pci_read_config_word(dev, pci_pcie_cap(dev) + reg, value);
50 static inline int pciehp_readl(struct controller *ctrl, int reg, u32 *value)
52 struct pci_dev *dev = ctrl->pcie->port;
53 return pci_read_config_dword(dev, pci_pcie_cap(dev) + reg, value);
56 static inline int pciehp_writew(struct controller *ctrl, int reg, u16 value)
58 struct pci_dev *dev = ctrl->pcie->port;
59 return pci_write_config_word(dev, pci_pcie_cap(dev) + reg, value);
62 static inline int pciehp_writel(struct controller *ctrl, int reg, u32 value)
64 struct pci_dev *dev = ctrl->pcie->port;
65 return pci_write_config_dword(dev, pci_pcie_cap(dev) + reg, value);
68 /* Power Control Command */
70 #define POWER_OFF PCI_EXP_SLTCTL_PCC
72 static irqreturn_t pcie_isr(int irq, void *dev_id);
73 static void start_int_poll_timer(struct controller *ctrl, int sec);
75 /* This is the interrupt polling timeout function. */
76 static void int_poll_timeout(unsigned long data)
78 struct controller *ctrl = (struct controller *)data;
80 /* Poll for interrupt events. regs == NULL => polling */
83 init_timer(&ctrl->poll_timer);
84 if (!pciehp_poll_time)
85 pciehp_poll_time = 2; /* default polling interval is 2 sec */
87 start_int_poll_timer(ctrl, pciehp_poll_time);
90 /* This function starts the interrupt polling timer. */
91 static void start_int_poll_timer(struct controller *ctrl, int sec)
93 /* Clamp to sane value */
94 if ((sec <= 0) || (sec > 60))
97 ctrl->poll_timer.function = &int_poll_timeout;
98 ctrl->poll_timer.data = (unsigned long)ctrl;
99 ctrl->poll_timer.expires = jiffies + sec * HZ;
100 add_timer(&ctrl->poll_timer);
103 static inline int pciehp_request_irq(struct controller *ctrl)
105 int retval, irq = ctrl->pcie->irq;
107 /* Install interrupt polling timer. Start with 10 sec delay */
108 if (pciehp_poll_mode) {
109 init_timer(&ctrl->poll_timer);
110 start_int_poll_timer(ctrl, 10);
114 /* Installs the interrupt handler */
115 retval = request_irq(irq, pcie_isr, IRQF_SHARED, MY_NAME, ctrl);
117 ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n",
122 static inline void pciehp_free_irq(struct controller *ctrl)
124 if (pciehp_poll_mode)
125 del_timer_sync(&ctrl->poll_timer);
127 free_irq(ctrl->pcie->irq, ctrl);
130 static int pcie_poll_cmd(struct controller *ctrl)
133 int err, timeout = 1000;
135 err = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
136 if (!err && (slot_status & PCI_EXP_SLTSTA_CC)) {
137 pciehp_writew(ctrl, PCI_EXP_SLTSTA, PCI_EXP_SLTSTA_CC);
140 while (timeout > 0) {
143 err = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
144 if (!err && (slot_status & PCI_EXP_SLTSTA_CC)) {
145 pciehp_writew(ctrl, PCI_EXP_SLTSTA, PCI_EXP_SLTSTA_CC);
149 return 0; /* timeout */
152 static void pcie_wait_cmd(struct controller *ctrl, int poll)
154 unsigned int msecs = pciehp_poll_mode ? 2500 : 1000;
155 unsigned long timeout = msecs_to_jiffies(msecs);
159 rc = pcie_poll_cmd(ctrl);
161 rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout);
163 ctrl_dbg(ctrl, "Command not completed in 1000 msec\n");
167 * pcie_write_cmd - Issue controller command
168 * @ctrl: controller to which the command is issued
169 * @cmd: command value written to slot control register
170 * @mask: bitmask of slot control register to be modified
172 static int pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask)
178 mutex_lock(&ctrl->ctrl_lock);
180 retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
182 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
187 if (slot_status & PCI_EXP_SLTSTA_CC) {
188 if (!ctrl->no_cmd_complete) {
190 * After 1 sec and CMD_COMPLETED still not set, just
191 * proceed forward to issue the next command according
192 * to spec. Just print out the error message.
194 ctrl_dbg(ctrl, "CMD_COMPLETED not clear after 1 sec\n");
195 } else if (!NO_CMD_CMPL(ctrl)) {
197 * This controller semms to notify of command completed
198 * event even though it supports none of power
199 * controller, attention led, power led and EMI.
201 ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Need to "
202 "wait for command completed event.\n");
203 ctrl->no_cmd_complete = 0;
205 ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Maybe "
206 "the controller is broken.\n");
210 retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl);
212 ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__);
217 slot_ctrl |= (cmd & mask);
220 retval = pciehp_writew(ctrl, PCI_EXP_SLTCTL, slot_ctrl);
222 ctrl_err(ctrl, "Cannot write to SLOTCTRL register\n");
225 * Wait for command completion.
227 if (!retval && !ctrl->no_cmd_complete) {
230 * if hotplug interrupt is not enabled or command
231 * completed interrupt is not enabled, we need to poll
232 * command completed event.
234 if (!(slot_ctrl & PCI_EXP_SLTCTL_HPIE) ||
235 !(slot_ctrl & PCI_EXP_SLTCTL_CCIE))
237 pcie_wait_cmd(ctrl, poll);
240 mutex_unlock(&ctrl->ctrl_lock);
244 static inline int check_link_active(struct controller *ctrl)
248 if (pciehp_readw(ctrl, PCI_EXP_LNKSTA, &link_status))
250 return !!(link_status & PCI_EXP_LNKSTA_DLLLA);
253 static void pcie_wait_link_active(struct controller *ctrl)
257 if (check_link_active(ctrl))
259 while (timeout > 0) {
262 if (check_link_active(ctrl))
265 ctrl_dbg(ctrl, "Data Link Layer Link Active not set in 1000 msec\n");
268 int pciehp_check_link_status(struct controller *ctrl)
274 * Data Link Layer Link Active Reporting must be capable for
275 * hot-plug capable downstream port. But old controller might
276 * not implement it. In this case, we wait for 1000 ms.
278 if (ctrl->link_active_reporting){
279 /* Wait for Data Link Layer Link Active bit to be set */
280 pcie_wait_link_active(ctrl);
282 * We must wait for 100 ms after the Data Link Layer
283 * Link Active bit reads 1b before initiating a
284 * configuration access to the hot added device.
290 retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status);
292 ctrl_err(ctrl, "Cannot read LNKSTATUS register\n");
296 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
297 if ((lnk_status & PCI_EXP_LNKSTA_LT) ||
298 !(lnk_status & PCI_EXP_LNKSTA_NLW)) {
299 ctrl_err(ctrl, "Link Training Error occurs \n");
307 int pciehp_get_attention_status(struct slot *slot, u8 *status)
309 struct controller *ctrl = slot->ctrl;
314 retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl);
316 ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__);
320 ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", __func__,
321 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
323 atten_led_state = (slot_ctrl & PCI_EXP_SLTCTL_AIC) >> 6;
325 switch (atten_led_state) {
327 *status = 0xFF; /* Reserved */
330 *status = 1; /* On */
333 *status = 2; /* Blink */
336 *status = 0; /* Off */
346 int pciehp_get_power_status(struct slot *slot, u8 *status)
348 struct controller *ctrl = slot->ctrl;
353 retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl);
355 ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__);
358 ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", __func__,
359 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
361 pwr_state = (slot_ctrl & PCI_EXP_SLTCTL_PCC) >> 10;
378 int pciehp_get_latch_status(struct slot *slot, u8 *status)
380 struct controller *ctrl = slot->ctrl;
384 retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
386 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
390 *status = !!(slot_status & PCI_EXP_SLTSTA_MRLSS);
394 int pciehp_get_adapter_status(struct slot *slot, u8 *status)
396 struct controller *ctrl = slot->ctrl;
400 retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
402 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
406 *status = !!(slot_status & PCI_EXP_SLTSTA_PDS);
410 int pciehp_query_power_fault(struct slot *slot)
412 struct controller *ctrl = slot->ctrl;
416 retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
418 ctrl_err(ctrl, "Cannot check for power fault\n");
421 return !!(slot_status & PCI_EXP_SLTSTA_PFD);
424 int pciehp_set_attention_status(struct slot *slot, u8 value)
426 struct controller *ctrl = slot->ctrl;
430 cmd_mask = PCI_EXP_SLTCTL_AIC;
432 case 0 : /* turn off */
435 case 1: /* turn on */
438 case 2: /* turn blink */
444 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
445 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
446 return pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
449 void pciehp_green_led_on(struct slot *slot)
451 struct controller *ctrl = slot->ctrl;
456 cmd_mask = PCI_EXP_SLTCTL_PIC;
457 pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
458 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
459 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
462 void pciehp_green_led_off(struct slot *slot)
464 struct controller *ctrl = slot->ctrl;
469 cmd_mask = PCI_EXP_SLTCTL_PIC;
470 pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
471 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
472 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
475 void pciehp_green_led_blink(struct slot *slot)
477 struct controller *ctrl = slot->ctrl;
482 cmd_mask = PCI_EXP_SLTCTL_PIC;
483 pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
484 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
485 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
488 int pciehp_power_on_slot(struct slot * slot)
490 struct controller *ctrl = slot->ctrl;
497 /* Clear sticky power-fault bit from previous power failures */
498 retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
500 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
504 slot_status &= PCI_EXP_SLTSTA_PFD;
506 retval = pciehp_writew(ctrl, PCI_EXP_SLTSTA, slot_status);
509 "%s: Cannot write to SLOTSTATUS register\n",
514 ctrl->power_fault_detected = 0;
517 cmd_mask = PCI_EXP_SLTCTL_PCC;
518 retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
520 ctrl_err(ctrl, "Write %x command failed!\n", slot_cmd);
523 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
524 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
526 retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status);
528 ctrl_err(ctrl, "%s: Cannot read LNKSTA register\n",
532 pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status);
537 int pciehp_power_off_slot(struct slot * slot)
539 struct controller *ctrl = slot->ctrl;
544 slot_cmd = POWER_OFF;
545 cmd_mask = PCI_EXP_SLTCTL_PCC;
546 retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
548 ctrl_err(ctrl, "Write command failed!\n");
551 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
552 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
556 static irqreturn_t pcie_isr(int irq, void *dev_id)
558 struct controller *ctrl = (struct controller *)dev_id;
559 struct slot *slot = ctrl->slot;
560 u16 detected, intr_loc;
563 * In order to guarantee that all interrupt events are
564 * serviced, we need to re-inspect Slot Status register after
565 * clearing what is presumed to be the last pending interrupt.
569 if (pciehp_readw(ctrl, PCI_EXP_SLTSTA, &detected)) {
570 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS\n",
575 detected &= (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
576 PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC |
578 detected &= ~intr_loc;
579 intr_loc |= detected;
582 if (detected && pciehp_writew(ctrl, PCI_EXP_SLTSTA, intr_loc)) {
583 ctrl_err(ctrl, "%s: Cannot write to SLOTSTATUS\n",
589 ctrl_dbg(ctrl, "%s: intr_loc %x\n", __func__, intr_loc);
591 /* Check Command Complete Interrupt Pending */
592 if (intr_loc & PCI_EXP_SLTSTA_CC) {
595 wake_up(&ctrl->queue);
598 if (!(intr_loc & ~PCI_EXP_SLTSTA_CC))
601 /* Check MRL Sensor Changed */
602 if (intr_loc & PCI_EXP_SLTSTA_MRLSC)
603 pciehp_handle_switch_change(slot);
605 /* Check Attention Button Pressed */
606 if (intr_loc & PCI_EXP_SLTSTA_ABP)
607 pciehp_handle_attention_button(slot);
609 /* Check Presence Detect Changed */
610 if (intr_loc & PCI_EXP_SLTSTA_PDC)
611 pciehp_handle_presence_change(slot);
613 /* Check Power Fault Detected */
614 if ((intr_loc & PCI_EXP_SLTSTA_PFD) && !ctrl->power_fault_detected) {
615 ctrl->power_fault_detected = 1;
616 pciehp_handle_power_fault(slot);
621 int pciehp_get_max_lnk_width(struct slot *slot,
622 enum pcie_link_width *value)
624 struct controller *ctrl = slot->ctrl;
625 enum pcie_link_width lnk_wdth;
629 retval = pciehp_readl(ctrl, PCI_EXP_LNKCAP, &lnk_cap);
631 ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__);
635 switch ((lnk_cap & PCI_EXP_LNKSTA_NLW) >> 4){
637 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
640 lnk_wdth = PCIE_LNK_X1;
643 lnk_wdth = PCIE_LNK_X2;
646 lnk_wdth = PCIE_LNK_X4;
649 lnk_wdth = PCIE_LNK_X8;
652 lnk_wdth = PCIE_LNK_X12;
655 lnk_wdth = PCIE_LNK_X16;
658 lnk_wdth = PCIE_LNK_X32;
661 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
666 ctrl_dbg(ctrl, "Max link width = %d\n", lnk_wdth);
671 int pciehp_get_cur_lnk_width(struct slot *slot,
672 enum pcie_link_width *value)
674 struct controller *ctrl = slot->ctrl;
675 enum pcie_link_width lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
679 retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status);
681 ctrl_err(ctrl, "%s: Cannot read LNKSTATUS register\n",
686 switch ((lnk_status & PCI_EXP_LNKSTA_NLW) >> 4){
688 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
691 lnk_wdth = PCIE_LNK_X1;
694 lnk_wdth = PCIE_LNK_X2;
697 lnk_wdth = PCIE_LNK_X4;
700 lnk_wdth = PCIE_LNK_X8;
703 lnk_wdth = PCIE_LNK_X12;
706 lnk_wdth = PCIE_LNK_X16;
709 lnk_wdth = PCIE_LNK_X32;
712 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
717 ctrl_dbg(ctrl, "Current link width = %d\n", lnk_wdth);
722 int pcie_enable_notification(struct controller *ctrl)
727 * TBD: Power fault detected software notification support.
729 * Power fault detected software notification is not enabled
730 * now, because it caused power fault detected interrupt storm
731 * on some machines. On those machines, power fault detected
732 * bit in the slot status register was set again immediately
733 * when it is cleared in the interrupt service routine, and
734 * next power fault detected interrupt was notified again.
736 cmd = PCI_EXP_SLTCTL_PDCE;
737 if (ATTN_BUTTN(ctrl))
738 cmd |= PCI_EXP_SLTCTL_ABPE;
740 cmd |= PCI_EXP_SLTCTL_MRLSCE;
741 if (!pciehp_poll_mode)
742 cmd |= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE;
744 mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
745 PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE |
746 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE);
748 if (pcie_write_cmd(ctrl, cmd, mask)) {
749 ctrl_err(ctrl, "Cannot enable software notification\n");
755 static void pcie_disable_notification(struct controller *ctrl)
758 mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
759 PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE |
760 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE |
761 PCI_EXP_SLTCTL_DLLSCE);
762 if (pcie_write_cmd(ctrl, 0, mask))
763 ctrl_warn(ctrl, "Cannot disable software notification\n");
766 int pcie_init_notification(struct controller *ctrl)
768 if (pciehp_request_irq(ctrl))
770 if (pcie_enable_notification(ctrl)) {
771 pciehp_free_irq(ctrl);
774 ctrl->notification_enabled = 1;
778 static void pcie_shutdown_notification(struct controller *ctrl)
780 if (ctrl->notification_enabled) {
781 pcie_disable_notification(ctrl);
782 pciehp_free_irq(ctrl);
783 ctrl->notification_enabled = 0;
787 static int pcie_init_slot(struct controller *ctrl)
791 slot = kzalloc(sizeof(*slot), GFP_KERNEL);
796 mutex_init(&slot->lock);
797 INIT_DELAYED_WORK(&slot->work, pciehp_queue_pushbutton_work);
802 static void pcie_cleanup_slot(struct controller *ctrl)
804 struct slot *slot = ctrl->slot;
805 cancel_delayed_work(&slot->work);
806 flush_workqueue(pciehp_wq);
807 flush_workqueue(pciehp_ordered_wq);
811 static inline void dbg_ctrl(struct controller *ctrl)
815 struct pci_dev *pdev = ctrl->pcie->port;
820 ctrl_info(ctrl, "Hotplug Controller:\n");
821 ctrl_info(ctrl, " Seg/Bus/Dev/Func/IRQ : %s IRQ %d\n",
822 pci_name(pdev), pdev->irq);
823 ctrl_info(ctrl, " Vendor ID : 0x%04x\n", pdev->vendor);
824 ctrl_info(ctrl, " Device ID : 0x%04x\n", pdev->device);
825 ctrl_info(ctrl, " Subsystem ID : 0x%04x\n",
826 pdev->subsystem_device);
827 ctrl_info(ctrl, " Subsystem Vendor ID : 0x%04x\n",
828 pdev->subsystem_vendor);
829 ctrl_info(ctrl, " PCIe Cap offset : 0x%02x\n",
831 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
832 if (!pci_resource_len(pdev, i))
834 ctrl_info(ctrl, " PCI resource [%d] : %pR\n",
835 i, &pdev->resource[i]);
837 ctrl_info(ctrl, "Slot Capabilities : 0x%08x\n", ctrl->slot_cap);
838 ctrl_info(ctrl, " Physical Slot Number : %d\n", PSN(ctrl));
839 ctrl_info(ctrl, " Attention Button : %3s\n",
840 ATTN_BUTTN(ctrl) ? "yes" : "no");
841 ctrl_info(ctrl, " Power Controller : %3s\n",
842 POWER_CTRL(ctrl) ? "yes" : "no");
843 ctrl_info(ctrl, " MRL Sensor : %3s\n",
844 MRL_SENS(ctrl) ? "yes" : "no");
845 ctrl_info(ctrl, " Attention Indicator : %3s\n",
846 ATTN_LED(ctrl) ? "yes" : "no");
847 ctrl_info(ctrl, " Power Indicator : %3s\n",
848 PWR_LED(ctrl) ? "yes" : "no");
849 ctrl_info(ctrl, " Hot-Plug Surprise : %3s\n",
850 HP_SUPR_RM(ctrl) ? "yes" : "no");
851 ctrl_info(ctrl, " EMI Present : %3s\n",
852 EMI(ctrl) ? "yes" : "no");
853 ctrl_info(ctrl, " Command Completed : %3s\n",
854 NO_CMD_CMPL(ctrl) ? "no" : "yes");
855 pciehp_readw(ctrl, PCI_EXP_SLTSTA, ®16);
856 ctrl_info(ctrl, "Slot Status : 0x%04x\n", reg16);
857 pciehp_readw(ctrl, PCI_EXP_SLTCTL, ®16);
858 ctrl_info(ctrl, "Slot Control : 0x%04x\n", reg16);
861 struct controller *pcie_init(struct pcie_device *dev)
863 struct controller *ctrl;
864 u32 slot_cap, link_cap;
865 struct pci_dev *pdev = dev->port;
867 ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
869 dev_err(&dev->device, "%s: Out of memory\n", __func__);
873 if (!pci_pcie_cap(pdev)) {
874 ctrl_err(ctrl, "Cannot find PCI Express capability\n");
877 if (pciehp_readl(ctrl, PCI_EXP_SLTCAP, &slot_cap)) {
878 ctrl_err(ctrl, "Cannot read SLOTCAP register\n");
882 ctrl->slot_cap = slot_cap;
883 mutex_init(&ctrl->ctrl_lock);
884 init_waitqueue_head(&ctrl->queue);
887 * Controller doesn't notify of command completion if the "No
888 * Command Completed Support" bit is set in Slot Capability
889 * register or the controller supports none of power
890 * controller, attention led, power led and EMI.
892 if (NO_CMD_CMPL(ctrl) ||
893 !(POWER_CTRL(ctrl) | ATTN_LED(ctrl) | PWR_LED(ctrl) | EMI(ctrl)))
894 ctrl->no_cmd_complete = 1;
896 /* Check if Data Link Layer Link Active Reporting is implemented */
897 if (pciehp_readl(ctrl, PCI_EXP_LNKCAP, &link_cap)) {
898 ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__);
901 if (link_cap & PCI_EXP_LNKCAP_DLLLARC) {
902 ctrl_dbg(ctrl, "Link Active Reporting supported\n");
903 ctrl->link_active_reporting = 1;
906 /* Clear all remaining event bits in Slot Status register */
907 if (pciehp_writew(ctrl, PCI_EXP_SLTSTA, 0x1f))
910 /* Disable sotfware notification */
911 pcie_disable_notification(ctrl);
913 ctrl_info(ctrl, "HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n",
914 pdev->vendor, pdev->device, pdev->subsystem_vendor,
915 pdev->subsystem_device);
917 if (pcie_init_slot(ctrl))
928 void pciehp_release_ctrl(struct controller *ctrl)
930 pcie_shutdown_notification(ctrl);
931 pcie_cleanup_slot(ctrl);