2 * PCI Express PCI Hot Plug Driver
4 * Copyright (C) 1995,2001 Compaq Computer Corporation
5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
6 * Copyright (C) 2001 IBM Corp.
7 * Copyright (C) 2003-2004 Intel Corporation
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
19 * NON INFRINGEMENT. See the GNU General Public License for more
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/types.h>
33 #include <linux/signal.h>
34 #include <linux/jiffies.h>
35 #include <linux/timer.h>
36 #include <linux/pci.h>
37 #include <linux/interrupt.h>
38 #include <linux/time.h>
43 #define DBG_K_TRACE_ENTRY ((unsigned int)0x00000001) /* On function entry */
44 #define DBG_K_TRACE_EXIT ((unsigned int)0x00000002) /* On function exit */
45 #define DBG_K_INFO ((unsigned int)0x00000004) /* Info messages */
46 #define DBG_K_ERROR ((unsigned int)0x00000008) /* Error messages */
47 #define DBG_K_TRACE (DBG_K_TRACE_ENTRY|DBG_K_TRACE_EXIT)
48 #define DBG_K_STANDARD (DBG_K_INFO|DBG_K_ERROR|DBG_K_TRACE)
49 /* Redefine this flagword to set debug level */
50 #define DEBUG_LEVEL DBG_K_STANDARD
52 #define DEFINE_DBG_BUFFER char __dbg_str_buf[256];
54 #define DBG_PRINT( dbg_flags, args... ) \
56 if ( DEBUG_LEVEL & ( dbg_flags ) ) \
59 len = sprintf( __dbg_str_buf, "%s:%d: %s: ", \
60 __FILE__, __LINE__, __FUNCTION__ ); \
61 sprintf( __dbg_str_buf + len, args ); \
62 printk( KERN_NOTICE "%s\n", __dbg_str_buf ); \
66 #define DBG_ENTER_ROUTINE DBG_PRINT (DBG_K_TRACE_ENTRY, "%s", "[Entry]");
67 #define DBG_LEAVE_ROUTINE DBG_PRINT (DBG_K_TRACE_EXIT, "%s", "[Exit]");
69 #define DEFINE_DBG_BUFFER
70 #define DBG_ENTER_ROUTINE
71 #define DBG_LEAVE_ROUTINE
74 static atomic_t pciehp_num_controllers = ATOMIC_INIT(0);
92 } __attribute__ ((packed));
94 /* offsets to the controller registers based on the above structure layout */
96 PCIECAPID = offsetof(struct ctrl_reg, cap_id),
97 NXTCAPPTR = offsetof(struct ctrl_reg, nxt_ptr),
98 CAPREG = offsetof(struct ctrl_reg, cap_reg),
99 DEVCAP = offsetof(struct ctrl_reg, dev_cap),
100 DEVCTRL = offsetof(struct ctrl_reg, dev_ctrl),
101 DEVSTATUS = offsetof(struct ctrl_reg, dev_status),
102 LNKCAP = offsetof(struct ctrl_reg, lnk_cap),
103 LNKCTRL = offsetof(struct ctrl_reg, lnk_ctrl),
104 LNKSTATUS = offsetof(struct ctrl_reg, lnk_status),
105 SLOTCAP = offsetof(struct ctrl_reg, slot_cap),
106 SLOTCTRL = offsetof(struct ctrl_reg, slot_ctrl),
107 SLOTSTATUS = offsetof(struct ctrl_reg, slot_status),
108 ROOTCTRL = offsetof(struct ctrl_reg, root_ctrl),
109 ROOTSTATUS = offsetof(struct ctrl_reg, root_status),
112 static inline int pciehp_readw(struct controller *ctrl, int reg, u16 *value)
114 struct pci_dev *dev = ctrl->pci_dev;
115 return pci_read_config_word(dev, ctrl->cap_base + reg, value);
118 static inline int pciehp_readl(struct controller *ctrl, int reg, u32 *value)
120 struct pci_dev *dev = ctrl->pci_dev;
121 return pci_read_config_dword(dev, ctrl->cap_base + reg, value);
124 static inline int pciehp_writew(struct controller *ctrl, int reg, u16 value)
126 struct pci_dev *dev = ctrl->pci_dev;
127 return pci_write_config_word(dev, ctrl->cap_base + reg, value);
130 static inline int pciehp_writel(struct controller *ctrl, int reg, u32 value)
132 struct pci_dev *dev = ctrl->pci_dev;
133 return pci_write_config_dword(dev, ctrl->cap_base + reg, value);
136 /* Field definitions in PCI Express Capabilities Register */
137 #define CAP_VER 0x000F
138 #define DEV_PORT_TYPE 0x00F0
139 #define SLOT_IMPL 0x0100
140 #define MSG_NUM 0x3E00
142 /* Device or Port Type */
143 #define NAT_ENDPT 0x00
144 #define LEG_ENDPT 0x01
145 #define ROOT_PORT 0x04
146 #define UP_STREAM 0x05
147 #define DN_STREAM 0x06
148 #define PCIE_PCI_BRDG 0x07
149 #define PCI_PCIE_BRDG 0x10
151 /* Field definitions in Device Capabilities Register */
152 #define DATTN_BUTTN_PRSN 0x1000
153 #define DATTN_LED_PRSN 0x2000
154 #define DPWR_LED_PRSN 0x4000
156 /* Field definitions in Link Capabilities Register */
157 #define MAX_LNK_SPEED 0x000F
158 #define MAX_LNK_WIDTH 0x03F0
160 /* Link Width Encoding */
169 /*Field definitions of Link Status Register */
170 #define LNK_SPEED 0x000F
171 #define NEG_LINK_WD 0x03F0
172 #define LNK_TRN_ERR 0x0400
173 #define LNK_TRN 0x0800
174 #define SLOT_CLK_CONF 0x1000
176 /* Field definitions in Slot Capabilities Register */
177 #define ATTN_BUTTN_PRSN 0x00000001
178 #define PWR_CTRL_PRSN 0x00000002
179 #define MRL_SENS_PRSN 0x00000004
180 #define ATTN_LED_PRSN 0x00000008
181 #define PWR_LED_PRSN 0x00000010
182 #define HP_SUPR_RM_SUP 0x00000020
183 #define HP_CAP 0x00000040
184 #define SLOT_PWR_VALUE 0x000003F8
185 #define SLOT_PWR_LIMIT 0x00000C00
186 #define PSN 0xFFF80000 /* PSN: Physical Slot Number */
188 /* Field definitions in Slot Control Register */
189 #define ATTN_BUTTN_ENABLE 0x0001
190 #define PWR_FAULT_DETECT_ENABLE 0x0002
191 #define MRL_DETECT_ENABLE 0x0004
192 #define PRSN_DETECT_ENABLE 0x0008
193 #define CMD_CMPL_INTR_ENABLE 0x0010
194 #define HP_INTR_ENABLE 0x0020
195 #define ATTN_LED_CTRL 0x00C0
196 #define PWR_LED_CTRL 0x0300
197 #define PWR_CTRL 0x0400
198 #define EMI_CTRL 0x0800
200 /* Attention indicator and Power indicator states */
202 #define LED_BLINK 0x10
205 /* Power Control Command */
207 #define POWER_OFF 0x0400
209 /* EMI Status defines */
210 #define EMI_DISENGAGED 0
211 #define EMI_ENGAGED 1
213 /* Field definitions in Slot Status Register */
214 #define ATTN_BUTTN_PRESSED 0x0001
215 #define PWR_FAULT_DETECTED 0x0002
216 #define MRL_SENS_CHANGED 0x0004
217 #define PRSN_DETECT_CHANGED 0x0008
218 #define CMD_COMPLETED 0x0010
219 #define MRL_STATE 0x0020
220 #define PRSN_STATE 0x0040
221 #define EMI_STATE 0x0080
222 #define EMI_STATUS_BIT 7
224 DEFINE_DBG_BUFFER /* Debug string buffer for entire HPC defined here */
226 static irqreturn_t pcie_isr(int irq, void *dev_id);
227 static void start_int_poll_timer(struct controller *ctrl, int sec);
229 /* This is the interrupt polling timeout function. */
230 static void int_poll_timeout(unsigned long data)
232 struct controller *ctrl = (struct controller *)data;
236 /* Poll for interrupt events. regs == NULL => polling */
239 init_timer(&ctrl->poll_timer);
240 if (!pciehp_poll_time)
241 pciehp_poll_time = 2; /* reset timer to poll in 2 secs if user doesn't specify at module installation*/
243 start_int_poll_timer(ctrl, pciehp_poll_time);
246 /* This function starts the interrupt polling timer. */
247 static void start_int_poll_timer(struct controller *ctrl, int sec)
249 /* Clamp to sane value */
250 if ((sec <= 0) || (sec > 60))
253 ctrl->poll_timer.function = &int_poll_timeout;
254 ctrl->poll_timer.data = (unsigned long)ctrl;
255 ctrl->poll_timer.expires = jiffies + sec * HZ;
256 add_timer(&ctrl->poll_timer);
259 static inline int pcie_wait_cmd(struct controller *ctrl)
262 unsigned int msecs = pciehp_poll_mode ? 2500 : 1000;
263 unsigned long timeout = msecs_to_jiffies(msecs);
266 rc = wait_event_interruptible_timeout(ctrl->queue,
267 !ctrl->cmd_busy, timeout);
269 dbg("Command not completed in 1000 msec\n");
272 info("Command was interrupted by a signal\n");
279 * pcie_write_cmd - Issue controller command
280 * @slot: slot to which the command is issued
281 * @cmd: command value written to slot control register
282 * @mask: bitmask of slot control register to be modified
284 static int pcie_write_cmd(struct slot *slot, u16 cmd, u16 mask)
286 struct controller *ctrl = slot->ctrl;
294 mutex_lock(&ctrl->ctrl_lock);
296 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
298 err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__);
302 if ((slot_status & CMD_COMPLETED) == CMD_COMPLETED ) {
303 /* After 1 sec and CMD_COMPLETED still not set, just
304 proceed forward to issue the next command according
305 to spec. Just print out the error message */
306 dbg("%s: CMD_COMPLETED not clear after 1 sec.\n",
310 spin_lock_irqsave(&ctrl->lock, flags);
311 retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
313 err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__);
314 goto out_spin_unlock;
318 slot_ctrl |= ((cmd & mask) | CMD_CMPL_INTR_ENABLE);
321 retval = pciehp_writew(ctrl, SLOTCTRL, slot_ctrl);
323 err("%s: Cannot write to SLOTCTRL register\n", __FUNCTION__);
326 spin_unlock_irqrestore(&ctrl->lock, flags);
329 * Wait for command completion.
332 retval = pcie_wait_cmd(ctrl);
334 mutex_unlock(&ctrl->ctrl_lock);
339 static int hpc_check_lnk_status(struct controller *ctrl)
346 retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status);
348 err("%s: Cannot read LNKSTATUS register\n", __FUNCTION__);
352 dbg("%s: lnk_status = %x\n", __FUNCTION__, lnk_status);
353 if ( (lnk_status & LNK_TRN) || (lnk_status & LNK_TRN_ERR) ||
354 !(lnk_status & NEG_LINK_WD)) {
355 err("%s : Link Training Error occurs \n", __FUNCTION__);
365 static int hpc_get_attention_status(struct slot *slot, u8 *status)
367 struct controller *ctrl = slot->ctrl;
374 retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
376 err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__);
380 dbg("%s: SLOTCTRL %x, value read %x\n",
381 __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_ctrl);
383 atten_led_state = (slot_ctrl & ATTN_LED_CTRL) >> 6;
385 switch (atten_led_state) {
387 *status = 0xFF; /* Reserved */
390 *status = 1; /* On */
393 *status = 2; /* Blink */
396 *status = 0; /* Off */
407 static int hpc_get_power_status(struct slot *slot, u8 *status)
409 struct controller *ctrl = slot->ctrl;
416 retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
418 err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__);
421 dbg("%s: SLOTCTRL %x value read %x\n",
422 __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_ctrl);
424 pwr_state = (slot_ctrl & PWR_CTRL) >> 10;
443 static int hpc_get_latch_status(struct slot *slot, u8 *status)
445 struct controller *ctrl = slot->ctrl;
451 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
453 err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__);
457 *status = (((slot_status & MRL_STATE) >> 5) == 0) ? 0 : 1;
463 static int hpc_get_adapter_status(struct slot *slot, u8 *status)
465 struct controller *ctrl = slot->ctrl;
472 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
474 err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__);
477 card_state = (u8)((slot_status & PRSN_STATE) >> 6);
478 *status = (card_state == 1) ? 1 : 0;
484 static int hpc_query_power_fault(struct slot *slot)
486 struct controller *ctrl = slot->ctrl;
493 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
495 err("%s: Cannot check for power fault\n", __FUNCTION__);
498 pwr_fault = (u8)((slot_status & PWR_FAULT_DETECTED) >> 1);
504 static int hpc_get_emi_status(struct slot *slot, u8 *status)
506 struct controller *ctrl = slot->ctrl;
512 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
514 err("%s : Cannot check EMI status\n", __FUNCTION__);
517 *status = (slot_status & EMI_STATE) >> EMI_STATUS_BIT;
523 static int hpc_toggle_emi(struct slot *slot)
533 if (!pciehp_poll_mode) {
534 slot_cmd = slot_cmd | HP_INTR_ENABLE;
535 cmd_mask = cmd_mask | HP_INTR_ENABLE;
538 rc = pcie_write_cmd(slot, slot_cmd, cmd_mask);
539 slot->last_emi_toggle = get_seconds();
544 static int hpc_set_attention_status(struct slot *slot, u8 value)
546 struct controller *ctrl = slot->ctrl;
553 cmd_mask = ATTN_LED_CTRL;
555 case 0 : /* turn off */
558 case 1: /* turn on */
561 case 2: /* turn blink */
567 if (!pciehp_poll_mode) {
568 slot_cmd = slot_cmd | HP_INTR_ENABLE;
569 cmd_mask = cmd_mask | HP_INTR_ENABLE;
572 rc = pcie_write_cmd(slot, slot_cmd, cmd_mask);
573 dbg("%s: SLOTCTRL %x write cmd %x\n",
574 __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd);
581 static void hpc_set_green_led_on(struct slot *slot)
583 struct controller *ctrl = slot->ctrl;
590 cmd_mask = PWR_LED_CTRL;
591 if (!pciehp_poll_mode) {
592 slot_cmd = slot_cmd | HP_INTR_ENABLE;
593 cmd_mask = cmd_mask | HP_INTR_ENABLE;
596 pcie_write_cmd(slot, slot_cmd, cmd_mask);
598 dbg("%s: SLOTCTRL %x write cmd %x\n",
599 __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd);
604 static void hpc_set_green_led_off(struct slot *slot)
606 struct controller *ctrl = slot->ctrl;
613 cmd_mask = PWR_LED_CTRL;
614 if (!pciehp_poll_mode) {
615 slot_cmd = slot_cmd | HP_INTR_ENABLE;
616 cmd_mask = cmd_mask | HP_INTR_ENABLE;
619 pcie_write_cmd(slot, slot_cmd, cmd_mask);
620 dbg("%s: SLOTCTRL %x write cmd %x\n",
621 __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd);
627 static void hpc_set_green_led_blink(struct slot *slot)
629 struct controller *ctrl = slot->ctrl;
636 cmd_mask = PWR_LED_CTRL;
637 if (!pciehp_poll_mode) {
638 slot_cmd = slot_cmd | HP_INTR_ENABLE;
639 cmd_mask = cmd_mask | HP_INTR_ENABLE;
642 pcie_write_cmd(slot, slot_cmd, cmd_mask);
644 dbg("%s: SLOTCTRL %x write cmd %x\n",
645 __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd);
650 static void hpc_release_ctlr(struct controller *ctrl)
654 if (pciehp_poll_mode)
655 del_timer(&ctrl->poll_timer);
657 free_irq(ctrl->pci_dev->irq, ctrl);
660 * If this is the last controller to be released, destroy the
663 if (atomic_dec_and_test(&pciehp_num_controllers))
664 destroy_workqueue(pciehp_wq);
669 static int hpc_power_on_slot(struct slot * slot)
671 struct controller *ctrl = slot->ctrl;
679 dbg("%s: slot->hp_slot %x\n", __FUNCTION__, slot->hp_slot);
681 /* Clear sticky power-fault bit from previous power failures */
682 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
684 err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__);
687 slot_status &= PWR_FAULT_DETECTED;
689 retval = pciehp_writew(ctrl, SLOTSTATUS, slot_status);
691 err("%s: Cannot write to SLOTSTATUS register\n",
699 /* Enable detection that we turned off at slot power-off time */
700 if (!pciehp_poll_mode) {
701 slot_cmd = slot_cmd |
702 PWR_FAULT_DETECT_ENABLE |
706 cmd_mask = cmd_mask |
707 PWR_FAULT_DETECT_ENABLE |
713 retval = pcie_write_cmd(slot, slot_cmd, cmd_mask);
716 err("%s: Write %x command failed!\n", __FUNCTION__, slot_cmd);
719 dbg("%s: SLOTCTRL %x write cmd %x\n",
720 __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd);
727 static int hpc_power_off_slot(struct slot * slot)
729 struct controller *ctrl = slot->ctrl;
736 dbg("%s: slot->hp_slot %x\n", __FUNCTION__, slot->hp_slot);
738 slot_cmd = POWER_OFF;
741 * If we get MRL or presence detect interrupts now, the isr
742 * will notice the sticky power-fault bit too and issue power
743 * indicator change commands. This will lead to an endless loop
744 * of command completions, since the power-fault bit remains on
745 * till the slot is powered on again.
747 if (!pciehp_poll_mode) {
748 slot_cmd = (slot_cmd &
749 ~PWR_FAULT_DETECT_ENABLE &
751 ~PRSN_DETECT_ENABLE) | HP_INTR_ENABLE;
752 cmd_mask = cmd_mask |
753 PWR_FAULT_DETECT_ENABLE |
759 retval = pcie_write_cmd(slot, slot_cmd, cmd_mask);
761 err("%s: Write command failed!\n", __FUNCTION__);
764 dbg("%s: SLOTCTRL %x write cmd %x\n",
765 __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd);
772 static irqreturn_t pcie_isr(int irq, void *dev_id)
774 struct controller *ctrl = (struct controller *)dev_id;
775 u16 slot_status, intr_detect, intr_loc;
777 int hp_slot = 0; /* only 1 slot per PCI Express port */
781 rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
783 err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__);
787 intr_detect = ( ATTN_BUTTN_PRESSED | PWR_FAULT_DETECTED | MRL_SENS_CHANGED |
788 PRSN_DETECT_CHANGED | CMD_COMPLETED );
790 intr_loc = slot_status & intr_detect;
792 /* Check to see if it was our interrupt */
796 dbg("%s: intr_loc %x\n", __FUNCTION__, intr_loc);
797 /* Mask Hot-plug Interrupt Enable */
798 if (!pciehp_poll_mode) {
799 spin_lock_irqsave(&ctrl->lock, flags);
800 rc = pciehp_readw(ctrl, SLOTCTRL, &temp_word);
802 err("%s: Cannot read SLOT_CTRL register\n",
804 spin_unlock_irqrestore(&ctrl->lock, flags);
808 dbg("%s: pciehp_readw(SLOTCTRL) with value %x\n",
809 __FUNCTION__, temp_word);
810 temp_word = (temp_word & ~HP_INTR_ENABLE & ~CMD_CMPL_INTR_ENABLE) | 0x00;
811 rc = pciehp_writew(ctrl, SLOTCTRL, temp_word);
813 err("%s: Cannot write to SLOTCTRL register\n",
815 spin_unlock_irqrestore(&ctrl->lock, flags);
818 spin_unlock_irqrestore(&ctrl->lock, flags);
820 rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
822 err("%s: Cannot read SLOT_STATUS register\n",
826 dbg("%s: pciehp_readw(SLOTSTATUS) with value %x\n",
827 __FUNCTION__, slot_status);
829 /* Clear command complete interrupt caused by this write */
831 rc = pciehp_writew(ctrl, SLOTSTATUS, temp_word);
833 err("%s: Cannot write to SLOTSTATUS register\n",
839 if (intr_loc & CMD_COMPLETED) {
841 * Command Complete Interrupt Pending
844 wake_up_interruptible(&ctrl->queue);
847 if (intr_loc & MRL_SENS_CHANGED)
848 pciehp_handle_switch_change(hp_slot, ctrl);
850 if (intr_loc & ATTN_BUTTN_PRESSED)
851 pciehp_handle_attention_button(hp_slot, ctrl);
853 if (intr_loc & PRSN_DETECT_CHANGED)
854 pciehp_handle_presence_change(hp_slot, ctrl);
856 if (intr_loc & PWR_FAULT_DETECTED)
857 pciehp_handle_power_fault(hp_slot, ctrl);
859 /* Clear all events after serving them */
861 rc = pciehp_writew(ctrl, SLOTSTATUS, temp_word);
863 err("%s: Cannot write to SLOTSTATUS register\n", __FUNCTION__);
866 /* Unmask Hot-plug Interrupt Enable */
867 if (!pciehp_poll_mode) {
868 spin_lock_irqsave(&ctrl->lock, flags);
869 rc = pciehp_readw(ctrl, SLOTCTRL, &temp_word);
871 err("%s: Cannot read SLOTCTRL register\n",
873 spin_unlock_irqrestore(&ctrl->lock, flags);
877 dbg("%s: Unmask Hot-plug Interrupt Enable\n", __FUNCTION__);
878 temp_word = (temp_word & ~HP_INTR_ENABLE) | HP_INTR_ENABLE;
880 rc = pciehp_writew(ctrl, SLOTCTRL, temp_word);
882 err("%s: Cannot write to SLOTCTRL register\n",
884 spin_unlock_irqrestore(&ctrl->lock, flags);
887 spin_unlock_irqrestore(&ctrl->lock, flags);
889 rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
891 err("%s: Cannot read SLOT_STATUS register\n",
896 /* Clear command complete interrupt caused by this write */
898 rc = pciehp_writew(ctrl, SLOTSTATUS, temp_word);
900 err("%s: Cannot write to SLOTSTATUS failed\n",
904 dbg("%s: pciehp_writew(SLOTSTATUS) with value %x\n",
905 __FUNCTION__, temp_word);
911 static int hpc_get_max_lnk_speed (struct slot *slot, enum pci_bus_speed *value)
913 struct controller *ctrl = slot->ctrl;
914 enum pcie_link_speed lnk_speed;
920 retval = pciehp_readl(ctrl, LNKCAP, &lnk_cap);
922 err("%s: Cannot read LNKCAP register\n", __FUNCTION__);
926 switch (lnk_cap & 0x000F) {
928 lnk_speed = PCIE_2PT5GB;
931 lnk_speed = PCIE_LNK_SPEED_UNKNOWN;
936 dbg("Max link speed = %d\n", lnk_speed);
941 static int hpc_get_max_lnk_width (struct slot *slot, enum pcie_link_width *value)
943 struct controller *ctrl = slot->ctrl;
944 enum pcie_link_width lnk_wdth;
950 retval = pciehp_readl(ctrl, LNKCAP, &lnk_cap);
952 err("%s: Cannot read LNKCAP register\n", __FUNCTION__);
956 switch ((lnk_cap & 0x03F0) >> 4){
958 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
961 lnk_wdth = PCIE_LNK_X1;
964 lnk_wdth = PCIE_LNK_X2;
967 lnk_wdth = PCIE_LNK_X4;
970 lnk_wdth = PCIE_LNK_X8;
973 lnk_wdth = PCIE_LNK_X12;
976 lnk_wdth = PCIE_LNK_X16;
979 lnk_wdth = PCIE_LNK_X32;
982 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
987 dbg("Max link width = %d\n", lnk_wdth);
992 static int hpc_get_cur_lnk_speed (struct slot *slot, enum pci_bus_speed *value)
994 struct controller *ctrl = slot->ctrl;
995 enum pcie_link_speed lnk_speed = PCI_SPEED_UNKNOWN;
1001 retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status);
1003 err("%s: Cannot read LNKSTATUS register\n", __FUNCTION__);
1007 switch (lnk_status & 0x0F) {
1009 lnk_speed = PCIE_2PT5GB;
1012 lnk_speed = PCIE_LNK_SPEED_UNKNOWN;
1017 dbg("Current link speed = %d\n", lnk_speed);
1022 static int hpc_get_cur_lnk_width (struct slot *slot, enum pcie_link_width *value)
1024 struct controller *ctrl = slot->ctrl;
1025 enum pcie_link_width lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
1031 retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status);
1033 err("%s: Cannot read LNKSTATUS register\n", __FUNCTION__);
1037 switch ((lnk_status & 0x03F0) >> 4){
1039 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
1042 lnk_wdth = PCIE_LNK_X1;
1045 lnk_wdth = PCIE_LNK_X2;
1048 lnk_wdth = PCIE_LNK_X4;
1051 lnk_wdth = PCIE_LNK_X8;
1054 lnk_wdth = PCIE_LNK_X12;
1057 lnk_wdth = PCIE_LNK_X16;
1060 lnk_wdth = PCIE_LNK_X32;
1063 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
1068 dbg("Current link width = %d\n", lnk_wdth);
1073 static struct hpc_ops pciehp_hpc_ops = {
1074 .power_on_slot = hpc_power_on_slot,
1075 .power_off_slot = hpc_power_off_slot,
1076 .set_attention_status = hpc_set_attention_status,
1077 .get_power_status = hpc_get_power_status,
1078 .get_attention_status = hpc_get_attention_status,
1079 .get_latch_status = hpc_get_latch_status,
1080 .get_adapter_status = hpc_get_adapter_status,
1081 .get_emi_status = hpc_get_emi_status,
1082 .toggle_emi = hpc_toggle_emi,
1084 .get_max_bus_speed = hpc_get_max_lnk_speed,
1085 .get_cur_bus_speed = hpc_get_cur_lnk_speed,
1086 .get_max_lnk_width = hpc_get_max_lnk_width,
1087 .get_cur_lnk_width = hpc_get_cur_lnk_width,
1089 .query_power_fault = hpc_query_power_fault,
1090 .green_led_on = hpc_set_green_led_on,
1091 .green_led_off = hpc_set_green_led_off,
1092 .green_led_blink = hpc_set_green_led_blink,
1094 .release_ctlr = hpc_release_ctlr,
1095 .check_lnk_status = hpc_check_lnk_status,
1099 int pciehp_acpi_get_hp_hw_control_from_firmware(struct pci_dev *dev)
1102 acpi_handle chandle, handle = DEVICE_ACPI_HANDLE(&(dev->dev));
1103 struct pci_dev *pdev = dev;
1104 struct pci_bus *parent;
1105 struct acpi_buffer string = { ACPI_ALLOCATE_BUFFER, NULL };
1108 * Per PCI firmware specification, we should run the ACPI _OSC
1109 * method to get control of hotplug hardware before using it.
1110 * If an _OSC is missing, we look for an OSHP to do the same thing.
1111 * To handle different BIOS behavior, we look for _OSC and OSHP
1112 * within the scope of the hotplug controller and its parents, upto
1113 * the host bridge under which this controller exists.
1117 * This hotplug controller was not listed in the ACPI name
1118 * space at all. Try to get acpi handle of parent pci bus.
1120 if (!pdev || !pdev->bus->parent)
1122 parent = pdev->bus->parent;
1123 dbg("Could not find %s in acpi namespace, trying parent\n",
1126 /* Parent must be a host bridge */
1127 handle = acpi_get_pci_rootbridge_handle(
1128 pci_domain_nr(parent),
1131 handle = DEVICE_ACPI_HANDLE(
1132 &(parent->self->dev));
1133 pdev = parent->self;
1137 acpi_get_name(handle, ACPI_FULL_PATHNAME, &string);
1138 dbg("Trying to get hotplug control for %s \n",
1139 (char *)string.pointer);
1140 status = pci_osc_control_set(handle,
1141 OSC_PCI_EXPRESS_CAP_STRUCTURE_CONTROL |
1142 OSC_PCI_EXPRESS_NATIVE_HP_CONTROL);
1143 if (status == AE_NOT_FOUND)
1144 status = acpi_run_oshp(handle);
1145 if (ACPI_SUCCESS(status)) {
1146 dbg("Gained control for hotplug HW for pci %s (%s)\n",
1147 pci_name(dev), (char *)string.pointer);
1148 kfree(string.pointer);
1151 if (acpi_root_bridge(handle))
1154 status = acpi_get_parent(chandle, &handle);
1155 if (ACPI_FAILURE(status))
1159 err("Cannot get control of hotplug hardware for pci %s\n",
1162 kfree(string.pointer);
1169 int pcie_init(struct controller * ctrl, struct pcie_device *dev)
1174 u16 intr_enable = 0;
1177 u16 slot_status, slot_ctrl;
1178 struct pci_dev *pdev;
1183 ctrl->pci_dev = pdev; /* save pci_dev in context */
1185 dbg("%s: hotplug controller vendor id 0x%x device id 0x%x\n",
1186 __FUNCTION__, pdev->vendor, pdev->device);
1188 if ((cap_base = pci_find_capability(pdev, PCI_CAP_ID_EXP)) == 0) {
1189 dbg("%s: Can't find PCI_CAP_ID_EXP (0x10)\n", __FUNCTION__);
1190 goto abort_free_ctlr;
1193 ctrl->cap_base = cap_base;
1195 dbg("%s: pcie_cap_base %x\n", __FUNCTION__, cap_base);
1197 rc = pciehp_readw(ctrl, CAPREG, &cap_reg);
1199 err("%s: Cannot read CAPREG register\n", __FUNCTION__);
1200 goto abort_free_ctlr;
1202 dbg("%s: CAPREG offset %x cap_reg %x\n",
1203 __FUNCTION__, ctrl->cap_base + CAPREG, cap_reg);
1205 if (((cap_reg & SLOT_IMPL) == 0) || (((cap_reg & DEV_PORT_TYPE) != 0x0040)
1206 && ((cap_reg & DEV_PORT_TYPE) != 0x0060))) {
1207 dbg("%s : This is not a root port or the port is not connected to a slot\n", __FUNCTION__);
1208 goto abort_free_ctlr;
1211 rc = pciehp_readl(ctrl, SLOTCAP, &slot_cap);
1213 err("%s: Cannot read SLOTCAP register\n", __FUNCTION__);
1214 goto abort_free_ctlr;
1216 dbg("%s: SLOTCAP offset %x slot_cap %x\n",
1217 __FUNCTION__, ctrl->cap_base + SLOTCAP, slot_cap);
1219 if (!(slot_cap & HP_CAP)) {
1220 dbg("%s : This slot is not hot-plug capable\n", __FUNCTION__);
1221 goto abort_free_ctlr;
1223 /* For debugging purpose */
1224 rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
1226 err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__);
1227 goto abort_free_ctlr;
1229 dbg("%s: SLOTSTATUS offset %x slot_status %x\n",
1230 __FUNCTION__, ctrl->cap_base + SLOTSTATUS, slot_status);
1232 rc = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
1234 err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__);
1235 goto abort_free_ctlr;
1237 dbg("%s: SLOTCTRL offset %x slot_ctrl %x\n",
1238 __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_ctrl);
1240 for ( rc = 0; rc < DEVICE_COUNT_RESOURCE; rc++)
1241 if (pci_resource_len(pdev, rc) > 0)
1242 dbg("pci resource[%d] start=0x%llx(len=0x%llx)\n", rc,
1243 (unsigned long long)pci_resource_start(pdev, rc),
1244 (unsigned long long)pci_resource_len(pdev, rc));
1246 info("HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", pdev->vendor, pdev->device,
1247 pdev->subsystem_vendor, pdev->subsystem_device);
1249 mutex_init(&ctrl->crit_sect);
1250 mutex_init(&ctrl->ctrl_lock);
1251 spin_lock_init(&ctrl->lock);
1253 /* setup wait queue */
1254 init_waitqueue_head(&ctrl->queue);
1256 /* return PCI Controller Info */
1257 ctrl->slot_device_offset = 0;
1258 ctrl->num_slots = 1;
1259 ctrl->first_slot = slot_cap >> 19;
1260 ctrl->ctrlcap = slot_cap & 0x0000007f;
1262 /* Mask Hot-plug Interrupt Enable */
1263 rc = pciehp_readw(ctrl, SLOTCTRL, &temp_word);
1265 err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__);
1266 goto abort_free_ctlr;
1269 dbg("%s: SLOTCTRL %x value read %x\n",
1270 __FUNCTION__, ctrl->cap_base + SLOTCTRL, temp_word);
1271 temp_word = (temp_word & ~HP_INTR_ENABLE & ~CMD_CMPL_INTR_ENABLE) | 0x00;
1273 rc = pciehp_writew(ctrl, SLOTCTRL, temp_word);
1275 err("%s: Cannot write to SLOTCTRL register\n", __FUNCTION__);
1276 goto abort_free_ctlr;
1279 rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
1281 err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__);
1282 goto abort_free_ctlr;
1285 temp_word = 0x1F; /* Clear all events */
1286 rc = pciehp_writew(ctrl, SLOTSTATUS, temp_word);
1288 err("%s: Cannot write to SLOTSTATUS register\n", __FUNCTION__);
1289 goto abort_free_ctlr;
1292 if (pciehp_poll_mode) {
1293 /* Install interrupt polling timer. Start with 10 sec delay */
1294 init_timer(&ctrl->poll_timer);
1295 start_int_poll_timer(ctrl, 10);
1297 /* Installs the interrupt handler */
1298 rc = request_irq(ctrl->pci_dev->irq, pcie_isr, IRQF_SHARED,
1299 MY_NAME, (void *)ctrl);
1300 dbg("%s: request_irq %d for hpc%d (returns %d)\n",
1301 __FUNCTION__, ctrl->pci_dev->irq,
1302 atomic_read(&pciehp_num_controllers), rc);
1304 err("Can't get irq %d for the hotplug controller\n",
1305 ctrl->pci_dev->irq);
1306 goto abort_free_ctlr;
1309 dbg("pciehp ctrl b:d:f:irq=0x%x:%x:%x:%x\n", pdev->bus->number,
1310 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), dev->irq);
1313 * If this is the first controller to be initialized,
1314 * initialize the pciehp work queue
1316 if (atomic_add_return(1, &pciehp_num_controllers) == 1) {
1317 pciehp_wq = create_singlethread_workqueue("pciehpd");
1320 goto abort_free_irq;
1324 rc = pciehp_readw(ctrl, SLOTCTRL, &temp_word);
1326 err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__);
1327 goto abort_free_irq;
1330 intr_enable = intr_enable | PRSN_DETECT_ENABLE;
1332 if (ATTN_BUTTN(slot_cap))
1333 intr_enable = intr_enable | ATTN_BUTTN_ENABLE;
1335 if (POWER_CTRL(slot_cap))
1336 intr_enable = intr_enable | PWR_FAULT_DETECT_ENABLE;
1338 if (MRL_SENS(slot_cap))
1339 intr_enable = intr_enable | MRL_DETECT_ENABLE;
1341 temp_word = (temp_word & ~intr_enable) | intr_enable;
1343 if (pciehp_poll_mode) {
1344 temp_word = (temp_word & ~HP_INTR_ENABLE) | 0x0;
1346 temp_word = (temp_word & ~HP_INTR_ENABLE) | HP_INTR_ENABLE;
1349 /* Unmask Hot-plug Interrupt Enable for the interrupt notification mechanism case */
1350 rc = pciehp_writew(ctrl, SLOTCTRL, temp_word);
1352 err("%s: Cannot write to SLOTCTRL register\n", __FUNCTION__);
1353 goto abort_free_irq;
1355 rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
1357 err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__);
1358 goto abort_disable_intr;
1361 temp_word = 0x1F; /* Clear all events */
1362 rc = pciehp_writew(ctrl, SLOTSTATUS, temp_word);
1364 err("%s: Cannot write to SLOTSTATUS register\n", __FUNCTION__);
1365 goto abort_disable_intr;
1369 dbg("Bypassing BIOS check for pciehp use on %s\n",
1370 pci_name(ctrl->pci_dev));
1372 rc = pciehp_get_hp_hw_control_from_firmware(ctrl->pci_dev);
1374 goto abort_disable_intr;
1377 ctrl->hpc_ops = &pciehp_hpc_ops;
1382 /* We end up here for the many possible ways to fail this API. */
1384 rc = pciehp_readw(ctrl, SLOTCTRL, &temp_word);
1386 temp_word &= ~(intr_enable | HP_INTR_ENABLE);
1387 rc = pciehp_writew(ctrl, SLOTCTRL, temp_word);
1390 err("%s : disabling interrupts failed\n", __FUNCTION__);
1393 if (pciehp_poll_mode)
1394 del_timer_sync(&ctrl->poll_timer);
1396 free_irq(ctrl->pci_dev->irq, ctrl);