2 * PCI Express PCI Hot Plug Driver
4 * Copyright (C) 1995,2001 Compaq Computer Corporation
5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
6 * Copyright (C) 2001 IBM Corp.
7 * Copyright (C) 2003-2004 Intel Corporation
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
19 * NON INFRINGEMENT. See the GNU General Public License for more
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/types.h>
33 #include <linux/signal.h>
34 #include <linux/jiffies.h>
35 #include <linux/timer.h>
36 #include <linux/pci.h>
37 #include <linux/interrupt.h>
38 #include <linux/time.h>
39 #include <linux/slab.h>
44 static inline int pciehp_readw(struct controller *ctrl, int reg, u16 *value)
46 struct pci_dev *dev = ctrl->pcie->port;
47 return pci_read_config_word(dev, pci_pcie_cap(dev) + reg, value);
50 static inline int pciehp_readl(struct controller *ctrl, int reg, u32 *value)
52 struct pci_dev *dev = ctrl->pcie->port;
53 return pci_read_config_dword(dev, pci_pcie_cap(dev) + reg, value);
56 static inline int pciehp_writew(struct controller *ctrl, int reg, u16 value)
58 struct pci_dev *dev = ctrl->pcie->port;
59 return pci_write_config_word(dev, pci_pcie_cap(dev) + reg, value);
62 static inline int pciehp_writel(struct controller *ctrl, int reg, u32 value)
64 struct pci_dev *dev = ctrl->pcie->port;
65 return pci_write_config_dword(dev, pci_pcie_cap(dev) + reg, value);
68 /* Power Control Command */
70 #define POWER_OFF PCI_EXP_SLTCTL_PCC
72 static irqreturn_t pcie_isr(int irq, void *dev_id);
73 static void start_int_poll_timer(struct controller *ctrl, int sec);
75 /* This is the interrupt polling timeout function. */
76 static void int_poll_timeout(unsigned long data)
78 struct controller *ctrl = (struct controller *)data;
80 /* Poll for interrupt events. regs == NULL => polling */
83 init_timer(&ctrl->poll_timer);
84 if (!pciehp_poll_time)
85 pciehp_poll_time = 2; /* default polling interval is 2 sec */
87 start_int_poll_timer(ctrl, pciehp_poll_time);
90 /* This function starts the interrupt polling timer. */
91 static void start_int_poll_timer(struct controller *ctrl, int sec)
93 /* Clamp to sane value */
94 if ((sec <= 0) || (sec > 60))
97 ctrl->poll_timer.function = &int_poll_timeout;
98 ctrl->poll_timer.data = (unsigned long)ctrl;
99 ctrl->poll_timer.expires = jiffies + sec * HZ;
100 add_timer(&ctrl->poll_timer);
103 static inline int pciehp_request_irq(struct controller *ctrl)
105 int retval, irq = ctrl->pcie->irq;
107 /* Install interrupt polling timer. Start with 10 sec delay */
108 if (pciehp_poll_mode) {
109 init_timer(&ctrl->poll_timer);
110 start_int_poll_timer(ctrl, 10);
114 /* Installs the interrupt handler */
115 retval = request_irq(irq, pcie_isr, IRQF_SHARED, MY_NAME, ctrl);
117 ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n",
122 static inline void pciehp_free_irq(struct controller *ctrl)
124 if (pciehp_poll_mode)
125 del_timer_sync(&ctrl->poll_timer);
127 free_irq(ctrl->pcie->irq, ctrl);
130 static int pcie_poll_cmd(struct controller *ctrl)
133 int err, timeout = 1000;
135 err = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
136 if (!err && (slot_status & PCI_EXP_SLTSTA_CC)) {
137 pciehp_writew(ctrl, PCI_EXP_SLTSTA, PCI_EXP_SLTSTA_CC);
140 while (timeout > 0) {
143 err = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
144 if (!err && (slot_status & PCI_EXP_SLTSTA_CC)) {
145 pciehp_writew(ctrl, PCI_EXP_SLTSTA, PCI_EXP_SLTSTA_CC);
149 return 0; /* timeout */
152 static void pcie_wait_cmd(struct controller *ctrl, int poll)
154 unsigned int msecs = pciehp_poll_mode ? 2500 : 1000;
155 unsigned long timeout = msecs_to_jiffies(msecs);
159 rc = pcie_poll_cmd(ctrl);
161 rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout);
163 ctrl_dbg(ctrl, "Command not completed in 1000 msec\n");
167 * pcie_write_cmd - Issue controller command
168 * @ctrl: controller to which the command is issued
169 * @cmd: command value written to slot control register
170 * @mask: bitmask of slot control register to be modified
172 static int pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask)
178 mutex_lock(&ctrl->ctrl_lock);
180 retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
182 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
187 if (slot_status & PCI_EXP_SLTSTA_CC) {
188 if (!ctrl->no_cmd_complete) {
190 * After 1 sec and CMD_COMPLETED still not set, just
191 * proceed forward to issue the next command according
192 * to spec. Just print out the error message.
194 ctrl_dbg(ctrl, "CMD_COMPLETED not clear after 1 sec\n");
195 } else if (!NO_CMD_CMPL(ctrl)) {
197 * This controller semms to notify of command completed
198 * event even though it supports none of power
199 * controller, attention led, power led and EMI.
201 ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Need to "
202 "wait for command completed event.\n");
203 ctrl->no_cmd_complete = 0;
205 ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Maybe "
206 "the controller is broken.\n");
210 retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl);
212 ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__);
217 slot_ctrl |= (cmd & mask);
220 retval = pciehp_writew(ctrl, PCI_EXP_SLTCTL, slot_ctrl);
222 ctrl_err(ctrl, "Cannot write to SLOTCTRL register\n");
225 * Wait for command completion.
227 if (!retval && !ctrl->no_cmd_complete) {
230 * if hotplug interrupt is not enabled or command
231 * completed interrupt is not enabled, we need to poll
232 * command completed event.
234 if (!(slot_ctrl & PCI_EXP_SLTCTL_HPIE) ||
235 !(slot_ctrl & PCI_EXP_SLTCTL_CCIE))
237 pcie_wait_cmd(ctrl, poll);
240 mutex_unlock(&ctrl->ctrl_lock);
244 static inline int check_link_active(struct controller *ctrl)
248 if (pciehp_readw(ctrl, PCI_EXP_LNKSTA, &link_status))
250 return !!(link_status & PCI_EXP_LNKSTA_DLLLA);
253 static void pcie_wait_link_active(struct controller *ctrl)
257 if (check_link_active(ctrl))
259 while (timeout > 0) {
262 if (check_link_active(ctrl))
265 ctrl_dbg(ctrl, "Data Link Layer Link Active not set in 1000 msec\n");
268 int pciehp_check_link_status(struct controller *ctrl)
274 * Data Link Layer Link Active Reporting must be capable for
275 * hot-plug capable downstream port. But old controller might
276 * not implement it. In this case, we wait for 1000 ms.
278 if (ctrl->link_active_reporting)
279 pcie_wait_link_active(ctrl);
283 retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status);
285 ctrl_err(ctrl, "Cannot read LNKSTATUS register\n");
289 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
290 if ((lnk_status & PCI_EXP_LNKSTA_LT) ||
291 !(lnk_status & PCI_EXP_LNKSTA_NLW)) {
292 ctrl_err(ctrl, "Link Training Error occurs \n");
300 int pciehp_get_attention_status(struct slot *slot, u8 *status)
302 struct controller *ctrl = slot->ctrl;
307 retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl);
309 ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__);
313 ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", __func__,
314 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
316 atten_led_state = (slot_ctrl & PCI_EXP_SLTCTL_AIC) >> 6;
318 switch (atten_led_state) {
320 *status = 0xFF; /* Reserved */
323 *status = 1; /* On */
326 *status = 2; /* Blink */
329 *status = 0; /* Off */
339 int pciehp_get_power_status(struct slot *slot, u8 *status)
341 struct controller *ctrl = slot->ctrl;
346 retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl);
348 ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__);
351 ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", __func__,
352 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
354 pwr_state = (slot_ctrl & PCI_EXP_SLTCTL_PCC) >> 10;
371 int pciehp_get_latch_status(struct slot *slot, u8 *status)
373 struct controller *ctrl = slot->ctrl;
377 retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
379 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
383 *status = !!(slot_status & PCI_EXP_SLTSTA_MRLSS);
387 int pciehp_get_adapter_status(struct slot *slot, u8 *status)
389 struct controller *ctrl = slot->ctrl;
393 retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
395 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
399 *status = !!(slot_status & PCI_EXP_SLTSTA_PDS);
403 int pciehp_query_power_fault(struct slot *slot)
405 struct controller *ctrl = slot->ctrl;
409 retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
411 ctrl_err(ctrl, "Cannot check for power fault\n");
414 return !!(slot_status & PCI_EXP_SLTSTA_PFD);
417 int pciehp_set_attention_status(struct slot *slot, u8 value)
419 struct controller *ctrl = slot->ctrl;
423 cmd_mask = PCI_EXP_SLTCTL_AIC;
425 case 0 : /* turn off */
428 case 1: /* turn on */
431 case 2: /* turn blink */
437 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
438 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
439 return pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
442 void pciehp_green_led_on(struct slot *slot)
444 struct controller *ctrl = slot->ctrl;
449 cmd_mask = PCI_EXP_SLTCTL_PIC;
450 pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
451 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
452 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
455 void pciehp_green_led_off(struct slot *slot)
457 struct controller *ctrl = slot->ctrl;
462 cmd_mask = PCI_EXP_SLTCTL_PIC;
463 pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
464 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
465 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
468 void pciehp_green_led_blink(struct slot *slot)
470 struct controller *ctrl = slot->ctrl;
475 cmd_mask = PCI_EXP_SLTCTL_PIC;
476 pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
477 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
478 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
481 int pciehp_power_on_slot(struct slot * slot)
483 struct controller *ctrl = slot->ctrl;
490 /* Clear sticky power-fault bit from previous power failures */
491 retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status);
493 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n",
497 slot_status &= PCI_EXP_SLTSTA_PFD;
499 retval = pciehp_writew(ctrl, PCI_EXP_SLTSTA, slot_status);
502 "%s: Cannot write to SLOTSTATUS register\n",
507 ctrl->power_fault_detected = 0;
510 cmd_mask = PCI_EXP_SLTCTL_PCC;
511 retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
513 ctrl_err(ctrl, "Write %x command failed!\n", slot_cmd);
516 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
517 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
519 retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status);
521 ctrl_err(ctrl, "%s: Cannot read LNKSTA register\n",
525 pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status);
530 int pciehp_power_off_slot(struct slot * slot)
532 struct controller *ctrl = slot->ctrl;
537 slot_cmd = POWER_OFF;
538 cmd_mask = PCI_EXP_SLTCTL_PCC;
539 retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
541 ctrl_err(ctrl, "Write command failed!\n");
544 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
545 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
549 static irqreturn_t pcie_isr(int irq, void *dev_id)
551 struct controller *ctrl = (struct controller *)dev_id;
552 struct slot *slot = ctrl->slot;
553 u16 detected, intr_loc;
556 * In order to guarantee that all interrupt events are
557 * serviced, we need to re-inspect Slot Status register after
558 * clearing what is presumed to be the last pending interrupt.
562 if (pciehp_readw(ctrl, PCI_EXP_SLTSTA, &detected)) {
563 ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS\n",
568 detected &= (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
569 PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC |
571 detected &= ~intr_loc;
572 intr_loc |= detected;
575 if (detected && pciehp_writew(ctrl, PCI_EXP_SLTSTA, intr_loc)) {
576 ctrl_err(ctrl, "%s: Cannot write to SLOTSTATUS\n",
582 ctrl_dbg(ctrl, "%s: intr_loc %x\n", __func__, intr_loc);
584 /* Check Command Complete Interrupt Pending */
585 if (intr_loc & PCI_EXP_SLTSTA_CC) {
588 wake_up(&ctrl->queue);
591 if (!(intr_loc & ~PCI_EXP_SLTSTA_CC))
594 /* Check MRL Sensor Changed */
595 if (intr_loc & PCI_EXP_SLTSTA_MRLSC)
596 pciehp_handle_switch_change(slot);
598 /* Check Attention Button Pressed */
599 if (intr_loc & PCI_EXP_SLTSTA_ABP)
600 pciehp_handle_attention_button(slot);
602 /* Check Presence Detect Changed */
603 if (intr_loc & PCI_EXP_SLTSTA_PDC)
604 pciehp_handle_presence_change(slot);
606 /* Check Power Fault Detected */
607 if ((intr_loc & PCI_EXP_SLTSTA_PFD) && !ctrl->power_fault_detected) {
608 ctrl->power_fault_detected = 1;
609 pciehp_handle_power_fault(slot);
614 int pciehp_get_max_lnk_width(struct slot *slot,
615 enum pcie_link_width *value)
617 struct controller *ctrl = slot->ctrl;
618 enum pcie_link_width lnk_wdth;
622 retval = pciehp_readl(ctrl, PCI_EXP_LNKCAP, &lnk_cap);
624 ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__);
628 switch ((lnk_cap & PCI_EXP_LNKSTA_NLW) >> 4){
630 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
633 lnk_wdth = PCIE_LNK_X1;
636 lnk_wdth = PCIE_LNK_X2;
639 lnk_wdth = PCIE_LNK_X4;
642 lnk_wdth = PCIE_LNK_X8;
645 lnk_wdth = PCIE_LNK_X12;
648 lnk_wdth = PCIE_LNK_X16;
651 lnk_wdth = PCIE_LNK_X32;
654 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
659 ctrl_dbg(ctrl, "Max link width = %d\n", lnk_wdth);
664 int pciehp_get_cur_lnk_width(struct slot *slot,
665 enum pcie_link_width *value)
667 struct controller *ctrl = slot->ctrl;
668 enum pcie_link_width lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
672 retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status);
674 ctrl_err(ctrl, "%s: Cannot read LNKSTATUS register\n",
679 switch ((lnk_status & PCI_EXP_LNKSTA_NLW) >> 4){
681 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
684 lnk_wdth = PCIE_LNK_X1;
687 lnk_wdth = PCIE_LNK_X2;
690 lnk_wdth = PCIE_LNK_X4;
693 lnk_wdth = PCIE_LNK_X8;
696 lnk_wdth = PCIE_LNK_X12;
699 lnk_wdth = PCIE_LNK_X16;
702 lnk_wdth = PCIE_LNK_X32;
705 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
710 ctrl_dbg(ctrl, "Current link width = %d\n", lnk_wdth);
715 int pcie_enable_notification(struct controller *ctrl)
720 * TBD: Power fault detected software notification support.
722 * Power fault detected software notification is not enabled
723 * now, because it caused power fault detected interrupt storm
724 * on some machines. On those machines, power fault detected
725 * bit in the slot status register was set again immediately
726 * when it is cleared in the interrupt service routine, and
727 * next power fault detected interrupt was notified again.
729 cmd = PCI_EXP_SLTCTL_PDCE;
730 if (ATTN_BUTTN(ctrl))
731 cmd |= PCI_EXP_SLTCTL_ABPE;
733 cmd |= PCI_EXP_SLTCTL_MRLSCE;
734 if (!pciehp_poll_mode)
735 cmd |= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE;
737 mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
738 PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE |
739 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE);
741 if (pcie_write_cmd(ctrl, cmd, mask)) {
742 ctrl_err(ctrl, "Cannot enable software notification\n");
748 static void pcie_disable_notification(struct controller *ctrl)
751 mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
752 PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE |
753 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE |
754 PCI_EXP_SLTCTL_DLLSCE);
755 if (pcie_write_cmd(ctrl, 0, mask))
756 ctrl_warn(ctrl, "Cannot disable software notification\n");
759 int pcie_init_notification(struct controller *ctrl)
761 if (pciehp_request_irq(ctrl))
763 if (pcie_enable_notification(ctrl)) {
764 pciehp_free_irq(ctrl);
767 ctrl->notification_enabled = 1;
771 static void pcie_shutdown_notification(struct controller *ctrl)
773 if (ctrl->notification_enabled) {
774 pcie_disable_notification(ctrl);
775 pciehp_free_irq(ctrl);
776 ctrl->notification_enabled = 0;
780 static int pcie_init_slot(struct controller *ctrl)
784 slot = kzalloc(sizeof(*slot), GFP_KERNEL);
789 mutex_init(&slot->lock);
790 INIT_DELAYED_WORK(&slot->work, pciehp_queue_pushbutton_work);
795 static void pcie_cleanup_slot(struct controller *ctrl)
797 struct slot *slot = ctrl->slot;
798 cancel_delayed_work(&slot->work);
799 flush_workqueue(pciehp_wq);
800 flush_workqueue(pciehp_ordered_wq);
804 static inline void dbg_ctrl(struct controller *ctrl)
808 struct pci_dev *pdev = ctrl->pcie->port;
813 ctrl_info(ctrl, "Hotplug Controller:\n");
814 ctrl_info(ctrl, " Seg/Bus/Dev/Func/IRQ : %s IRQ %d\n",
815 pci_name(pdev), pdev->irq);
816 ctrl_info(ctrl, " Vendor ID : 0x%04x\n", pdev->vendor);
817 ctrl_info(ctrl, " Device ID : 0x%04x\n", pdev->device);
818 ctrl_info(ctrl, " Subsystem ID : 0x%04x\n",
819 pdev->subsystem_device);
820 ctrl_info(ctrl, " Subsystem Vendor ID : 0x%04x\n",
821 pdev->subsystem_vendor);
822 ctrl_info(ctrl, " PCIe Cap offset : 0x%02x\n",
824 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
825 if (!pci_resource_len(pdev, i))
827 ctrl_info(ctrl, " PCI resource [%d] : %pR\n",
828 i, &pdev->resource[i]);
830 ctrl_info(ctrl, "Slot Capabilities : 0x%08x\n", ctrl->slot_cap);
831 ctrl_info(ctrl, " Physical Slot Number : %d\n", PSN(ctrl));
832 ctrl_info(ctrl, " Attention Button : %3s\n",
833 ATTN_BUTTN(ctrl) ? "yes" : "no");
834 ctrl_info(ctrl, " Power Controller : %3s\n",
835 POWER_CTRL(ctrl) ? "yes" : "no");
836 ctrl_info(ctrl, " MRL Sensor : %3s\n",
837 MRL_SENS(ctrl) ? "yes" : "no");
838 ctrl_info(ctrl, " Attention Indicator : %3s\n",
839 ATTN_LED(ctrl) ? "yes" : "no");
840 ctrl_info(ctrl, " Power Indicator : %3s\n",
841 PWR_LED(ctrl) ? "yes" : "no");
842 ctrl_info(ctrl, " Hot-Plug Surprise : %3s\n",
843 HP_SUPR_RM(ctrl) ? "yes" : "no");
844 ctrl_info(ctrl, " EMI Present : %3s\n",
845 EMI(ctrl) ? "yes" : "no");
846 ctrl_info(ctrl, " Command Completed : %3s\n",
847 NO_CMD_CMPL(ctrl) ? "no" : "yes");
848 pciehp_readw(ctrl, PCI_EXP_SLTSTA, ®16);
849 ctrl_info(ctrl, "Slot Status : 0x%04x\n", reg16);
850 pciehp_readw(ctrl, PCI_EXP_SLTCTL, ®16);
851 ctrl_info(ctrl, "Slot Control : 0x%04x\n", reg16);
854 struct controller *pcie_init(struct pcie_device *dev)
856 struct controller *ctrl;
857 u32 slot_cap, link_cap;
858 struct pci_dev *pdev = dev->port;
860 ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
862 dev_err(&dev->device, "%s: Out of memory\n", __func__);
866 if (!pci_pcie_cap(pdev)) {
867 ctrl_err(ctrl, "Cannot find PCI Express capability\n");
870 if (pciehp_readl(ctrl, PCI_EXP_SLTCAP, &slot_cap)) {
871 ctrl_err(ctrl, "Cannot read SLOTCAP register\n");
875 ctrl->slot_cap = slot_cap;
876 mutex_init(&ctrl->ctrl_lock);
877 init_waitqueue_head(&ctrl->queue);
880 * Controller doesn't notify of command completion if the "No
881 * Command Completed Support" bit is set in Slot Capability
882 * register or the controller supports none of power
883 * controller, attention led, power led and EMI.
885 if (NO_CMD_CMPL(ctrl) ||
886 !(POWER_CTRL(ctrl) | ATTN_LED(ctrl) | PWR_LED(ctrl) | EMI(ctrl)))
887 ctrl->no_cmd_complete = 1;
889 /* Check if Data Link Layer Link Active Reporting is implemented */
890 if (pciehp_readl(ctrl, PCI_EXP_LNKCAP, &link_cap)) {
891 ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__);
894 if (link_cap & PCI_EXP_LNKCAP_DLLLARC) {
895 ctrl_dbg(ctrl, "Link Active Reporting supported\n");
896 ctrl->link_active_reporting = 1;
899 /* Clear all remaining event bits in Slot Status register */
900 if (pciehp_writew(ctrl, PCI_EXP_SLTSTA, 0x1f))
903 /* Disable sotfware notification */
904 pcie_disable_notification(ctrl);
906 ctrl_info(ctrl, "HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n",
907 pdev->vendor, pdev->device, pdev->subsystem_vendor,
908 pdev->subsystem_device);
910 if (pcie_init_slot(ctrl))
921 void pciehp_release_ctrl(struct controller *ctrl)
923 pcie_shutdown_notification(ctrl);
924 pcie_cleanup_slot(ctrl);