2 * PCI Express PCI Hot Plug Driver
4 * Copyright (C) 1995,2001 Compaq Computer Corporation
5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
6 * Copyright (C) 2001 IBM Corp.
7 * Copyright (C) 2003-2004 Intel Corporation
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
19 * NON INFRINGEMENT. See the GNU General Public License for more
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/types.h>
33 #include <linux/signal.h>
34 #include <linux/jiffies.h>
35 #include <linux/timer.h>
36 #include <linux/pci.h>
37 #include <linux/interrupt.h>
38 #include <linux/time.h>
39 #include <linux/slab.h>
44 static inline struct pci_dev *ctrl_dev(struct controller *ctrl)
46 return ctrl->pcie->port;
49 static irqreturn_t pcie_isr(int irq, void *dev_id);
50 static void start_int_poll_timer(struct controller *ctrl, int sec);
52 /* This is the interrupt polling timeout function. */
53 static void int_poll_timeout(unsigned long data)
55 struct controller *ctrl = (struct controller *)data;
57 /* Poll for interrupt events. regs == NULL => polling */
60 init_timer(&ctrl->poll_timer);
61 if (!pciehp_poll_time)
62 pciehp_poll_time = 2; /* default polling interval is 2 sec */
64 start_int_poll_timer(ctrl, pciehp_poll_time);
67 /* This function starts the interrupt polling timer. */
68 static void start_int_poll_timer(struct controller *ctrl, int sec)
70 /* Clamp to sane value */
71 if ((sec <= 0) || (sec > 60))
74 ctrl->poll_timer.function = &int_poll_timeout;
75 ctrl->poll_timer.data = (unsigned long)ctrl;
76 ctrl->poll_timer.expires = jiffies + sec * HZ;
77 add_timer(&ctrl->poll_timer);
80 static inline int pciehp_request_irq(struct controller *ctrl)
82 int retval, irq = ctrl->pcie->irq;
84 /* Install interrupt polling timer. Start with 10 sec delay */
85 if (pciehp_poll_mode) {
86 init_timer(&ctrl->poll_timer);
87 start_int_poll_timer(ctrl, 10);
91 /* Installs the interrupt handler */
92 retval = request_irq(irq, pcie_isr, IRQF_SHARED, MY_NAME, ctrl);
94 ctrl_err(ctrl, "Cannot get irq %d for the hotplug controller\n",
99 static inline void pciehp_free_irq(struct controller *ctrl)
101 if (pciehp_poll_mode)
102 del_timer_sync(&ctrl->poll_timer);
104 free_irq(ctrl->pcie->irq, ctrl);
107 static int pcie_poll_cmd(struct controller *ctrl)
109 struct pci_dev *pdev = ctrl_dev(ctrl);
113 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
114 if (slot_status & PCI_EXP_SLTSTA_CC) {
115 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
119 while (timeout > 0) {
122 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
123 if (slot_status & PCI_EXP_SLTSTA_CC) {
124 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
129 return 0; /* timeout */
132 static void pcie_wait_cmd(struct controller *ctrl, int poll)
134 unsigned int msecs = pciehp_poll_mode ? 2500 : 1000;
135 unsigned long timeout = msecs_to_jiffies(msecs);
139 rc = pcie_poll_cmd(ctrl);
141 rc = wait_event_timeout(ctrl->queue, !ctrl->cmd_busy, timeout);
143 ctrl_dbg(ctrl, "Command not completed in 1000 msec\n");
147 * pcie_write_cmd - Issue controller command
148 * @ctrl: controller to which the command is issued
149 * @cmd: command value written to slot control register
150 * @mask: bitmask of slot control register to be modified
152 static void pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask)
154 struct pci_dev *pdev = ctrl_dev(ctrl);
158 mutex_lock(&ctrl->ctrl_lock);
160 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
161 if (slot_status & PCI_EXP_SLTSTA_CC) {
162 if (!ctrl->no_cmd_complete) {
164 * After 1 sec and CMD_COMPLETED still not set, just
165 * proceed forward to issue the next command according
166 * to spec. Just print out the error message.
168 ctrl_dbg(ctrl, "CMD_COMPLETED not clear after 1 sec\n");
169 } else if (!NO_CMD_CMPL(ctrl)) {
171 * This controller seems to notify of command completed
172 * event even though it supports none of power
173 * controller, attention led, power led and EMI.
175 ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Need to "
176 "wait for command completed event.\n");
177 ctrl->no_cmd_complete = 0;
179 ctrl_dbg(ctrl, "Unexpected CMD_COMPLETED. Maybe "
180 "the controller is broken.\n");
184 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
186 slot_ctrl |= (cmd & mask);
189 pcie_capability_write_word(pdev, PCI_EXP_SLTCTL, slot_ctrl);
192 * Wait for command completion.
194 if (!ctrl->no_cmd_complete) {
197 * if hotplug interrupt is not enabled or command
198 * completed interrupt is not enabled, we need to poll
199 * command completed event.
201 if (!(slot_ctrl & PCI_EXP_SLTCTL_HPIE) ||
202 !(slot_ctrl & PCI_EXP_SLTCTL_CCIE))
204 pcie_wait_cmd(ctrl, poll);
206 mutex_unlock(&ctrl->ctrl_lock);
209 static bool check_link_active(struct controller *ctrl)
211 struct pci_dev *pdev = ctrl_dev(ctrl);
215 pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
216 ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA);
219 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
224 static void __pcie_wait_link_active(struct controller *ctrl, bool active)
228 if (check_link_active(ctrl) == active)
230 while (timeout > 0) {
233 if (check_link_active(ctrl) == active)
236 ctrl_dbg(ctrl, "Data Link Layer Link Active not %s in 1000 msec\n",
237 active ? "set" : "cleared");
240 static void pcie_wait_link_active(struct controller *ctrl)
242 __pcie_wait_link_active(ctrl, true);
245 static void pcie_wait_link_not_active(struct controller *ctrl)
247 __pcie_wait_link_active(ctrl, false);
250 static bool pci_bus_check_dev(struct pci_bus *bus, int devfn)
254 int delay = 1000, step = 20;
258 found = pci_bus_read_dev_vendor_id(bus, devfn, &l, 0);
268 if (count > 1 && pciehp_debug)
269 printk(KERN_DEBUG "pci %04x:%02x:%02x.%d id reading try %d times with interval %d ms to get %08x\n",
270 pci_domain_nr(bus), bus->number, PCI_SLOT(devfn),
271 PCI_FUNC(devfn), count, step, l);
276 int pciehp_check_link_status(struct controller *ctrl)
278 struct pci_dev *pdev = ctrl_dev(ctrl);
283 * Data Link Layer Link Active Reporting must be capable for
284 * hot-plug capable downstream port. But old controller might
285 * not implement it. In this case, we wait for 1000 ms.
287 if (ctrl->link_active_reporting)
288 pcie_wait_link_active(ctrl);
292 /* wait 100ms before read pci conf, and try in 1s */
294 found = pci_bus_check_dev(ctrl->pcie->port->subordinate,
297 pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
298 ctrl_dbg(ctrl, "%s: lnk_status = %x\n", __func__, lnk_status);
299 if ((lnk_status & PCI_EXP_LNKSTA_LT) ||
300 !(lnk_status & PCI_EXP_LNKSTA_NLW)) {
301 ctrl_err(ctrl, "Link Training Error occurs \n");
305 pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status);
313 static int __pciehp_link_set(struct controller *ctrl, bool enable)
315 struct pci_dev *pdev = ctrl_dev(ctrl);
318 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &lnk_ctrl);
321 lnk_ctrl &= ~PCI_EXP_LNKCTL_LD;
323 lnk_ctrl |= PCI_EXP_LNKCTL_LD;
325 pcie_capability_write_word(pdev, PCI_EXP_LNKCTL, lnk_ctrl);
326 ctrl_dbg(ctrl, "%s: lnk_ctrl = %x\n", __func__, lnk_ctrl);
330 static int pciehp_link_enable(struct controller *ctrl)
332 return __pciehp_link_set(ctrl, true);
335 static int pciehp_link_disable(struct controller *ctrl)
337 return __pciehp_link_set(ctrl, false);
340 void pciehp_get_attention_status(struct slot *slot, u8 *status)
342 struct controller *ctrl = slot->ctrl;
343 struct pci_dev *pdev = ctrl_dev(ctrl);
346 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
347 ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", __func__,
348 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
350 switch (slot_ctrl & PCI_EXP_SLTCTL_AIC) {
351 case PCI_EXP_SLTCTL_ATTN_IND_ON:
352 *status = 1; /* On */
354 case PCI_EXP_SLTCTL_ATTN_IND_BLINK:
355 *status = 2; /* Blink */
357 case PCI_EXP_SLTCTL_ATTN_IND_OFF:
358 *status = 0; /* Off */
366 void pciehp_get_power_status(struct slot *slot, u8 *status)
368 struct controller *ctrl = slot->ctrl;
369 struct pci_dev *pdev = ctrl_dev(ctrl);
372 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
373 ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", __func__,
374 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_ctrl);
376 switch (slot_ctrl & PCI_EXP_SLTCTL_PCC) {
377 case PCI_EXP_SLTCTL_PWR_ON:
378 *status = 1; /* On */
380 case PCI_EXP_SLTCTL_PWR_OFF:
381 *status = 0; /* Off */
389 void pciehp_get_latch_status(struct slot *slot, u8 *status)
391 struct pci_dev *pdev = ctrl_dev(slot->ctrl);
394 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
395 *status = !!(slot_status & PCI_EXP_SLTSTA_MRLSS);
398 void pciehp_get_adapter_status(struct slot *slot, u8 *status)
400 struct pci_dev *pdev = ctrl_dev(slot->ctrl);
403 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
404 *status = !!(slot_status & PCI_EXP_SLTSTA_PDS);
407 int pciehp_query_power_fault(struct slot *slot)
409 struct pci_dev *pdev = ctrl_dev(slot->ctrl);
412 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
413 return !!(slot_status & PCI_EXP_SLTSTA_PFD);
416 void pciehp_set_attention_status(struct slot *slot, u8 value)
418 struct controller *ctrl = slot->ctrl;
422 case 0 : /* turn off */
423 slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_OFF;
425 case 1: /* turn on */
426 slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_ON;
428 case 2: /* turn blink */
429 slot_cmd = PCI_EXP_SLTCTL_ATTN_IND_BLINK;
434 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
435 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
436 pcie_write_cmd(ctrl, slot_cmd, PCI_EXP_SLTCTL_AIC);
439 void pciehp_green_led_on(struct slot *slot)
441 struct controller *ctrl = slot->ctrl;
443 pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_IND_ON, PCI_EXP_SLTCTL_PIC);
444 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
445 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
446 PCI_EXP_SLTCTL_PWR_IND_ON);
449 void pciehp_green_led_off(struct slot *slot)
451 struct controller *ctrl = slot->ctrl;
453 pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_IND_OFF, PCI_EXP_SLTCTL_PIC);
454 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
455 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
456 PCI_EXP_SLTCTL_PWR_IND_OFF);
459 void pciehp_green_led_blink(struct slot *slot)
461 struct controller *ctrl = slot->ctrl;
463 pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_IND_BLINK, PCI_EXP_SLTCTL_PIC);
464 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
465 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
466 PCI_EXP_SLTCTL_PWR_IND_BLINK);
469 int pciehp_power_on_slot(struct slot * slot)
471 struct controller *ctrl = slot->ctrl;
472 struct pci_dev *pdev = ctrl_dev(ctrl);
476 /* Clear sticky power-fault bit from previous power failures */
477 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
478 if (slot_status & PCI_EXP_SLTSTA_PFD)
479 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
481 ctrl->power_fault_detected = 0;
483 pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_ON, PCI_EXP_SLTCTL_PCC);
484 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
485 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
486 PCI_EXP_SLTCTL_PWR_ON);
488 retval = pciehp_link_enable(ctrl);
490 ctrl_err(ctrl, "%s: Can not enable the link!\n", __func__);
495 void pciehp_power_off_slot(struct slot * slot)
497 struct controller *ctrl = slot->ctrl;
499 /* Disable the link at first */
500 pciehp_link_disable(ctrl);
501 /* wait the link is down */
502 if (ctrl->link_active_reporting)
503 pcie_wait_link_not_active(ctrl);
507 pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_OFF, PCI_EXP_SLTCTL_PCC);
508 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
509 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
510 PCI_EXP_SLTCTL_PWR_OFF);
513 static irqreturn_t pcie_isr(int irq, void *dev_id)
515 struct controller *ctrl = (struct controller *)dev_id;
516 struct pci_dev *pdev = ctrl_dev(ctrl);
517 struct slot *slot = ctrl->slot;
518 u16 detected, intr_loc;
521 * In order to guarantee that all interrupt events are
522 * serviced, we need to re-inspect Slot Status register after
523 * clearing what is presumed to be the last pending interrupt.
527 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &detected);
529 detected &= (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
530 PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC |
532 detected &= ~intr_loc;
533 intr_loc |= detected;
537 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
541 ctrl_dbg(ctrl, "%s: intr_loc %x\n", __func__, intr_loc);
543 /* Check Command Complete Interrupt Pending */
544 if (intr_loc & PCI_EXP_SLTSTA_CC) {
547 wake_up(&ctrl->queue);
550 if (!(intr_loc & ~PCI_EXP_SLTSTA_CC))
553 /* Check MRL Sensor Changed */
554 if (intr_loc & PCI_EXP_SLTSTA_MRLSC)
555 pciehp_handle_switch_change(slot);
557 /* Check Attention Button Pressed */
558 if (intr_loc & PCI_EXP_SLTSTA_ABP)
559 pciehp_handle_attention_button(slot);
561 /* Check Presence Detect Changed */
562 if (intr_loc & PCI_EXP_SLTSTA_PDC)
563 pciehp_handle_presence_change(slot);
565 /* Check Power Fault Detected */
566 if ((intr_loc & PCI_EXP_SLTSTA_PFD) && !ctrl->power_fault_detected) {
567 ctrl->power_fault_detected = 1;
568 pciehp_handle_power_fault(slot);
573 void pcie_enable_notification(struct controller *ctrl)
578 * TBD: Power fault detected software notification support.
580 * Power fault detected software notification is not enabled
581 * now, because it caused power fault detected interrupt storm
582 * on some machines. On those machines, power fault detected
583 * bit in the slot status register was set again immediately
584 * when it is cleared in the interrupt service routine, and
585 * next power fault detected interrupt was notified again.
587 cmd = PCI_EXP_SLTCTL_PDCE;
588 if (ATTN_BUTTN(ctrl))
589 cmd |= PCI_EXP_SLTCTL_ABPE;
591 cmd |= PCI_EXP_SLTCTL_MRLSCE;
592 if (!pciehp_poll_mode)
593 cmd |= PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE;
595 mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
596 PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE |
597 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE);
599 pcie_write_cmd(ctrl, cmd, mask);
602 static void pcie_disable_notification(struct controller *ctrl)
606 mask = (PCI_EXP_SLTCTL_PDCE | PCI_EXP_SLTCTL_ABPE |
607 PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE |
608 PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE |
609 PCI_EXP_SLTCTL_DLLSCE);
610 pcie_write_cmd(ctrl, 0, mask);
614 * pciehp has a 1:1 bus:slot relationship so we ultimately want a secondary
615 * bus reset of the bridge, but if the slot supports surprise removal we need
616 * to disable presence detection around the bus reset and clear any spurious
619 int pciehp_reset_slot(struct slot *slot, int probe)
621 struct controller *ctrl = slot->ctrl;
622 struct pci_dev *pdev = ctrl_dev(ctrl);
627 if (HP_SUPR_RM(ctrl)) {
628 pcie_write_cmd(ctrl, 0, PCI_EXP_SLTCTL_PDCE);
629 if (pciehp_poll_mode)
630 del_timer_sync(&ctrl->poll_timer);
633 pci_reset_bridge_secondary_bus(ctrl->pcie->port);
635 if (HP_SUPR_RM(ctrl)) {
636 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
638 pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PDCE, PCI_EXP_SLTCTL_PDCE);
639 if (pciehp_poll_mode)
640 int_poll_timeout(ctrl->poll_timer.data);
646 int pcie_init_notification(struct controller *ctrl)
648 if (pciehp_request_irq(ctrl))
650 pcie_enable_notification(ctrl);
651 ctrl->notification_enabled = 1;
655 static void pcie_shutdown_notification(struct controller *ctrl)
657 if (ctrl->notification_enabled) {
658 pcie_disable_notification(ctrl);
659 pciehp_free_irq(ctrl);
660 ctrl->notification_enabled = 0;
664 static int pcie_init_slot(struct controller *ctrl)
668 slot = kzalloc(sizeof(*slot), GFP_KERNEL);
672 slot->wq = alloc_workqueue("pciehp-%u", 0, 0, PSN(ctrl));
677 mutex_init(&slot->lock);
678 INIT_DELAYED_WORK(&slot->work, pciehp_queue_pushbutton_work);
686 static void pcie_cleanup_slot(struct controller *ctrl)
688 struct slot *slot = ctrl->slot;
689 cancel_delayed_work(&slot->work);
690 destroy_workqueue(slot->wq);
694 static inline void dbg_ctrl(struct controller *ctrl)
698 struct pci_dev *pdev = ctrl->pcie->port;
703 ctrl_info(ctrl, "Hotplug Controller:\n");
704 ctrl_info(ctrl, " Seg/Bus/Dev/Func/IRQ : %s IRQ %d\n",
705 pci_name(pdev), pdev->irq);
706 ctrl_info(ctrl, " Vendor ID : 0x%04x\n", pdev->vendor);
707 ctrl_info(ctrl, " Device ID : 0x%04x\n", pdev->device);
708 ctrl_info(ctrl, " Subsystem ID : 0x%04x\n",
709 pdev->subsystem_device);
710 ctrl_info(ctrl, " Subsystem Vendor ID : 0x%04x\n",
711 pdev->subsystem_vendor);
712 ctrl_info(ctrl, " PCIe Cap offset : 0x%02x\n",
714 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
715 if (!pci_resource_len(pdev, i))
717 ctrl_info(ctrl, " PCI resource [%d] : %pR\n",
718 i, &pdev->resource[i]);
720 ctrl_info(ctrl, "Slot Capabilities : 0x%08x\n", ctrl->slot_cap);
721 ctrl_info(ctrl, " Physical Slot Number : %d\n", PSN(ctrl));
722 ctrl_info(ctrl, " Attention Button : %3s\n",
723 ATTN_BUTTN(ctrl) ? "yes" : "no");
724 ctrl_info(ctrl, " Power Controller : %3s\n",
725 POWER_CTRL(ctrl) ? "yes" : "no");
726 ctrl_info(ctrl, " MRL Sensor : %3s\n",
727 MRL_SENS(ctrl) ? "yes" : "no");
728 ctrl_info(ctrl, " Attention Indicator : %3s\n",
729 ATTN_LED(ctrl) ? "yes" : "no");
730 ctrl_info(ctrl, " Power Indicator : %3s\n",
731 PWR_LED(ctrl) ? "yes" : "no");
732 ctrl_info(ctrl, " Hot-Plug Surprise : %3s\n",
733 HP_SUPR_RM(ctrl) ? "yes" : "no");
734 ctrl_info(ctrl, " EMI Present : %3s\n",
735 EMI(ctrl) ? "yes" : "no");
736 ctrl_info(ctrl, " Command Completed : %3s\n",
737 NO_CMD_CMPL(ctrl) ? "no" : "yes");
738 pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, ®16);
739 ctrl_info(ctrl, "Slot Status : 0x%04x\n", reg16);
740 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, ®16);
741 ctrl_info(ctrl, "Slot Control : 0x%04x\n", reg16);
744 #define FLAG(x,y) (((x) & (y)) ? '+' : '-')
746 struct controller *pcie_init(struct pcie_device *dev)
748 struct controller *ctrl;
749 u32 slot_cap, link_cap;
750 struct pci_dev *pdev = dev->port;
752 ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
754 dev_err(&dev->device, "%s: Out of memory\n", __func__);
758 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &slot_cap);
759 ctrl->slot_cap = slot_cap;
760 mutex_init(&ctrl->ctrl_lock);
761 init_waitqueue_head(&ctrl->queue);
764 * Controller doesn't notify of command completion if the "No
765 * Command Completed Support" bit is set in Slot Capability
766 * register or the controller supports none of power
767 * controller, attention led, power led and EMI.
769 if (NO_CMD_CMPL(ctrl) ||
770 !(POWER_CTRL(ctrl) | ATTN_LED(ctrl) | PWR_LED(ctrl) | EMI(ctrl)))
771 ctrl->no_cmd_complete = 1;
773 /* Check if Data Link Layer Link Active Reporting is implemented */
774 pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, &link_cap);
775 if (link_cap & PCI_EXP_LNKCAP_DLLLARC) {
776 ctrl_dbg(ctrl, "Link Active Reporting supported\n");
777 ctrl->link_active_reporting = 1;
780 /* Clear all remaining event bits in Slot Status register */
781 pcie_capability_write_word(pdev, PCI_EXP_SLTSTA,
782 PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
783 PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC |
786 /* Disable software notification */
787 pcie_disable_notification(ctrl);
789 ctrl_info(ctrl, "Slot #%d AttnBtn%c AttnInd%c PwrInd%c PwrCtrl%c MRL%c Interlock%c NoCompl%c LLActRep%c\n",
790 (slot_cap & PCI_EXP_SLTCAP_PSN) >> 19,
791 FLAG(slot_cap, PCI_EXP_SLTCAP_ABP),
792 FLAG(slot_cap, PCI_EXP_SLTCAP_AIP),
793 FLAG(slot_cap, PCI_EXP_SLTCAP_PIP),
794 FLAG(slot_cap, PCI_EXP_SLTCAP_PCP),
795 FLAG(slot_cap, PCI_EXP_SLTCAP_MRLSP),
796 FLAG(slot_cap, PCI_EXP_SLTCAP_EIP),
797 FLAG(slot_cap, PCI_EXP_SLTCAP_NCCS),
798 FLAG(link_cap, PCI_EXP_LNKCAP_DLLLARC));
800 if (pcie_init_slot(ctrl))
811 void pciehp_release_ctrl(struct controller *ctrl)
813 pcie_shutdown_notification(ctrl);
814 pcie_cleanup_slot(ctrl);