2 * Copyright (c) 2006, Intel Corporation.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
15 * Place - Suite 330, Boston, MA 02111-1307 USA.
17 * Copyright (C) 2006-2008 Intel Corporation
18 * Author: Ashok Raj <ashok.raj@intel.com>
19 * Author: Shaohua Li <shaohua.li@intel.com>
20 * Author: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
21 * Author: Fenghua Yu <fenghua.yu@intel.com>
24 #include <linux/init.h>
25 #include <linux/bitmap.h>
26 #include <linux/debugfs.h>
27 #include <linux/slab.h>
28 #include <linux/irq.h>
29 #include <linux/interrupt.h>
30 #include <linux/spinlock.h>
31 #include <linux/pci.h>
32 #include <linux/dmar.h>
33 #include <linux/dma-mapping.h>
34 #include <linux/mempool.h>
35 #include <linux/timer.h>
36 #include <linux/iova.h>
37 #include <linux/iommu.h>
38 #include <linux/intel-iommu.h>
39 #include <linux/sysdev.h>
40 #include <asm/cacheflush.h>
41 #include <asm/iommu.h>
45 #define ROOT_SIZE VTD_PAGE_SIZE
46 #define CONTEXT_SIZE VTD_PAGE_SIZE
48 #define IS_GFX_DEVICE(pdev) ((pdev->class >> 16) == PCI_BASE_CLASS_DISPLAY)
49 #define IS_ISA_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_BRIDGE_ISA)
51 #define IOAPIC_RANGE_START (0xfee00000)
52 #define IOAPIC_RANGE_END (0xfeefffff)
53 #define IOVA_START_ADDR (0x1000)
55 #define DEFAULT_DOMAIN_ADDRESS_WIDTH 48
57 #define MAX_AGAW_WIDTH 64
59 #define DOMAIN_MAX_ADDR(gaw) ((((u64)1) << gaw) - 1)
61 #define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
62 #define DMA_32BIT_PFN IOVA_PFN(DMA_BIT_MASK(32))
63 #define DMA_64BIT_PFN IOVA_PFN(DMA_BIT_MASK(64))
65 #ifndef PHYSICAL_PAGE_MASK
66 #define PHYSICAL_PAGE_MASK PAGE_MASK
69 /* global iommu list, set NULL for ignored DMAR units */
70 static struct intel_iommu **g_iommus;
72 static int rwbf_quirk;
77 * 12-63: Context Ptr (12 - (haw-1))
84 #define ROOT_ENTRY_NR (VTD_PAGE_SIZE/sizeof(struct root_entry))
85 static inline bool root_present(struct root_entry *root)
87 return (root->val & 1);
89 static inline void set_root_present(struct root_entry *root)
93 static inline void set_root_value(struct root_entry *root, unsigned long value)
95 root->val |= value & VTD_PAGE_MASK;
98 static inline struct context_entry *
99 get_context_addr_from_root(struct root_entry *root)
101 return (struct context_entry *)
102 (root_present(root)?phys_to_virt(
103 root->val & VTD_PAGE_MASK) :
110 * 1: fault processing disable
111 * 2-3: translation type
112 * 12-63: address space root
118 struct context_entry {
123 static inline bool context_present(struct context_entry *context)
125 return (context->lo & 1);
127 static inline void context_set_present(struct context_entry *context)
132 static inline void context_set_fault_enable(struct context_entry *context)
134 context->lo &= (((u64)-1) << 2) | 1;
137 static inline void context_set_translation_type(struct context_entry *context,
140 context->lo &= (((u64)-1) << 4) | 3;
141 context->lo |= (value & 3) << 2;
144 static inline void context_set_address_root(struct context_entry *context,
147 context->lo |= value & VTD_PAGE_MASK;
150 static inline void context_set_address_width(struct context_entry *context,
153 context->hi |= value & 7;
156 static inline void context_set_domain_id(struct context_entry *context,
159 context->hi |= (value & ((1 << 16) - 1)) << 8;
162 static inline void context_clear_entry(struct context_entry *context)
175 * 12-63: Host physcial address
181 static inline void dma_clear_pte(struct dma_pte *pte)
186 static inline void dma_set_pte_readable(struct dma_pte *pte)
188 pte->val |= DMA_PTE_READ;
191 static inline void dma_set_pte_writable(struct dma_pte *pte)
193 pte->val |= DMA_PTE_WRITE;
196 static inline void dma_set_pte_snp(struct dma_pte *pte)
198 pte->val |= DMA_PTE_SNP;
201 static inline void dma_set_pte_prot(struct dma_pte *pte, unsigned long prot)
203 pte->val = (pte->val & ~3) | (prot & 3);
206 static inline u64 dma_pte_addr(struct dma_pte *pte)
208 return (pte->val & VTD_PAGE_MASK);
211 static inline void dma_set_pte_addr(struct dma_pte *pte, u64 addr)
213 pte->val |= (addr & VTD_PAGE_MASK);
216 static inline bool dma_pte_present(struct dma_pte *pte)
218 return (pte->val & 3) != 0;
222 * This domain is a statically identity mapping domain.
223 * 1. This domain creats a static 1:1 mapping to all usable memory.
224 * 2. It maps to each iommu if successful.
225 * 3. Each iommu mapps to this domain if successful.
227 struct dmar_domain *si_domain;
229 /* devices under the same p2p bridge are owned in one domain */
230 #define DOMAIN_FLAG_P2P_MULTIPLE_DEVICES (1 << 0)
232 /* domain represents a virtual machine, more than one devices
233 * across iommus may be owned in one domain, e.g. kvm guest.
235 #define DOMAIN_FLAG_VIRTUAL_MACHINE (1 << 1)
237 /* si_domain contains mulitple devices */
238 #define DOMAIN_FLAG_STATIC_IDENTITY (1 << 2)
241 int id; /* domain id */
242 unsigned long iommu_bmp; /* bitmap of iommus this domain uses*/
244 struct list_head devices; /* all devices' list */
245 struct iova_domain iovad; /* iova's that belong to this domain */
247 struct dma_pte *pgd; /* virtual address */
248 spinlock_t mapping_lock; /* page table lock */
249 int gaw; /* max guest address width */
251 /* adjusted guest address width, 0 is level 2 30-bit */
254 int flags; /* flags to find out type of domain */
256 int iommu_coherency;/* indicate coherency of iommu access */
257 int iommu_snooping; /* indicate snooping control feature*/
258 int iommu_count; /* reference count of iommu */
259 spinlock_t iommu_lock; /* protect iommu set in domain */
260 u64 max_addr; /* maximum mapped address */
263 /* PCI domain-device relationship */
264 struct device_domain_info {
265 struct list_head link; /* link to domain siblings */
266 struct list_head global; /* link to global list */
267 int segment; /* PCI domain */
268 u8 bus; /* PCI bus number */
269 u8 devfn; /* PCI devfn number */
270 struct pci_dev *dev; /* it's NULL for PCIE-to-PCI bridge */
271 struct intel_iommu *iommu; /* IOMMU used by this device */
272 struct dmar_domain *domain; /* pointer to domain */
275 static void flush_unmaps_timeout(unsigned long data);
277 DEFINE_TIMER(unmap_timer, flush_unmaps_timeout, 0, 0);
279 #define HIGH_WATER_MARK 250
280 struct deferred_flush_tables {
282 struct iova *iova[HIGH_WATER_MARK];
283 struct dmar_domain *domain[HIGH_WATER_MARK];
286 static struct deferred_flush_tables *deferred_flush;
288 /* bitmap for indexing intel_iommus */
289 static int g_num_of_iommus;
291 static DEFINE_SPINLOCK(async_umap_flush_lock);
292 static LIST_HEAD(unmaps_to_do);
295 static long list_size;
297 static void domain_remove_dev_info(struct dmar_domain *domain);
299 #ifdef CONFIG_DMAR_DEFAULT_ON
300 int dmar_disabled = 0;
302 int dmar_disabled = 1;
303 #endif /*CONFIG_DMAR_DEFAULT_ON*/
305 static int __initdata dmar_map_gfx = 1;
306 static int dmar_forcedac;
307 static int intel_iommu_strict;
309 #define DUMMY_DEVICE_DOMAIN_INFO ((struct device_domain_info *)(-1))
310 static DEFINE_SPINLOCK(device_domain_lock);
311 static LIST_HEAD(device_domain_list);
313 static struct iommu_ops intel_iommu_ops;
315 static int __init intel_iommu_setup(char *str)
320 if (!strncmp(str, "on", 2)) {
322 printk(KERN_INFO "Intel-IOMMU: enabled\n");
323 } else if (!strncmp(str, "off", 3)) {
325 printk(KERN_INFO "Intel-IOMMU: disabled\n");
326 } else if (!strncmp(str, "igfx_off", 8)) {
329 "Intel-IOMMU: disable GFX device mapping\n");
330 } else if (!strncmp(str, "forcedac", 8)) {
332 "Intel-IOMMU: Forcing DAC for PCI devices\n");
334 } else if (!strncmp(str, "strict", 6)) {
336 "Intel-IOMMU: disable batched IOTLB flush\n");
337 intel_iommu_strict = 1;
340 str += strcspn(str, ",");
346 __setup("intel_iommu=", intel_iommu_setup);
348 static struct kmem_cache *iommu_domain_cache;
349 static struct kmem_cache *iommu_devinfo_cache;
350 static struct kmem_cache *iommu_iova_cache;
352 static inline void *iommu_kmem_cache_alloc(struct kmem_cache *cachep)
357 /* trying to avoid low memory issues */
358 flags = current->flags & PF_MEMALLOC;
359 current->flags |= PF_MEMALLOC;
360 vaddr = kmem_cache_alloc(cachep, GFP_ATOMIC);
361 current->flags &= (~PF_MEMALLOC | flags);
366 static inline void *alloc_pgtable_page(void)
371 /* trying to avoid low memory issues */
372 flags = current->flags & PF_MEMALLOC;
373 current->flags |= PF_MEMALLOC;
374 vaddr = (void *)get_zeroed_page(GFP_ATOMIC);
375 current->flags &= (~PF_MEMALLOC | flags);
379 static inline void free_pgtable_page(void *vaddr)
381 free_page((unsigned long)vaddr);
384 static inline void *alloc_domain_mem(void)
386 return iommu_kmem_cache_alloc(iommu_domain_cache);
389 static void free_domain_mem(void *vaddr)
391 kmem_cache_free(iommu_domain_cache, vaddr);
394 static inline void * alloc_devinfo_mem(void)
396 return iommu_kmem_cache_alloc(iommu_devinfo_cache);
399 static inline void free_devinfo_mem(void *vaddr)
401 kmem_cache_free(iommu_devinfo_cache, vaddr);
404 struct iova *alloc_iova_mem(void)
406 return iommu_kmem_cache_alloc(iommu_iova_cache);
409 void free_iova_mem(struct iova *iova)
411 kmem_cache_free(iommu_iova_cache, iova);
415 static inline int width_to_agaw(int width);
417 static int __iommu_calculate_agaw(struct intel_iommu *iommu, int max_gaw)
422 sagaw = cap_sagaw(iommu->cap);
423 for (agaw = width_to_agaw(max_gaw);
425 if (test_bit(agaw, &sagaw))
433 * Calculate max SAGAW for each iommu.
435 int iommu_calculate_max_sagaw(struct intel_iommu *iommu)
437 return __iommu_calculate_agaw(iommu, MAX_AGAW_WIDTH);
441 * calculate agaw for each iommu.
442 * "SAGAW" may be different across iommus, use a default agaw, and
443 * get a supported less agaw for iommus that don't support the default agaw.
445 int iommu_calculate_agaw(struct intel_iommu *iommu)
447 return __iommu_calculate_agaw(iommu, DEFAULT_DOMAIN_ADDRESS_WIDTH);
450 /* This functionin only returns single iommu in a domain */
451 static struct intel_iommu *domain_get_iommu(struct dmar_domain *domain)
455 /* si_domain and vm domain should not get here. */
456 BUG_ON(domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE);
457 BUG_ON(domain->flags & DOMAIN_FLAG_STATIC_IDENTITY);
459 iommu_id = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
460 if (iommu_id < 0 || iommu_id >= g_num_of_iommus)
463 return g_iommus[iommu_id];
466 static void domain_update_iommu_coherency(struct dmar_domain *domain)
470 domain->iommu_coherency = 1;
472 i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
473 for (; i < g_num_of_iommus; ) {
474 if (!ecap_coherent(g_iommus[i]->ecap)) {
475 domain->iommu_coherency = 0;
478 i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1);
482 static void domain_update_iommu_snooping(struct dmar_domain *domain)
486 domain->iommu_snooping = 1;
488 i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
489 for (; i < g_num_of_iommus; ) {
490 if (!ecap_sc_support(g_iommus[i]->ecap)) {
491 domain->iommu_snooping = 0;
494 i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1);
498 /* Some capabilities may be different across iommus */
499 static void domain_update_iommu_cap(struct dmar_domain *domain)
501 domain_update_iommu_coherency(domain);
502 domain_update_iommu_snooping(domain);
505 static struct intel_iommu *device_to_iommu(int segment, u8 bus, u8 devfn)
507 struct dmar_drhd_unit *drhd = NULL;
510 for_each_drhd_unit(drhd) {
513 if (segment != drhd->segment)
516 for (i = 0; i < drhd->devices_cnt; i++) {
517 if (drhd->devices[i] &&
518 drhd->devices[i]->bus->number == bus &&
519 drhd->devices[i]->devfn == devfn)
521 if (drhd->devices[i] &&
522 drhd->devices[i]->subordinate &&
523 drhd->devices[i]->subordinate->number <= bus &&
524 drhd->devices[i]->subordinate->subordinate >= bus)
528 if (drhd->include_all)
535 static void domain_flush_cache(struct dmar_domain *domain,
536 void *addr, int size)
538 if (!domain->iommu_coherency)
539 clflush_cache_range(addr, size);
542 /* Gets context entry for a given bus and devfn */
543 static struct context_entry * device_to_context_entry(struct intel_iommu *iommu,
546 struct root_entry *root;
547 struct context_entry *context;
548 unsigned long phy_addr;
551 spin_lock_irqsave(&iommu->lock, flags);
552 root = &iommu->root_entry[bus];
553 context = get_context_addr_from_root(root);
555 context = (struct context_entry *)alloc_pgtable_page();
557 spin_unlock_irqrestore(&iommu->lock, flags);
560 __iommu_flush_cache(iommu, (void *)context, CONTEXT_SIZE);
561 phy_addr = virt_to_phys((void *)context);
562 set_root_value(root, phy_addr);
563 set_root_present(root);
564 __iommu_flush_cache(iommu, root, sizeof(*root));
566 spin_unlock_irqrestore(&iommu->lock, flags);
567 return &context[devfn];
570 static int device_context_mapped(struct intel_iommu *iommu, u8 bus, u8 devfn)
572 struct root_entry *root;
573 struct context_entry *context;
577 spin_lock_irqsave(&iommu->lock, flags);
578 root = &iommu->root_entry[bus];
579 context = get_context_addr_from_root(root);
584 ret = context_present(&context[devfn]);
586 spin_unlock_irqrestore(&iommu->lock, flags);
590 static void clear_context_table(struct intel_iommu *iommu, u8 bus, u8 devfn)
592 struct root_entry *root;
593 struct context_entry *context;
596 spin_lock_irqsave(&iommu->lock, flags);
597 root = &iommu->root_entry[bus];
598 context = get_context_addr_from_root(root);
600 context_clear_entry(&context[devfn]);
601 __iommu_flush_cache(iommu, &context[devfn], \
604 spin_unlock_irqrestore(&iommu->lock, flags);
607 static void free_context_table(struct intel_iommu *iommu)
609 struct root_entry *root;
612 struct context_entry *context;
614 spin_lock_irqsave(&iommu->lock, flags);
615 if (!iommu->root_entry) {
618 for (i = 0; i < ROOT_ENTRY_NR; i++) {
619 root = &iommu->root_entry[i];
620 context = get_context_addr_from_root(root);
622 free_pgtable_page(context);
624 free_pgtable_page(iommu->root_entry);
625 iommu->root_entry = NULL;
627 spin_unlock_irqrestore(&iommu->lock, flags);
630 /* page table handling */
631 #define LEVEL_STRIDE (9)
632 #define LEVEL_MASK (((u64)1 << LEVEL_STRIDE) - 1)
634 static inline int agaw_to_level(int agaw)
639 static inline int agaw_to_width(int agaw)
641 return 30 + agaw * LEVEL_STRIDE;
645 static inline int width_to_agaw(int width)
647 return (width - 30) / LEVEL_STRIDE;
650 static inline unsigned int level_to_offset_bits(int level)
652 return (12 + (level - 1) * LEVEL_STRIDE);
655 static inline int address_level_offset(u64 addr, int level)
657 return ((addr >> level_to_offset_bits(level)) & LEVEL_MASK);
660 static inline u64 level_mask(int level)
662 return ((u64)-1 << level_to_offset_bits(level));
665 static inline u64 level_size(int level)
667 return ((u64)1 << level_to_offset_bits(level));
670 static inline u64 align_to_level(u64 addr, int level)
672 return ((addr + level_size(level) - 1) & level_mask(level));
675 static struct dma_pte * addr_to_dma_pte(struct dmar_domain *domain, u64 addr)
677 int addr_width = agaw_to_width(domain->agaw);
678 struct dma_pte *parent, *pte = NULL;
679 int level = agaw_to_level(domain->agaw);
683 BUG_ON(!domain->pgd);
685 addr &= (((u64)1) << addr_width) - 1;
686 parent = domain->pgd;
688 spin_lock_irqsave(&domain->mapping_lock, flags);
692 offset = address_level_offset(addr, level);
693 pte = &parent[offset];
697 if (!dma_pte_present(pte)) {
698 tmp_page = alloc_pgtable_page();
701 spin_unlock_irqrestore(&domain->mapping_lock,
705 domain_flush_cache(domain, tmp_page, PAGE_SIZE);
706 dma_set_pte_addr(pte, virt_to_phys(tmp_page));
708 * high level table always sets r/w, last level page
709 * table control read/write
711 dma_set_pte_readable(pte);
712 dma_set_pte_writable(pte);
713 domain_flush_cache(domain, pte, sizeof(*pte));
715 parent = phys_to_virt(dma_pte_addr(pte));
719 spin_unlock_irqrestore(&domain->mapping_lock, flags);
723 /* return address's pte at specific level */
724 static struct dma_pte *dma_addr_level_pte(struct dmar_domain *domain, u64 addr,
727 struct dma_pte *parent, *pte = NULL;
728 int total = agaw_to_level(domain->agaw);
731 parent = domain->pgd;
732 while (level <= total) {
733 offset = address_level_offset(addr, total);
734 pte = &parent[offset];
738 if (!dma_pte_present(pte))
740 parent = phys_to_virt(dma_pte_addr(pte));
746 /* clear one page's page table */
747 static void dma_pte_clear_one(struct dmar_domain *domain, u64 addr)
749 struct dma_pte *pte = NULL;
751 /* get last level pte */
752 pte = dma_addr_level_pte(domain, addr, 1);
756 domain_flush_cache(domain, pte, sizeof(*pte));
760 /* clear last level pte, a tlb flush should be followed */
761 static void dma_pte_clear_range(struct dmar_domain *domain, u64 start, u64 end)
763 int addr_width = agaw_to_width(domain->agaw);
766 start &= (((u64)1) << addr_width) - 1;
767 end &= (((u64)1) << addr_width) - 1;
768 /* in case it's partial page */
770 end = PAGE_ALIGN(end);
771 npages = (end - start) / VTD_PAGE_SIZE;
773 /* we don't need lock here, nobody else touches the iova range */
775 dma_pte_clear_one(domain, start);
776 start += VTD_PAGE_SIZE;
780 /* free page table pages. last level pte should already be cleared */
781 static void dma_pte_free_pagetable(struct dmar_domain *domain,
784 int addr_width = agaw_to_width(domain->agaw);
786 int total = agaw_to_level(domain->agaw);
790 start &= (((u64)1) << addr_width) - 1;
791 end &= (((u64)1) << addr_width) - 1;
793 /* we don't need lock here, nobody else touches the iova range */
795 while (level <= total) {
796 tmp = align_to_level(start, level);
797 if (tmp >= end || (tmp + level_size(level) > end))
801 pte = dma_addr_level_pte(domain, tmp, level);
804 phys_to_virt(dma_pte_addr(pte)));
806 domain_flush_cache(domain, pte, sizeof(*pte));
808 tmp += level_size(level);
813 if (start == 0 && end >= ((((u64)1) << addr_width) - 1)) {
814 free_pgtable_page(domain->pgd);
820 static int iommu_alloc_root_entry(struct intel_iommu *iommu)
822 struct root_entry *root;
825 root = (struct root_entry *)alloc_pgtable_page();
829 __iommu_flush_cache(iommu, root, ROOT_SIZE);
831 spin_lock_irqsave(&iommu->lock, flags);
832 iommu->root_entry = root;
833 spin_unlock_irqrestore(&iommu->lock, flags);
838 static void iommu_set_root_entry(struct intel_iommu *iommu)
844 addr = iommu->root_entry;
846 spin_lock_irqsave(&iommu->register_lock, flag);
847 dmar_writeq(iommu->reg + DMAR_RTADDR_REG, virt_to_phys(addr));
849 writel(iommu->gcmd | DMA_GCMD_SRTP, iommu->reg + DMAR_GCMD_REG);
851 /* Make sure hardware complete it */
852 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
853 readl, (sts & DMA_GSTS_RTPS), sts);
855 spin_unlock_irqrestore(&iommu->register_lock, flag);
858 static void iommu_flush_write_buffer(struct intel_iommu *iommu)
863 if (!rwbf_quirk && !cap_rwbf(iommu->cap))
866 spin_lock_irqsave(&iommu->register_lock, flag);
867 writel(iommu->gcmd | DMA_GCMD_WBF, iommu->reg + DMAR_GCMD_REG);
869 /* Make sure hardware complete it */
870 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
871 readl, (!(val & DMA_GSTS_WBFS)), val);
873 spin_unlock_irqrestore(&iommu->register_lock, flag);
876 /* return value determine if we need a write buffer flush */
877 static void __iommu_flush_context(struct intel_iommu *iommu,
878 u16 did, u16 source_id, u8 function_mask,
885 case DMA_CCMD_GLOBAL_INVL:
886 val = DMA_CCMD_GLOBAL_INVL;
888 case DMA_CCMD_DOMAIN_INVL:
889 val = DMA_CCMD_DOMAIN_INVL|DMA_CCMD_DID(did);
891 case DMA_CCMD_DEVICE_INVL:
892 val = DMA_CCMD_DEVICE_INVL|DMA_CCMD_DID(did)
893 | DMA_CCMD_SID(source_id) | DMA_CCMD_FM(function_mask);
900 spin_lock_irqsave(&iommu->register_lock, flag);
901 dmar_writeq(iommu->reg + DMAR_CCMD_REG, val);
903 /* Make sure hardware complete it */
904 IOMMU_WAIT_OP(iommu, DMAR_CCMD_REG,
905 dmar_readq, (!(val & DMA_CCMD_ICC)), val);
907 spin_unlock_irqrestore(&iommu->register_lock, flag);
910 /* return value determine if we need a write buffer flush */
911 static void __iommu_flush_iotlb(struct intel_iommu *iommu, u16 did,
912 u64 addr, unsigned int size_order, u64 type)
914 int tlb_offset = ecap_iotlb_offset(iommu->ecap);
915 u64 val = 0, val_iva = 0;
919 case DMA_TLB_GLOBAL_FLUSH:
920 /* global flush doesn't need set IVA_REG */
921 val = DMA_TLB_GLOBAL_FLUSH|DMA_TLB_IVT;
923 case DMA_TLB_DSI_FLUSH:
924 val = DMA_TLB_DSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
926 case DMA_TLB_PSI_FLUSH:
927 val = DMA_TLB_PSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
928 /* Note: always flush non-leaf currently */
929 val_iva = size_order | addr;
934 /* Note: set drain read/write */
937 * This is probably to be super secure.. Looks like we can
938 * ignore it without any impact.
940 if (cap_read_drain(iommu->cap))
941 val |= DMA_TLB_READ_DRAIN;
943 if (cap_write_drain(iommu->cap))
944 val |= DMA_TLB_WRITE_DRAIN;
946 spin_lock_irqsave(&iommu->register_lock, flag);
947 /* Note: Only uses first TLB reg currently */
949 dmar_writeq(iommu->reg + tlb_offset, val_iva);
950 dmar_writeq(iommu->reg + tlb_offset + 8, val);
952 /* Make sure hardware complete it */
953 IOMMU_WAIT_OP(iommu, tlb_offset + 8,
954 dmar_readq, (!(val & DMA_TLB_IVT)), val);
956 spin_unlock_irqrestore(&iommu->register_lock, flag);
958 /* check IOTLB invalidation granularity */
959 if (DMA_TLB_IAIG(val) == 0)
960 printk(KERN_ERR"IOMMU: flush IOTLB failed\n");
961 if (DMA_TLB_IAIG(val) != DMA_TLB_IIRG(type))
962 pr_debug("IOMMU: tlb flush request %Lx, actual %Lx\n",
963 (unsigned long long)DMA_TLB_IIRG(type),
964 (unsigned long long)DMA_TLB_IAIG(val));
967 static struct device_domain_info *iommu_support_dev_iotlb(
968 struct dmar_domain *domain, int segment, u8 bus, u8 devfn)
972 struct device_domain_info *info;
973 struct intel_iommu *iommu = device_to_iommu(segment, bus, devfn);
975 if (!ecap_dev_iotlb_support(iommu->ecap))
981 spin_lock_irqsave(&device_domain_lock, flags);
982 list_for_each_entry(info, &domain->devices, link)
983 if (info->bus == bus && info->devfn == devfn) {
987 spin_unlock_irqrestore(&device_domain_lock, flags);
989 if (!found || !info->dev)
992 if (!pci_find_ext_capability(info->dev, PCI_EXT_CAP_ID_ATS))
995 if (!dmar_find_matched_atsr_unit(info->dev))
1003 static void iommu_enable_dev_iotlb(struct device_domain_info *info)
1008 pci_enable_ats(info->dev, VTD_PAGE_SHIFT);
1011 static void iommu_disable_dev_iotlb(struct device_domain_info *info)
1013 if (!info->dev || !pci_ats_enabled(info->dev))
1016 pci_disable_ats(info->dev);
1019 static void iommu_flush_dev_iotlb(struct dmar_domain *domain,
1020 u64 addr, unsigned mask)
1023 unsigned long flags;
1024 struct device_domain_info *info;
1026 spin_lock_irqsave(&device_domain_lock, flags);
1027 list_for_each_entry(info, &domain->devices, link) {
1028 if (!info->dev || !pci_ats_enabled(info->dev))
1031 sid = info->bus << 8 | info->devfn;
1032 qdep = pci_ats_queue_depth(info->dev);
1033 qi_flush_dev_iotlb(info->iommu, sid, qdep, addr, mask);
1035 spin_unlock_irqrestore(&device_domain_lock, flags);
1038 static void iommu_flush_iotlb_psi(struct intel_iommu *iommu, u16 did,
1039 u64 addr, unsigned int pages)
1041 unsigned int mask = ilog2(__roundup_pow_of_two(pages));
1043 BUG_ON(addr & (~VTD_PAGE_MASK));
1047 * Fallback to domain selective flush if no PSI support or the size is
1049 * PSI requires page size to be 2 ^ x, and the base address is naturally
1050 * aligned to the size
1052 if (!cap_pgsel_inv(iommu->cap) || mask > cap_max_amask_val(iommu->cap))
1053 iommu->flush.flush_iotlb(iommu, did, 0, 0,
1056 iommu->flush.flush_iotlb(iommu, did, addr, mask,
1059 iommu_flush_dev_iotlb(iommu->domains[did], addr, mask);
1062 static void iommu_disable_protect_mem_regions(struct intel_iommu *iommu)
1065 unsigned long flags;
1067 spin_lock_irqsave(&iommu->register_lock, flags);
1068 pmen = readl(iommu->reg + DMAR_PMEN_REG);
1069 pmen &= ~DMA_PMEN_EPM;
1070 writel(pmen, iommu->reg + DMAR_PMEN_REG);
1072 /* wait for the protected region status bit to clear */
1073 IOMMU_WAIT_OP(iommu, DMAR_PMEN_REG,
1074 readl, !(pmen & DMA_PMEN_PRS), pmen);
1076 spin_unlock_irqrestore(&iommu->register_lock, flags);
1079 static int iommu_enable_translation(struct intel_iommu *iommu)
1082 unsigned long flags;
1084 spin_lock_irqsave(&iommu->register_lock, flags);
1085 iommu->gcmd |= DMA_GCMD_TE;
1086 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
1088 /* Make sure hardware complete it */
1089 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
1090 readl, (sts & DMA_GSTS_TES), sts);
1092 spin_unlock_irqrestore(&iommu->register_lock, flags);
1096 static int iommu_disable_translation(struct intel_iommu *iommu)
1101 spin_lock_irqsave(&iommu->register_lock, flag);
1102 iommu->gcmd &= ~DMA_GCMD_TE;
1103 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
1105 /* Make sure hardware complete it */
1106 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
1107 readl, (!(sts & DMA_GSTS_TES)), sts);
1109 spin_unlock_irqrestore(&iommu->register_lock, flag);
1114 static int iommu_init_domains(struct intel_iommu *iommu)
1116 unsigned long ndomains;
1117 unsigned long nlongs;
1119 ndomains = cap_ndoms(iommu->cap);
1120 pr_debug("Number of Domains supportd <%ld>\n", ndomains);
1121 nlongs = BITS_TO_LONGS(ndomains);
1123 /* TBD: there might be 64K domains,
1124 * consider other allocation for future chip
1126 iommu->domain_ids = kcalloc(nlongs, sizeof(unsigned long), GFP_KERNEL);
1127 if (!iommu->domain_ids) {
1128 printk(KERN_ERR "Allocating domain id array failed\n");
1131 iommu->domains = kcalloc(ndomains, sizeof(struct dmar_domain *),
1133 if (!iommu->domains) {
1134 printk(KERN_ERR "Allocating domain array failed\n");
1135 kfree(iommu->domain_ids);
1139 spin_lock_init(&iommu->lock);
1142 * if Caching mode is set, then invalid translations are tagged
1143 * with domainid 0. Hence we need to pre-allocate it.
1145 if (cap_caching_mode(iommu->cap))
1146 set_bit(0, iommu->domain_ids);
1151 static void domain_exit(struct dmar_domain *domain);
1152 static void vm_domain_exit(struct dmar_domain *domain);
1154 void free_dmar_iommu(struct intel_iommu *iommu)
1156 struct dmar_domain *domain;
1158 unsigned long flags;
1160 i = find_first_bit(iommu->domain_ids, cap_ndoms(iommu->cap));
1161 for (; i < cap_ndoms(iommu->cap); ) {
1162 domain = iommu->domains[i];
1163 clear_bit(i, iommu->domain_ids);
1165 spin_lock_irqsave(&domain->iommu_lock, flags);
1166 if (--domain->iommu_count == 0) {
1167 if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE)
1168 vm_domain_exit(domain);
1170 domain_exit(domain);
1172 spin_unlock_irqrestore(&domain->iommu_lock, flags);
1174 i = find_next_bit(iommu->domain_ids,
1175 cap_ndoms(iommu->cap), i+1);
1178 if (iommu->gcmd & DMA_GCMD_TE)
1179 iommu_disable_translation(iommu);
1182 set_irq_data(iommu->irq, NULL);
1183 /* This will mask the irq */
1184 free_irq(iommu->irq, iommu);
1185 destroy_irq(iommu->irq);
1188 kfree(iommu->domains);
1189 kfree(iommu->domain_ids);
1191 g_iommus[iommu->seq_id] = NULL;
1193 /* if all iommus are freed, free g_iommus */
1194 for (i = 0; i < g_num_of_iommus; i++) {
1199 if (i == g_num_of_iommus)
1202 /* free context mapping */
1203 free_context_table(iommu);
1206 static struct dmar_domain *alloc_domain(void)
1208 struct dmar_domain *domain;
1210 domain = alloc_domain_mem();
1214 memset(&domain->iommu_bmp, 0, sizeof(unsigned long));
1220 static int iommu_attach_domain(struct dmar_domain *domain,
1221 struct intel_iommu *iommu)
1224 unsigned long ndomains;
1225 unsigned long flags;
1227 ndomains = cap_ndoms(iommu->cap);
1229 spin_lock_irqsave(&iommu->lock, flags);
1231 num = find_first_zero_bit(iommu->domain_ids, ndomains);
1232 if (num >= ndomains) {
1233 spin_unlock_irqrestore(&iommu->lock, flags);
1234 printk(KERN_ERR "IOMMU: no free domain ids\n");
1239 set_bit(num, iommu->domain_ids);
1240 set_bit(iommu->seq_id, &domain->iommu_bmp);
1241 iommu->domains[num] = domain;
1242 spin_unlock_irqrestore(&iommu->lock, flags);
1247 static void iommu_detach_domain(struct dmar_domain *domain,
1248 struct intel_iommu *iommu)
1250 unsigned long flags;
1254 spin_lock_irqsave(&iommu->lock, flags);
1255 ndomains = cap_ndoms(iommu->cap);
1256 num = find_first_bit(iommu->domain_ids, ndomains);
1257 for (; num < ndomains; ) {
1258 if (iommu->domains[num] == domain) {
1262 num = find_next_bit(iommu->domain_ids,
1263 cap_ndoms(iommu->cap), num+1);
1267 clear_bit(num, iommu->domain_ids);
1268 clear_bit(iommu->seq_id, &domain->iommu_bmp);
1269 iommu->domains[num] = NULL;
1271 spin_unlock_irqrestore(&iommu->lock, flags);
1274 static struct iova_domain reserved_iova_list;
1275 static struct lock_class_key reserved_alloc_key;
1276 static struct lock_class_key reserved_rbtree_key;
1278 static void dmar_init_reserved_ranges(void)
1280 struct pci_dev *pdev = NULL;
1285 init_iova_domain(&reserved_iova_list, DMA_32BIT_PFN);
1287 lockdep_set_class(&reserved_iova_list.iova_alloc_lock,
1288 &reserved_alloc_key);
1289 lockdep_set_class(&reserved_iova_list.iova_rbtree_lock,
1290 &reserved_rbtree_key);
1292 /* IOAPIC ranges shouldn't be accessed by DMA */
1293 iova = reserve_iova(&reserved_iova_list, IOVA_PFN(IOAPIC_RANGE_START),
1294 IOVA_PFN(IOAPIC_RANGE_END));
1296 printk(KERN_ERR "Reserve IOAPIC range failed\n");
1298 /* Reserve all PCI MMIO to avoid peer-to-peer access */
1299 for_each_pci_dev(pdev) {
1302 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1303 r = &pdev->resource[i];
1304 if (!r->flags || !(r->flags & IORESOURCE_MEM))
1307 addr &= PHYSICAL_PAGE_MASK;
1308 size = r->end - addr;
1309 size = PAGE_ALIGN(size);
1310 iova = reserve_iova(&reserved_iova_list, IOVA_PFN(addr),
1311 IOVA_PFN(size + addr) - 1);
1313 printk(KERN_ERR "Reserve iova failed\n");
1319 static void domain_reserve_special_ranges(struct dmar_domain *domain)
1321 copy_reserved_iova(&reserved_iova_list, &domain->iovad);
1324 static inline int guestwidth_to_adjustwidth(int gaw)
1327 int r = (gaw - 12) % 9;
1338 static int domain_init(struct dmar_domain *domain, int guest_width)
1340 struct intel_iommu *iommu;
1341 int adjust_width, agaw;
1342 unsigned long sagaw;
1344 init_iova_domain(&domain->iovad, DMA_32BIT_PFN);
1345 spin_lock_init(&domain->mapping_lock);
1346 spin_lock_init(&domain->iommu_lock);
1348 domain_reserve_special_ranges(domain);
1350 /* calculate AGAW */
1351 iommu = domain_get_iommu(domain);
1352 if (guest_width > cap_mgaw(iommu->cap))
1353 guest_width = cap_mgaw(iommu->cap);
1354 domain->gaw = guest_width;
1355 adjust_width = guestwidth_to_adjustwidth(guest_width);
1356 agaw = width_to_agaw(adjust_width);
1357 sagaw = cap_sagaw(iommu->cap);
1358 if (!test_bit(agaw, &sagaw)) {
1359 /* hardware doesn't support it, choose a bigger one */
1360 pr_debug("IOMMU: hardware doesn't support agaw %d\n", agaw);
1361 agaw = find_next_bit(&sagaw, 5, agaw);
1365 domain->agaw = agaw;
1366 INIT_LIST_HEAD(&domain->devices);
1368 if (ecap_coherent(iommu->ecap))
1369 domain->iommu_coherency = 1;
1371 domain->iommu_coherency = 0;
1373 if (ecap_sc_support(iommu->ecap))
1374 domain->iommu_snooping = 1;
1376 domain->iommu_snooping = 0;
1378 domain->iommu_count = 1;
1380 /* always allocate the top pgd */
1381 domain->pgd = (struct dma_pte *)alloc_pgtable_page();
1384 __iommu_flush_cache(iommu, domain->pgd, PAGE_SIZE);
1388 static void domain_exit(struct dmar_domain *domain)
1390 struct dmar_drhd_unit *drhd;
1391 struct intel_iommu *iommu;
1394 /* Domain 0 is reserved, so dont process it */
1398 domain_remove_dev_info(domain);
1400 put_iova_domain(&domain->iovad);
1401 end = DOMAIN_MAX_ADDR(domain->gaw);
1402 end = end & (~PAGE_MASK);
1405 dma_pte_clear_range(domain, 0, end);
1407 /* free page tables */
1408 dma_pte_free_pagetable(domain, 0, end);
1410 for_each_active_iommu(iommu, drhd)
1411 if (test_bit(iommu->seq_id, &domain->iommu_bmp))
1412 iommu_detach_domain(domain, iommu);
1414 free_domain_mem(domain);
1417 static int domain_context_mapping_one(struct dmar_domain *domain, int segment,
1418 u8 bus, u8 devfn, int translation)
1420 struct context_entry *context;
1421 unsigned long flags;
1422 struct intel_iommu *iommu;
1423 struct dma_pte *pgd;
1425 unsigned long ndomains;
1428 struct device_domain_info *info = NULL;
1430 pr_debug("Set context mapping for %02x:%02x.%d\n",
1431 bus, PCI_SLOT(devfn), PCI_FUNC(devfn));
1433 BUG_ON(!domain->pgd);
1434 BUG_ON(translation != CONTEXT_TT_PASS_THROUGH &&
1435 translation != CONTEXT_TT_MULTI_LEVEL);
1437 iommu = device_to_iommu(segment, bus, devfn);
1441 context = device_to_context_entry(iommu, bus, devfn);
1444 spin_lock_irqsave(&iommu->lock, flags);
1445 if (context_present(context)) {
1446 spin_unlock_irqrestore(&iommu->lock, flags);
1453 if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE ||
1454 domain->flags & DOMAIN_FLAG_STATIC_IDENTITY) {
1457 /* find an available domain id for this device in iommu */
1458 ndomains = cap_ndoms(iommu->cap);
1459 num = find_first_bit(iommu->domain_ids, ndomains);
1460 for (; num < ndomains; ) {
1461 if (iommu->domains[num] == domain) {
1466 num = find_next_bit(iommu->domain_ids,
1467 cap_ndoms(iommu->cap), num+1);
1471 num = find_first_zero_bit(iommu->domain_ids, ndomains);
1472 if (num >= ndomains) {
1473 spin_unlock_irqrestore(&iommu->lock, flags);
1474 printk(KERN_ERR "IOMMU: no free domain ids\n");
1478 set_bit(num, iommu->domain_ids);
1479 set_bit(iommu->seq_id, &domain->iommu_bmp);
1480 iommu->domains[num] = domain;
1484 /* Skip top levels of page tables for
1485 * iommu which has less agaw than default.
1487 for (agaw = domain->agaw; agaw != iommu->agaw; agaw--) {
1488 pgd = phys_to_virt(dma_pte_addr(pgd));
1489 if (!dma_pte_present(pgd)) {
1490 spin_unlock_irqrestore(&iommu->lock, flags);
1496 context_set_domain_id(context, id);
1498 if (translation != CONTEXT_TT_PASS_THROUGH) {
1499 info = iommu_support_dev_iotlb(domain, segment, bus, devfn);
1500 translation = info ? CONTEXT_TT_DEV_IOTLB :
1501 CONTEXT_TT_MULTI_LEVEL;
1504 * In pass through mode, AW must be programmed to indicate the largest
1505 * AGAW value supported by hardware. And ASR is ignored by hardware.
1507 if (unlikely(translation == CONTEXT_TT_PASS_THROUGH))
1508 context_set_address_width(context, iommu->msagaw);
1510 context_set_address_root(context, virt_to_phys(pgd));
1511 context_set_address_width(context, iommu->agaw);
1514 context_set_translation_type(context, translation);
1515 context_set_fault_enable(context);
1516 context_set_present(context);
1517 domain_flush_cache(domain, context, sizeof(*context));
1520 * It's a non-present to present mapping. If hardware doesn't cache
1521 * non-present entry we only need to flush the write-buffer. If the
1522 * _does_ cache non-present entries, then it does so in the special
1523 * domain #0, which we have to flush:
1525 if (cap_caching_mode(iommu->cap)) {
1526 iommu->flush.flush_context(iommu, 0,
1527 (((u16)bus) << 8) | devfn,
1528 DMA_CCMD_MASK_NOBIT,
1529 DMA_CCMD_DEVICE_INVL);
1530 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_DSI_FLUSH);
1532 iommu_flush_write_buffer(iommu);
1534 iommu_enable_dev_iotlb(info);
1535 spin_unlock_irqrestore(&iommu->lock, flags);
1537 spin_lock_irqsave(&domain->iommu_lock, flags);
1538 if (!test_and_set_bit(iommu->seq_id, &domain->iommu_bmp)) {
1539 domain->iommu_count++;
1540 domain_update_iommu_cap(domain);
1542 spin_unlock_irqrestore(&domain->iommu_lock, flags);
1547 domain_context_mapping(struct dmar_domain *domain, struct pci_dev *pdev,
1551 struct pci_dev *tmp, *parent;
1553 ret = domain_context_mapping_one(domain, pci_domain_nr(pdev->bus),
1554 pdev->bus->number, pdev->devfn,
1559 /* dependent device mapping */
1560 tmp = pci_find_upstream_pcie_bridge(pdev);
1563 /* Secondary interface's bus number and devfn 0 */
1564 parent = pdev->bus->self;
1565 while (parent != tmp) {
1566 ret = domain_context_mapping_one(domain,
1567 pci_domain_nr(parent->bus),
1568 parent->bus->number,
1569 parent->devfn, translation);
1572 parent = parent->bus->self;
1574 if (tmp->is_pcie) /* this is a PCIE-to-PCI bridge */
1575 return domain_context_mapping_one(domain,
1576 pci_domain_nr(tmp->subordinate),
1577 tmp->subordinate->number, 0,
1579 else /* this is a legacy PCI bridge */
1580 return domain_context_mapping_one(domain,
1581 pci_domain_nr(tmp->bus),
1587 static int domain_context_mapped(struct pci_dev *pdev)
1590 struct pci_dev *tmp, *parent;
1591 struct intel_iommu *iommu;
1593 iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
1598 ret = device_context_mapped(iommu, pdev->bus->number, pdev->devfn);
1601 /* dependent device mapping */
1602 tmp = pci_find_upstream_pcie_bridge(pdev);
1605 /* Secondary interface's bus number and devfn 0 */
1606 parent = pdev->bus->self;
1607 while (parent != tmp) {
1608 ret = device_context_mapped(iommu, parent->bus->number,
1612 parent = parent->bus->self;
1615 return device_context_mapped(iommu, tmp->subordinate->number,
1618 return device_context_mapped(iommu, tmp->bus->number,
1623 domain_page_mapping(struct dmar_domain *domain, dma_addr_t iova,
1624 u64 hpa, size_t size, int prot)
1626 u64 start_pfn, end_pfn;
1627 struct dma_pte *pte;
1629 int addr_width = agaw_to_width(domain->agaw);
1631 hpa &= (((u64)1) << addr_width) - 1;
1633 if ((prot & (DMA_PTE_READ|DMA_PTE_WRITE)) == 0)
1636 start_pfn = ((u64)hpa) >> VTD_PAGE_SHIFT;
1637 end_pfn = (VTD_PAGE_ALIGN(((u64)hpa) + size)) >> VTD_PAGE_SHIFT;
1639 while (start_pfn < end_pfn) {
1640 pte = addr_to_dma_pte(domain, iova + VTD_PAGE_SIZE * index);
1643 /* We don't need lock here, nobody else
1644 * touches the iova range
1646 BUG_ON(dma_pte_addr(pte));
1647 dma_set_pte_addr(pte, start_pfn << VTD_PAGE_SHIFT);
1648 dma_set_pte_prot(pte, prot);
1649 if (prot & DMA_PTE_SNP)
1650 dma_set_pte_snp(pte);
1651 domain_flush_cache(domain, pte, sizeof(*pte));
1658 static void iommu_detach_dev(struct intel_iommu *iommu, u8 bus, u8 devfn)
1663 clear_context_table(iommu, bus, devfn);
1664 iommu->flush.flush_context(iommu, 0, 0, 0,
1665 DMA_CCMD_GLOBAL_INVL);
1666 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
1669 static void domain_remove_dev_info(struct dmar_domain *domain)
1671 struct device_domain_info *info;
1672 unsigned long flags;
1673 struct intel_iommu *iommu;
1675 spin_lock_irqsave(&device_domain_lock, flags);
1676 while (!list_empty(&domain->devices)) {
1677 info = list_entry(domain->devices.next,
1678 struct device_domain_info, link);
1679 list_del(&info->link);
1680 list_del(&info->global);
1682 info->dev->dev.archdata.iommu = NULL;
1683 spin_unlock_irqrestore(&device_domain_lock, flags);
1685 iommu_disable_dev_iotlb(info);
1686 iommu = device_to_iommu(info->segment, info->bus, info->devfn);
1687 iommu_detach_dev(iommu, info->bus, info->devfn);
1688 free_devinfo_mem(info);
1690 spin_lock_irqsave(&device_domain_lock, flags);
1692 spin_unlock_irqrestore(&device_domain_lock, flags);
1697 * Note: we use struct pci_dev->dev.archdata.iommu stores the info
1699 static struct dmar_domain *
1700 find_domain(struct pci_dev *pdev)
1702 struct device_domain_info *info;
1704 /* No lock here, assumes no domain exit in normal case */
1705 info = pdev->dev.archdata.iommu;
1707 return info->domain;
1711 /* domain is initialized */
1712 static struct dmar_domain *get_domain_for_dev(struct pci_dev *pdev, int gaw)
1714 struct dmar_domain *domain, *found = NULL;
1715 struct intel_iommu *iommu;
1716 struct dmar_drhd_unit *drhd;
1717 struct device_domain_info *info, *tmp;
1718 struct pci_dev *dev_tmp;
1719 unsigned long flags;
1720 int bus = 0, devfn = 0;
1724 domain = find_domain(pdev);
1728 segment = pci_domain_nr(pdev->bus);
1730 dev_tmp = pci_find_upstream_pcie_bridge(pdev);
1732 if (dev_tmp->is_pcie) {
1733 bus = dev_tmp->subordinate->number;
1736 bus = dev_tmp->bus->number;
1737 devfn = dev_tmp->devfn;
1739 spin_lock_irqsave(&device_domain_lock, flags);
1740 list_for_each_entry(info, &device_domain_list, global) {
1741 if (info->segment == segment &&
1742 info->bus == bus && info->devfn == devfn) {
1743 found = info->domain;
1747 spin_unlock_irqrestore(&device_domain_lock, flags);
1748 /* pcie-pci bridge already has a domain, uses it */
1755 domain = alloc_domain();
1759 /* Allocate new domain for the device */
1760 drhd = dmar_find_matched_drhd_unit(pdev);
1762 printk(KERN_ERR "IOMMU: can't find DMAR for device %s\n",
1766 iommu = drhd->iommu;
1768 ret = iommu_attach_domain(domain, iommu);
1770 domain_exit(domain);
1774 if (domain_init(domain, gaw)) {
1775 domain_exit(domain);
1779 /* register pcie-to-pci device */
1781 info = alloc_devinfo_mem();
1783 domain_exit(domain);
1786 info->segment = segment;
1788 info->devfn = devfn;
1790 info->domain = domain;
1791 /* This domain is shared by devices under p2p bridge */
1792 domain->flags |= DOMAIN_FLAG_P2P_MULTIPLE_DEVICES;
1794 /* pcie-to-pci bridge already has a domain, uses it */
1796 spin_lock_irqsave(&device_domain_lock, flags);
1797 list_for_each_entry(tmp, &device_domain_list, global) {
1798 if (tmp->segment == segment &&
1799 tmp->bus == bus && tmp->devfn == devfn) {
1800 found = tmp->domain;
1805 free_devinfo_mem(info);
1806 domain_exit(domain);
1809 list_add(&info->link, &domain->devices);
1810 list_add(&info->global, &device_domain_list);
1812 spin_unlock_irqrestore(&device_domain_lock, flags);
1816 info = alloc_devinfo_mem();
1819 info->segment = segment;
1820 info->bus = pdev->bus->number;
1821 info->devfn = pdev->devfn;
1823 info->domain = domain;
1824 spin_lock_irqsave(&device_domain_lock, flags);
1825 /* somebody is fast */
1826 found = find_domain(pdev);
1827 if (found != NULL) {
1828 spin_unlock_irqrestore(&device_domain_lock, flags);
1829 if (found != domain) {
1830 domain_exit(domain);
1833 free_devinfo_mem(info);
1836 list_add(&info->link, &domain->devices);
1837 list_add(&info->global, &device_domain_list);
1838 pdev->dev.archdata.iommu = info;
1839 spin_unlock_irqrestore(&device_domain_lock, flags);
1842 /* recheck it here, maybe others set it */
1843 return find_domain(pdev);
1846 static int iommu_identity_mapping;
1848 static int iommu_prepare_identity_map(struct pci_dev *pdev,
1849 unsigned long long start,
1850 unsigned long long end)
1852 struct dmar_domain *domain;
1854 unsigned long long base;
1858 "IOMMU: Setting identity map for device %s [0x%Lx - 0x%Lx]\n",
1859 pci_name(pdev), start, end);
1860 if (iommu_identity_mapping)
1863 /* page table init */
1864 domain = get_domain_for_dev(pdev, DEFAULT_DOMAIN_ADDRESS_WIDTH);
1868 /* The address might not be aligned */
1869 base = start & PAGE_MASK;
1871 size = PAGE_ALIGN(size);
1872 if (!reserve_iova(&domain->iovad, IOVA_PFN(base),
1873 IOVA_PFN(base + size) - 1)) {
1874 printk(KERN_ERR "IOMMU: reserve iova failed\n");
1879 pr_debug("Mapping reserved region %lx@%llx for %s\n",
1880 size, base, pci_name(pdev));
1882 * RMRR range might have overlap with physical memory range,
1885 dma_pte_clear_range(domain, base, base + size);
1887 ret = domain_page_mapping(domain, base, base, size,
1888 DMA_PTE_READ|DMA_PTE_WRITE);
1892 /* context entry init */
1893 ret = domain_context_mapping(domain, pdev, CONTEXT_TT_MULTI_LEVEL);
1897 domain_exit(domain);
1902 static inline int iommu_prepare_rmrr_dev(struct dmar_rmrr_unit *rmrr,
1903 struct pci_dev *pdev)
1905 if (pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO)
1907 return iommu_prepare_identity_map(pdev, rmrr->base_address,
1908 rmrr->end_address + 1);
1911 #ifdef CONFIG_DMAR_GFX_WA
1912 struct iommu_prepare_data {
1913 struct pci_dev *pdev;
1917 static int __init iommu_prepare_work_fn(unsigned long start_pfn,
1918 unsigned long end_pfn, void *datax)
1920 struct iommu_prepare_data *data;
1922 data = (struct iommu_prepare_data *)datax;
1924 data->ret = iommu_prepare_identity_map(data->pdev,
1925 start_pfn<<PAGE_SHIFT, end_pfn<<PAGE_SHIFT);
1930 static int __init iommu_prepare_with_active_regions(struct pci_dev *pdev)
1933 struct iommu_prepare_data data;
1938 for_each_online_node(nid) {
1939 work_with_active_regions(nid, iommu_prepare_work_fn, &data);
1946 static void __init iommu_prepare_gfx_mapping(void)
1948 struct pci_dev *pdev = NULL;
1951 for_each_pci_dev(pdev) {
1952 if (pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO ||
1953 !IS_GFX_DEVICE(pdev))
1955 printk(KERN_INFO "IOMMU: gfx device %s 1-1 mapping\n",
1957 ret = iommu_prepare_with_active_regions(pdev);
1959 printk(KERN_ERR "IOMMU: mapping reserved region failed\n");
1962 #else /* !CONFIG_DMAR_GFX_WA */
1963 static inline void iommu_prepare_gfx_mapping(void)
1969 #ifdef CONFIG_DMAR_FLOPPY_WA
1970 static inline void iommu_prepare_isa(void)
1972 struct pci_dev *pdev;
1975 pdev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
1979 printk(KERN_INFO "IOMMU: Prepare 0-16M unity mapping for LPC\n");
1980 ret = iommu_prepare_identity_map(pdev, 0, 16*1024*1024);
1983 printk(KERN_ERR "IOMMU: Failed to create 0-64M identity map, "
1984 "floppy might not work\n");
1988 static inline void iommu_prepare_isa(void)
1992 #endif /* !CONFIG_DMAR_FLPY_WA */
1994 /* Initialize each context entry as pass through.*/
1995 static int __init init_context_pass_through(void)
1997 struct pci_dev *pdev = NULL;
1998 struct dmar_domain *domain;
2001 for_each_pci_dev(pdev) {
2002 domain = get_domain_for_dev(pdev, DEFAULT_DOMAIN_ADDRESS_WIDTH);
2003 ret = domain_context_mapping(domain, pdev,
2004 CONTEXT_TT_PASS_THROUGH);
2011 static int md_domain_init(struct dmar_domain *domain, int guest_width);
2012 static int si_domain_init(void)
2014 struct dmar_drhd_unit *drhd;
2015 struct intel_iommu *iommu;
2018 si_domain = alloc_domain();
2023 for_each_active_iommu(iommu, drhd) {
2024 ret = iommu_attach_domain(si_domain, iommu);
2026 domain_exit(si_domain);
2031 if (md_domain_init(si_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) {
2032 domain_exit(si_domain);
2036 si_domain->flags = DOMAIN_FLAG_STATIC_IDENTITY;
2041 static void domain_remove_one_dev_info(struct dmar_domain *domain,
2042 struct pci_dev *pdev);
2043 static int identity_mapping(struct pci_dev *pdev)
2045 struct device_domain_info *info;
2047 if (likely(!iommu_identity_mapping))
2051 list_for_each_entry(info, &si_domain->devices, link)
2052 if (info->dev == pdev)
2057 static int domain_add_dev_info(struct dmar_domain *domain,
2058 struct pci_dev *pdev)
2060 struct device_domain_info *info;
2061 unsigned long flags;
2063 info = alloc_devinfo_mem();
2067 info->segment = pci_domain_nr(pdev->bus);
2068 info->bus = pdev->bus->number;
2069 info->devfn = pdev->devfn;
2071 info->domain = domain;
2073 spin_lock_irqsave(&device_domain_lock, flags);
2074 list_add(&info->link, &domain->devices);
2075 list_add(&info->global, &device_domain_list);
2076 pdev->dev.archdata.iommu = info;
2077 spin_unlock_irqrestore(&device_domain_lock, flags);
2082 static int iommu_prepare_static_identity_mapping(void)
2085 struct pci_dev *pdev = NULL;
2088 ret = si_domain_init();
2092 printk(KERN_INFO "IOMMU: Setting identity map:\n");
2093 for_each_pci_dev(pdev) {
2094 for (i = 0; i < e820.nr_map; i++) {
2095 struct e820entry *ei = &e820.map[i];
2097 if (ei->type == E820_RAM) {
2098 ret = iommu_prepare_identity_map(pdev,
2099 ei->addr, ei->addr + ei->size);
2101 printk(KERN_INFO "1:1 mapping to one domain failed.\n");
2106 ret = domain_add_dev_info(si_domain, pdev);
2114 int __init init_dmars(void)
2116 struct dmar_drhd_unit *drhd;
2117 struct dmar_rmrr_unit *rmrr;
2118 struct pci_dev *pdev;
2119 struct intel_iommu *iommu;
2121 int pass_through = 1;
2124 * In case pass through can not be enabled, iommu tries to use identity
2127 if (iommu_pass_through)
2128 iommu_identity_mapping = 1;
2133 * initialize and program root entry to not present
2136 for_each_drhd_unit(drhd) {
2139 * lock not needed as this is only incremented in the single
2140 * threaded kernel __init code path all other access are read
2145 g_iommus = kcalloc(g_num_of_iommus, sizeof(struct intel_iommu *),
2148 printk(KERN_ERR "Allocating global iommu array failed\n");
2153 deferred_flush = kzalloc(g_num_of_iommus *
2154 sizeof(struct deferred_flush_tables), GFP_KERNEL);
2155 if (!deferred_flush) {
2161 for_each_drhd_unit(drhd) {
2165 iommu = drhd->iommu;
2166 g_iommus[iommu->seq_id] = iommu;
2168 ret = iommu_init_domains(iommu);
2174 * we could share the same root & context tables
2175 * amoung all IOMMU's. Need to Split it later.
2177 ret = iommu_alloc_root_entry(iommu);
2179 printk(KERN_ERR "IOMMU: allocate root entry failed\n");
2182 if (!ecap_pass_through(iommu->ecap))
2185 if (iommu_pass_through)
2186 if (!pass_through) {
2188 "Pass Through is not supported by hardware.\n");
2189 iommu_pass_through = 0;
2193 * Start from the sane iommu hardware state.
2195 for_each_drhd_unit(drhd) {
2199 iommu = drhd->iommu;
2202 * If the queued invalidation is already initialized by us
2203 * (for example, while enabling interrupt-remapping) then
2204 * we got the things already rolling from a sane state.
2210 * Clear any previous faults.
2212 dmar_fault(-1, iommu);
2214 * Disable queued invalidation if supported and already enabled
2215 * before OS handover.
2217 dmar_disable_qi(iommu);
2220 for_each_drhd_unit(drhd) {
2224 iommu = drhd->iommu;
2226 if (dmar_enable_qi(iommu)) {
2228 * Queued Invalidate not enabled, use Register Based
2231 iommu->flush.flush_context = __iommu_flush_context;
2232 iommu->flush.flush_iotlb = __iommu_flush_iotlb;
2233 printk(KERN_INFO "IOMMU 0x%Lx: using Register based "
2235 (unsigned long long)drhd->reg_base_addr);
2237 iommu->flush.flush_context = qi_flush_context;
2238 iommu->flush.flush_iotlb = qi_flush_iotlb;
2239 printk(KERN_INFO "IOMMU 0x%Lx: using Queued "
2241 (unsigned long long)drhd->reg_base_addr);
2246 * If pass through is set and enabled, context entries of all pci
2247 * devices are intialized by pass through translation type.
2249 if (iommu_pass_through) {
2250 ret = init_context_pass_through();
2252 printk(KERN_ERR "IOMMU: Pass through init failed.\n");
2253 iommu_pass_through = 0;
2258 * If pass through is not set or not enabled, setup context entries for
2259 * identity mappings for rmrr, gfx, and isa and may fall back to static
2260 * identity mapping if iommu_identity_mapping is set.
2262 if (!iommu_pass_through) {
2263 if (iommu_identity_mapping)
2264 iommu_prepare_static_identity_mapping();
2267 * for each dev attached to rmrr
2269 * locate drhd for dev, alloc domain for dev
2270 * allocate free domain
2271 * allocate page table entries for rmrr
2272 * if context not allocated for bus
2273 * allocate and init context
2274 * set present in root table for this bus
2275 * init context with domain, translation etc
2279 printk(KERN_INFO "IOMMU: Setting RMRR:\n");
2280 for_each_rmrr_units(rmrr) {
2281 for (i = 0; i < rmrr->devices_cnt; i++) {
2282 pdev = rmrr->devices[i];
2284 * some BIOS lists non-exist devices in DMAR
2289 ret = iommu_prepare_rmrr_dev(rmrr, pdev);
2292 "IOMMU: mapping reserved region failed\n");
2296 iommu_prepare_gfx_mapping();
2298 iommu_prepare_isa();
2304 * global invalidate context cache
2305 * global invalidate iotlb
2306 * enable translation
2308 for_each_drhd_unit(drhd) {
2311 iommu = drhd->iommu;
2313 iommu_flush_write_buffer(iommu);
2315 ret = dmar_set_interrupt(iommu);
2319 iommu_set_root_entry(iommu);
2321 iommu->flush.flush_context(iommu, 0, 0, 0, DMA_CCMD_GLOBAL_INVL);
2322 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
2323 iommu_disable_protect_mem_regions(iommu);
2325 ret = iommu_enable_translation(iommu);
2332 for_each_drhd_unit(drhd) {
2335 iommu = drhd->iommu;
2342 static inline u64 aligned_size(u64 host_addr, size_t size)
2345 addr = (host_addr & (~PAGE_MASK)) + size;
2346 return PAGE_ALIGN(addr);
2350 iommu_alloc_iova(struct dmar_domain *domain, size_t size, u64 end)
2354 /* Make sure it's in range */
2355 end = min_t(u64, DOMAIN_MAX_ADDR(domain->gaw), end);
2356 if (!size || (IOVA_START_ADDR + size > end))
2359 piova = alloc_iova(&domain->iovad,
2360 size >> PAGE_SHIFT, IOVA_PFN(end), 1);
2364 static struct iova *
2365 __intel_alloc_iova(struct device *dev, struct dmar_domain *domain,
2366 size_t size, u64 dma_mask)
2368 struct pci_dev *pdev = to_pci_dev(dev);
2369 struct iova *iova = NULL;
2371 if (dma_mask <= DMA_BIT_MASK(32) || dmar_forcedac)
2372 iova = iommu_alloc_iova(domain, size, dma_mask);
2375 * First try to allocate an io virtual address in
2376 * DMA_BIT_MASK(32) and if that fails then try allocating
2379 iova = iommu_alloc_iova(domain, size, DMA_BIT_MASK(32));
2381 iova = iommu_alloc_iova(domain, size, dma_mask);
2385 printk(KERN_ERR"Allocating iova for %s failed", pci_name(pdev));
2392 static struct dmar_domain *
2393 get_valid_domain_for_dev(struct pci_dev *pdev)
2395 struct dmar_domain *domain;
2398 domain = get_domain_for_dev(pdev,
2399 DEFAULT_DOMAIN_ADDRESS_WIDTH);
2402 "Allocating domain for %s failed", pci_name(pdev));
2406 /* make sure context mapping is ok */
2407 if (unlikely(!domain_context_mapped(pdev))) {
2408 ret = domain_context_mapping(domain, pdev,
2409 CONTEXT_TT_MULTI_LEVEL);
2412 "Domain context map for %s failed",
2421 static int iommu_dummy(struct pci_dev *pdev)
2423 return pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO;
2426 /* Check if the pdev needs to go through non-identity map and unmap process.*/
2427 static int iommu_no_mapping(struct pci_dev *pdev)
2431 if (!iommu_identity_mapping)
2432 return iommu_dummy(pdev);
2434 found = identity_mapping(pdev);
2436 if (pdev->dma_mask > DMA_BIT_MASK(32))
2440 * 32 bit DMA is removed from si_domain and fall back
2441 * to non-identity mapping.
2443 domain_remove_one_dev_info(si_domain, pdev);
2444 printk(KERN_INFO "32bit %s uses non-identity mapping\n",
2450 * In case of a detached 64 bit DMA device from vm, the device
2451 * is put into si_domain for identity mapping.
2453 if (pdev->dma_mask > DMA_BIT_MASK(32)) {
2455 ret = domain_add_dev_info(si_domain, pdev);
2457 printk(KERN_INFO "64bit %s uses identity mapping\n",
2464 return iommu_dummy(pdev);
2467 static dma_addr_t __intel_map_single(struct device *hwdev, phys_addr_t paddr,
2468 size_t size, int dir, u64 dma_mask)
2470 struct pci_dev *pdev = to_pci_dev(hwdev);
2471 struct dmar_domain *domain;
2472 phys_addr_t start_paddr;
2476 struct intel_iommu *iommu;
2478 BUG_ON(dir == DMA_NONE);
2480 if (iommu_no_mapping(pdev))
2483 domain = get_valid_domain_for_dev(pdev);
2487 iommu = domain_get_iommu(domain);
2488 size = aligned_size((u64)paddr, size);
2490 iova = __intel_alloc_iova(hwdev, domain, size, pdev->dma_mask);
2494 start_paddr = (phys_addr_t)iova->pfn_lo << PAGE_SHIFT;
2497 * Check if DMAR supports zero-length reads on write only
2500 if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
2501 !cap_zlr(iommu->cap))
2502 prot |= DMA_PTE_READ;
2503 if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
2504 prot |= DMA_PTE_WRITE;
2506 * paddr - (paddr + size) might be partial page, we should map the whole
2507 * page. Note: if two part of one page are separately mapped, we
2508 * might have two guest_addr mapping to the same host paddr, but this
2509 * is not a big problem
2511 ret = domain_page_mapping(domain, start_paddr,
2512 ((u64)paddr) & PHYSICAL_PAGE_MASK,
2517 /* it's a non-present to present mapping. Only flush if caching mode */
2518 if (cap_caching_mode(iommu->cap))
2519 iommu_flush_iotlb_psi(iommu, 0, start_paddr,
2520 size >> VTD_PAGE_SHIFT);
2522 iommu_flush_write_buffer(iommu);
2524 return start_paddr + ((u64)paddr & (~PAGE_MASK));
2528 __free_iova(&domain->iovad, iova);
2529 printk(KERN_ERR"Device %s request: %zx@%llx dir %d --- failed\n",
2530 pci_name(pdev), size, (unsigned long long)paddr, dir);
2534 static dma_addr_t intel_map_page(struct device *dev, struct page *page,
2535 unsigned long offset, size_t size,
2536 enum dma_data_direction dir,
2537 struct dma_attrs *attrs)
2539 return __intel_map_single(dev, page_to_phys(page) + offset, size,
2540 dir, to_pci_dev(dev)->dma_mask);
2543 static void flush_unmaps(void)
2549 /* just flush them all */
2550 for (i = 0; i < g_num_of_iommus; i++) {
2551 struct intel_iommu *iommu = g_iommus[i];
2555 if (!deferred_flush[i].next)
2558 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
2559 DMA_TLB_GLOBAL_FLUSH);
2560 for (j = 0; j < deferred_flush[i].next; j++) {
2562 struct iova *iova = deferred_flush[i].iova[j];
2564 mask = (iova->pfn_hi - iova->pfn_lo + 1) << PAGE_SHIFT;
2565 mask = ilog2(mask >> VTD_PAGE_SHIFT);
2566 iommu_flush_dev_iotlb(deferred_flush[i].domain[j],
2567 iova->pfn_lo << PAGE_SHIFT, mask);
2568 __free_iova(&deferred_flush[i].domain[j]->iovad, iova);
2570 deferred_flush[i].next = 0;
2576 static void flush_unmaps_timeout(unsigned long data)
2578 unsigned long flags;
2580 spin_lock_irqsave(&async_umap_flush_lock, flags);
2582 spin_unlock_irqrestore(&async_umap_flush_lock, flags);
2585 static void add_unmap(struct dmar_domain *dom, struct iova *iova)
2587 unsigned long flags;
2589 struct intel_iommu *iommu;
2591 spin_lock_irqsave(&async_umap_flush_lock, flags);
2592 if (list_size == HIGH_WATER_MARK)
2595 iommu = domain_get_iommu(dom);
2596 iommu_id = iommu->seq_id;
2598 next = deferred_flush[iommu_id].next;
2599 deferred_flush[iommu_id].domain[next] = dom;
2600 deferred_flush[iommu_id].iova[next] = iova;
2601 deferred_flush[iommu_id].next++;
2604 mod_timer(&unmap_timer, jiffies + msecs_to_jiffies(10));
2608 spin_unlock_irqrestore(&async_umap_flush_lock, flags);
2611 static void intel_unmap_page(struct device *dev, dma_addr_t dev_addr,
2612 size_t size, enum dma_data_direction dir,
2613 struct dma_attrs *attrs)
2615 struct pci_dev *pdev = to_pci_dev(dev);
2616 struct dmar_domain *domain;
2617 unsigned long start_addr;
2619 struct intel_iommu *iommu;
2621 if (iommu_no_mapping(pdev))
2624 domain = find_domain(pdev);
2627 iommu = domain_get_iommu(domain);
2629 iova = find_iova(&domain->iovad, IOVA_PFN(dev_addr));
2633 start_addr = iova->pfn_lo << PAGE_SHIFT;
2634 size = aligned_size((u64)dev_addr, size);
2636 pr_debug("Device %s unmapping: %zx@%llx\n",
2637 pci_name(pdev), size, (unsigned long long)start_addr);
2639 /* clear the whole page */
2640 dma_pte_clear_range(domain, start_addr, start_addr + size);
2641 /* free page tables */
2642 dma_pte_free_pagetable(domain, start_addr, start_addr + size);
2643 if (intel_iommu_strict) {
2644 iommu_flush_iotlb_psi(iommu, domain->id, start_addr,
2645 size >> VTD_PAGE_SHIFT);
2647 __free_iova(&domain->iovad, iova);
2649 add_unmap(domain, iova);
2651 * queue up the release of the unmap to save the 1/6th of the
2652 * cpu used up by the iotlb flush operation...
2657 static void intel_unmap_single(struct device *dev, dma_addr_t dev_addr, size_t size,
2660 intel_unmap_page(dev, dev_addr, size, dir, NULL);
2663 static void *intel_alloc_coherent(struct device *hwdev, size_t size,
2664 dma_addr_t *dma_handle, gfp_t flags)
2669 size = PAGE_ALIGN(size);
2670 order = get_order(size);
2671 flags &= ~(GFP_DMA | GFP_DMA32);
2673 vaddr = (void *)__get_free_pages(flags, order);
2676 memset(vaddr, 0, size);
2678 *dma_handle = __intel_map_single(hwdev, virt_to_bus(vaddr), size,
2680 hwdev->coherent_dma_mask);
2683 free_pages((unsigned long)vaddr, order);
2687 static void intel_free_coherent(struct device *hwdev, size_t size, void *vaddr,
2688 dma_addr_t dma_handle)
2692 size = PAGE_ALIGN(size);
2693 order = get_order(size);
2695 intel_unmap_single(hwdev, dma_handle, size, DMA_BIDIRECTIONAL);
2696 free_pages((unsigned long)vaddr, order);
2699 static void intel_unmap_sg(struct device *hwdev, struct scatterlist *sglist,
2700 int nelems, enum dma_data_direction dir,
2701 struct dma_attrs *attrs)
2704 struct pci_dev *pdev = to_pci_dev(hwdev);
2705 struct dmar_domain *domain;
2706 unsigned long start_addr;
2710 struct scatterlist *sg;
2711 struct intel_iommu *iommu;
2713 if (iommu_no_mapping(pdev))
2716 domain = find_domain(pdev);
2719 iommu = domain_get_iommu(domain);
2721 iova = find_iova(&domain->iovad, IOVA_PFN(sglist[0].dma_address));
2724 for_each_sg(sglist, sg, nelems, i) {
2725 addr = page_to_phys(sg_page(sg)) + sg->offset;
2726 size += aligned_size((u64)addr, sg->length);
2729 start_addr = iova->pfn_lo << PAGE_SHIFT;
2731 /* clear the whole page */
2732 dma_pte_clear_range(domain, start_addr, start_addr + size);
2733 /* free page tables */
2734 dma_pte_free_pagetable(domain, start_addr, start_addr + size);
2736 iommu_flush_iotlb_psi(iommu, domain->id, start_addr,
2737 size >> VTD_PAGE_SHIFT);
2740 __free_iova(&domain->iovad, iova);
2743 static int intel_nontranslate_map_sg(struct device *hddev,
2744 struct scatterlist *sglist, int nelems, int dir)
2747 struct scatterlist *sg;
2749 for_each_sg(sglist, sg, nelems, i) {
2750 BUG_ON(!sg_page(sg));
2751 sg->dma_address = page_to_phys(sg_page(sg)) + sg->offset;
2752 sg->dma_length = sg->length;
2757 static int intel_map_sg(struct device *hwdev, struct scatterlist *sglist, int nelems,
2758 enum dma_data_direction dir, struct dma_attrs *attrs)
2762 struct pci_dev *pdev = to_pci_dev(hwdev);
2763 struct dmar_domain *domain;
2767 struct iova *iova = NULL;
2769 struct scatterlist *sg;
2770 unsigned long start_addr;
2771 struct intel_iommu *iommu;
2773 BUG_ON(dir == DMA_NONE);
2774 if (iommu_no_mapping(pdev))
2775 return intel_nontranslate_map_sg(hwdev, sglist, nelems, dir);
2777 domain = get_valid_domain_for_dev(pdev);
2781 iommu = domain_get_iommu(domain);
2783 for_each_sg(sglist, sg, nelems, i) {
2784 addr = page_to_phys(sg_page(sg)) + sg->offset;
2785 size += aligned_size((u64)addr, sg->length);
2788 iova = __intel_alloc_iova(hwdev, domain, size, pdev->dma_mask);
2790 sglist->dma_length = 0;
2795 * Check if DMAR supports zero-length reads on write only
2798 if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
2799 !cap_zlr(iommu->cap))
2800 prot |= DMA_PTE_READ;
2801 if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
2802 prot |= DMA_PTE_WRITE;
2804 start_addr = iova->pfn_lo << PAGE_SHIFT;
2806 for_each_sg(sglist, sg, nelems, i) {
2807 addr = page_to_phys(sg_page(sg)) + sg->offset;
2808 size = aligned_size((u64)addr, sg->length);
2809 ret = domain_page_mapping(domain, start_addr + offset,
2810 ((u64)addr) & PHYSICAL_PAGE_MASK,
2813 /* clear the page */
2814 dma_pte_clear_range(domain, start_addr,
2815 start_addr + offset);
2816 /* free page tables */
2817 dma_pte_free_pagetable(domain, start_addr,
2818 start_addr + offset);
2820 __free_iova(&domain->iovad, iova);
2823 sg->dma_address = start_addr + offset +
2824 ((u64)addr & (~PAGE_MASK));
2825 sg->dma_length = sg->length;
2829 /* it's a non-present to present mapping. Only flush if caching mode */
2830 if (cap_caching_mode(iommu->cap))
2831 iommu_flush_iotlb_psi(iommu, 0, start_addr,
2832 offset >> VTD_PAGE_SHIFT);
2834 iommu_flush_write_buffer(iommu);
2839 static int intel_mapping_error(struct device *dev, dma_addr_t dma_addr)
2844 struct dma_map_ops intel_dma_ops = {
2845 .alloc_coherent = intel_alloc_coherent,
2846 .free_coherent = intel_free_coherent,
2847 .map_sg = intel_map_sg,
2848 .unmap_sg = intel_unmap_sg,
2849 .map_page = intel_map_page,
2850 .unmap_page = intel_unmap_page,
2851 .mapping_error = intel_mapping_error,
2854 static inline int iommu_domain_cache_init(void)
2858 iommu_domain_cache = kmem_cache_create("iommu_domain",
2859 sizeof(struct dmar_domain),
2864 if (!iommu_domain_cache) {
2865 printk(KERN_ERR "Couldn't create iommu_domain cache\n");
2872 static inline int iommu_devinfo_cache_init(void)
2876 iommu_devinfo_cache = kmem_cache_create("iommu_devinfo",
2877 sizeof(struct device_domain_info),
2881 if (!iommu_devinfo_cache) {
2882 printk(KERN_ERR "Couldn't create devinfo cache\n");
2889 static inline int iommu_iova_cache_init(void)
2893 iommu_iova_cache = kmem_cache_create("iommu_iova",
2894 sizeof(struct iova),
2898 if (!iommu_iova_cache) {
2899 printk(KERN_ERR "Couldn't create iova cache\n");
2906 static int __init iommu_init_mempool(void)
2909 ret = iommu_iova_cache_init();
2913 ret = iommu_domain_cache_init();
2917 ret = iommu_devinfo_cache_init();
2921 kmem_cache_destroy(iommu_domain_cache);
2923 kmem_cache_destroy(iommu_iova_cache);
2928 static void __init iommu_exit_mempool(void)
2930 kmem_cache_destroy(iommu_devinfo_cache);
2931 kmem_cache_destroy(iommu_domain_cache);
2932 kmem_cache_destroy(iommu_iova_cache);
2936 static void __init init_no_remapping_devices(void)
2938 struct dmar_drhd_unit *drhd;
2940 for_each_drhd_unit(drhd) {
2941 if (!drhd->include_all) {
2943 for (i = 0; i < drhd->devices_cnt; i++)
2944 if (drhd->devices[i] != NULL)
2946 /* ignore DMAR unit if no pci devices exist */
2947 if (i == drhd->devices_cnt)
2955 for_each_drhd_unit(drhd) {
2957 if (drhd->ignored || drhd->include_all)
2960 for (i = 0; i < drhd->devices_cnt; i++)
2961 if (drhd->devices[i] &&
2962 !IS_GFX_DEVICE(drhd->devices[i]))
2965 if (i < drhd->devices_cnt)
2968 /* bypass IOMMU if it is just for gfx devices */
2970 for (i = 0; i < drhd->devices_cnt; i++) {
2971 if (!drhd->devices[i])
2973 drhd->devices[i]->dev.archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO;
2978 #ifdef CONFIG_SUSPEND
2979 static int init_iommu_hw(void)
2981 struct dmar_drhd_unit *drhd;
2982 struct intel_iommu *iommu = NULL;
2984 for_each_active_iommu(iommu, drhd)
2986 dmar_reenable_qi(iommu);
2988 for_each_active_iommu(iommu, drhd) {
2989 iommu_flush_write_buffer(iommu);
2991 iommu_set_root_entry(iommu);
2993 iommu->flush.flush_context(iommu, 0, 0, 0,
2994 DMA_CCMD_GLOBAL_INVL);
2995 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
2996 DMA_TLB_GLOBAL_FLUSH);
2997 iommu_disable_protect_mem_regions(iommu);
2998 iommu_enable_translation(iommu);
3004 static void iommu_flush_all(void)
3006 struct dmar_drhd_unit *drhd;
3007 struct intel_iommu *iommu;
3009 for_each_active_iommu(iommu, drhd) {
3010 iommu->flush.flush_context(iommu, 0, 0, 0,
3011 DMA_CCMD_GLOBAL_INVL);
3012 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
3013 DMA_TLB_GLOBAL_FLUSH);
3017 static int iommu_suspend(struct sys_device *dev, pm_message_t state)
3019 struct dmar_drhd_unit *drhd;
3020 struct intel_iommu *iommu = NULL;
3023 for_each_active_iommu(iommu, drhd) {
3024 iommu->iommu_state = kzalloc(sizeof(u32) * MAX_SR_DMAR_REGS,
3026 if (!iommu->iommu_state)
3032 for_each_active_iommu(iommu, drhd) {
3033 iommu_disable_translation(iommu);
3035 spin_lock_irqsave(&iommu->register_lock, flag);
3037 iommu->iommu_state[SR_DMAR_FECTL_REG] =
3038 readl(iommu->reg + DMAR_FECTL_REG);
3039 iommu->iommu_state[SR_DMAR_FEDATA_REG] =
3040 readl(iommu->reg + DMAR_FEDATA_REG);
3041 iommu->iommu_state[SR_DMAR_FEADDR_REG] =
3042 readl(iommu->reg + DMAR_FEADDR_REG);
3043 iommu->iommu_state[SR_DMAR_FEUADDR_REG] =
3044 readl(iommu->reg + DMAR_FEUADDR_REG);
3046 spin_unlock_irqrestore(&iommu->register_lock, flag);
3051 for_each_active_iommu(iommu, drhd)
3052 kfree(iommu->iommu_state);
3057 static int iommu_resume(struct sys_device *dev)
3059 struct dmar_drhd_unit *drhd;
3060 struct intel_iommu *iommu = NULL;
3063 if (init_iommu_hw()) {
3064 WARN(1, "IOMMU setup failed, DMAR can not resume!\n");
3068 for_each_active_iommu(iommu, drhd) {
3070 spin_lock_irqsave(&iommu->register_lock, flag);
3072 writel(iommu->iommu_state[SR_DMAR_FECTL_REG],
3073 iommu->reg + DMAR_FECTL_REG);
3074 writel(iommu->iommu_state[SR_DMAR_FEDATA_REG],
3075 iommu->reg + DMAR_FEDATA_REG);
3076 writel(iommu->iommu_state[SR_DMAR_FEADDR_REG],
3077 iommu->reg + DMAR_FEADDR_REG);
3078 writel(iommu->iommu_state[SR_DMAR_FEUADDR_REG],
3079 iommu->reg + DMAR_FEUADDR_REG);
3081 spin_unlock_irqrestore(&iommu->register_lock, flag);
3084 for_each_active_iommu(iommu, drhd)
3085 kfree(iommu->iommu_state);
3090 static struct sysdev_class iommu_sysclass = {
3092 .resume = iommu_resume,
3093 .suspend = iommu_suspend,
3096 static struct sys_device device_iommu = {
3097 .cls = &iommu_sysclass,
3100 static int __init init_iommu_sysfs(void)
3104 error = sysdev_class_register(&iommu_sysclass);
3108 error = sysdev_register(&device_iommu);
3110 sysdev_class_unregister(&iommu_sysclass);
3116 static int __init init_iommu_sysfs(void)
3120 #endif /* CONFIG_PM */
3122 int __init intel_iommu_init(void)
3126 if (dmar_table_init())
3129 if (dmar_dev_scope_init())
3133 * Check the need for DMA-remapping initialization now.
3134 * Above initialization will also be used by Interrupt-remapping.
3136 if (no_iommu || (swiotlb && !iommu_pass_through) || dmar_disabled)
3139 iommu_init_mempool();
3140 dmar_init_reserved_ranges();
3142 init_no_remapping_devices();
3146 printk(KERN_ERR "IOMMU: dmar init failed\n");
3147 put_iova_domain(&reserved_iova_list);
3148 iommu_exit_mempool();
3152 "PCI-DMA: Intel(R) Virtualization Technology for Directed I/O\n");
3154 init_timer(&unmap_timer);
3157 if (!iommu_pass_through) {
3159 "Multi-level page-table translation for DMAR.\n");
3160 dma_ops = &intel_dma_ops;
3163 "DMAR: Pass through translation for DMAR.\n");
3167 register_iommu(&intel_iommu_ops);
3172 static void iommu_detach_dependent_devices(struct intel_iommu *iommu,
3173 struct pci_dev *pdev)
3175 struct pci_dev *tmp, *parent;
3177 if (!iommu || !pdev)
3180 /* dependent device detach */
3181 tmp = pci_find_upstream_pcie_bridge(pdev);
3182 /* Secondary interface's bus number and devfn 0 */
3184 parent = pdev->bus->self;
3185 while (parent != tmp) {
3186 iommu_detach_dev(iommu, parent->bus->number,
3188 parent = parent->bus->self;
3190 if (tmp->is_pcie) /* this is a PCIE-to-PCI bridge */
3191 iommu_detach_dev(iommu,
3192 tmp->subordinate->number, 0);
3193 else /* this is a legacy PCI bridge */
3194 iommu_detach_dev(iommu, tmp->bus->number,
3199 static void domain_remove_one_dev_info(struct dmar_domain *domain,
3200 struct pci_dev *pdev)
3202 struct device_domain_info *info;
3203 struct intel_iommu *iommu;
3204 unsigned long flags;
3206 struct list_head *entry, *tmp;
3208 iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
3213 spin_lock_irqsave(&device_domain_lock, flags);
3214 list_for_each_safe(entry, tmp, &domain->devices) {
3215 info = list_entry(entry, struct device_domain_info, link);
3216 /* No need to compare PCI domain; it has to be the same */
3217 if (info->bus == pdev->bus->number &&
3218 info->devfn == pdev->devfn) {
3219 list_del(&info->link);
3220 list_del(&info->global);
3222 info->dev->dev.archdata.iommu = NULL;
3223 spin_unlock_irqrestore(&device_domain_lock, flags);
3225 iommu_disable_dev_iotlb(info);
3226 iommu_detach_dev(iommu, info->bus, info->devfn);
3227 iommu_detach_dependent_devices(iommu, pdev);
3228 free_devinfo_mem(info);
3230 spin_lock_irqsave(&device_domain_lock, flags);
3238 /* if there is no other devices under the same iommu
3239 * owned by this domain, clear this iommu in iommu_bmp
3240 * update iommu count and coherency
3242 if (iommu == device_to_iommu(info->segment, info->bus,
3248 unsigned long tmp_flags;
3249 spin_lock_irqsave(&domain->iommu_lock, tmp_flags);
3250 clear_bit(iommu->seq_id, &domain->iommu_bmp);
3251 domain->iommu_count--;
3252 domain_update_iommu_cap(domain);
3253 spin_unlock_irqrestore(&domain->iommu_lock, tmp_flags);
3256 spin_unlock_irqrestore(&device_domain_lock, flags);
3259 static void vm_domain_remove_all_dev_info(struct dmar_domain *domain)
3261 struct device_domain_info *info;
3262 struct intel_iommu *iommu;
3263 unsigned long flags1, flags2;
3265 spin_lock_irqsave(&device_domain_lock, flags1);
3266 while (!list_empty(&domain->devices)) {
3267 info = list_entry(domain->devices.next,
3268 struct device_domain_info, link);
3269 list_del(&info->link);
3270 list_del(&info->global);
3272 info->dev->dev.archdata.iommu = NULL;
3274 spin_unlock_irqrestore(&device_domain_lock, flags1);
3276 iommu_disable_dev_iotlb(info);
3277 iommu = device_to_iommu(info->segment, info->bus, info->devfn);
3278 iommu_detach_dev(iommu, info->bus, info->devfn);
3279 iommu_detach_dependent_devices(iommu, info->dev);
3281 /* clear this iommu in iommu_bmp, update iommu count
3284 spin_lock_irqsave(&domain->iommu_lock, flags2);
3285 if (test_and_clear_bit(iommu->seq_id,
3286 &domain->iommu_bmp)) {
3287 domain->iommu_count--;
3288 domain_update_iommu_cap(domain);
3290 spin_unlock_irqrestore(&domain->iommu_lock, flags2);
3292 free_devinfo_mem(info);
3293 spin_lock_irqsave(&device_domain_lock, flags1);
3295 spin_unlock_irqrestore(&device_domain_lock, flags1);
3298 /* domain id for virtual machine, it won't be set in context */
3299 static unsigned long vm_domid;
3301 static int vm_domain_min_agaw(struct dmar_domain *domain)
3304 int min_agaw = domain->agaw;
3306 i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
3307 for (; i < g_num_of_iommus; ) {
3308 if (min_agaw > g_iommus[i]->agaw)
3309 min_agaw = g_iommus[i]->agaw;
3311 i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1);
3317 static struct dmar_domain *iommu_alloc_vm_domain(void)
3319 struct dmar_domain *domain;
3321 domain = alloc_domain_mem();
3325 domain->id = vm_domid++;
3326 memset(&domain->iommu_bmp, 0, sizeof(unsigned long));
3327 domain->flags = DOMAIN_FLAG_VIRTUAL_MACHINE;
3332 static int md_domain_init(struct dmar_domain *domain, int guest_width)
3336 init_iova_domain(&domain->iovad, DMA_32BIT_PFN);
3337 spin_lock_init(&domain->mapping_lock);
3338 spin_lock_init(&domain->iommu_lock);
3340 domain_reserve_special_ranges(domain);
3342 /* calculate AGAW */
3343 domain->gaw = guest_width;
3344 adjust_width = guestwidth_to_adjustwidth(guest_width);
3345 domain->agaw = width_to_agaw(adjust_width);
3347 INIT_LIST_HEAD(&domain->devices);
3349 domain->iommu_count = 0;
3350 domain->iommu_coherency = 0;
3351 domain->max_addr = 0;
3353 /* always allocate the top pgd */
3354 domain->pgd = (struct dma_pte *)alloc_pgtable_page();
3357 domain_flush_cache(domain, domain->pgd, PAGE_SIZE);
3361 static void iommu_free_vm_domain(struct dmar_domain *domain)
3363 unsigned long flags;
3364 struct dmar_drhd_unit *drhd;
3365 struct intel_iommu *iommu;
3367 unsigned long ndomains;
3369 for_each_drhd_unit(drhd) {
3372 iommu = drhd->iommu;
3374 ndomains = cap_ndoms(iommu->cap);
3375 i = find_first_bit(iommu->domain_ids, ndomains);
3376 for (; i < ndomains; ) {
3377 if (iommu->domains[i] == domain) {
3378 spin_lock_irqsave(&iommu->lock, flags);
3379 clear_bit(i, iommu->domain_ids);
3380 iommu->domains[i] = NULL;
3381 spin_unlock_irqrestore(&iommu->lock, flags);
3384 i = find_next_bit(iommu->domain_ids, ndomains, i+1);
3389 static void vm_domain_exit(struct dmar_domain *domain)
3393 /* Domain 0 is reserved, so dont process it */
3397 vm_domain_remove_all_dev_info(domain);
3399 put_iova_domain(&domain->iovad);
3400 end = DOMAIN_MAX_ADDR(domain->gaw);
3401 end = end & (~VTD_PAGE_MASK);
3404 dma_pte_clear_range(domain, 0, end);
3406 /* free page tables */
3407 dma_pte_free_pagetable(domain, 0, end);
3409 iommu_free_vm_domain(domain);
3410 free_domain_mem(domain);
3413 static int intel_iommu_domain_init(struct iommu_domain *domain)
3415 struct dmar_domain *dmar_domain;
3417 dmar_domain = iommu_alloc_vm_domain();
3420 "intel_iommu_domain_init: dmar_domain == NULL\n");
3423 if (md_domain_init(dmar_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) {
3425 "intel_iommu_domain_init() failed\n");
3426 vm_domain_exit(dmar_domain);
3429 domain->priv = dmar_domain;
3434 static void intel_iommu_domain_destroy(struct iommu_domain *domain)
3436 struct dmar_domain *dmar_domain = domain->priv;
3438 domain->priv = NULL;
3439 vm_domain_exit(dmar_domain);
3442 static int intel_iommu_attach_device(struct iommu_domain *domain,
3445 struct dmar_domain *dmar_domain = domain->priv;
3446 struct pci_dev *pdev = to_pci_dev(dev);
3447 struct intel_iommu *iommu;
3452 /* normally pdev is not mapped */
3453 if (unlikely(domain_context_mapped(pdev))) {
3454 struct dmar_domain *old_domain;
3456 old_domain = find_domain(pdev);
3458 if (dmar_domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE ||
3459 dmar_domain->flags & DOMAIN_FLAG_STATIC_IDENTITY)
3460 domain_remove_one_dev_info(old_domain, pdev);
3462 domain_remove_dev_info(old_domain);
3466 iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
3471 /* check if this iommu agaw is sufficient for max mapped address */
3472 addr_width = agaw_to_width(iommu->agaw);
3473 end = DOMAIN_MAX_ADDR(addr_width);
3474 end = end & VTD_PAGE_MASK;
3475 if (end < dmar_domain->max_addr) {
3476 printk(KERN_ERR "%s: iommu agaw (%d) is not "
3477 "sufficient for the mapped address (%llx)\n",
3478 __func__, iommu->agaw, dmar_domain->max_addr);
3482 ret = domain_add_dev_info(dmar_domain, pdev);
3486 ret = domain_context_mapping(dmar_domain, pdev, CONTEXT_TT_MULTI_LEVEL);
3490 static void intel_iommu_detach_device(struct iommu_domain *domain,
3493 struct dmar_domain *dmar_domain = domain->priv;
3494 struct pci_dev *pdev = to_pci_dev(dev);
3496 domain_remove_one_dev_info(dmar_domain, pdev);
3499 static int intel_iommu_map_range(struct iommu_domain *domain,
3500 unsigned long iova, phys_addr_t hpa,
3501 size_t size, int iommu_prot)
3503 struct dmar_domain *dmar_domain = domain->priv;
3509 if (iommu_prot & IOMMU_READ)
3510 prot |= DMA_PTE_READ;
3511 if (iommu_prot & IOMMU_WRITE)
3512 prot |= DMA_PTE_WRITE;
3513 if ((iommu_prot & IOMMU_CACHE) && dmar_domain->iommu_snooping)
3514 prot |= DMA_PTE_SNP;
3516 max_addr = (iova & VTD_PAGE_MASK) + VTD_PAGE_ALIGN(size);
3517 if (dmar_domain->max_addr < max_addr) {
3521 /* check if minimum agaw is sufficient for mapped address */
3522 min_agaw = vm_domain_min_agaw(dmar_domain);
3523 addr_width = agaw_to_width(min_agaw);
3524 end = DOMAIN_MAX_ADDR(addr_width);
3525 end = end & VTD_PAGE_MASK;
3526 if (end < max_addr) {
3527 printk(KERN_ERR "%s: iommu agaw (%d) is not "
3528 "sufficient for the mapped address (%llx)\n",
3529 __func__, min_agaw, max_addr);
3532 dmar_domain->max_addr = max_addr;
3535 ret = domain_page_mapping(dmar_domain, iova, hpa, size, prot);
3539 static void intel_iommu_unmap_range(struct iommu_domain *domain,
3540 unsigned long iova, size_t size)
3542 struct dmar_domain *dmar_domain = domain->priv;
3545 /* The address might not be aligned */
3546 base = iova & VTD_PAGE_MASK;
3547 size = VTD_PAGE_ALIGN(size);
3548 dma_pte_clear_range(dmar_domain, base, base + size);
3550 if (dmar_domain->max_addr == base + size)
3551 dmar_domain->max_addr = base;
3554 static phys_addr_t intel_iommu_iova_to_phys(struct iommu_domain *domain,
3557 struct dmar_domain *dmar_domain = domain->priv;
3558 struct dma_pte *pte;
3561 pte = addr_to_dma_pte(dmar_domain, iova);
3563 phys = dma_pte_addr(pte);
3568 static int intel_iommu_domain_has_cap(struct iommu_domain *domain,
3571 struct dmar_domain *dmar_domain = domain->priv;
3573 if (cap == IOMMU_CAP_CACHE_COHERENCY)
3574 return dmar_domain->iommu_snooping;
3579 static struct iommu_ops intel_iommu_ops = {
3580 .domain_init = intel_iommu_domain_init,
3581 .domain_destroy = intel_iommu_domain_destroy,
3582 .attach_dev = intel_iommu_attach_device,
3583 .detach_dev = intel_iommu_detach_device,
3584 .map = intel_iommu_map_range,
3585 .unmap = intel_iommu_unmap_range,
3586 .iova_to_phys = intel_iommu_iova_to_phys,
3587 .domain_has_cap = intel_iommu_domain_has_cap,
3590 static void __devinit quirk_iommu_rwbf(struct pci_dev *dev)
3593 * Mobile 4 Series Chipset neglects to set RWBF capability,
3596 printk(KERN_INFO "DMAR: Forcing write-buffer flush capability\n");
3600 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_rwbf);