2 * Copyright (c) 2006, Intel Corporation.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
15 * Place - Suite 330, Boston, MA 02111-1307 USA.
17 * Copyright (C) 2006-2008 Intel Corporation
18 * Author: Ashok Raj <ashok.raj@intel.com>
19 * Author: Shaohua Li <shaohua.li@intel.com>
20 * Author: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
21 * Author: Fenghua Yu <fenghua.yu@intel.com>
24 #include <linux/init.h>
25 #include <linux/bitmap.h>
26 #include <linux/debugfs.h>
27 #include <linux/slab.h>
28 #include <linux/irq.h>
29 #include <linux/interrupt.h>
30 #include <linux/spinlock.h>
31 #include <linux/pci.h>
32 #include <linux/dmar.h>
33 #include <linux/dma-mapping.h>
34 #include <linux/mempool.h>
35 #include <linux/timer.h>
36 #include <linux/iova.h>
37 #include <linux/iommu.h>
38 #include <linux/intel-iommu.h>
39 #include <linux/sysdev.h>
40 #include <linux/tboot.h>
41 #include <linux/dmi.h>
42 #include <asm/cacheflush.h>
43 #include <asm/iommu.h>
46 #define ROOT_SIZE VTD_PAGE_SIZE
47 #define CONTEXT_SIZE VTD_PAGE_SIZE
49 #define IS_GFX_DEVICE(pdev) ((pdev->class >> 16) == PCI_BASE_CLASS_DISPLAY)
50 #define IS_ISA_DEVICE(pdev) ((pdev->class >> 8) == PCI_CLASS_BRIDGE_ISA)
52 #define IOAPIC_RANGE_START (0xfee00000)
53 #define IOAPIC_RANGE_END (0xfeefffff)
54 #define IOVA_START_ADDR (0x1000)
56 #define DEFAULT_DOMAIN_ADDRESS_WIDTH 48
58 #define MAX_AGAW_WIDTH 64
60 #define __DOMAIN_MAX_PFN(gaw) ((((uint64_t)1) << (gaw-VTD_PAGE_SHIFT)) - 1)
61 #define __DOMAIN_MAX_ADDR(gaw) ((((uint64_t)1) << gaw) - 1)
63 /* We limit DOMAIN_MAX_PFN to fit in an unsigned long, and DOMAIN_MAX_ADDR
64 to match. That way, we can use 'unsigned long' for PFNs with impunity. */
65 #define DOMAIN_MAX_PFN(gaw) ((unsigned long) min_t(uint64_t, \
66 __DOMAIN_MAX_PFN(gaw), (unsigned long)-1))
67 #define DOMAIN_MAX_ADDR(gaw) (((uint64_t)__DOMAIN_MAX_PFN(gaw)) << VTD_PAGE_SHIFT)
69 #define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
70 #define DMA_32BIT_PFN IOVA_PFN(DMA_BIT_MASK(32))
71 #define DMA_64BIT_PFN IOVA_PFN(DMA_BIT_MASK(64))
74 /* VT-d pages must always be _smaller_ than MM pages. Otherwise things
75 are never going to work. */
76 static inline unsigned long dma_to_mm_pfn(unsigned long dma_pfn)
78 return dma_pfn >> (PAGE_SHIFT - VTD_PAGE_SHIFT);
81 static inline unsigned long mm_to_dma_pfn(unsigned long mm_pfn)
83 return mm_pfn << (PAGE_SHIFT - VTD_PAGE_SHIFT);
85 static inline unsigned long page_to_dma_pfn(struct page *pg)
87 return mm_to_dma_pfn(page_to_pfn(pg));
89 static inline unsigned long virt_to_dma_pfn(void *p)
91 return page_to_dma_pfn(virt_to_page(p));
94 /* global iommu list, set NULL for ignored DMAR units */
95 static struct intel_iommu **g_iommus;
97 static int rwbf_quirk;
102 * 12-63: Context Ptr (12 - (haw-1))
109 #define ROOT_ENTRY_NR (VTD_PAGE_SIZE/sizeof(struct root_entry))
110 static inline bool root_present(struct root_entry *root)
112 return (root->val & 1);
114 static inline void set_root_present(struct root_entry *root)
118 static inline void set_root_value(struct root_entry *root, unsigned long value)
120 root->val |= value & VTD_PAGE_MASK;
123 static inline struct context_entry *
124 get_context_addr_from_root(struct root_entry *root)
126 return (struct context_entry *)
127 (root_present(root)?phys_to_virt(
128 root->val & VTD_PAGE_MASK) :
135 * 1: fault processing disable
136 * 2-3: translation type
137 * 12-63: address space root
143 struct context_entry {
148 static inline bool context_present(struct context_entry *context)
150 return (context->lo & 1);
152 static inline void context_set_present(struct context_entry *context)
157 static inline void context_set_fault_enable(struct context_entry *context)
159 context->lo &= (((u64)-1) << 2) | 1;
162 static inline void context_set_translation_type(struct context_entry *context,
165 context->lo &= (((u64)-1) << 4) | 3;
166 context->lo |= (value & 3) << 2;
169 static inline void context_set_address_root(struct context_entry *context,
172 context->lo |= value & VTD_PAGE_MASK;
175 static inline void context_set_address_width(struct context_entry *context,
178 context->hi |= value & 7;
181 static inline void context_set_domain_id(struct context_entry *context,
184 context->hi |= (value & ((1 << 16) - 1)) << 8;
187 static inline void context_clear_entry(struct context_entry *context)
200 * 12-63: Host physcial address
206 static inline void dma_clear_pte(struct dma_pte *pte)
211 static inline void dma_set_pte_readable(struct dma_pte *pte)
213 pte->val |= DMA_PTE_READ;
216 static inline void dma_set_pte_writable(struct dma_pte *pte)
218 pte->val |= DMA_PTE_WRITE;
221 static inline void dma_set_pte_snp(struct dma_pte *pte)
223 pte->val |= DMA_PTE_SNP;
226 static inline void dma_set_pte_prot(struct dma_pte *pte, unsigned long prot)
228 pte->val = (pte->val & ~3) | (prot & 3);
231 static inline u64 dma_pte_addr(struct dma_pte *pte)
234 return pte->val & VTD_PAGE_MASK;
236 /* Must have a full atomic 64-bit read */
237 return __cmpxchg64(pte, 0ULL, 0ULL) & VTD_PAGE_MASK;
241 static inline void dma_set_pte_pfn(struct dma_pte *pte, unsigned long pfn)
243 pte->val |= (uint64_t)pfn << VTD_PAGE_SHIFT;
246 static inline bool dma_pte_present(struct dma_pte *pte)
248 return (pte->val & 3) != 0;
251 static inline int first_pte_in_page(struct dma_pte *pte)
253 return !((unsigned long)pte & ~VTD_PAGE_MASK);
257 * This domain is a statically identity mapping domain.
258 * 1. This domain creats a static 1:1 mapping to all usable memory.
259 * 2. It maps to each iommu if successful.
260 * 3. Each iommu mapps to this domain if successful.
262 static struct dmar_domain *si_domain;
263 static int hw_pass_through = 1;
265 /* devices under the same p2p bridge are owned in one domain */
266 #define DOMAIN_FLAG_P2P_MULTIPLE_DEVICES (1 << 0)
268 /* domain represents a virtual machine, more than one devices
269 * across iommus may be owned in one domain, e.g. kvm guest.
271 #define DOMAIN_FLAG_VIRTUAL_MACHINE (1 << 1)
273 /* si_domain contains mulitple devices */
274 #define DOMAIN_FLAG_STATIC_IDENTITY (1 << 2)
277 int id; /* domain id */
278 unsigned long iommu_bmp; /* bitmap of iommus this domain uses*/
280 struct list_head devices; /* all devices' list */
281 struct iova_domain iovad; /* iova's that belong to this domain */
283 struct dma_pte *pgd; /* virtual address */
284 int gaw; /* max guest address width */
286 /* adjusted guest address width, 0 is level 2 30-bit */
289 int flags; /* flags to find out type of domain */
291 int iommu_coherency;/* indicate coherency of iommu access */
292 int iommu_snooping; /* indicate snooping control feature*/
293 int iommu_count; /* reference count of iommu */
294 spinlock_t iommu_lock; /* protect iommu set in domain */
295 u64 max_addr; /* maximum mapped address */
298 /* PCI domain-device relationship */
299 struct device_domain_info {
300 struct list_head link; /* link to domain siblings */
301 struct list_head global; /* link to global list */
302 int segment; /* PCI domain */
303 u8 bus; /* PCI bus number */
304 u8 devfn; /* PCI devfn number */
305 struct pci_dev *dev; /* it's NULL for PCIE-to-PCI bridge */
306 struct intel_iommu *iommu; /* IOMMU used by this device */
307 struct dmar_domain *domain; /* pointer to domain */
310 static void flush_unmaps_timeout(unsigned long data);
312 DEFINE_TIMER(unmap_timer, flush_unmaps_timeout, 0, 0);
314 #define HIGH_WATER_MARK 250
315 struct deferred_flush_tables {
317 struct iova *iova[HIGH_WATER_MARK];
318 struct dmar_domain *domain[HIGH_WATER_MARK];
321 static struct deferred_flush_tables *deferred_flush;
323 /* bitmap for indexing intel_iommus */
324 static int g_num_of_iommus;
326 static DEFINE_SPINLOCK(async_umap_flush_lock);
327 static LIST_HEAD(unmaps_to_do);
330 static long list_size;
332 static void domain_remove_dev_info(struct dmar_domain *domain);
334 #ifdef CONFIG_DMAR_DEFAULT_ON
335 int dmar_disabled = 0;
337 int dmar_disabled = 1;
338 #endif /*CONFIG_DMAR_DEFAULT_ON*/
340 static int __initdata dmar_map_gfx = 1;
341 static int dmar_forcedac;
342 static int intel_iommu_strict;
344 #define DUMMY_DEVICE_DOMAIN_INFO ((struct device_domain_info *)(-1))
345 static DEFINE_SPINLOCK(device_domain_lock);
346 static LIST_HEAD(device_domain_list);
348 static struct iommu_ops intel_iommu_ops;
350 static int __init intel_iommu_setup(char *str)
355 if (!strncmp(str, "on", 2)) {
357 printk(KERN_INFO "Intel-IOMMU: enabled\n");
358 } else if (!strncmp(str, "off", 3)) {
360 printk(KERN_INFO "Intel-IOMMU: disabled\n");
361 } else if (!strncmp(str, "igfx_off", 8)) {
364 "Intel-IOMMU: disable GFX device mapping\n");
365 } else if (!strncmp(str, "forcedac", 8)) {
367 "Intel-IOMMU: Forcing DAC for PCI devices\n");
369 } else if (!strncmp(str, "strict", 6)) {
371 "Intel-IOMMU: disable batched IOTLB flush\n");
372 intel_iommu_strict = 1;
375 str += strcspn(str, ",");
381 __setup("intel_iommu=", intel_iommu_setup);
383 static struct kmem_cache *iommu_domain_cache;
384 static struct kmem_cache *iommu_devinfo_cache;
385 static struct kmem_cache *iommu_iova_cache;
387 static inline void *iommu_kmem_cache_alloc(struct kmem_cache *cachep)
392 /* trying to avoid low memory issues */
393 flags = current->flags & PF_MEMALLOC;
394 current->flags |= PF_MEMALLOC;
395 vaddr = kmem_cache_alloc(cachep, GFP_ATOMIC);
396 current->flags &= (~PF_MEMALLOC | flags);
401 static inline void *alloc_pgtable_page(void)
406 /* trying to avoid low memory issues */
407 flags = current->flags & PF_MEMALLOC;
408 current->flags |= PF_MEMALLOC;
409 vaddr = (void *)get_zeroed_page(GFP_ATOMIC);
410 current->flags &= (~PF_MEMALLOC | flags);
414 static inline void free_pgtable_page(void *vaddr)
416 free_page((unsigned long)vaddr);
419 static inline void *alloc_domain_mem(void)
421 return iommu_kmem_cache_alloc(iommu_domain_cache);
424 static void free_domain_mem(void *vaddr)
426 kmem_cache_free(iommu_domain_cache, vaddr);
429 static inline void * alloc_devinfo_mem(void)
431 return iommu_kmem_cache_alloc(iommu_devinfo_cache);
434 static inline void free_devinfo_mem(void *vaddr)
436 kmem_cache_free(iommu_devinfo_cache, vaddr);
439 struct iova *alloc_iova_mem(void)
441 return iommu_kmem_cache_alloc(iommu_iova_cache);
444 void free_iova_mem(struct iova *iova)
446 kmem_cache_free(iommu_iova_cache, iova);
450 static inline int width_to_agaw(int width);
452 static int __iommu_calculate_agaw(struct intel_iommu *iommu, int max_gaw)
457 sagaw = cap_sagaw(iommu->cap);
458 for (agaw = width_to_agaw(max_gaw);
460 if (test_bit(agaw, &sagaw))
468 * Calculate max SAGAW for each iommu.
470 int iommu_calculate_max_sagaw(struct intel_iommu *iommu)
472 return __iommu_calculate_agaw(iommu, MAX_AGAW_WIDTH);
476 * calculate agaw for each iommu.
477 * "SAGAW" may be different across iommus, use a default agaw, and
478 * get a supported less agaw for iommus that don't support the default agaw.
480 int iommu_calculate_agaw(struct intel_iommu *iommu)
482 return __iommu_calculate_agaw(iommu, DEFAULT_DOMAIN_ADDRESS_WIDTH);
485 /* This functionin only returns single iommu in a domain */
486 static struct intel_iommu *domain_get_iommu(struct dmar_domain *domain)
490 /* si_domain and vm domain should not get here. */
491 BUG_ON(domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE);
492 BUG_ON(domain->flags & DOMAIN_FLAG_STATIC_IDENTITY);
494 iommu_id = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
495 if (iommu_id < 0 || iommu_id >= g_num_of_iommus)
498 return g_iommus[iommu_id];
501 static void domain_update_iommu_coherency(struct dmar_domain *domain)
505 domain->iommu_coherency = 1;
507 i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
508 for (; i < g_num_of_iommus; ) {
509 if (!ecap_coherent(g_iommus[i]->ecap)) {
510 domain->iommu_coherency = 0;
513 i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1);
517 static void domain_update_iommu_snooping(struct dmar_domain *domain)
521 domain->iommu_snooping = 1;
523 i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
524 for (; i < g_num_of_iommus; ) {
525 if (!ecap_sc_support(g_iommus[i]->ecap)) {
526 domain->iommu_snooping = 0;
529 i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1);
533 /* Some capabilities may be different across iommus */
534 static void domain_update_iommu_cap(struct dmar_domain *domain)
536 domain_update_iommu_coherency(domain);
537 domain_update_iommu_snooping(domain);
540 static struct intel_iommu *device_to_iommu(int segment, u8 bus, u8 devfn)
542 struct dmar_drhd_unit *drhd = NULL;
545 for_each_drhd_unit(drhd) {
548 if (segment != drhd->segment)
551 for (i = 0; i < drhd->devices_cnt; i++) {
552 if (drhd->devices[i] &&
553 drhd->devices[i]->bus->number == bus &&
554 drhd->devices[i]->devfn == devfn)
556 if (drhd->devices[i] &&
557 drhd->devices[i]->subordinate &&
558 drhd->devices[i]->subordinate->number <= bus &&
559 drhd->devices[i]->subordinate->subordinate >= bus)
563 if (drhd->include_all)
570 static void domain_flush_cache(struct dmar_domain *domain,
571 void *addr, int size)
573 if (!domain->iommu_coherency)
574 clflush_cache_range(addr, size);
577 /* Gets context entry for a given bus and devfn */
578 static struct context_entry * device_to_context_entry(struct intel_iommu *iommu,
581 struct root_entry *root;
582 struct context_entry *context;
583 unsigned long phy_addr;
586 spin_lock_irqsave(&iommu->lock, flags);
587 root = &iommu->root_entry[bus];
588 context = get_context_addr_from_root(root);
590 context = (struct context_entry *)alloc_pgtable_page();
592 spin_unlock_irqrestore(&iommu->lock, flags);
595 __iommu_flush_cache(iommu, (void *)context, CONTEXT_SIZE);
596 phy_addr = virt_to_phys((void *)context);
597 set_root_value(root, phy_addr);
598 set_root_present(root);
599 __iommu_flush_cache(iommu, root, sizeof(*root));
601 spin_unlock_irqrestore(&iommu->lock, flags);
602 return &context[devfn];
605 static int device_context_mapped(struct intel_iommu *iommu, u8 bus, u8 devfn)
607 struct root_entry *root;
608 struct context_entry *context;
612 spin_lock_irqsave(&iommu->lock, flags);
613 root = &iommu->root_entry[bus];
614 context = get_context_addr_from_root(root);
619 ret = context_present(&context[devfn]);
621 spin_unlock_irqrestore(&iommu->lock, flags);
625 static void clear_context_table(struct intel_iommu *iommu, u8 bus, u8 devfn)
627 struct root_entry *root;
628 struct context_entry *context;
631 spin_lock_irqsave(&iommu->lock, flags);
632 root = &iommu->root_entry[bus];
633 context = get_context_addr_from_root(root);
635 context_clear_entry(&context[devfn]);
636 __iommu_flush_cache(iommu, &context[devfn], \
639 spin_unlock_irqrestore(&iommu->lock, flags);
642 static void free_context_table(struct intel_iommu *iommu)
644 struct root_entry *root;
647 struct context_entry *context;
649 spin_lock_irqsave(&iommu->lock, flags);
650 if (!iommu->root_entry) {
653 for (i = 0; i < ROOT_ENTRY_NR; i++) {
654 root = &iommu->root_entry[i];
655 context = get_context_addr_from_root(root);
657 free_pgtable_page(context);
659 free_pgtable_page(iommu->root_entry);
660 iommu->root_entry = NULL;
662 spin_unlock_irqrestore(&iommu->lock, flags);
665 /* page table handling */
666 #define LEVEL_STRIDE (9)
667 #define LEVEL_MASK (((u64)1 << LEVEL_STRIDE) - 1)
669 static inline int agaw_to_level(int agaw)
674 static inline int agaw_to_width(int agaw)
676 return 30 + agaw * LEVEL_STRIDE;
680 static inline int width_to_agaw(int width)
682 return (width - 30) / LEVEL_STRIDE;
685 static inline unsigned int level_to_offset_bits(int level)
687 return (level - 1) * LEVEL_STRIDE;
690 static inline int pfn_level_offset(unsigned long pfn, int level)
692 return (pfn >> level_to_offset_bits(level)) & LEVEL_MASK;
695 static inline unsigned long level_mask(int level)
697 return -1UL << level_to_offset_bits(level);
700 static inline unsigned long level_size(int level)
702 return 1UL << level_to_offset_bits(level);
705 static inline unsigned long align_to_level(unsigned long pfn, int level)
707 return (pfn + level_size(level) - 1) & level_mask(level);
710 static struct dma_pte *pfn_to_dma_pte(struct dmar_domain *domain,
713 int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
714 struct dma_pte *parent, *pte = NULL;
715 int level = agaw_to_level(domain->agaw);
718 BUG_ON(!domain->pgd);
719 BUG_ON(addr_width < BITS_PER_LONG && pfn >> addr_width);
720 parent = domain->pgd;
725 offset = pfn_level_offset(pfn, level);
726 pte = &parent[offset];
730 if (!dma_pte_present(pte)) {
733 tmp_page = alloc_pgtable_page();
738 domain_flush_cache(domain, tmp_page, VTD_PAGE_SIZE);
739 pteval = ((uint64_t)virt_to_dma_pfn(tmp_page) << VTD_PAGE_SHIFT) | DMA_PTE_READ | DMA_PTE_WRITE;
740 if (cmpxchg64(&pte->val, 0ULL, pteval)) {
741 /* Someone else set it while we were thinking; use theirs. */
742 free_pgtable_page(tmp_page);
745 domain_flush_cache(domain, pte, sizeof(*pte));
748 parent = phys_to_virt(dma_pte_addr(pte));
755 /* return address's pte at specific level */
756 static struct dma_pte *dma_pfn_level_pte(struct dmar_domain *domain,
760 struct dma_pte *parent, *pte = NULL;
761 int total = agaw_to_level(domain->agaw);
764 parent = domain->pgd;
765 while (level <= total) {
766 offset = pfn_level_offset(pfn, total);
767 pte = &parent[offset];
771 if (!dma_pte_present(pte))
773 parent = phys_to_virt(dma_pte_addr(pte));
779 /* clear last level pte, a tlb flush should be followed */
780 static void dma_pte_clear_range(struct dmar_domain *domain,
781 unsigned long start_pfn,
782 unsigned long last_pfn)
784 int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
785 struct dma_pte *first_pte, *pte;
787 BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width);
788 BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width);
789 BUG_ON(start_pfn > last_pfn);
791 /* we don't need lock here; nobody else touches the iova range */
793 first_pte = pte = dma_pfn_level_pte(domain, start_pfn, 1);
795 start_pfn = align_to_level(start_pfn + 1, 2);
802 } while (start_pfn <= last_pfn && !first_pte_in_page(pte));
804 domain_flush_cache(domain, first_pte,
805 (void *)pte - (void *)first_pte);
807 } while (start_pfn && start_pfn <= last_pfn);
810 /* free page table pages. last level pte should already be cleared */
811 static void dma_pte_free_pagetable(struct dmar_domain *domain,
812 unsigned long start_pfn,
813 unsigned long last_pfn)
815 int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
816 struct dma_pte *first_pte, *pte;
817 int total = agaw_to_level(domain->agaw);
821 BUG_ON(addr_width < BITS_PER_LONG && start_pfn >> addr_width);
822 BUG_ON(addr_width < BITS_PER_LONG && last_pfn >> addr_width);
823 BUG_ON(start_pfn > last_pfn);
825 /* We don't need lock here; nobody else touches the iova range */
827 while (level <= total) {
828 tmp = align_to_level(start_pfn, level);
830 /* If we can't even clear one PTE at this level, we're done */
831 if (tmp + level_size(level) - 1 > last_pfn)
835 first_pte = pte = dma_pfn_level_pte(domain, tmp, level);
837 tmp = align_to_level(tmp + 1, level + 1);
841 if (dma_pte_present(pte)) {
842 free_pgtable_page(phys_to_virt(dma_pte_addr(pte)));
846 tmp += level_size(level);
847 } while (!first_pte_in_page(pte) &&
848 tmp + level_size(level) - 1 <= last_pfn);
850 domain_flush_cache(domain, first_pte,
851 (void *)pte - (void *)first_pte);
853 } while (tmp && tmp + level_size(level) - 1 <= last_pfn);
857 if (start_pfn == 0 && last_pfn == DOMAIN_MAX_PFN(domain->gaw)) {
858 free_pgtable_page(domain->pgd);
864 static int iommu_alloc_root_entry(struct intel_iommu *iommu)
866 struct root_entry *root;
869 root = (struct root_entry *)alloc_pgtable_page();
873 __iommu_flush_cache(iommu, root, ROOT_SIZE);
875 spin_lock_irqsave(&iommu->lock, flags);
876 iommu->root_entry = root;
877 spin_unlock_irqrestore(&iommu->lock, flags);
882 static void iommu_set_root_entry(struct intel_iommu *iommu)
888 addr = iommu->root_entry;
890 spin_lock_irqsave(&iommu->register_lock, flag);
891 dmar_writeq(iommu->reg + DMAR_RTADDR_REG, virt_to_phys(addr));
893 writel(iommu->gcmd | DMA_GCMD_SRTP, iommu->reg + DMAR_GCMD_REG);
895 /* Make sure hardware complete it */
896 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
897 readl, (sts & DMA_GSTS_RTPS), sts);
899 spin_unlock_irqrestore(&iommu->register_lock, flag);
902 static void iommu_flush_write_buffer(struct intel_iommu *iommu)
907 if (!rwbf_quirk && !cap_rwbf(iommu->cap))
910 spin_lock_irqsave(&iommu->register_lock, flag);
911 writel(iommu->gcmd | DMA_GCMD_WBF, iommu->reg + DMAR_GCMD_REG);
913 /* Make sure hardware complete it */
914 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
915 readl, (!(val & DMA_GSTS_WBFS)), val);
917 spin_unlock_irqrestore(&iommu->register_lock, flag);
920 /* return value determine if we need a write buffer flush */
921 static void __iommu_flush_context(struct intel_iommu *iommu,
922 u16 did, u16 source_id, u8 function_mask,
929 case DMA_CCMD_GLOBAL_INVL:
930 val = DMA_CCMD_GLOBAL_INVL;
932 case DMA_CCMD_DOMAIN_INVL:
933 val = DMA_CCMD_DOMAIN_INVL|DMA_CCMD_DID(did);
935 case DMA_CCMD_DEVICE_INVL:
936 val = DMA_CCMD_DEVICE_INVL|DMA_CCMD_DID(did)
937 | DMA_CCMD_SID(source_id) | DMA_CCMD_FM(function_mask);
944 spin_lock_irqsave(&iommu->register_lock, flag);
945 dmar_writeq(iommu->reg + DMAR_CCMD_REG, val);
947 /* Make sure hardware complete it */
948 IOMMU_WAIT_OP(iommu, DMAR_CCMD_REG,
949 dmar_readq, (!(val & DMA_CCMD_ICC)), val);
951 spin_unlock_irqrestore(&iommu->register_lock, flag);
954 /* return value determine if we need a write buffer flush */
955 static void __iommu_flush_iotlb(struct intel_iommu *iommu, u16 did,
956 u64 addr, unsigned int size_order, u64 type)
958 int tlb_offset = ecap_iotlb_offset(iommu->ecap);
959 u64 val = 0, val_iva = 0;
963 case DMA_TLB_GLOBAL_FLUSH:
964 /* global flush doesn't need set IVA_REG */
965 val = DMA_TLB_GLOBAL_FLUSH|DMA_TLB_IVT;
967 case DMA_TLB_DSI_FLUSH:
968 val = DMA_TLB_DSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
970 case DMA_TLB_PSI_FLUSH:
971 val = DMA_TLB_PSI_FLUSH|DMA_TLB_IVT|DMA_TLB_DID(did);
972 /* Note: always flush non-leaf currently */
973 val_iva = size_order | addr;
978 /* Note: set drain read/write */
981 * This is probably to be super secure.. Looks like we can
982 * ignore it without any impact.
984 if (cap_read_drain(iommu->cap))
985 val |= DMA_TLB_READ_DRAIN;
987 if (cap_write_drain(iommu->cap))
988 val |= DMA_TLB_WRITE_DRAIN;
990 spin_lock_irqsave(&iommu->register_lock, flag);
991 /* Note: Only uses first TLB reg currently */
993 dmar_writeq(iommu->reg + tlb_offset, val_iva);
994 dmar_writeq(iommu->reg + tlb_offset + 8, val);
996 /* Make sure hardware complete it */
997 IOMMU_WAIT_OP(iommu, tlb_offset + 8,
998 dmar_readq, (!(val & DMA_TLB_IVT)), val);
1000 spin_unlock_irqrestore(&iommu->register_lock, flag);
1002 /* check IOTLB invalidation granularity */
1003 if (DMA_TLB_IAIG(val) == 0)
1004 printk(KERN_ERR"IOMMU: flush IOTLB failed\n");
1005 if (DMA_TLB_IAIG(val) != DMA_TLB_IIRG(type))
1006 pr_debug("IOMMU: tlb flush request %Lx, actual %Lx\n",
1007 (unsigned long long)DMA_TLB_IIRG(type),
1008 (unsigned long long)DMA_TLB_IAIG(val));
1011 static struct device_domain_info *iommu_support_dev_iotlb(
1012 struct dmar_domain *domain, int segment, u8 bus, u8 devfn)
1015 unsigned long flags;
1016 struct device_domain_info *info;
1017 struct intel_iommu *iommu = device_to_iommu(segment, bus, devfn);
1019 if (!ecap_dev_iotlb_support(iommu->ecap))
1025 spin_lock_irqsave(&device_domain_lock, flags);
1026 list_for_each_entry(info, &domain->devices, link)
1027 if (info->bus == bus && info->devfn == devfn) {
1031 spin_unlock_irqrestore(&device_domain_lock, flags);
1033 if (!found || !info->dev)
1036 if (!pci_find_ext_capability(info->dev, PCI_EXT_CAP_ID_ATS))
1039 if (!dmar_find_matched_atsr_unit(info->dev))
1042 info->iommu = iommu;
1047 static void iommu_enable_dev_iotlb(struct device_domain_info *info)
1052 pci_enable_ats(info->dev, VTD_PAGE_SHIFT);
1055 static void iommu_disable_dev_iotlb(struct device_domain_info *info)
1057 if (!info->dev || !pci_ats_enabled(info->dev))
1060 pci_disable_ats(info->dev);
1063 static void iommu_flush_dev_iotlb(struct dmar_domain *domain,
1064 u64 addr, unsigned mask)
1067 unsigned long flags;
1068 struct device_domain_info *info;
1070 spin_lock_irqsave(&device_domain_lock, flags);
1071 list_for_each_entry(info, &domain->devices, link) {
1072 if (!info->dev || !pci_ats_enabled(info->dev))
1075 sid = info->bus << 8 | info->devfn;
1076 qdep = pci_ats_queue_depth(info->dev);
1077 qi_flush_dev_iotlb(info->iommu, sid, qdep, addr, mask);
1079 spin_unlock_irqrestore(&device_domain_lock, flags);
1082 static void iommu_flush_iotlb_psi(struct intel_iommu *iommu, u16 did,
1083 unsigned long pfn, unsigned int pages)
1085 unsigned int mask = ilog2(__roundup_pow_of_two(pages));
1086 uint64_t addr = (uint64_t)pfn << VTD_PAGE_SHIFT;
1091 * Fallback to domain selective flush if no PSI support or the size is
1093 * PSI requires page size to be 2 ^ x, and the base address is naturally
1094 * aligned to the size
1096 if (!cap_pgsel_inv(iommu->cap) || mask > cap_max_amask_val(iommu->cap))
1097 iommu->flush.flush_iotlb(iommu, did, 0, 0,
1100 iommu->flush.flush_iotlb(iommu, did, addr, mask,
1104 * In caching mode, domain ID 0 is reserved for non-present to present
1105 * mapping flush. Device IOTLB doesn't need to be flushed in this case.
1107 if (!cap_caching_mode(iommu->cap) || did)
1108 iommu_flush_dev_iotlb(iommu->domains[did], addr, mask);
1111 static void iommu_disable_protect_mem_regions(struct intel_iommu *iommu)
1114 unsigned long flags;
1116 spin_lock_irqsave(&iommu->register_lock, flags);
1117 pmen = readl(iommu->reg + DMAR_PMEN_REG);
1118 pmen &= ~DMA_PMEN_EPM;
1119 writel(pmen, iommu->reg + DMAR_PMEN_REG);
1121 /* wait for the protected region status bit to clear */
1122 IOMMU_WAIT_OP(iommu, DMAR_PMEN_REG,
1123 readl, !(pmen & DMA_PMEN_PRS), pmen);
1125 spin_unlock_irqrestore(&iommu->register_lock, flags);
1128 static int iommu_enable_translation(struct intel_iommu *iommu)
1131 unsigned long flags;
1133 spin_lock_irqsave(&iommu->register_lock, flags);
1134 iommu->gcmd |= DMA_GCMD_TE;
1135 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
1137 /* Make sure hardware complete it */
1138 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
1139 readl, (sts & DMA_GSTS_TES), sts);
1141 spin_unlock_irqrestore(&iommu->register_lock, flags);
1145 static int iommu_disable_translation(struct intel_iommu *iommu)
1150 spin_lock_irqsave(&iommu->register_lock, flag);
1151 iommu->gcmd &= ~DMA_GCMD_TE;
1152 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
1154 /* Make sure hardware complete it */
1155 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
1156 readl, (!(sts & DMA_GSTS_TES)), sts);
1158 spin_unlock_irqrestore(&iommu->register_lock, flag);
1163 static int iommu_init_domains(struct intel_iommu *iommu)
1165 unsigned long ndomains;
1166 unsigned long nlongs;
1168 ndomains = cap_ndoms(iommu->cap);
1169 pr_debug("Number of Domains supportd <%ld>\n", ndomains);
1170 nlongs = BITS_TO_LONGS(ndomains);
1172 spin_lock_init(&iommu->lock);
1174 /* TBD: there might be 64K domains,
1175 * consider other allocation for future chip
1177 iommu->domain_ids = kcalloc(nlongs, sizeof(unsigned long), GFP_KERNEL);
1178 if (!iommu->domain_ids) {
1179 printk(KERN_ERR "Allocating domain id array failed\n");
1182 iommu->domains = kcalloc(ndomains, sizeof(struct dmar_domain *),
1184 if (!iommu->domains) {
1185 printk(KERN_ERR "Allocating domain array failed\n");
1190 * if Caching mode is set, then invalid translations are tagged
1191 * with domainid 0. Hence we need to pre-allocate it.
1193 if (cap_caching_mode(iommu->cap))
1194 set_bit(0, iommu->domain_ids);
1199 static void domain_exit(struct dmar_domain *domain);
1200 static void vm_domain_exit(struct dmar_domain *domain);
1202 void free_dmar_iommu(struct intel_iommu *iommu)
1204 struct dmar_domain *domain;
1206 unsigned long flags;
1208 if ((iommu->domains) && (iommu->domain_ids)) {
1209 i = find_first_bit(iommu->domain_ids, cap_ndoms(iommu->cap));
1210 for (; i < cap_ndoms(iommu->cap); ) {
1211 domain = iommu->domains[i];
1212 clear_bit(i, iommu->domain_ids);
1214 spin_lock_irqsave(&domain->iommu_lock, flags);
1215 if (--domain->iommu_count == 0) {
1216 if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE)
1217 vm_domain_exit(domain);
1219 domain_exit(domain);
1221 spin_unlock_irqrestore(&domain->iommu_lock, flags);
1223 i = find_next_bit(iommu->domain_ids,
1224 cap_ndoms(iommu->cap), i+1);
1228 if (iommu->gcmd & DMA_GCMD_TE)
1229 iommu_disable_translation(iommu);
1232 set_irq_data(iommu->irq, NULL);
1233 /* This will mask the irq */
1234 free_irq(iommu->irq, iommu);
1235 destroy_irq(iommu->irq);
1238 kfree(iommu->domains);
1239 kfree(iommu->domain_ids);
1241 g_iommus[iommu->seq_id] = NULL;
1243 /* if all iommus are freed, free g_iommus */
1244 for (i = 0; i < g_num_of_iommus; i++) {
1249 if (i == g_num_of_iommus)
1252 /* free context mapping */
1253 free_context_table(iommu);
1256 static struct dmar_domain *alloc_domain(void)
1258 struct dmar_domain *domain;
1260 domain = alloc_domain_mem();
1264 memset(&domain->iommu_bmp, 0, sizeof(unsigned long));
1270 static int iommu_attach_domain(struct dmar_domain *domain,
1271 struct intel_iommu *iommu)
1274 unsigned long ndomains;
1275 unsigned long flags;
1277 ndomains = cap_ndoms(iommu->cap);
1279 spin_lock_irqsave(&iommu->lock, flags);
1281 num = find_first_zero_bit(iommu->domain_ids, ndomains);
1282 if (num >= ndomains) {
1283 spin_unlock_irqrestore(&iommu->lock, flags);
1284 printk(KERN_ERR "IOMMU: no free domain ids\n");
1289 set_bit(num, iommu->domain_ids);
1290 set_bit(iommu->seq_id, &domain->iommu_bmp);
1291 iommu->domains[num] = domain;
1292 spin_unlock_irqrestore(&iommu->lock, flags);
1297 static void iommu_detach_domain(struct dmar_domain *domain,
1298 struct intel_iommu *iommu)
1300 unsigned long flags;
1304 spin_lock_irqsave(&iommu->lock, flags);
1305 ndomains = cap_ndoms(iommu->cap);
1306 num = find_first_bit(iommu->domain_ids, ndomains);
1307 for (; num < ndomains; ) {
1308 if (iommu->domains[num] == domain) {
1312 num = find_next_bit(iommu->domain_ids,
1313 cap_ndoms(iommu->cap), num+1);
1317 clear_bit(num, iommu->domain_ids);
1318 clear_bit(iommu->seq_id, &domain->iommu_bmp);
1319 iommu->domains[num] = NULL;
1321 spin_unlock_irqrestore(&iommu->lock, flags);
1324 static struct iova_domain reserved_iova_list;
1325 static struct lock_class_key reserved_rbtree_key;
1327 static void dmar_init_reserved_ranges(void)
1329 struct pci_dev *pdev = NULL;
1333 init_iova_domain(&reserved_iova_list, DMA_32BIT_PFN);
1335 lockdep_set_class(&reserved_iova_list.iova_rbtree_lock,
1336 &reserved_rbtree_key);
1338 /* IOAPIC ranges shouldn't be accessed by DMA */
1339 iova = reserve_iova(&reserved_iova_list, IOVA_PFN(IOAPIC_RANGE_START),
1340 IOVA_PFN(IOAPIC_RANGE_END));
1342 printk(KERN_ERR "Reserve IOAPIC range failed\n");
1344 /* Reserve all PCI MMIO to avoid peer-to-peer access */
1345 for_each_pci_dev(pdev) {
1348 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1349 r = &pdev->resource[i];
1350 if (!r->flags || !(r->flags & IORESOURCE_MEM))
1352 iova = reserve_iova(&reserved_iova_list,
1356 printk(KERN_ERR "Reserve iova failed\n");
1362 static void domain_reserve_special_ranges(struct dmar_domain *domain)
1364 copy_reserved_iova(&reserved_iova_list, &domain->iovad);
1367 static inline int guestwidth_to_adjustwidth(int gaw)
1370 int r = (gaw - 12) % 9;
1381 static int domain_init(struct dmar_domain *domain, int guest_width)
1383 struct intel_iommu *iommu;
1384 int adjust_width, agaw;
1385 unsigned long sagaw;
1387 init_iova_domain(&domain->iovad, DMA_32BIT_PFN);
1388 spin_lock_init(&domain->iommu_lock);
1390 domain_reserve_special_ranges(domain);
1392 /* calculate AGAW */
1393 iommu = domain_get_iommu(domain);
1394 if (guest_width > cap_mgaw(iommu->cap))
1395 guest_width = cap_mgaw(iommu->cap);
1396 domain->gaw = guest_width;
1397 adjust_width = guestwidth_to_adjustwidth(guest_width);
1398 agaw = width_to_agaw(adjust_width);
1399 sagaw = cap_sagaw(iommu->cap);
1400 if (!test_bit(agaw, &sagaw)) {
1401 /* hardware doesn't support it, choose a bigger one */
1402 pr_debug("IOMMU: hardware doesn't support agaw %d\n", agaw);
1403 agaw = find_next_bit(&sagaw, 5, agaw);
1407 domain->agaw = agaw;
1408 INIT_LIST_HEAD(&domain->devices);
1410 if (ecap_coherent(iommu->ecap))
1411 domain->iommu_coherency = 1;
1413 domain->iommu_coherency = 0;
1415 if (ecap_sc_support(iommu->ecap))
1416 domain->iommu_snooping = 1;
1418 domain->iommu_snooping = 0;
1420 domain->iommu_count = 1;
1422 /* always allocate the top pgd */
1423 domain->pgd = (struct dma_pte *)alloc_pgtable_page();
1426 __iommu_flush_cache(iommu, domain->pgd, PAGE_SIZE);
1430 static void domain_exit(struct dmar_domain *domain)
1432 struct dmar_drhd_unit *drhd;
1433 struct intel_iommu *iommu;
1435 /* Domain 0 is reserved, so dont process it */
1439 domain_remove_dev_info(domain);
1441 put_iova_domain(&domain->iovad);
1444 dma_pte_clear_range(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
1446 /* free page tables */
1447 dma_pte_free_pagetable(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
1449 for_each_active_iommu(iommu, drhd)
1450 if (test_bit(iommu->seq_id, &domain->iommu_bmp))
1451 iommu_detach_domain(domain, iommu);
1453 free_domain_mem(domain);
1456 static int domain_context_mapping_one(struct dmar_domain *domain, int segment,
1457 u8 bus, u8 devfn, int translation)
1459 struct context_entry *context;
1460 unsigned long flags;
1461 struct intel_iommu *iommu;
1462 struct dma_pte *pgd;
1464 unsigned long ndomains;
1467 struct device_domain_info *info = NULL;
1469 pr_debug("Set context mapping for %02x:%02x.%d\n",
1470 bus, PCI_SLOT(devfn), PCI_FUNC(devfn));
1472 BUG_ON(!domain->pgd);
1473 BUG_ON(translation != CONTEXT_TT_PASS_THROUGH &&
1474 translation != CONTEXT_TT_MULTI_LEVEL);
1476 iommu = device_to_iommu(segment, bus, devfn);
1480 context = device_to_context_entry(iommu, bus, devfn);
1483 spin_lock_irqsave(&iommu->lock, flags);
1484 if (context_present(context)) {
1485 spin_unlock_irqrestore(&iommu->lock, flags);
1492 if (domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE ||
1493 domain->flags & DOMAIN_FLAG_STATIC_IDENTITY) {
1496 /* find an available domain id for this device in iommu */
1497 ndomains = cap_ndoms(iommu->cap);
1498 num = find_first_bit(iommu->domain_ids, ndomains);
1499 for (; num < ndomains; ) {
1500 if (iommu->domains[num] == domain) {
1505 num = find_next_bit(iommu->domain_ids,
1506 cap_ndoms(iommu->cap), num+1);
1510 num = find_first_zero_bit(iommu->domain_ids, ndomains);
1511 if (num >= ndomains) {
1512 spin_unlock_irqrestore(&iommu->lock, flags);
1513 printk(KERN_ERR "IOMMU: no free domain ids\n");
1517 set_bit(num, iommu->domain_ids);
1518 iommu->domains[num] = domain;
1522 /* Skip top levels of page tables for
1523 * iommu which has less agaw than default.
1525 for (agaw = domain->agaw; agaw != iommu->agaw; agaw--) {
1526 pgd = phys_to_virt(dma_pte_addr(pgd));
1527 if (!dma_pte_present(pgd)) {
1528 spin_unlock_irqrestore(&iommu->lock, flags);
1534 context_set_domain_id(context, id);
1536 if (translation != CONTEXT_TT_PASS_THROUGH) {
1537 info = iommu_support_dev_iotlb(domain, segment, bus, devfn);
1538 translation = info ? CONTEXT_TT_DEV_IOTLB :
1539 CONTEXT_TT_MULTI_LEVEL;
1542 * In pass through mode, AW must be programmed to indicate the largest
1543 * AGAW value supported by hardware. And ASR is ignored by hardware.
1545 if (unlikely(translation == CONTEXT_TT_PASS_THROUGH))
1546 context_set_address_width(context, iommu->msagaw);
1548 context_set_address_root(context, virt_to_phys(pgd));
1549 context_set_address_width(context, iommu->agaw);
1552 context_set_translation_type(context, translation);
1553 context_set_fault_enable(context);
1554 context_set_present(context);
1555 domain_flush_cache(domain, context, sizeof(*context));
1558 * It's a non-present to present mapping. If hardware doesn't cache
1559 * non-present entry we only need to flush the write-buffer. If the
1560 * _does_ cache non-present entries, then it does so in the special
1561 * domain #0, which we have to flush:
1563 if (cap_caching_mode(iommu->cap)) {
1564 iommu->flush.flush_context(iommu, 0,
1565 (((u16)bus) << 8) | devfn,
1566 DMA_CCMD_MASK_NOBIT,
1567 DMA_CCMD_DEVICE_INVL);
1568 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_DSI_FLUSH);
1570 iommu_flush_write_buffer(iommu);
1572 iommu_enable_dev_iotlb(info);
1573 spin_unlock_irqrestore(&iommu->lock, flags);
1575 spin_lock_irqsave(&domain->iommu_lock, flags);
1576 if (!test_and_set_bit(iommu->seq_id, &domain->iommu_bmp)) {
1577 domain->iommu_count++;
1578 domain_update_iommu_cap(domain);
1580 spin_unlock_irqrestore(&domain->iommu_lock, flags);
1585 domain_context_mapping(struct dmar_domain *domain, struct pci_dev *pdev,
1589 struct pci_dev *tmp, *parent;
1591 ret = domain_context_mapping_one(domain, pci_domain_nr(pdev->bus),
1592 pdev->bus->number, pdev->devfn,
1597 /* dependent device mapping */
1598 tmp = pci_find_upstream_pcie_bridge(pdev);
1601 /* Secondary interface's bus number and devfn 0 */
1602 parent = pdev->bus->self;
1603 while (parent != tmp) {
1604 ret = domain_context_mapping_one(domain,
1605 pci_domain_nr(parent->bus),
1606 parent->bus->number,
1607 parent->devfn, translation);
1610 parent = parent->bus->self;
1612 if (tmp->is_pcie) /* this is a PCIE-to-PCI bridge */
1613 return domain_context_mapping_one(domain,
1614 pci_domain_nr(tmp->subordinate),
1615 tmp->subordinate->number, 0,
1617 else /* this is a legacy PCI bridge */
1618 return domain_context_mapping_one(domain,
1619 pci_domain_nr(tmp->bus),
1625 static int domain_context_mapped(struct pci_dev *pdev)
1628 struct pci_dev *tmp, *parent;
1629 struct intel_iommu *iommu;
1631 iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
1636 ret = device_context_mapped(iommu, pdev->bus->number, pdev->devfn);
1639 /* dependent device mapping */
1640 tmp = pci_find_upstream_pcie_bridge(pdev);
1643 /* Secondary interface's bus number and devfn 0 */
1644 parent = pdev->bus->self;
1645 while (parent != tmp) {
1646 ret = device_context_mapped(iommu, parent->bus->number,
1650 parent = parent->bus->self;
1653 return device_context_mapped(iommu, tmp->subordinate->number,
1656 return device_context_mapped(iommu, tmp->bus->number,
1660 /* Returns a number of VTD pages, but aligned to MM page size */
1661 static inline unsigned long aligned_nrpages(unsigned long host_addr,
1664 host_addr &= ~PAGE_MASK;
1665 return PAGE_ALIGN(host_addr + size) >> VTD_PAGE_SHIFT;
1668 static int __domain_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
1669 struct scatterlist *sg, unsigned long phys_pfn,
1670 unsigned long nr_pages, int prot)
1672 struct dma_pte *first_pte = NULL, *pte = NULL;
1673 phys_addr_t uninitialized_var(pteval);
1674 int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT;
1675 unsigned long sg_res;
1677 BUG_ON(addr_width < BITS_PER_LONG && (iov_pfn + nr_pages - 1) >> addr_width);
1679 if ((prot & (DMA_PTE_READ|DMA_PTE_WRITE)) == 0)
1682 prot &= DMA_PTE_READ | DMA_PTE_WRITE | DMA_PTE_SNP;
1687 sg_res = nr_pages + 1;
1688 pteval = ((phys_addr_t)phys_pfn << VTD_PAGE_SHIFT) | prot;
1691 while (nr_pages--) {
1695 sg_res = aligned_nrpages(sg->offset, sg->length);
1696 sg->dma_address = ((dma_addr_t)iov_pfn << VTD_PAGE_SHIFT) + sg->offset;
1697 sg->dma_length = sg->length;
1698 pteval = page_to_phys(sg_page(sg)) | prot;
1701 first_pte = pte = pfn_to_dma_pte(domain, iov_pfn);
1705 /* We don't need lock here, nobody else
1706 * touches the iova range
1708 tmp = cmpxchg64_local(&pte->val, 0ULL, pteval);
1710 static int dumps = 5;
1711 printk(KERN_CRIT "ERROR: DMA PTE for vPFN 0x%lx already set (to %llx not %llx)\n",
1712 iov_pfn, tmp, (unsigned long long)pteval);
1715 debug_dma_dump_mappings(NULL);
1720 if (!nr_pages || first_pte_in_page(pte)) {
1721 domain_flush_cache(domain, first_pte,
1722 (void *)pte - (void *)first_pte);
1726 pteval += VTD_PAGE_SIZE;
1734 static inline int domain_sg_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
1735 struct scatterlist *sg, unsigned long nr_pages,
1738 return __domain_mapping(domain, iov_pfn, sg, 0, nr_pages, prot);
1741 static inline int domain_pfn_mapping(struct dmar_domain *domain, unsigned long iov_pfn,
1742 unsigned long phys_pfn, unsigned long nr_pages,
1745 return __domain_mapping(domain, iov_pfn, NULL, phys_pfn, nr_pages, prot);
1748 static void iommu_detach_dev(struct intel_iommu *iommu, u8 bus, u8 devfn)
1753 clear_context_table(iommu, bus, devfn);
1754 iommu->flush.flush_context(iommu, 0, 0, 0,
1755 DMA_CCMD_GLOBAL_INVL);
1756 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
1759 static void domain_remove_dev_info(struct dmar_domain *domain)
1761 struct device_domain_info *info;
1762 unsigned long flags;
1763 struct intel_iommu *iommu;
1765 spin_lock_irqsave(&device_domain_lock, flags);
1766 while (!list_empty(&domain->devices)) {
1767 info = list_entry(domain->devices.next,
1768 struct device_domain_info, link);
1769 list_del(&info->link);
1770 list_del(&info->global);
1772 info->dev->dev.archdata.iommu = NULL;
1773 spin_unlock_irqrestore(&device_domain_lock, flags);
1775 iommu_disable_dev_iotlb(info);
1776 iommu = device_to_iommu(info->segment, info->bus, info->devfn);
1777 iommu_detach_dev(iommu, info->bus, info->devfn);
1778 free_devinfo_mem(info);
1780 spin_lock_irqsave(&device_domain_lock, flags);
1782 spin_unlock_irqrestore(&device_domain_lock, flags);
1787 * Note: we use struct pci_dev->dev.archdata.iommu stores the info
1789 static struct dmar_domain *
1790 find_domain(struct pci_dev *pdev)
1792 struct device_domain_info *info;
1794 /* No lock here, assumes no domain exit in normal case */
1795 info = pdev->dev.archdata.iommu;
1797 return info->domain;
1801 /* domain is initialized */
1802 static struct dmar_domain *get_domain_for_dev(struct pci_dev *pdev, int gaw)
1804 struct dmar_domain *domain, *found = NULL;
1805 struct intel_iommu *iommu;
1806 struct dmar_drhd_unit *drhd;
1807 struct device_domain_info *info, *tmp;
1808 struct pci_dev *dev_tmp;
1809 unsigned long flags;
1810 int bus = 0, devfn = 0;
1814 domain = find_domain(pdev);
1818 segment = pci_domain_nr(pdev->bus);
1820 dev_tmp = pci_find_upstream_pcie_bridge(pdev);
1822 if (dev_tmp->is_pcie) {
1823 bus = dev_tmp->subordinate->number;
1826 bus = dev_tmp->bus->number;
1827 devfn = dev_tmp->devfn;
1829 spin_lock_irqsave(&device_domain_lock, flags);
1830 list_for_each_entry(info, &device_domain_list, global) {
1831 if (info->segment == segment &&
1832 info->bus == bus && info->devfn == devfn) {
1833 found = info->domain;
1837 spin_unlock_irqrestore(&device_domain_lock, flags);
1838 /* pcie-pci bridge already has a domain, uses it */
1845 domain = alloc_domain();
1849 /* Allocate new domain for the device */
1850 drhd = dmar_find_matched_drhd_unit(pdev);
1852 printk(KERN_ERR "IOMMU: can't find DMAR for device %s\n",
1856 iommu = drhd->iommu;
1858 ret = iommu_attach_domain(domain, iommu);
1860 domain_exit(domain);
1864 if (domain_init(domain, gaw)) {
1865 domain_exit(domain);
1869 /* register pcie-to-pci device */
1871 info = alloc_devinfo_mem();
1873 domain_exit(domain);
1876 info->segment = segment;
1878 info->devfn = devfn;
1880 info->domain = domain;
1881 /* This domain is shared by devices under p2p bridge */
1882 domain->flags |= DOMAIN_FLAG_P2P_MULTIPLE_DEVICES;
1884 /* pcie-to-pci bridge already has a domain, uses it */
1886 spin_lock_irqsave(&device_domain_lock, flags);
1887 list_for_each_entry(tmp, &device_domain_list, global) {
1888 if (tmp->segment == segment &&
1889 tmp->bus == bus && tmp->devfn == devfn) {
1890 found = tmp->domain;
1895 free_devinfo_mem(info);
1896 domain_exit(domain);
1899 list_add(&info->link, &domain->devices);
1900 list_add(&info->global, &device_domain_list);
1902 spin_unlock_irqrestore(&device_domain_lock, flags);
1906 info = alloc_devinfo_mem();
1909 info->segment = segment;
1910 info->bus = pdev->bus->number;
1911 info->devfn = pdev->devfn;
1913 info->domain = domain;
1914 spin_lock_irqsave(&device_domain_lock, flags);
1915 /* somebody is fast */
1916 found = find_domain(pdev);
1917 if (found != NULL) {
1918 spin_unlock_irqrestore(&device_domain_lock, flags);
1919 if (found != domain) {
1920 domain_exit(domain);
1923 free_devinfo_mem(info);
1926 list_add(&info->link, &domain->devices);
1927 list_add(&info->global, &device_domain_list);
1928 pdev->dev.archdata.iommu = info;
1929 spin_unlock_irqrestore(&device_domain_lock, flags);
1932 /* recheck it here, maybe others set it */
1933 return find_domain(pdev);
1936 static int iommu_identity_mapping;
1938 static int iommu_domain_identity_map(struct dmar_domain *domain,
1939 unsigned long long start,
1940 unsigned long long end)
1942 unsigned long first_vpfn = start >> VTD_PAGE_SHIFT;
1943 unsigned long last_vpfn = end >> VTD_PAGE_SHIFT;
1945 if (!reserve_iova(&domain->iovad, dma_to_mm_pfn(first_vpfn),
1946 dma_to_mm_pfn(last_vpfn))) {
1947 printk(KERN_ERR "IOMMU: reserve iova failed\n");
1951 pr_debug("Mapping reserved region %llx-%llx for domain %d\n",
1952 start, end, domain->id);
1954 * RMRR range might have overlap with physical memory range,
1957 dma_pte_clear_range(domain, first_vpfn, last_vpfn);
1959 return domain_pfn_mapping(domain, first_vpfn, first_vpfn,
1960 last_vpfn - first_vpfn + 1,
1961 DMA_PTE_READ|DMA_PTE_WRITE);
1964 static int iommu_prepare_identity_map(struct pci_dev *pdev,
1965 unsigned long long start,
1966 unsigned long long end)
1968 struct dmar_domain *domain;
1971 domain = get_domain_for_dev(pdev, DEFAULT_DOMAIN_ADDRESS_WIDTH);
1975 /* For _hardware_ passthrough, don't bother. But for software
1976 passthrough, we do it anyway -- it may indicate a memory
1977 range which is reserved in E820, so which didn't get set
1978 up to start with in si_domain */
1979 if (domain == si_domain && hw_pass_through) {
1980 printk("Ignoring identity map for HW passthrough device %s [0x%Lx - 0x%Lx]\n",
1981 pci_name(pdev), start, end);
1986 "IOMMU: Setting identity map for device %s [0x%Lx - 0x%Lx]\n",
1987 pci_name(pdev), start, end);
1989 if (end >> agaw_to_width(domain->agaw)) {
1990 WARN(1, "Your BIOS is broken; RMRR exceeds permitted address width (%d bits)\n"
1991 "BIOS vendor: %s; Ver: %s; Product Version: %s\n",
1992 agaw_to_width(domain->agaw),
1993 dmi_get_system_info(DMI_BIOS_VENDOR),
1994 dmi_get_system_info(DMI_BIOS_VERSION),
1995 dmi_get_system_info(DMI_PRODUCT_VERSION));
2000 ret = iommu_domain_identity_map(domain, start, end);
2004 /* context entry init */
2005 ret = domain_context_mapping(domain, pdev, CONTEXT_TT_MULTI_LEVEL);
2012 domain_exit(domain);
2016 static inline int iommu_prepare_rmrr_dev(struct dmar_rmrr_unit *rmrr,
2017 struct pci_dev *pdev)
2019 if (pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO)
2021 return iommu_prepare_identity_map(pdev, rmrr->base_address,
2022 rmrr->end_address + 1);
2025 #ifdef CONFIG_DMAR_FLOPPY_WA
2026 static inline void iommu_prepare_isa(void)
2028 struct pci_dev *pdev;
2031 pdev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
2035 printk(KERN_INFO "IOMMU: Prepare 0-16MiB unity mapping for LPC\n");
2036 ret = iommu_prepare_identity_map(pdev, 0, 16*1024*1024);
2039 printk(KERN_ERR "IOMMU: Failed to create 0-16MiB identity map; "
2040 "floppy might not work\n");
2044 static inline void iommu_prepare_isa(void)
2048 #endif /* !CONFIG_DMAR_FLPY_WA */
2050 static int md_domain_init(struct dmar_domain *domain, int guest_width);
2052 static int __init si_domain_work_fn(unsigned long start_pfn,
2053 unsigned long end_pfn, void *datax)
2057 *ret = iommu_domain_identity_map(si_domain,
2058 (uint64_t)start_pfn << PAGE_SHIFT,
2059 (uint64_t)end_pfn << PAGE_SHIFT);
2064 static int __init si_domain_init(int hw)
2066 struct dmar_drhd_unit *drhd;
2067 struct intel_iommu *iommu;
2070 si_domain = alloc_domain();
2074 pr_debug("Identity mapping domain is domain %d\n", si_domain->id);
2076 for_each_active_iommu(iommu, drhd) {
2077 ret = iommu_attach_domain(si_domain, iommu);
2079 domain_exit(si_domain);
2084 if (md_domain_init(si_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) {
2085 domain_exit(si_domain);
2089 si_domain->flags = DOMAIN_FLAG_STATIC_IDENTITY;
2094 for_each_online_node(nid) {
2095 work_with_active_regions(nid, si_domain_work_fn, &ret);
2103 static void domain_remove_one_dev_info(struct dmar_domain *domain,
2104 struct pci_dev *pdev);
2105 static int identity_mapping(struct pci_dev *pdev)
2107 struct device_domain_info *info;
2109 if (likely(!iommu_identity_mapping))
2113 list_for_each_entry(info, &si_domain->devices, link)
2114 if (info->dev == pdev)
2119 static int domain_add_dev_info(struct dmar_domain *domain,
2120 struct pci_dev *pdev,
2123 struct device_domain_info *info;
2124 unsigned long flags;
2127 info = alloc_devinfo_mem();
2131 ret = domain_context_mapping(domain, pdev, translation);
2133 free_devinfo_mem(info);
2137 info->segment = pci_domain_nr(pdev->bus);
2138 info->bus = pdev->bus->number;
2139 info->devfn = pdev->devfn;
2141 info->domain = domain;
2143 spin_lock_irqsave(&device_domain_lock, flags);
2144 list_add(&info->link, &domain->devices);
2145 list_add(&info->global, &device_domain_list);
2146 pdev->dev.archdata.iommu = info;
2147 spin_unlock_irqrestore(&device_domain_lock, flags);
2152 static int iommu_should_identity_map(struct pci_dev *pdev, int startup)
2154 if (iommu_identity_mapping == 2)
2155 return IS_GFX_DEVICE(pdev);
2158 * We want to start off with all devices in the 1:1 domain, and
2159 * take them out later if we find they can't access all of memory.
2161 * However, we can't do this for PCI devices behind bridges,
2162 * because all PCI devices behind the same bridge will end up
2163 * with the same source-id on their transactions.
2165 * Practically speaking, we can't change things around for these
2166 * devices at run-time, because we can't be sure there'll be no
2167 * DMA transactions in flight for any of their siblings.
2169 * So PCI devices (unless they're on the root bus) as well as
2170 * their parent PCI-PCI or PCIe-PCI bridges must be left _out_ of
2171 * the 1:1 domain, just in _case_ one of their siblings turns out
2172 * not to be able to map all of memory.
2174 if (!pdev->is_pcie) {
2175 if (!pci_is_root_bus(pdev->bus))
2177 if (pdev->class >> 8 == PCI_CLASS_BRIDGE_PCI)
2179 } else if (pdev->pcie_type == PCI_EXP_TYPE_PCI_BRIDGE)
2183 * At boot time, we don't yet know if devices will be 64-bit capable.
2184 * Assume that they will -- if they turn out not to be, then we can
2185 * take them out of the 1:1 domain later.
2188 return pdev->dma_mask > DMA_BIT_MASK(32);
2193 static int __init iommu_prepare_static_identity_mapping(int hw)
2195 struct pci_dev *pdev = NULL;
2198 ret = si_domain_init(hw);
2202 for_each_pci_dev(pdev) {
2203 if (iommu_should_identity_map(pdev, 1)) {
2204 printk(KERN_INFO "IOMMU: %s identity mapping for device %s\n",
2205 hw ? "hardware" : "software", pci_name(pdev));
2207 ret = domain_add_dev_info(si_domain, pdev,
2208 hw ? CONTEXT_TT_PASS_THROUGH :
2209 CONTEXT_TT_MULTI_LEVEL);
2218 int __init init_dmars(void)
2220 struct dmar_drhd_unit *drhd;
2221 struct dmar_rmrr_unit *rmrr;
2222 struct pci_dev *pdev;
2223 struct intel_iommu *iommu;
2229 * initialize and program root entry to not present
2232 for_each_drhd_unit(drhd) {
2235 * lock not needed as this is only incremented in the single
2236 * threaded kernel __init code path all other access are read
2241 g_iommus = kcalloc(g_num_of_iommus, sizeof(struct intel_iommu *),
2244 printk(KERN_ERR "Allocating global iommu array failed\n");
2249 deferred_flush = kzalloc(g_num_of_iommus *
2250 sizeof(struct deferred_flush_tables), GFP_KERNEL);
2251 if (!deferred_flush) {
2256 for_each_drhd_unit(drhd) {
2260 iommu = drhd->iommu;
2261 g_iommus[iommu->seq_id] = iommu;
2263 ret = iommu_init_domains(iommu);
2269 * we could share the same root & context tables
2270 * amoung all IOMMU's. Need to Split it later.
2272 ret = iommu_alloc_root_entry(iommu);
2274 printk(KERN_ERR "IOMMU: allocate root entry failed\n");
2277 if (!ecap_pass_through(iommu->ecap))
2278 hw_pass_through = 0;
2282 * Start from the sane iommu hardware state.
2284 for_each_drhd_unit(drhd) {
2288 iommu = drhd->iommu;
2291 * If the queued invalidation is already initialized by us
2292 * (for example, while enabling interrupt-remapping) then
2293 * we got the things already rolling from a sane state.
2299 * Clear any previous faults.
2301 dmar_fault(-1, iommu);
2303 * Disable queued invalidation if supported and already enabled
2304 * before OS handover.
2306 dmar_disable_qi(iommu);
2309 for_each_drhd_unit(drhd) {
2313 iommu = drhd->iommu;
2315 if (dmar_enable_qi(iommu)) {
2317 * Queued Invalidate not enabled, use Register Based
2320 iommu->flush.flush_context = __iommu_flush_context;
2321 iommu->flush.flush_iotlb = __iommu_flush_iotlb;
2322 printk(KERN_INFO "IOMMU 0x%Lx: using Register based "
2324 (unsigned long long)drhd->reg_base_addr);
2326 iommu->flush.flush_context = qi_flush_context;
2327 iommu->flush.flush_iotlb = qi_flush_iotlb;
2328 printk(KERN_INFO "IOMMU 0x%Lx: using Queued "
2330 (unsigned long long)drhd->reg_base_addr);
2334 if (iommu_pass_through)
2335 iommu_identity_mapping = 1;
2336 #ifdef CONFIG_DMAR_BROKEN_GFX_WA
2338 iommu_identity_mapping = 2;
2341 * If pass through is not set or not enabled, setup context entries for
2342 * identity mappings for rmrr, gfx, and isa and may fall back to static
2343 * identity mapping if iommu_identity_mapping is set.
2345 if (iommu_identity_mapping) {
2346 ret = iommu_prepare_static_identity_mapping(hw_pass_through);
2348 printk(KERN_CRIT "Failed to setup IOMMU pass-through\n");
2354 * for each dev attached to rmrr
2356 * locate drhd for dev, alloc domain for dev
2357 * allocate free domain
2358 * allocate page table entries for rmrr
2359 * if context not allocated for bus
2360 * allocate and init context
2361 * set present in root table for this bus
2362 * init context with domain, translation etc
2366 printk(KERN_INFO "IOMMU: Setting RMRR:\n");
2367 for_each_rmrr_units(rmrr) {
2368 for (i = 0; i < rmrr->devices_cnt; i++) {
2369 pdev = rmrr->devices[i];
2371 * some BIOS lists non-exist devices in DMAR
2376 ret = iommu_prepare_rmrr_dev(rmrr, pdev);
2379 "IOMMU: mapping reserved region failed\n");
2383 iommu_prepare_isa();
2388 * global invalidate context cache
2389 * global invalidate iotlb
2390 * enable translation
2392 for_each_drhd_unit(drhd) {
2395 iommu = drhd->iommu;
2397 iommu_flush_write_buffer(iommu);
2399 ret = dmar_set_interrupt(iommu);
2403 iommu_set_root_entry(iommu);
2405 iommu->flush.flush_context(iommu, 0, 0, 0, DMA_CCMD_GLOBAL_INVL);
2406 iommu->flush.flush_iotlb(iommu, 0, 0, 0, DMA_TLB_GLOBAL_FLUSH);
2408 ret = iommu_enable_translation(iommu);
2412 iommu_disable_protect_mem_regions(iommu);
2417 for_each_drhd_unit(drhd) {
2420 iommu = drhd->iommu;
2427 /* This takes a number of _MM_ pages, not VTD pages */
2428 static struct iova *intel_alloc_iova(struct device *dev,
2429 struct dmar_domain *domain,
2430 unsigned long nrpages, uint64_t dma_mask)
2432 struct pci_dev *pdev = to_pci_dev(dev);
2433 struct iova *iova = NULL;
2435 /* Restrict dma_mask to the width that the iommu can handle */
2436 dma_mask = min_t(uint64_t, DOMAIN_MAX_ADDR(domain->gaw), dma_mask);
2438 if (!dmar_forcedac && dma_mask > DMA_BIT_MASK(32)) {
2440 * First try to allocate an io virtual address in
2441 * DMA_BIT_MASK(32) and if that fails then try allocating
2444 iova = alloc_iova(&domain->iovad, nrpages,
2445 IOVA_PFN(DMA_BIT_MASK(32)), 1);
2449 iova = alloc_iova(&domain->iovad, nrpages, IOVA_PFN(dma_mask), 1);
2450 if (unlikely(!iova)) {
2451 printk(KERN_ERR "Allocating %ld-page iova for %s failed",
2452 nrpages, pci_name(pdev));
2459 static struct dmar_domain *__get_valid_domain_for_dev(struct pci_dev *pdev)
2461 struct dmar_domain *domain;
2464 domain = get_domain_for_dev(pdev,
2465 DEFAULT_DOMAIN_ADDRESS_WIDTH);
2468 "Allocating domain for %s failed", pci_name(pdev));
2472 /* make sure context mapping is ok */
2473 if (unlikely(!domain_context_mapped(pdev))) {
2474 ret = domain_context_mapping(domain, pdev,
2475 CONTEXT_TT_MULTI_LEVEL);
2478 "Domain context map for %s failed",
2487 static inline struct dmar_domain *get_valid_domain_for_dev(struct pci_dev *dev)
2489 struct device_domain_info *info;
2491 /* No lock here, assumes no domain exit in normal case */
2492 info = dev->dev.archdata.iommu;
2494 return info->domain;
2496 return __get_valid_domain_for_dev(dev);
2499 static int iommu_dummy(struct pci_dev *pdev)
2501 return pdev->dev.archdata.iommu == DUMMY_DEVICE_DOMAIN_INFO;
2504 /* Check if the pdev needs to go through non-identity map and unmap process.*/
2505 static int iommu_no_mapping(struct device *dev)
2507 struct pci_dev *pdev;
2510 if (unlikely(dev->bus != &pci_bus_type))
2513 pdev = to_pci_dev(dev);
2514 if (iommu_dummy(pdev))
2517 if (!iommu_identity_mapping)
2520 found = identity_mapping(pdev);
2522 if (iommu_should_identity_map(pdev, 0))
2526 * 32 bit DMA is removed from si_domain and fall back
2527 * to non-identity mapping.
2529 domain_remove_one_dev_info(si_domain, pdev);
2530 printk(KERN_INFO "32bit %s uses non-identity mapping\n",
2536 * In case of a detached 64 bit DMA device from vm, the device
2537 * is put into si_domain for identity mapping.
2539 if (iommu_should_identity_map(pdev, 0)) {
2541 ret = domain_add_dev_info(si_domain, pdev,
2543 CONTEXT_TT_PASS_THROUGH :
2544 CONTEXT_TT_MULTI_LEVEL);
2546 printk(KERN_INFO "64bit %s uses identity mapping\n",
2556 static dma_addr_t __intel_map_single(struct device *hwdev, phys_addr_t paddr,
2557 size_t size, int dir, u64 dma_mask)
2559 struct pci_dev *pdev = to_pci_dev(hwdev);
2560 struct dmar_domain *domain;
2561 phys_addr_t start_paddr;
2565 struct intel_iommu *iommu;
2566 unsigned long paddr_pfn = paddr >> PAGE_SHIFT;
2568 BUG_ON(dir == DMA_NONE);
2570 if (iommu_no_mapping(hwdev))
2573 domain = get_valid_domain_for_dev(pdev);
2577 iommu = domain_get_iommu(domain);
2578 size = aligned_nrpages(paddr, size);
2580 iova = intel_alloc_iova(hwdev, domain, dma_to_mm_pfn(size),
2586 * Check if DMAR supports zero-length reads on write only
2589 if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
2590 !cap_zlr(iommu->cap))
2591 prot |= DMA_PTE_READ;
2592 if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
2593 prot |= DMA_PTE_WRITE;
2595 * paddr - (paddr + size) might be partial page, we should map the whole
2596 * page. Note: if two part of one page are separately mapped, we
2597 * might have two guest_addr mapping to the same host paddr, but this
2598 * is not a big problem
2600 ret = domain_pfn_mapping(domain, mm_to_dma_pfn(iova->pfn_lo),
2601 mm_to_dma_pfn(paddr_pfn), size, prot);
2605 /* it's a non-present to present mapping. Only flush if caching mode */
2606 if (cap_caching_mode(iommu->cap))
2607 iommu_flush_iotlb_psi(iommu, 0, mm_to_dma_pfn(iova->pfn_lo), size);
2609 iommu_flush_write_buffer(iommu);
2611 start_paddr = (phys_addr_t)iova->pfn_lo << PAGE_SHIFT;
2612 start_paddr += paddr & ~PAGE_MASK;
2617 __free_iova(&domain->iovad, iova);
2618 printk(KERN_ERR"Device %s request: %zx@%llx dir %d --- failed\n",
2619 pci_name(pdev), size, (unsigned long long)paddr, dir);
2623 static dma_addr_t intel_map_page(struct device *dev, struct page *page,
2624 unsigned long offset, size_t size,
2625 enum dma_data_direction dir,
2626 struct dma_attrs *attrs)
2628 return __intel_map_single(dev, page_to_phys(page) + offset, size,
2629 dir, to_pci_dev(dev)->dma_mask);
2632 static void flush_unmaps(void)
2638 /* just flush them all */
2639 for (i = 0; i < g_num_of_iommus; i++) {
2640 struct intel_iommu *iommu = g_iommus[i];
2644 if (!deferred_flush[i].next)
2647 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
2648 DMA_TLB_GLOBAL_FLUSH);
2649 for (j = 0; j < deferred_flush[i].next; j++) {
2651 struct iova *iova = deferred_flush[i].iova[j];
2653 mask = ilog2(mm_to_dma_pfn(iova->pfn_hi - iova->pfn_lo + 1));
2654 iommu_flush_dev_iotlb(deferred_flush[i].domain[j],
2655 (uint64_t)iova->pfn_lo << PAGE_SHIFT, mask);
2656 __free_iova(&deferred_flush[i].domain[j]->iovad, iova);
2658 deferred_flush[i].next = 0;
2664 static void flush_unmaps_timeout(unsigned long data)
2666 unsigned long flags;
2668 spin_lock_irqsave(&async_umap_flush_lock, flags);
2670 spin_unlock_irqrestore(&async_umap_flush_lock, flags);
2673 static void add_unmap(struct dmar_domain *dom, struct iova *iova)
2675 unsigned long flags;
2677 struct intel_iommu *iommu;
2679 spin_lock_irqsave(&async_umap_flush_lock, flags);
2680 if (list_size == HIGH_WATER_MARK)
2683 iommu = domain_get_iommu(dom);
2684 iommu_id = iommu->seq_id;
2686 next = deferred_flush[iommu_id].next;
2687 deferred_flush[iommu_id].domain[next] = dom;
2688 deferred_flush[iommu_id].iova[next] = iova;
2689 deferred_flush[iommu_id].next++;
2692 mod_timer(&unmap_timer, jiffies + msecs_to_jiffies(10));
2696 spin_unlock_irqrestore(&async_umap_flush_lock, flags);
2699 static void intel_unmap_page(struct device *dev, dma_addr_t dev_addr,
2700 size_t size, enum dma_data_direction dir,
2701 struct dma_attrs *attrs)
2703 struct pci_dev *pdev = to_pci_dev(dev);
2704 struct dmar_domain *domain;
2705 unsigned long start_pfn, last_pfn;
2707 struct intel_iommu *iommu;
2709 if (iommu_no_mapping(dev))
2712 domain = find_domain(pdev);
2715 iommu = domain_get_iommu(domain);
2717 iova = find_iova(&domain->iovad, IOVA_PFN(dev_addr));
2718 if (WARN_ONCE(!iova, "Driver unmaps unmatched page at PFN %llx\n",
2719 (unsigned long long)dev_addr))
2722 start_pfn = mm_to_dma_pfn(iova->pfn_lo);
2723 last_pfn = mm_to_dma_pfn(iova->pfn_hi + 1) - 1;
2725 pr_debug("Device %s unmapping: pfn %lx-%lx\n",
2726 pci_name(pdev), start_pfn, last_pfn);
2728 /* clear the whole page */
2729 dma_pte_clear_range(domain, start_pfn, last_pfn);
2731 /* free page tables */
2732 dma_pte_free_pagetable(domain, start_pfn, last_pfn);
2734 if (intel_iommu_strict) {
2735 iommu_flush_iotlb_psi(iommu, domain->id, start_pfn,
2736 last_pfn - start_pfn + 1);
2738 __free_iova(&domain->iovad, iova);
2740 add_unmap(domain, iova);
2742 * queue up the release of the unmap to save the 1/6th of the
2743 * cpu used up by the iotlb flush operation...
2748 static void *intel_alloc_coherent(struct device *hwdev, size_t size,
2749 dma_addr_t *dma_handle, gfp_t flags)
2754 size = PAGE_ALIGN(size);
2755 order = get_order(size);
2756 flags &= ~(GFP_DMA | GFP_DMA32);
2758 vaddr = (void *)__get_free_pages(flags, order);
2761 memset(vaddr, 0, size);
2763 *dma_handle = __intel_map_single(hwdev, virt_to_bus(vaddr), size,
2765 hwdev->coherent_dma_mask);
2768 free_pages((unsigned long)vaddr, order);
2772 static void intel_free_coherent(struct device *hwdev, size_t size, void *vaddr,
2773 dma_addr_t dma_handle)
2777 size = PAGE_ALIGN(size);
2778 order = get_order(size);
2780 intel_unmap_page(hwdev, dma_handle, size, DMA_BIDIRECTIONAL, NULL);
2781 free_pages((unsigned long)vaddr, order);
2784 static void intel_unmap_sg(struct device *hwdev, struct scatterlist *sglist,
2785 int nelems, enum dma_data_direction dir,
2786 struct dma_attrs *attrs)
2788 struct pci_dev *pdev = to_pci_dev(hwdev);
2789 struct dmar_domain *domain;
2790 unsigned long start_pfn, last_pfn;
2792 struct intel_iommu *iommu;
2794 if (iommu_no_mapping(hwdev))
2797 domain = find_domain(pdev);
2800 iommu = domain_get_iommu(domain);
2802 iova = find_iova(&domain->iovad, IOVA_PFN(sglist[0].dma_address));
2803 if (WARN_ONCE(!iova, "Driver unmaps unmatched sglist at PFN %llx\n",
2804 (unsigned long long)sglist[0].dma_address))
2807 start_pfn = mm_to_dma_pfn(iova->pfn_lo);
2808 last_pfn = mm_to_dma_pfn(iova->pfn_hi + 1) - 1;
2810 /* clear the whole page */
2811 dma_pte_clear_range(domain, start_pfn, last_pfn);
2813 /* free page tables */
2814 dma_pte_free_pagetable(domain, start_pfn, last_pfn);
2816 if (intel_iommu_strict) {
2817 iommu_flush_iotlb_psi(iommu, domain->id, start_pfn,
2818 last_pfn - start_pfn + 1);
2820 __free_iova(&domain->iovad, iova);
2822 add_unmap(domain, iova);
2824 * queue up the release of the unmap to save the 1/6th of the
2825 * cpu used up by the iotlb flush operation...
2830 static int intel_nontranslate_map_sg(struct device *hddev,
2831 struct scatterlist *sglist, int nelems, int dir)
2834 struct scatterlist *sg;
2836 for_each_sg(sglist, sg, nelems, i) {
2837 BUG_ON(!sg_page(sg));
2838 sg->dma_address = page_to_phys(sg_page(sg)) + sg->offset;
2839 sg->dma_length = sg->length;
2844 static int intel_map_sg(struct device *hwdev, struct scatterlist *sglist, int nelems,
2845 enum dma_data_direction dir, struct dma_attrs *attrs)
2848 struct pci_dev *pdev = to_pci_dev(hwdev);
2849 struct dmar_domain *domain;
2852 size_t offset_pfn = 0;
2853 struct iova *iova = NULL;
2855 struct scatterlist *sg;
2856 unsigned long start_vpfn;
2857 struct intel_iommu *iommu;
2859 BUG_ON(dir == DMA_NONE);
2860 if (iommu_no_mapping(hwdev))
2861 return intel_nontranslate_map_sg(hwdev, sglist, nelems, dir);
2863 domain = get_valid_domain_for_dev(pdev);
2867 iommu = domain_get_iommu(domain);
2869 for_each_sg(sglist, sg, nelems, i)
2870 size += aligned_nrpages(sg->offset, sg->length);
2872 iova = intel_alloc_iova(hwdev, domain, dma_to_mm_pfn(size),
2875 sglist->dma_length = 0;
2880 * Check if DMAR supports zero-length reads on write only
2883 if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL || \
2884 !cap_zlr(iommu->cap))
2885 prot |= DMA_PTE_READ;
2886 if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
2887 prot |= DMA_PTE_WRITE;
2889 start_vpfn = mm_to_dma_pfn(iova->pfn_lo);
2891 ret = domain_sg_mapping(domain, start_vpfn, sglist, size, prot);
2892 if (unlikely(ret)) {
2893 /* clear the page */
2894 dma_pte_clear_range(domain, start_vpfn,
2895 start_vpfn + size - 1);
2896 /* free page tables */
2897 dma_pte_free_pagetable(domain, start_vpfn,
2898 start_vpfn + size - 1);
2900 __free_iova(&domain->iovad, iova);
2904 /* it's a non-present to present mapping. Only flush if caching mode */
2905 if (cap_caching_mode(iommu->cap))
2906 iommu_flush_iotlb_psi(iommu, 0, start_vpfn, offset_pfn);
2908 iommu_flush_write_buffer(iommu);
2913 static int intel_mapping_error(struct device *dev, dma_addr_t dma_addr)
2918 struct dma_map_ops intel_dma_ops = {
2919 .alloc_coherent = intel_alloc_coherent,
2920 .free_coherent = intel_free_coherent,
2921 .map_sg = intel_map_sg,
2922 .unmap_sg = intel_unmap_sg,
2923 .map_page = intel_map_page,
2924 .unmap_page = intel_unmap_page,
2925 .mapping_error = intel_mapping_error,
2928 static inline int iommu_domain_cache_init(void)
2932 iommu_domain_cache = kmem_cache_create("iommu_domain",
2933 sizeof(struct dmar_domain),
2938 if (!iommu_domain_cache) {
2939 printk(KERN_ERR "Couldn't create iommu_domain cache\n");
2946 static inline int iommu_devinfo_cache_init(void)
2950 iommu_devinfo_cache = kmem_cache_create("iommu_devinfo",
2951 sizeof(struct device_domain_info),
2955 if (!iommu_devinfo_cache) {
2956 printk(KERN_ERR "Couldn't create devinfo cache\n");
2963 static inline int iommu_iova_cache_init(void)
2967 iommu_iova_cache = kmem_cache_create("iommu_iova",
2968 sizeof(struct iova),
2972 if (!iommu_iova_cache) {
2973 printk(KERN_ERR "Couldn't create iova cache\n");
2980 static int __init iommu_init_mempool(void)
2983 ret = iommu_iova_cache_init();
2987 ret = iommu_domain_cache_init();
2991 ret = iommu_devinfo_cache_init();
2995 kmem_cache_destroy(iommu_domain_cache);
2997 kmem_cache_destroy(iommu_iova_cache);
3002 static void __init iommu_exit_mempool(void)
3004 kmem_cache_destroy(iommu_devinfo_cache);
3005 kmem_cache_destroy(iommu_domain_cache);
3006 kmem_cache_destroy(iommu_iova_cache);
3010 static void __init init_no_remapping_devices(void)
3012 struct dmar_drhd_unit *drhd;
3014 for_each_drhd_unit(drhd) {
3015 if (!drhd->include_all) {
3017 for (i = 0; i < drhd->devices_cnt; i++)
3018 if (drhd->devices[i] != NULL)
3020 /* ignore DMAR unit if no pci devices exist */
3021 if (i == drhd->devices_cnt)
3029 for_each_drhd_unit(drhd) {
3031 if (drhd->ignored || drhd->include_all)
3034 for (i = 0; i < drhd->devices_cnt; i++)
3035 if (drhd->devices[i] &&
3036 !IS_GFX_DEVICE(drhd->devices[i]))
3039 if (i < drhd->devices_cnt)
3042 /* bypass IOMMU if it is just for gfx devices */
3044 for (i = 0; i < drhd->devices_cnt; i++) {
3045 if (!drhd->devices[i])
3047 drhd->devices[i]->dev.archdata.iommu = DUMMY_DEVICE_DOMAIN_INFO;
3052 #ifdef CONFIG_SUSPEND
3053 static int init_iommu_hw(void)
3055 struct dmar_drhd_unit *drhd;
3056 struct intel_iommu *iommu = NULL;
3058 for_each_active_iommu(iommu, drhd)
3060 dmar_reenable_qi(iommu);
3062 for_each_active_iommu(iommu, drhd) {
3063 iommu_flush_write_buffer(iommu);
3065 iommu_set_root_entry(iommu);
3067 iommu->flush.flush_context(iommu, 0, 0, 0,
3068 DMA_CCMD_GLOBAL_INVL);
3069 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
3070 DMA_TLB_GLOBAL_FLUSH);
3071 iommu_enable_translation(iommu);
3072 iommu_disable_protect_mem_regions(iommu);
3078 static void iommu_flush_all(void)
3080 struct dmar_drhd_unit *drhd;
3081 struct intel_iommu *iommu;
3083 for_each_active_iommu(iommu, drhd) {
3084 iommu->flush.flush_context(iommu, 0, 0, 0,
3085 DMA_CCMD_GLOBAL_INVL);
3086 iommu->flush.flush_iotlb(iommu, 0, 0, 0,
3087 DMA_TLB_GLOBAL_FLUSH);
3091 static int iommu_suspend(struct sys_device *dev, pm_message_t state)
3093 struct dmar_drhd_unit *drhd;
3094 struct intel_iommu *iommu = NULL;
3097 for_each_active_iommu(iommu, drhd) {
3098 iommu->iommu_state = kzalloc(sizeof(u32) * MAX_SR_DMAR_REGS,
3100 if (!iommu->iommu_state)
3106 for_each_active_iommu(iommu, drhd) {
3107 iommu_disable_translation(iommu);
3109 spin_lock_irqsave(&iommu->register_lock, flag);
3111 iommu->iommu_state[SR_DMAR_FECTL_REG] =
3112 readl(iommu->reg + DMAR_FECTL_REG);
3113 iommu->iommu_state[SR_DMAR_FEDATA_REG] =
3114 readl(iommu->reg + DMAR_FEDATA_REG);
3115 iommu->iommu_state[SR_DMAR_FEADDR_REG] =
3116 readl(iommu->reg + DMAR_FEADDR_REG);
3117 iommu->iommu_state[SR_DMAR_FEUADDR_REG] =
3118 readl(iommu->reg + DMAR_FEUADDR_REG);
3120 spin_unlock_irqrestore(&iommu->register_lock, flag);
3125 for_each_active_iommu(iommu, drhd)
3126 kfree(iommu->iommu_state);
3131 static int iommu_resume(struct sys_device *dev)
3133 struct dmar_drhd_unit *drhd;
3134 struct intel_iommu *iommu = NULL;
3137 if (init_iommu_hw()) {
3138 WARN(1, "IOMMU setup failed, DMAR can not resume!\n");
3142 for_each_active_iommu(iommu, drhd) {
3144 spin_lock_irqsave(&iommu->register_lock, flag);
3146 writel(iommu->iommu_state[SR_DMAR_FECTL_REG],
3147 iommu->reg + DMAR_FECTL_REG);
3148 writel(iommu->iommu_state[SR_DMAR_FEDATA_REG],
3149 iommu->reg + DMAR_FEDATA_REG);
3150 writel(iommu->iommu_state[SR_DMAR_FEADDR_REG],
3151 iommu->reg + DMAR_FEADDR_REG);
3152 writel(iommu->iommu_state[SR_DMAR_FEUADDR_REG],
3153 iommu->reg + DMAR_FEUADDR_REG);
3155 spin_unlock_irqrestore(&iommu->register_lock, flag);
3158 for_each_active_iommu(iommu, drhd)
3159 kfree(iommu->iommu_state);
3164 static struct sysdev_class iommu_sysclass = {
3166 .resume = iommu_resume,
3167 .suspend = iommu_suspend,
3170 static struct sys_device device_iommu = {
3171 .cls = &iommu_sysclass,
3174 static int __init init_iommu_sysfs(void)
3178 error = sysdev_class_register(&iommu_sysclass);
3182 error = sysdev_register(&device_iommu);
3184 sysdev_class_unregister(&iommu_sysclass);
3190 static int __init init_iommu_sysfs(void)
3194 #endif /* CONFIG_PM */
3196 int __init intel_iommu_init(void)
3201 /* VT-d is required for a TXT/tboot launch, so enforce that */
3202 force_on = tboot_force_iommu();
3204 if (dmar_table_init()) {
3206 panic("tboot: Failed to initialize DMAR table\n");
3210 if (dmar_dev_scope_init()) {
3212 panic("tboot: Failed to initialize DMAR device scope\n");
3217 * Check the need for DMA-remapping initialization now.
3218 * Above initialization will also be used by Interrupt-remapping.
3220 if (no_iommu || swiotlb || dmar_disabled)
3223 iommu_init_mempool();
3224 dmar_init_reserved_ranges();
3226 init_no_remapping_devices();
3231 panic("tboot: Failed to initialize DMARs\n");
3232 printk(KERN_ERR "IOMMU: dmar init failed\n");
3233 put_iova_domain(&reserved_iova_list);
3234 iommu_exit_mempool();
3238 "PCI-DMA: Intel(R) Virtualization Technology for Directed I/O\n");
3240 init_timer(&unmap_timer);
3242 dma_ops = &intel_dma_ops;
3246 register_iommu(&intel_iommu_ops);
3251 static void iommu_detach_dependent_devices(struct intel_iommu *iommu,
3252 struct pci_dev *pdev)
3254 struct pci_dev *tmp, *parent;
3256 if (!iommu || !pdev)
3259 /* dependent device detach */
3260 tmp = pci_find_upstream_pcie_bridge(pdev);
3261 /* Secondary interface's bus number and devfn 0 */
3263 parent = pdev->bus->self;
3264 while (parent != tmp) {
3265 iommu_detach_dev(iommu, parent->bus->number,
3267 parent = parent->bus->self;
3269 if (tmp->is_pcie) /* this is a PCIE-to-PCI bridge */
3270 iommu_detach_dev(iommu,
3271 tmp->subordinate->number, 0);
3272 else /* this is a legacy PCI bridge */
3273 iommu_detach_dev(iommu, tmp->bus->number,
3278 static void domain_remove_one_dev_info(struct dmar_domain *domain,
3279 struct pci_dev *pdev)
3281 struct device_domain_info *info;
3282 struct intel_iommu *iommu;
3283 unsigned long flags;
3285 struct list_head *entry, *tmp;
3287 iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
3292 spin_lock_irqsave(&device_domain_lock, flags);
3293 list_for_each_safe(entry, tmp, &domain->devices) {
3294 info = list_entry(entry, struct device_domain_info, link);
3295 /* No need to compare PCI domain; it has to be the same */
3296 if (info->bus == pdev->bus->number &&
3297 info->devfn == pdev->devfn) {
3298 list_del(&info->link);
3299 list_del(&info->global);
3301 info->dev->dev.archdata.iommu = NULL;
3302 spin_unlock_irqrestore(&device_domain_lock, flags);
3304 iommu_disable_dev_iotlb(info);
3305 iommu_detach_dev(iommu, info->bus, info->devfn);
3306 iommu_detach_dependent_devices(iommu, pdev);
3307 free_devinfo_mem(info);
3309 spin_lock_irqsave(&device_domain_lock, flags);
3317 /* if there is no other devices under the same iommu
3318 * owned by this domain, clear this iommu in iommu_bmp
3319 * update iommu count and coherency
3321 if (iommu == device_to_iommu(info->segment, info->bus,
3327 unsigned long tmp_flags;
3328 spin_lock_irqsave(&domain->iommu_lock, tmp_flags);
3329 clear_bit(iommu->seq_id, &domain->iommu_bmp);
3330 domain->iommu_count--;
3331 domain_update_iommu_cap(domain);
3332 spin_unlock_irqrestore(&domain->iommu_lock, tmp_flags);
3335 spin_unlock_irqrestore(&device_domain_lock, flags);
3338 static void vm_domain_remove_all_dev_info(struct dmar_domain *domain)
3340 struct device_domain_info *info;
3341 struct intel_iommu *iommu;
3342 unsigned long flags1, flags2;
3344 spin_lock_irqsave(&device_domain_lock, flags1);
3345 while (!list_empty(&domain->devices)) {
3346 info = list_entry(domain->devices.next,
3347 struct device_domain_info, link);
3348 list_del(&info->link);
3349 list_del(&info->global);
3351 info->dev->dev.archdata.iommu = NULL;
3353 spin_unlock_irqrestore(&device_domain_lock, flags1);
3355 iommu_disable_dev_iotlb(info);
3356 iommu = device_to_iommu(info->segment, info->bus, info->devfn);
3357 iommu_detach_dev(iommu, info->bus, info->devfn);
3358 iommu_detach_dependent_devices(iommu, info->dev);
3360 /* clear this iommu in iommu_bmp, update iommu count
3363 spin_lock_irqsave(&domain->iommu_lock, flags2);
3364 if (test_and_clear_bit(iommu->seq_id,
3365 &domain->iommu_bmp)) {
3366 domain->iommu_count--;
3367 domain_update_iommu_cap(domain);
3369 spin_unlock_irqrestore(&domain->iommu_lock, flags2);
3371 free_devinfo_mem(info);
3372 spin_lock_irqsave(&device_domain_lock, flags1);
3374 spin_unlock_irqrestore(&device_domain_lock, flags1);
3377 /* domain id for virtual machine, it won't be set in context */
3378 static unsigned long vm_domid;
3380 static int vm_domain_min_agaw(struct dmar_domain *domain)
3383 int min_agaw = domain->agaw;
3385 i = find_first_bit(&domain->iommu_bmp, g_num_of_iommus);
3386 for (; i < g_num_of_iommus; ) {
3387 if (min_agaw > g_iommus[i]->agaw)
3388 min_agaw = g_iommus[i]->agaw;
3390 i = find_next_bit(&domain->iommu_bmp, g_num_of_iommus, i+1);
3396 static struct dmar_domain *iommu_alloc_vm_domain(void)
3398 struct dmar_domain *domain;
3400 domain = alloc_domain_mem();
3404 domain->id = vm_domid++;
3405 memset(&domain->iommu_bmp, 0, sizeof(unsigned long));
3406 domain->flags = DOMAIN_FLAG_VIRTUAL_MACHINE;
3411 static int md_domain_init(struct dmar_domain *domain, int guest_width)
3415 init_iova_domain(&domain->iovad, DMA_32BIT_PFN);
3416 spin_lock_init(&domain->iommu_lock);
3418 domain_reserve_special_ranges(domain);
3420 /* calculate AGAW */
3421 domain->gaw = guest_width;
3422 adjust_width = guestwidth_to_adjustwidth(guest_width);
3423 domain->agaw = width_to_agaw(adjust_width);
3425 INIT_LIST_HEAD(&domain->devices);
3427 domain->iommu_count = 0;
3428 domain->iommu_coherency = 0;
3429 domain->iommu_snooping = 0;
3430 domain->max_addr = 0;
3432 /* always allocate the top pgd */
3433 domain->pgd = (struct dma_pte *)alloc_pgtable_page();
3436 domain_flush_cache(domain, domain->pgd, PAGE_SIZE);
3440 static void iommu_free_vm_domain(struct dmar_domain *domain)
3442 unsigned long flags;
3443 struct dmar_drhd_unit *drhd;
3444 struct intel_iommu *iommu;
3446 unsigned long ndomains;
3448 for_each_drhd_unit(drhd) {
3451 iommu = drhd->iommu;
3453 ndomains = cap_ndoms(iommu->cap);
3454 i = find_first_bit(iommu->domain_ids, ndomains);
3455 for (; i < ndomains; ) {
3456 if (iommu->domains[i] == domain) {
3457 spin_lock_irqsave(&iommu->lock, flags);
3458 clear_bit(i, iommu->domain_ids);
3459 iommu->domains[i] = NULL;
3460 spin_unlock_irqrestore(&iommu->lock, flags);
3463 i = find_next_bit(iommu->domain_ids, ndomains, i+1);
3468 static void vm_domain_exit(struct dmar_domain *domain)
3470 /* Domain 0 is reserved, so dont process it */
3474 vm_domain_remove_all_dev_info(domain);
3476 put_iova_domain(&domain->iovad);
3479 dma_pte_clear_range(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
3481 /* free page tables */
3482 dma_pte_free_pagetable(domain, 0, DOMAIN_MAX_PFN(domain->gaw));
3484 iommu_free_vm_domain(domain);
3485 free_domain_mem(domain);
3488 static int intel_iommu_domain_init(struct iommu_domain *domain)
3490 struct dmar_domain *dmar_domain;
3492 dmar_domain = iommu_alloc_vm_domain();
3495 "intel_iommu_domain_init: dmar_domain == NULL\n");
3498 if (md_domain_init(dmar_domain, DEFAULT_DOMAIN_ADDRESS_WIDTH)) {
3500 "intel_iommu_domain_init() failed\n");
3501 vm_domain_exit(dmar_domain);
3504 domain->priv = dmar_domain;
3509 static void intel_iommu_domain_destroy(struct iommu_domain *domain)
3511 struct dmar_domain *dmar_domain = domain->priv;
3513 domain->priv = NULL;
3514 vm_domain_exit(dmar_domain);
3517 static int intel_iommu_attach_device(struct iommu_domain *domain,
3520 struct dmar_domain *dmar_domain = domain->priv;
3521 struct pci_dev *pdev = to_pci_dev(dev);
3522 struct intel_iommu *iommu;
3526 /* normally pdev is not mapped */
3527 if (unlikely(domain_context_mapped(pdev))) {
3528 struct dmar_domain *old_domain;
3530 old_domain = find_domain(pdev);
3532 if (dmar_domain->flags & DOMAIN_FLAG_VIRTUAL_MACHINE ||
3533 dmar_domain->flags & DOMAIN_FLAG_STATIC_IDENTITY)
3534 domain_remove_one_dev_info(old_domain, pdev);
3536 domain_remove_dev_info(old_domain);
3540 iommu = device_to_iommu(pci_domain_nr(pdev->bus), pdev->bus->number,
3545 /* check if this iommu agaw is sufficient for max mapped address */
3546 addr_width = agaw_to_width(iommu->agaw);
3547 end = DOMAIN_MAX_ADDR(addr_width);
3548 end = end & VTD_PAGE_MASK;
3549 if (end < dmar_domain->max_addr) {
3550 printk(KERN_ERR "%s: iommu agaw (%d) is not "
3551 "sufficient for the mapped address (%llx)\n",
3552 __func__, iommu->agaw, dmar_domain->max_addr);
3556 return domain_add_dev_info(dmar_domain, pdev, CONTEXT_TT_MULTI_LEVEL);
3559 static void intel_iommu_detach_device(struct iommu_domain *domain,
3562 struct dmar_domain *dmar_domain = domain->priv;
3563 struct pci_dev *pdev = to_pci_dev(dev);
3565 domain_remove_one_dev_info(dmar_domain, pdev);
3568 static int intel_iommu_map_range(struct iommu_domain *domain,
3569 unsigned long iova, phys_addr_t hpa,
3570 size_t size, int iommu_prot)
3572 struct dmar_domain *dmar_domain = domain->priv;
3578 if (iommu_prot & IOMMU_READ)
3579 prot |= DMA_PTE_READ;
3580 if (iommu_prot & IOMMU_WRITE)
3581 prot |= DMA_PTE_WRITE;
3582 if ((iommu_prot & IOMMU_CACHE) && dmar_domain->iommu_snooping)
3583 prot |= DMA_PTE_SNP;
3585 max_addr = iova + size;
3586 if (dmar_domain->max_addr < max_addr) {
3590 /* check if minimum agaw is sufficient for mapped address */
3591 min_agaw = vm_domain_min_agaw(dmar_domain);
3592 addr_width = agaw_to_width(min_agaw);
3593 end = DOMAIN_MAX_ADDR(addr_width);
3594 end = end & VTD_PAGE_MASK;
3595 if (end < max_addr) {
3596 printk(KERN_ERR "%s: iommu agaw (%d) is not "
3597 "sufficient for the mapped address (%llx)\n",
3598 __func__, min_agaw, max_addr);
3601 dmar_domain->max_addr = max_addr;
3603 /* Round up size to next multiple of PAGE_SIZE, if it and
3604 the low bits of hpa would take us onto the next page */
3605 size = aligned_nrpages(hpa, size);
3606 ret = domain_pfn_mapping(dmar_domain, iova >> VTD_PAGE_SHIFT,
3607 hpa >> VTD_PAGE_SHIFT, size, prot);
3611 static void intel_iommu_unmap_range(struct iommu_domain *domain,
3612 unsigned long iova, size_t size)
3614 struct dmar_domain *dmar_domain = domain->priv;
3619 dma_pte_clear_range(dmar_domain, iova >> VTD_PAGE_SHIFT,
3620 (iova + size - 1) >> VTD_PAGE_SHIFT);
3622 if (dmar_domain->max_addr == iova + size)
3623 dmar_domain->max_addr = iova;
3626 static phys_addr_t intel_iommu_iova_to_phys(struct iommu_domain *domain,
3629 struct dmar_domain *dmar_domain = domain->priv;
3630 struct dma_pte *pte;
3633 pte = pfn_to_dma_pte(dmar_domain, iova >> VTD_PAGE_SHIFT);
3635 phys = dma_pte_addr(pte);
3640 static int intel_iommu_domain_has_cap(struct iommu_domain *domain,
3643 struct dmar_domain *dmar_domain = domain->priv;
3645 if (cap == IOMMU_CAP_CACHE_COHERENCY)
3646 return dmar_domain->iommu_snooping;
3651 static struct iommu_ops intel_iommu_ops = {
3652 .domain_init = intel_iommu_domain_init,
3653 .domain_destroy = intel_iommu_domain_destroy,
3654 .attach_dev = intel_iommu_attach_device,
3655 .detach_dev = intel_iommu_detach_device,
3656 .map = intel_iommu_map_range,
3657 .unmap = intel_iommu_unmap_range,
3658 .iova_to_phys = intel_iommu_iova_to_phys,
3659 .domain_has_cap = intel_iommu_domain_has_cap,
3662 static void __devinit quirk_iommu_rwbf(struct pci_dev *dev)
3665 * Mobile 4 Series Chipset neglects to set RWBF capability,
3668 printk(KERN_INFO "DMAR: Forcing write-buffer flush capability\n");
3672 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_rwbf);