4 * Copyright (C) 2009 Intel Corporation, Yu Zhao <yu.zhao@intel.com>
6 * PCI Express I/O Virtualization (IOV) support.
8 * Address Translation Service 1.0
11 #include <linux/pci.h>
12 #include <linux/mutex.h>
13 #include <linux/string.h>
14 #include <linux/delay.h>
17 #define VIRTFN_ID_LEN 16
19 static inline u8 virtfn_bus(struct pci_dev *dev, int id)
21 return dev->bus->number + ((dev->devfn + dev->sriov->offset +
22 dev->sriov->stride * id) >> 8);
25 static inline u8 virtfn_devfn(struct pci_dev *dev, int id)
27 return (dev->devfn + dev->sriov->offset +
28 dev->sriov->stride * id) & 0xff;
31 static struct pci_bus *virtfn_add_bus(struct pci_bus *bus, int busnr)
34 struct pci_bus *child;
36 if (bus->number == busnr)
39 child = pci_find_bus(pci_domain_nr(bus), busnr);
43 child = pci_add_new_bus(bus, NULL, busnr);
47 child->subordinate = busnr;
48 child->dev.parent = bus->bridge;
49 rc = pci_bus_add_child(child);
51 pci_remove_bus(child);
58 static void virtfn_remove_bus(struct pci_bus *bus, int busnr)
60 struct pci_bus *child;
62 if (bus->number == busnr)
65 child = pci_find_bus(pci_domain_nr(bus), busnr);
68 if (list_empty(&child->devices))
69 pci_remove_bus(child);
72 static int virtfn_add(struct pci_dev *dev, int id, int reset)
77 char buf[VIRTFN_ID_LEN];
78 struct pci_dev *virtfn;
80 struct pci_sriov *iov = dev->sriov;
82 virtfn = alloc_pci_dev();
86 mutex_lock(&iov->dev->sriov->lock);
87 virtfn->bus = virtfn_add_bus(dev->bus, virtfn_bus(dev, id));
90 mutex_unlock(&iov->dev->sriov->lock);
93 virtfn->devfn = virtfn_devfn(dev, id);
94 virtfn->vendor = dev->vendor;
95 pci_read_config_word(dev, iov->pos + PCI_SRIOV_VF_DID, &virtfn->device);
96 pci_setup_device(virtfn);
97 virtfn->dev.parent = dev->dev.parent;
99 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
100 res = dev->resource + PCI_IOV_RESOURCES + i;
103 virtfn->resource[i].name = pci_name(virtfn);
104 virtfn->resource[i].flags = res->flags;
105 size = resource_size(res);
106 do_div(size, iov->total);
107 virtfn->resource[i].start = res->start + size * id;
108 virtfn->resource[i].end = virtfn->resource[i].start + size - 1;
109 rc = request_resource(res, &virtfn->resource[i]);
114 __pci_reset_function(virtfn);
116 pci_device_add(virtfn, virtfn->bus);
117 mutex_unlock(&iov->dev->sriov->lock);
119 virtfn->physfn = pci_dev_get(dev);
120 virtfn->is_virtfn = 1;
122 rc = pci_bus_add_device(virtfn);
125 sprintf(buf, "virtfn%u", id);
126 rc = sysfs_create_link(&dev->dev.kobj, &virtfn->dev.kobj, buf);
129 rc = sysfs_create_link(&virtfn->dev.kobj, &dev->dev.kobj, "physfn");
133 kobject_uevent(&virtfn->dev.kobj, KOBJ_CHANGE);
138 sysfs_remove_link(&dev->dev.kobj, buf);
141 mutex_lock(&iov->dev->sriov->lock);
142 pci_remove_bus_device(virtfn);
143 virtfn_remove_bus(dev->bus, virtfn_bus(dev, id));
144 mutex_unlock(&iov->dev->sriov->lock);
149 static void virtfn_remove(struct pci_dev *dev, int id, int reset)
151 char buf[VIRTFN_ID_LEN];
153 struct pci_dev *virtfn;
154 struct pci_sriov *iov = dev->sriov;
156 bus = pci_find_bus(pci_domain_nr(dev->bus), virtfn_bus(dev, id));
160 virtfn = pci_get_slot(bus, virtfn_devfn(dev, id));
167 device_release_driver(&virtfn->dev);
168 __pci_reset_function(virtfn);
171 sprintf(buf, "virtfn%u", id);
172 sysfs_remove_link(&dev->dev.kobj, buf);
173 sysfs_remove_link(&virtfn->dev.kobj, "physfn");
175 mutex_lock(&iov->dev->sriov->lock);
176 pci_remove_bus_device(virtfn);
177 virtfn_remove_bus(dev->bus, virtfn_bus(dev, id));
178 mutex_unlock(&iov->dev->sriov->lock);
183 static int sriov_migration(struct pci_dev *dev)
186 struct pci_sriov *iov = dev->sriov;
191 if (!(iov->cap & PCI_SRIOV_CAP_VFM))
194 pci_read_config_word(dev, iov->pos + PCI_SRIOV_STATUS, &status);
195 if (!(status & PCI_SRIOV_STATUS_VFM))
198 schedule_work(&iov->mtask);
203 static void sriov_migration_task(struct work_struct *work)
208 struct pci_sriov *iov = container_of(work, struct pci_sriov, mtask);
210 for (i = iov->initial; i < iov->nr_virtfn; i++) {
211 state = readb(iov->mstate + i);
212 if (state == PCI_SRIOV_VFM_MI) {
213 writeb(PCI_SRIOV_VFM_AV, iov->mstate + i);
214 state = readb(iov->mstate + i);
215 if (state == PCI_SRIOV_VFM_AV)
216 virtfn_add(iov->self, i, 1);
217 } else if (state == PCI_SRIOV_VFM_MO) {
218 virtfn_remove(iov->self, i, 1);
219 writeb(PCI_SRIOV_VFM_UA, iov->mstate + i);
220 state = readb(iov->mstate + i);
221 if (state == PCI_SRIOV_VFM_AV)
222 virtfn_add(iov->self, i, 0);
226 pci_read_config_word(iov->self, iov->pos + PCI_SRIOV_STATUS, &status);
227 status &= ~PCI_SRIOV_STATUS_VFM;
228 pci_write_config_word(iov->self, iov->pos + PCI_SRIOV_STATUS, status);
231 static int sriov_enable_migration(struct pci_dev *dev, int nr_virtfn)
236 struct pci_sriov *iov = dev->sriov;
238 if (nr_virtfn <= iov->initial)
241 pci_read_config_dword(dev, iov->pos + PCI_SRIOV_VFM, &table);
242 bir = PCI_SRIOV_VFM_BIR(table);
243 if (bir > PCI_STD_RESOURCE_END)
246 table = PCI_SRIOV_VFM_OFFSET(table);
247 if (table + nr_virtfn > pci_resource_len(dev, bir))
250 pa = pci_resource_start(dev, bir) + table;
251 iov->mstate = ioremap(pa, nr_virtfn);
255 INIT_WORK(&iov->mtask, sriov_migration_task);
257 iov->ctrl |= PCI_SRIOV_CTRL_VFM | PCI_SRIOV_CTRL_INTR;
258 pci_write_config_word(dev, iov->pos + PCI_SRIOV_CTRL, iov->ctrl);
263 static void sriov_disable_migration(struct pci_dev *dev)
265 struct pci_sriov *iov = dev->sriov;
267 iov->ctrl &= ~(PCI_SRIOV_CTRL_VFM | PCI_SRIOV_CTRL_INTR);
268 pci_write_config_word(dev, iov->pos + PCI_SRIOV_CTRL, iov->ctrl);
270 cancel_work_sync(&iov->mtask);
271 iounmap(iov->mstate);
274 static int sriov_enable(struct pci_dev *dev, int nr_virtfn)
279 u16 offset, stride, initial;
280 struct resource *res;
281 struct pci_dev *pdev;
282 struct pci_sriov *iov = dev->sriov;
290 pci_read_config_word(dev, iov->pos + PCI_SRIOV_INITIAL_VF, &initial);
291 if (initial > iov->total ||
292 (!(iov->cap & PCI_SRIOV_CAP_VFM) && (initial != iov->total)))
295 if (nr_virtfn < 0 || nr_virtfn > iov->total ||
296 (!(iov->cap & PCI_SRIOV_CAP_VFM) && (nr_virtfn > initial)))
299 pci_write_config_word(dev, iov->pos + PCI_SRIOV_NUM_VF, nr_virtfn);
300 pci_read_config_word(dev, iov->pos + PCI_SRIOV_VF_OFFSET, &offset);
301 pci_read_config_word(dev, iov->pos + PCI_SRIOV_VF_STRIDE, &stride);
302 if (!offset || (nr_virtfn > 1 && !stride))
306 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
307 res = dev->resource + PCI_IOV_RESOURCES + i;
311 if (nres != iov->nres) {
312 dev_err(&dev->dev, "not enough MMIO resources for SR-IOV\n");
316 iov->offset = offset;
317 iov->stride = stride;
319 if (virtfn_bus(dev, nr_virtfn - 1) > dev->bus->subordinate) {
320 dev_err(&dev->dev, "SR-IOV: bus number out of range\n");
324 if (iov->link != dev->devfn) {
325 pdev = pci_get_slot(dev->bus, iov->link);
331 if (!pdev->is_physfn)
334 rc = sysfs_create_link(&dev->dev.kobj,
335 &pdev->dev.kobj, "dep_link");
340 iov->ctrl |= PCI_SRIOV_CTRL_VFE | PCI_SRIOV_CTRL_MSE;
341 pci_block_user_cfg_access(dev);
342 pci_write_config_word(dev, iov->pos + PCI_SRIOV_CTRL, iov->ctrl);
344 pci_unblock_user_cfg_access(dev);
346 iov->initial = initial;
347 if (nr_virtfn < initial)
350 for (i = 0; i < initial; i++) {
351 rc = virtfn_add(dev, i, 0);
356 if (iov->cap & PCI_SRIOV_CAP_VFM) {
357 rc = sriov_enable_migration(dev, nr_virtfn);
362 kobject_uevent(&dev->dev.kobj, KOBJ_CHANGE);
363 iov->nr_virtfn = nr_virtfn;
368 for (j = 0; j < i; j++)
369 virtfn_remove(dev, j, 0);
371 iov->ctrl &= ~(PCI_SRIOV_CTRL_VFE | PCI_SRIOV_CTRL_MSE);
372 pci_block_user_cfg_access(dev);
373 pci_write_config_word(dev, iov->pos + PCI_SRIOV_CTRL, iov->ctrl);
375 pci_unblock_user_cfg_access(dev);
377 if (iov->link != dev->devfn)
378 sysfs_remove_link(&dev->dev.kobj, "dep_link");
383 static void sriov_disable(struct pci_dev *dev)
386 struct pci_sriov *iov = dev->sriov;
391 if (iov->cap & PCI_SRIOV_CAP_VFM)
392 sriov_disable_migration(dev);
394 for (i = 0; i < iov->nr_virtfn; i++)
395 virtfn_remove(dev, i, 0);
397 iov->ctrl &= ~(PCI_SRIOV_CTRL_VFE | PCI_SRIOV_CTRL_MSE);
398 pci_block_user_cfg_access(dev);
399 pci_write_config_word(dev, iov->pos + PCI_SRIOV_CTRL, iov->ctrl);
401 pci_unblock_user_cfg_access(dev);
403 if (iov->link != dev->devfn)
404 sysfs_remove_link(&dev->dev.kobj, "dep_link");
409 static int sriov_init(struct pci_dev *dev, int pos)
415 u16 ctrl, total, offset, stride;
416 struct pci_sriov *iov;
417 struct resource *res;
418 struct pci_dev *pdev;
420 if (dev->pcie_type != PCI_EXP_TYPE_RC_END &&
421 dev->pcie_type != PCI_EXP_TYPE_ENDPOINT)
424 pci_read_config_word(dev, pos + PCI_SRIOV_CTRL, &ctrl);
425 if (ctrl & PCI_SRIOV_CTRL_VFE) {
426 pci_write_config_word(dev, pos + PCI_SRIOV_CTRL, 0);
430 pci_read_config_word(dev, pos + PCI_SRIOV_TOTAL_VF, &total);
435 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
440 if (pci_ari_enabled(dev->bus))
441 ctrl |= PCI_SRIOV_CTRL_ARI;
444 pci_write_config_word(dev, pos + PCI_SRIOV_CTRL, ctrl);
445 pci_write_config_word(dev, pos + PCI_SRIOV_NUM_VF, total);
446 pci_read_config_word(dev, pos + PCI_SRIOV_VF_OFFSET, &offset);
447 pci_read_config_word(dev, pos + PCI_SRIOV_VF_STRIDE, &stride);
448 if (!offset || (total > 1 && !stride))
451 pci_read_config_dword(dev, pos + PCI_SRIOV_SUP_PGSIZE, &pgsz);
452 i = PAGE_SHIFT > 12 ? PAGE_SHIFT - 12 : 0;
453 pgsz &= ~((1 << i) - 1);
458 pci_write_config_dword(dev, pos + PCI_SRIOV_SYS_PGSIZE, pgsz);
461 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
462 res = dev->resource + PCI_IOV_RESOURCES + i;
463 i += __pci_read_base(dev, pci_bar_unknown, res,
464 pos + PCI_SRIOV_BAR + i * 4);
467 if (resource_size(res) & (PAGE_SIZE - 1)) {
471 res->end = res->start + resource_size(res) * total - 1;
475 iov = kzalloc(sizeof(*iov), GFP_KERNEL);
485 iov->offset = offset;
486 iov->stride = stride;
489 pci_read_config_dword(dev, pos + PCI_SRIOV_CAP, &iov->cap);
490 pci_read_config_byte(dev, pos + PCI_SRIOV_FUNC_LINK, &iov->link);
491 if (dev->pcie_type == PCI_EXP_TYPE_RC_END)
492 iov->link = PCI_DEVFN(PCI_SLOT(dev->devfn), iov->link);
495 iov->dev = pci_dev_get(pdev);
499 mutex_init(&iov->lock);
507 for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
508 res = dev->resource + PCI_IOV_RESOURCES + i;
515 static void sriov_release(struct pci_dev *dev)
517 BUG_ON(dev->sriov->nr_virtfn);
519 if (dev != dev->sriov->dev)
520 pci_dev_put(dev->sriov->dev);
522 mutex_destroy(&dev->sriov->lock);
528 static void sriov_restore_state(struct pci_dev *dev)
532 struct pci_sriov *iov = dev->sriov;
534 pci_read_config_word(dev, iov->pos + PCI_SRIOV_CTRL, &ctrl);
535 if (ctrl & PCI_SRIOV_CTRL_VFE)
538 for (i = PCI_IOV_RESOURCES; i <= PCI_IOV_RESOURCE_END; i++)
539 pci_update_resource(dev, i);
541 pci_write_config_dword(dev, iov->pos + PCI_SRIOV_SYS_PGSIZE, iov->pgsz);
542 pci_write_config_word(dev, iov->pos + PCI_SRIOV_NUM_VF, iov->nr_virtfn);
543 pci_write_config_word(dev, iov->pos + PCI_SRIOV_CTRL, iov->ctrl);
544 if (iov->ctrl & PCI_SRIOV_CTRL_VFE)
549 * pci_iov_init - initialize the IOV capability
550 * @dev: the PCI device
552 * Returns 0 on success, or negative on failure.
554 int pci_iov_init(struct pci_dev *dev)
558 if (!pci_is_pcie(dev))
561 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_SRIOV);
563 return sriov_init(dev, pos);
569 * pci_iov_release - release resources used by the IOV capability
570 * @dev: the PCI device
572 void pci_iov_release(struct pci_dev *dev)
579 * pci_iov_resource_bar - get position of the SR-IOV BAR
580 * @dev: the PCI device
581 * @resno: the resource number
582 * @type: the BAR type to be filled in
584 * Returns position of the BAR encapsulated in the SR-IOV capability.
586 int pci_iov_resource_bar(struct pci_dev *dev, int resno,
587 enum pci_bar_type *type)
589 if (resno < PCI_IOV_RESOURCES || resno > PCI_IOV_RESOURCE_END)
592 BUG_ON(!dev->is_physfn);
594 *type = pci_bar_unknown;
596 return dev->sriov->pos + PCI_SRIOV_BAR +
597 4 * (resno - PCI_IOV_RESOURCES);
601 * pci_sriov_resource_alignment - get resource alignment for VF BAR
602 * @dev: the PCI device
603 * @resno: the resource number
605 * Returns the alignment of the VF BAR found in the SR-IOV capability.
606 * This is not the same as the resource size which is defined as
607 * the VF BAR size multiplied by the number of VFs. The alignment
608 * is just the VF BAR size.
610 int pci_sriov_resource_alignment(struct pci_dev *dev, int resno)
613 enum pci_bar_type type;
614 int reg = pci_iov_resource_bar(dev, resno, &type);
619 __pci_read_base(dev, type, &tmp, reg);
620 return resource_alignment(&tmp);
624 * pci_restore_iov_state - restore the state of the IOV capability
625 * @dev: the PCI device
627 void pci_restore_iov_state(struct pci_dev *dev)
630 sriov_restore_state(dev);
634 * pci_iov_bus_range - find bus range used by Virtual Function
637 * Returns max number of buses (exclude current one) used by Virtual
640 int pci_iov_bus_range(struct pci_bus *bus)
646 list_for_each_entry(dev, &bus->devices, bus_list) {
649 busnr = virtfn_bus(dev, dev->sriov->total - 1);
654 return max ? max - bus->number : 0;
658 * pci_enable_sriov - enable the SR-IOV capability
659 * @dev: the PCI device
660 * @nr_virtfn: number of virtual functions to enable
662 * Returns 0 on success, or negative on failure.
664 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
671 return sriov_enable(dev, nr_virtfn);
673 EXPORT_SYMBOL_GPL(pci_enable_sriov);
676 * pci_disable_sriov - disable the SR-IOV capability
677 * @dev: the PCI device
679 void pci_disable_sriov(struct pci_dev *dev)
688 EXPORT_SYMBOL_GPL(pci_disable_sriov);
691 * pci_sriov_migration - notify SR-IOV core of Virtual Function Migration
692 * @dev: the PCI device
694 * Returns IRQ_HANDLED if the IRQ is handled, or IRQ_NONE if not.
696 * Physical Function driver is responsible to register IRQ handler using
697 * VF Migration Interrupt Message Number, and call this function when the
698 * interrupt is generated by the hardware.
700 irqreturn_t pci_sriov_migration(struct pci_dev *dev)
705 return sriov_migration(dev) ? IRQ_HANDLED : IRQ_NONE;
707 EXPORT_SYMBOL_GPL(pci_sriov_migration);
710 * pci_num_vf - return number of VFs associated with a PF device_release_driver
711 * @dev: the PCI device
713 * Returns number of VFs, or 0 if SR-IOV is not enabled.
715 int pci_num_vf(struct pci_dev *dev)
717 if (!dev || !dev->is_physfn)
720 return dev->sriov->nr_virtfn;
722 EXPORT_SYMBOL_GPL(pci_num_vf);
724 static int ats_alloc_one(struct pci_dev *dev, int ps)
730 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ATS);
734 ats = kzalloc(sizeof(*ats), GFP_KERNEL);
740 pci_read_config_word(dev, pos + PCI_ATS_CAP, &cap);
741 ats->qdep = PCI_ATS_CAP_QDEP(cap) ? PCI_ATS_CAP_QDEP(cap) :
748 static void ats_free_one(struct pci_dev *dev)
755 * pci_enable_ats - enable the ATS capability
756 * @dev: the PCI device
757 * @ps: the IOMMU page shift
759 * Returns 0 on success, or negative on failure.
761 int pci_enable_ats(struct pci_dev *dev, int ps)
766 BUG_ON(dev->ats && dev->ats->is_enabled);
768 if (ps < PCI_ATS_MIN_STU)
771 if (dev->is_physfn || dev->is_virtfn) {
772 struct pci_dev *pdev = dev->is_physfn ? dev : dev->physfn;
774 mutex_lock(&pdev->sriov->lock);
776 rc = pdev->ats->stu == ps ? 0 : -EINVAL;
778 rc = ats_alloc_one(pdev, ps);
781 pdev->ats->ref_cnt++;
782 mutex_unlock(&pdev->sriov->lock);
787 if (!dev->is_physfn) {
788 rc = ats_alloc_one(dev, ps);
793 ctrl = PCI_ATS_CTRL_ENABLE;
795 ctrl |= PCI_ATS_CTRL_STU(ps - PCI_ATS_MIN_STU);
796 pci_write_config_word(dev, dev->ats->pos + PCI_ATS_CTRL, ctrl);
798 dev->ats->is_enabled = 1;
804 * pci_disable_ats - disable the ATS capability
805 * @dev: the PCI device
807 void pci_disable_ats(struct pci_dev *dev)
811 BUG_ON(!dev->ats || !dev->ats->is_enabled);
813 pci_read_config_word(dev, dev->ats->pos + PCI_ATS_CTRL, &ctrl);
814 ctrl &= ~PCI_ATS_CTRL_ENABLE;
815 pci_write_config_word(dev, dev->ats->pos + PCI_ATS_CTRL, ctrl);
817 dev->ats->is_enabled = 0;
819 if (dev->is_physfn || dev->is_virtfn) {
820 struct pci_dev *pdev = dev->is_physfn ? dev : dev->physfn;
822 mutex_lock(&pdev->sriov->lock);
823 pdev->ats->ref_cnt--;
824 if (!pdev->ats->ref_cnt)
826 mutex_unlock(&pdev->sriov->lock);
834 * pci_ats_queue_depth - query the ATS Invalidate Queue Depth
835 * @dev: the PCI device
837 * Returns the queue depth on success, or negative on failure.
839 * The ATS spec uses 0 in the Invalidate Queue Depth field to
840 * indicate that the function can accept 32 Invalidate Request.
841 * But here we use the `real' values (i.e. 1~32) for the Queue
842 * Depth; and 0 indicates the function shares the Queue with
843 * other functions (doesn't exclusively own a Queue).
845 int pci_ats_queue_depth(struct pci_dev *dev)
854 return dev->ats->qdep;
856 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ATS);
860 pci_read_config_word(dev, pos + PCI_ATS_CAP, &cap);
862 return PCI_ATS_CAP_QDEP(cap) ? PCI_ATS_CAP_QDEP(cap) :