3 * Purpose: PCI Message Signaled Interrupt (MSI)
5 * Copyright (C) 2003-2004 Intel
6 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
11 #include <linux/irq.h>
12 #include <linux/interrupt.h>
13 #include <linux/init.h>
14 #include <linux/ioport.h>
15 #include <linux/pci.h>
16 #include <linux/proc_fs.h>
17 #include <linux/msi.h>
18 #include <linux/smp.h>
19 #include <linux/errno.h>
21 #include <linux/slab.h>
26 static int pci_msi_enable = 1;
30 #ifndef arch_msi_check_device
31 int arch_msi_check_device(struct pci_dev *dev, int nvec, int type)
37 #ifndef arch_setup_msi_irqs
38 int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
40 struct msi_desc *entry;
44 * If an architecture wants to support multiple MSI, it needs to
45 * override arch_setup_msi_irqs()
47 if (type == PCI_CAP_ID_MSI && nvec > 1)
50 list_for_each_entry(entry, &dev->msi_list, list) {
51 ret = arch_setup_msi_irq(dev, entry);
62 #ifndef arch_teardown_msi_irqs
63 void arch_teardown_msi_irqs(struct pci_dev *dev)
65 struct msi_desc *entry;
67 list_for_each_entry(entry, &dev->msi_list, list) {
71 nvec = 1 << entry->msi_attrib.multiple;
72 for (i = 0; i < nvec; i++)
73 arch_teardown_msi_irq(entry->irq + i);
78 static void msi_set_enable(struct pci_dev *dev, int pos, int enable)
84 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
85 control &= ~PCI_MSI_FLAGS_ENABLE;
87 control |= PCI_MSI_FLAGS_ENABLE;
88 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
91 static void msix_set_enable(struct pci_dev *dev, int enable)
96 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
98 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
99 control &= ~PCI_MSIX_FLAGS_ENABLE;
101 control |= PCI_MSIX_FLAGS_ENABLE;
102 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
106 static inline __attribute_const__ u32 msi_mask(unsigned x)
108 /* Don't shift by >= width of type */
111 return (1 << (1 << x)) - 1;
114 static inline __attribute_const__ u32 msi_capable_mask(u16 control)
116 return msi_mask((control >> 1) & 7);
119 static inline __attribute_const__ u32 msi_enabled_mask(u16 control)
121 return msi_mask((control >> 4) & 7);
125 * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to
126 * mask all MSI interrupts by clearing the MSI enable bit does not work
127 * reliably as devices without an INTx disable bit will then generate a
128 * level IRQ which will never be cleared.
130 static u32 __msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
132 u32 mask_bits = desc->masked;
134 if (!desc->msi_attrib.maskbit)
139 pci_write_config_dword(desc->dev, desc->mask_pos, mask_bits);
144 static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
146 desc->masked = __msi_mask_irq(desc, mask, flag);
150 * This internal function does not flush PCI writes to the device.
151 * All users must ensure that they read from the device before either
152 * assuming that the device state is up to date, or returning out of this
153 * file. This saves a few milliseconds when initialising devices with lots
154 * of MSI-X interrupts.
156 static u32 __msix_mask_irq(struct msi_desc *desc, u32 flag)
158 u32 mask_bits = desc->masked;
159 unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
160 PCI_MSIX_ENTRY_VECTOR_CTRL;
163 writel(mask_bits, desc->mask_base + offset);
168 static void msix_mask_irq(struct msi_desc *desc, u32 flag)
170 desc->masked = __msix_mask_irq(desc, flag);
173 static void msi_set_mask_bit(unsigned irq, u32 flag)
175 struct msi_desc *desc = get_irq_msi(irq);
177 if (desc->msi_attrib.is_msix) {
178 msix_mask_irq(desc, flag);
179 readl(desc->mask_base); /* Flush write to device */
181 unsigned offset = irq - desc->dev->irq;
182 msi_mask_irq(desc, 1 << offset, flag << offset);
186 void mask_msi_irq(unsigned int irq)
188 msi_set_mask_bit(irq, 1);
191 void unmask_msi_irq(unsigned int irq)
193 msi_set_mask_bit(irq, 0);
196 void read_msi_msg_desc(struct irq_desc *desc, struct msi_msg *msg)
198 struct msi_desc *entry = get_irq_desc_msi(desc);
200 /* We do not touch the hardware (which may not even be
201 * accessible at the moment) but return the last message
202 * written. Assert that this is valid, assuming that
203 * valid messages are not all-zeroes. */
204 BUG_ON(!(entry->msg.address_hi | entry->msg.address_lo |
210 void read_msi_msg(unsigned int irq, struct msi_msg *msg)
212 struct irq_desc *desc = irq_to_desc(irq);
214 read_msi_msg_desc(desc, msg);
217 void write_msi_msg_desc(struct irq_desc *desc, struct msi_msg *msg)
219 struct msi_desc *entry = get_irq_desc_msi(desc);
221 if (entry->dev->current_state != PCI_D0) {
222 /* Don't touch the hardware now */
223 } else if (entry->msi_attrib.is_msix) {
225 base = entry->mask_base +
226 entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
228 writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR);
229 writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR);
230 writel(msg->data, base + PCI_MSIX_ENTRY_DATA);
232 struct pci_dev *dev = entry->dev;
233 int pos = entry->msi_attrib.pos;
236 pci_read_config_word(dev, msi_control_reg(pos), &msgctl);
237 msgctl &= ~PCI_MSI_FLAGS_QSIZE;
238 msgctl |= entry->msi_attrib.multiple << 4;
239 pci_write_config_word(dev, msi_control_reg(pos), msgctl);
241 pci_write_config_dword(dev, msi_lower_address_reg(pos),
243 if (entry->msi_attrib.is_64) {
244 pci_write_config_dword(dev, msi_upper_address_reg(pos),
246 pci_write_config_word(dev, msi_data_reg(pos, 1),
249 pci_write_config_word(dev, msi_data_reg(pos, 0),
256 void write_msi_msg(unsigned int irq, struct msi_msg *msg)
258 struct irq_desc *desc = irq_to_desc(irq);
260 write_msi_msg_desc(desc, msg);
263 static void free_msi_irqs(struct pci_dev *dev)
265 struct msi_desc *entry, *tmp;
267 list_for_each_entry(entry, &dev->msi_list, list) {
271 nvec = 1 << entry->msi_attrib.multiple;
272 for (i = 0; i < nvec; i++)
273 BUG_ON(irq_has_action(entry->irq + i));
276 arch_teardown_msi_irqs(dev);
278 list_for_each_entry_safe(entry, tmp, &dev->msi_list, list) {
279 if (entry->msi_attrib.is_msix) {
280 if (list_is_last(&entry->list, &dev->msi_list))
281 iounmap(entry->mask_base);
283 list_del(&entry->list);
288 static struct msi_desc *alloc_msi_entry(struct pci_dev *dev)
290 struct msi_desc *desc = kzalloc(sizeof(*desc), GFP_KERNEL);
294 INIT_LIST_HEAD(&desc->list);
300 static void pci_intx_for_msi(struct pci_dev *dev, int enable)
302 if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG))
303 pci_intx(dev, enable);
306 static void __pci_restore_msi_state(struct pci_dev *dev)
310 struct msi_desc *entry;
312 if (!dev->msi_enabled)
315 entry = get_irq_msi(dev->irq);
316 pos = entry->msi_attrib.pos;
318 pci_intx_for_msi(dev, 0);
319 msi_set_enable(dev, pos, 0);
320 write_msi_msg(dev->irq, &entry->msg);
322 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
323 msi_mask_irq(entry, msi_capable_mask(control), entry->masked);
324 control &= ~PCI_MSI_FLAGS_QSIZE;
325 control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE;
326 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
329 static void __pci_restore_msix_state(struct pci_dev *dev)
332 struct msi_desc *entry;
335 if (!dev->msix_enabled)
337 BUG_ON(list_empty(&dev->msi_list));
338 entry = list_first_entry(&dev->msi_list, struct msi_desc, list);
339 pos = entry->msi_attrib.pos;
340 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
342 /* route the table */
343 pci_intx_for_msi(dev, 0);
344 control |= PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL;
345 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
347 list_for_each_entry(entry, &dev->msi_list, list) {
348 write_msi_msg(entry->irq, &entry->msg);
349 msix_mask_irq(entry, entry->masked);
352 control &= ~PCI_MSIX_FLAGS_MASKALL;
353 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
356 void pci_restore_msi_state(struct pci_dev *dev)
358 __pci_restore_msi_state(dev);
359 __pci_restore_msix_state(dev);
361 EXPORT_SYMBOL_GPL(pci_restore_msi_state);
364 * msi_capability_init - configure device's MSI capability structure
365 * @dev: pointer to the pci_dev data structure of MSI device function
366 * @nvec: number of interrupts to allocate
368 * Setup the MSI capability structure of the device with the requested
369 * number of interrupts. A return value of zero indicates the successful
370 * setup of an entry with the new MSI irq. A negative return value indicates
371 * an error, and a positive return value indicates the number of interrupts
372 * which could have been allocated.
374 static int msi_capability_init(struct pci_dev *dev, int nvec)
376 struct msi_desc *entry;
381 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
382 msi_set_enable(dev, pos, 0); /* Disable MSI during set up */
384 pci_read_config_word(dev, msi_control_reg(pos), &control);
385 /* MSI Entry Initialization */
386 entry = alloc_msi_entry(dev);
390 entry->msi_attrib.is_msix = 0;
391 entry->msi_attrib.is_64 = is_64bit_address(control);
392 entry->msi_attrib.entry_nr = 0;
393 entry->msi_attrib.maskbit = is_mask_bit_support(control);
394 entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */
395 entry->msi_attrib.pos = pos;
397 entry->mask_pos = msi_mask_reg(pos, entry->msi_attrib.is_64);
398 /* All MSIs are unmasked by default, Mask them all */
399 if (entry->msi_attrib.maskbit)
400 pci_read_config_dword(dev, entry->mask_pos, &entry->masked);
401 mask = msi_capable_mask(control);
402 msi_mask_irq(entry, mask, mask);
404 list_add_tail(&entry->list, &dev->msi_list);
406 /* Configure MSI capability structure */
407 ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI);
409 msi_mask_irq(entry, mask, ~mask);
414 /* Set MSI enabled bits */
415 pci_intx_for_msi(dev, 0);
416 msi_set_enable(dev, pos, 1);
417 dev->msi_enabled = 1;
419 dev->irq = entry->irq;
423 static void __iomem *msix_map_region(struct pci_dev *dev, unsigned pos,
426 resource_size_t phys_addr;
430 pci_read_config_dword(dev, msix_table_offset_reg(pos), &table_offset);
431 bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK);
432 table_offset &= ~PCI_MSIX_FLAGS_BIRMASK;
433 phys_addr = pci_resource_start(dev, bir) + table_offset;
435 return ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE);
438 static int msix_setup_entries(struct pci_dev *dev, unsigned pos,
439 void __iomem *base, struct msix_entry *entries,
442 struct msi_desc *entry;
445 for (i = 0; i < nvec; i++) {
446 entry = alloc_msi_entry(dev);
452 /* No enough memory. Don't try again */
456 entry->msi_attrib.is_msix = 1;
457 entry->msi_attrib.is_64 = 1;
458 entry->msi_attrib.entry_nr = entries[i].entry;
459 entry->msi_attrib.default_irq = dev->irq;
460 entry->msi_attrib.pos = pos;
461 entry->mask_base = base;
463 list_add_tail(&entry->list, &dev->msi_list);
469 static void msix_program_entries(struct pci_dev *dev,
470 struct msix_entry *entries)
472 struct msi_desc *entry;
475 list_for_each_entry(entry, &dev->msi_list, list) {
476 int offset = entries[i].entry * PCI_MSIX_ENTRY_SIZE +
477 PCI_MSIX_ENTRY_VECTOR_CTRL;
479 entries[i].vector = entry->irq;
480 set_irq_msi(entry->irq, entry);
481 entry->masked = readl(entry->mask_base + offset);
482 msix_mask_irq(entry, 1);
488 * msix_capability_init - configure device's MSI-X capability
489 * @dev: pointer to the pci_dev data structure of MSI-X device function
490 * @entries: pointer to an array of struct msix_entry entries
491 * @nvec: number of @entries
493 * Setup the MSI-X capability structure of device function with a
494 * single MSI-X irq. A return of zero indicates the successful setup of
495 * requested MSI-X entries with allocated irqs or non-zero for otherwise.
497 static int msix_capability_init(struct pci_dev *dev,
498 struct msix_entry *entries, int nvec)
504 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
505 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
507 /* Ensure MSI-X is disabled while it is set up */
508 control &= ~PCI_MSIX_FLAGS_ENABLE;
509 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
511 /* Request & Map MSI-X table region */
512 base = msix_map_region(dev, pos, multi_msix_capable(control));
516 ret = msix_setup_entries(dev, pos, base, entries, nvec);
520 ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX);
525 * Some devices require MSI-X to be enabled before we can touch the
526 * MSI-X registers. We need to mask all the vectors to prevent
527 * interrupts coming in before they're fully set up.
529 control |= PCI_MSIX_FLAGS_MASKALL | PCI_MSIX_FLAGS_ENABLE;
530 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
532 msix_program_entries(dev, entries);
534 /* Set MSI-X enabled bits and unmask the function */
535 pci_intx_for_msi(dev, 0);
536 dev->msix_enabled = 1;
538 control &= ~PCI_MSIX_FLAGS_MASKALL;
539 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
546 * If we had some success, report the number of irqs
547 * we succeeded in setting up.
549 struct msi_desc *entry;
552 list_for_each_entry(entry, &dev->msi_list, list) {
566 * pci_msi_check_device - check whether MSI may be enabled on a device
567 * @dev: pointer to the pci_dev data structure of MSI device function
568 * @nvec: how many MSIs have been requested ?
569 * @type: are we checking for MSI or MSI-X ?
571 * Look at global flags, the device itself, and its parent busses
572 * to determine if MSI/-X are supported for the device. If MSI/-X is
573 * supported return 0, else return an error code.
575 static int pci_msi_check_device(struct pci_dev *dev, int nvec, int type)
580 /* MSI must be globally enabled and supported by the device */
581 if (!pci_msi_enable || !dev || dev->no_msi)
585 * You can't ask to have 0 or less MSIs configured.
587 * b) the list manipulation code assumes nvec >= 1.
593 * Any bridge which does NOT route MSI transactions from its
594 * secondary bus to its primary bus must set NO_MSI flag on
595 * the secondary pci_bus.
596 * We expect only arch-specific PCI host bus controller driver
597 * or quirks for specific PCI bridges to be setting NO_MSI.
599 for (bus = dev->bus; bus; bus = bus->parent)
600 if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI)
603 ret = arch_msi_check_device(dev, nvec, type);
607 if (!pci_find_capability(dev, type))
614 * pci_enable_msi_block - configure device's MSI capability structure
615 * @dev: device to configure
616 * @nvec: number of interrupts to configure
618 * Allocate IRQs for a device with the MSI capability.
619 * This function returns a negative errno if an error occurs. If it
620 * is unable to allocate the number of interrupts requested, it returns
621 * the number of interrupts it might be able to allocate. If it successfully
622 * allocates at least the number of interrupts requested, it returns 0 and
623 * updates the @dev's irq member to the lowest new interrupt number; the
624 * other interrupt numbers allocated to this device are consecutive.
626 int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec)
628 int status, pos, maxvec;
631 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
634 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl);
635 maxvec = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1);
639 status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSI);
643 WARN_ON(!!dev->msi_enabled);
645 /* Check whether driver already requested MSI-X irqs */
646 if (dev->msix_enabled) {
647 dev_info(&dev->dev, "can't enable MSI "
648 "(MSI-X already enabled)\n");
652 status = msi_capability_init(dev, nvec);
655 EXPORT_SYMBOL(pci_enable_msi_block);
657 void pci_msi_shutdown(struct pci_dev *dev)
659 struct msi_desc *desc;
664 if (!pci_msi_enable || !dev || !dev->msi_enabled)
667 BUG_ON(list_empty(&dev->msi_list));
668 desc = list_first_entry(&dev->msi_list, struct msi_desc, list);
669 pos = desc->msi_attrib.pos;
671 msi_set_enable(dev, pos, 0);
672 pci_intx_for_msi(dev, 1);
673 dev->msi_enabled = 0;
675 /* Return the device with MSI unmasked as initial states */
676 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &ctrl);
677 mask = msi_capable_mask(ctrl);
678 /* Keep cached state to be restored */
679 __msi_mask_irq(desc, mask, ~mask);
681 /* Restore dev->irq to its default pin-assertion irq */
682 dev->irq = desc->msi_attrib.default_irq;
685 void pci_disable_msi(struct pci_dev *dev)
687 if (!pci_msi_enable || !dev || !dev->msi_enabled)
690 pci_msi_shutdown(dev);
693 EXPORT_SYMBOL(pci_disable_msi);
696 * pci_msix_table_size - return the number of device's MSI-X table entries
697 * @dev: pointer to the pci_dev data structure of MSI-X device function
699 int pci_msix_table_size(struct pci_dev *dev)
704 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
708 pci_read_config_word(dev, msi_control_reg(pos), &control);
709 return multi_msix_capable(control);
713 * pci_enable_msix - configure device's MSI-X capability structure
714 * @dev: pointer to the pci_dev data structure of MSI-X device function
715 * @entries: pointer to an array of MSI-X entries
716 * @nvec: number of MSI-X irqs requested for allocation by device driver
718 * Setup the MSI-X capability structure of device function with the number
719 * of requested irqs upon its software driver call to request for
720 * MSI-X mode enabled on its hardware device function. A return of zero
721 * indicates the successful configuration of MSI-X capability structure
722 * with new allocated MSI-X irqs. A return of < 0 indicates a failure.
723 * Or a return of > 0 indicates that driver request is exceeding the number
724 * of irqs or MSI-X vectors available. Driver should use the returned value to
725 * re-send its request.
727 int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec)
729 int status, nr_entries;
735 status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSIX);
739 nr_entries = pci_msix_table_size(dev);
740 if (nvec > nr_entries)
743 /* Check for any invalid entries */
744 for (i = 0; i < nvec; i++) {
745 if (entries[i].entry >= nr_entries)
746 return -EINVAL; /* invalid entry */
747 for (j = i + 1; j < nvec; j++) {
748 if (entries[i].entry == entries[j].entry)
749 return -EINVAL; /* duplicate entry */
752 WARN_ON(!!dev->msix_enabled);
754 /* Check whether driver already requested for MSI irq */
755 if (dev->msi_enabled) {
756 dev_info(&dev->dev, "can't enable MSI-X "
757 "(MSI IRQ already assigned)\n");
760 status = msix_capability_init(dev, entries, nvec);
763 EXPORT_SYMBOL(pci_enable_msix);
765 void pci_msix_shutdown(struct pci_dev *dev)
767 struct msi_desc *entry;
769 if (!pci_msi_enable || !dev || !dev->msix_enabled)
772 /* Return the device with MSI-X masked as initial states */
773 list_for_each_entry(entry, &dev->msi_list, list) {
774 /* Keep cached states to be restored */
775 __msix_mask_irq(entry, 1);
778 msix_set_enable(dev, 0);
779 pci_intx_for_msi(dev, 1);
780 dev->msix_enabled = 0;
783 void pci_disable_msix(struct pci_dev *dev)
785 if (!pci_msi_enable || !dev || !dev->msix_enabled)
788 pci_msix_shutdown(dev);
791 EXPORT_SYMBOL(pci_disable_msix);
794 * msi_remove_pci_irq_vectors - reclaim MSI(X) irqs to unused state
795 * @dev: pointer to the pci_dev data structure of MSI(X) device function
797 * Being called during hotplug remove, from which the device function
798 * is hot-removed. All previous assigned MSI/MSI-X irqs, if
799 * allocated for this device function, are reclaimed to unused state,
800 * which may be used later on.
802 void msi_remove_pci_irq_vectors(struct pci_dev *dev)
804 if (!pci_msi_enable || !dev)
807 if (dev->msi_enabled || dev->msix_enabled)
811 void pci_no_msi(void)
817 * pci_msi_enabled - is MSI enabled?
819 * Returns true if MSI has not been disabled by the command-line option
822 int pci_msi_enabled(void)
824 return pci_msi_enable;
826 EXPORT_SYMBOL(pci_msi_enabled);
828 void pci_msi_init_pci_dev(struct pci_dev *dev)
830 INIT_LIST_HEAD(&dev->msi_list);