3 * Purpose: PCI Message Signaled Interrupt (MSI)
5 * Copyright (C) 2003-2004 Intel
6 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
11 #include <linux/irq.h>
12 #include <linux/interrupt.h>
13 #include <linux/init.h>
14 #include <linux/export.h>
15 #include <linux/ioport.h>
16 #include <linux/pci.h>
17 #include <linux/proc_fs.h>
18 #include <linux/msi.h>
19 #include <linux/smp.h>
20 #include <linux/errno.h>
22 #include <linux/slab.h>
27 static int pci_msi_enable = 1;
31 #ifndef arch_msi_check_device
32 int arch_msi_check_device(struct pci_dev *dev, int nvec, int type)
38 #ifndef arch_setup_msi_irqs
39 # define arch_setup_msi_irqs default_setup_msi_irqs
40 # define HAVE_DEFAULT_MSI_SETUP_IRQS
43 #ifdef HAVE_DEFAULT_MSI_SETUP_IRQS
44 int default_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
46 struct msi_desc *entry;
50 * If an architecture wants to support multiple MSI, it needs to
51 * override arch_setup_msi_irqs()
53 if (type == PCI_CAP_ID_MSI && nvec > 1)
56 list_for_each_entry(entry, &dev->msi_list, list) {
57 ret = arch_setup_msi_irq(dev, entry);
68 #ifndef arch_teardown_msi_irqs
69 # define arch_teardown_msi_irqs default_teardown_msi_irqs
70 # define HAVE_DEFAULT_MSI_TEARDOWN_IRQS
73 #ifdef HAVE_DEFAULT_MSI_TEARDOWN_IRQS
74 void default_teardown_msi_irqs(struct pci_dev *dev)
76 struct msi_desc *entry;
78 list_for_each_entry(entry, &dev->msi_list, list) {
82 nvec = 1 << entry->msi_attrib.multiple;
83 for (i = 0; i < nvec; i++)
84 arch_teardown_msi_irq(entry->irq + i);
89 static void msi_set_enable(struct pci_dev *dev, int pos, int enable)
95 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
96 control &= ~PCI_MSI_FLAGS_ENABLE;
98 control |= PCI_MSI_FLAGS_ENABLE;
99 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
102 static void msix_set_enable(struct pci_dev *dev, int enable)
107 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
109 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
110 control &= ~PCI_MSIX_FLAGS_ENABLE;
112 control |= PCI_MSIX_FLAGS_ENABLE;
113 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
117 static inline __attribute_const__ u32 msi_mask(unsigned x)
119 /* Don't shift by >= width of type */
122 return (1 << (1 << x)) - 1;
125 static inline __attribute_const__ u32 msi_capable_mask(u16 control)
127 return msi_mask((control >> 1) & 7);
130 static inline __attribute_const__ u32 msi_enabled_mask(u16 control)
132 return msi_mask((control >> 4) & 7);
136 * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to
137 * mask all MSI interrupts by clearing the MSI enable bit does not work
138 * reliably as devices without an INTx disable bit will then generate a
139 * level IRQ which will never be cleared.
141 static u32 __msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
143 u32 mask_bits = desc->masked;
145 if (!desc->msi_attrib.maskbit)
150 pci_write_config_dword(desc->dev, desc->mask_pos, mask_bits);
155 static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
157 desc->masked = __msi_mask_irq(desc, mask, flag);
161 * This internal function does not flush PCI writes to the device.
162 * All users must ensure that they read from the device before either
163 * assuming that the device state is up to date, or returning out of this
164 * file. This saves a few milliseconds when initialising devices with lots
165 * of MSI-X interrupts.
167 static u32 __msix_mask_irq(struct msi_desc *desc, u32 flag)
169 u32 mask_bits = desc->masked;
170 unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
171 PCI_MSIX_ENTRY_VECTOR_CTRL;
172 mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT;
174 mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT;
175 writel(mask_bits, desc->mask_base + offset);
180 static void msix_mask_irq(struct msi_desc *desc, u32 flag)
182 desc->masked = __msix_mask_irq(desc, flag);
185 static void msi_set_mask_bit(struct irq_data *data, u32 flag)
187 struct msi_desc *desc = irq_data_get_msi(data);
189 if (desc->msi_attrib.is_msix) {
190 msix_mask_irq(desc, flag);
191 readl(desc->mask_base); /* Flush write to device */
193 unsigned offset = data->irq - desc->dev->irq;
194 msi_mask_irq(desc, 1 << offset, flag << offset);
198 void mask_msi_irq(struct irq_data *data)
200 msi_set_mask_bit(data, 1);
203 void unmask_msi_irq(struct irq_data *data)
205 msi_set_mask_bit(data, 0);
208 void __read_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
210 BUG_ON(entry->dev->current_state != PCI_D0);
212 if (entry->msi_attrib.is_msix) {
213 void __iomem *base = entry->mask_base +
214 entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
216 msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR);
217 msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR);
218 msg->data = readl(base + PCI_MSIX_ENTRY_DATA);
220 struct pci_dev *dev = entry->dev;
221 int pos = entry->msi_attrib.pos;
224 pci_read_config_dword(dev, msi_lower_address_reg(pos),
226 if (entry->msi_attrib.is_64) {
227 pci_read_config_dword(dev, msi_upper_address_reg(pos),
229 pci_read_config_word(dev, msi_data_reg(pos, 1), &data);
232 pci_read_config_word(dev, msi_data_reg(pos, 0), &data);
238 void read_msi_msg(unsigned int irq, struct msi_msg *msg)
240 struct msi_desc *entry = irq_get_msi_desc(irq);
242 __read_msi_msg(entry, msg);
245 void __get_cached_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
247 /* Assert that the cache is valid, assuming that
248 * valid messages are not all-zeroes. */
249 BUG_ON(!(entry->msg.address_hi | entry->msg.address_lo |
255 void get_cached_msi_msg(unsigned int irq, struct msi_msg *msg)
257 struct msi_desc *entry = irq_get_msi_desc(irq);
259 __get_cached_msi_msg(entry, msg);
262 void __write_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
264 if (entry->dev->current_state != PCI_D0) {
265 /* Don't touch the hardware now */
266 } else if (entry->msi_attrib.is_msix) {
268 base = entry->mask_base +
269 entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
271 writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR);
272 writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR);
273 writel(msg->data, base + PCI_MSIX_ENTRY_DATA);
275 struct pci_dev *dev = entry->dev;
276 int pos = entry->msi_attrib.pos;
279 pci_read_config_word(dev, msi_control_reg(pos), &msgctl);
280 msgctl &= ~PCI_MSI_FLAGS_QSIZE;
281 msgctl |= entry->msi_attrib.multiple << 4;
282 pci_write_config_word(dev, msi_control_reg(pos), msgctl);
284 pci_write_config_dword(dev, msi_lower_address_reg(pos),
286 if (entry->msi_attrib.is_64) {
287 pci_write_config_dword(dev, msi_upper_address_reg(pos),
289 pci_write_config_word(dev, msi_data_reg(pos, 1),
292 pci_write_config_word(dev, msi_data_reg(pos, 0),
299 void write_msi_msg(unsigned int irq, struct msi_msg *msg)
301 struct msi_desc *entry = irq_get_msi_desc(irq);
303 __write_msi_msg(entry, msg);
306 static void free_msi_irqs(struct pci_dev *dev)
308 struct msi_desc *entry, *tmp;
310 list_for_each_entry(entry, &dev->msi_list, list) {
314 nvec = 1 << entry->msi_attrib.multiple;
315 for (i = 0; i < nvec; i++)
316 BUG_ON(irq_has_action(entry->irq + i));
319 arch_teardown_msi_irqs(dev);
321 list_for_each_entry_safe(entry, tmp, &dev->msi_list, list) {
322 if (entry->msi_attrib.is_msix) {
323 if (list_is_last(&entry->list, &dev->msi_list))
324 iounmap(entry->mask_base);
326 kobject_del(&entry->kobj);
327 kobject_put(&entry->kobj);
328 list_del(&entry->list);
333 static struct msi_desc *alloc_msi_entry(struct pci_dev *dev)
335 struct msi_desc *desc = kzalloc(sizeof(*desc), GFP_KERNEL);
339 INIT_LIST_HEAD(&desc->list);
345 static void pci_intx_for_msi(struct pci_dev *dev, int enable)
347 if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG))
348 pci_intx(dev, enable);
351 static void __pci_restore_msi_state(struct pci_dev *dev)
355 struct msi_desc *entry;
357 if (!dev->msi_enabled)
360 entry = irq_get_msi_desc(dev->irq);
361 pos = entry->msi_attrib.pos;
363 pci_intx_for_msi(dev, 0);
364 msi_set_enable(dev, pos, 0);
365 write_msi_msg(dev->irq, &entry->msg);
367 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
368 msi_mask_irq(entry, msi_capable_mask(control), entry->masked);
369 control &= ~PCI_MSI_FLAGS_QSIZE;
370 control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE;
371 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
374 static void __pci_restore_msix_state(struct pci_dev *dev)
377 struct msi_desc *entry;
380 if (!dev->msix_enabled)
382 BUG_ON(list_empty(&dev->msi_list));
383 entry = list_first_entry(&dev->msi_list, struct msi_desc, list);
384 pos = entry->msi_attrib.pos;
385 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
387 /* route the table */
388 pci_intx_for_msi(dev, 0);
389 control |= PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL;
390 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
392 list_for_each_entry(entry, &dev->msi_list, list) {
393 write_msi_msg(entry->irq, &entry->msg);
394 msix_mask_irq(entry, entry->masked);
397 control &= ~PCI_MSIX_FLAGS_MASKALL;
398 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
401 void pci_restore_msi_state(struct pci_dev *dev)
403 __pci_restore_msi_state(dev);
404 __pci_restore_msix_state(dev);
406 EXPORT_SYMBOL_GPL(pci_restore_msi_state);
409 #define to_msi_attr(obj) container_of(obj, struct msi_attribute, attr)
410 #define to_msi_desc(obj) container_of(obj, struct msi_desc, kobj)
412 struct msi_attribute {
413 struct attribute attr;
414 ssize_t (*show)(struct msi_desc *entry, struct msi_attribute *attr,
416 ssize_t (*store)(struct msi_desc *entry, struct msi_attribute *attr,
417 const char *buf, size_t count);
420 static ssize_t show_msi_mode(struct msi_desc *entry, struct msi_attribute *atr,
423 return sprintf(buf, "%s\n", entry->msi_attrib.is_msix ? "msix" : "msi");
426 static ssize_t msi_irq_attr_show(struct kobject *kobj,
427 struct attribute *attr, char *buf)
429 struct msi_attribute *attribute = to_msi_attr(attr);
430 struct msi_desc *entry = to_msi_desc(kobj);
432 if (!attribute->show)
435 return attribute->show(entry, attribute, buf);
438 static const struct sysfs_ops msi_irq_sysfs_ops = {
439 .show = msi_irq_attr_show,
442 static struct msi_attribute mode_attribute =
443 __ATTR(mode, S_IRUGO, show_msi_mode, NULL);
446 struct attribute *msi_irq_default_attrs[] = {
447 &mode_attribute.attr,
451 void msi_kobj_release(struct kobject *kobj)
453 struct msi_desc *entry = to_msi_desc(kobj);
455 pci_dev_put(entry->dev);
458 static struct kobj_type msi_irq_ktype = {
459 .release = msi_kobj_release,
460 .sysfs_ops = &msi_irq_sysfs_ops,
461 .default_attrs = msi_irq_default_attrs,
464 static int populate_msi_sysfs(struct pci_dev *pdev)
466 struct msi_desc *entry;
467 struct kobject *kobj;
471 pdev->msi_kset = kset_create_and_add("msi_irqs", NULL, &pdev->dev.kobj);
475 list_for_each_entry(entry, &pdev->msi_list, list) {
477 kobj->kset = pdev->msi_kset;
479 ret = kobject_init_and_add(kobj, &msi_irq_ktype, NULL,
490 list_for_each_entry(entry, &pdev->msi_list, list) {
493 kobject_del(&entry->kobj);
494 kobject_put(&entry->kobj);
501 * msi_capability_init - configure device's MSI capability structure
502 * @dev: pointer to the pci_dev data structure of MSI device function
503 * @nvec: number of interrupts to allocate
505 * Setup the MSI capability structure of the device with the requested
506 * number of interrupts. A return value of zero indicates the successful
507 * setup of an entry with the new MSI irq. A negative return value indicates
508 * an error, and a positive return value indicates the number of interrupts
509 * which could have been allocated.
511 static int msi_capability_init(struct pci_dev *dev, int nvec)
513 struct msi_desc *entry;
518 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
519 msi_set_enable(dev, pos, 0); /* Disable MSI during set up */
521 pci_read_config_word(dev, msi_control_reg(pos), &control);
522 /* MSI Entry Initialization */
523 entry = alloc_msi_entry(dev);
527 entry->msi_attrib.is_msix = 0;
528 entry->msi_attrib.is_64 = is_64bit_address(control);
529 entry->msi_attrib.entry_nr = 0;
530 entry->msi_attrib.maskbit = is_mask_bit_support(control);
531 entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */
532 entry->msi_attrib.pos = pos;
534 entry->mask_pos = msi_mask_reg(pos, entry->msi_attrib.is_64);
535 /* All MSIs are unmasked by default, Mask them all */
536 if (entry->msi_attrib.maskbit)
537 pci_read_config_dword(dev, entry->mask_pos, &entry->masked);
538 mask = msi_capable_mask(control);
539 msi_mask_irq(entry, mask, mask);
541 list_add_tail(&entry->list, &dev->msi_list);
543 /* Configure MSI capability structure */
544 ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI);
546 msi_mask_irq(entry, mask, ~mask);
551 ret = populate_msi_sysfs(dev);
553 msi_mask_irq(entry, mask, ~mask);
558 /* Set MSI enabled bits */
559 pci_intx_for_msi(dev, 0);
560 msi_set_enable(dev, pos, 1);
561 dev->msi_enabled = 1;
563 dev->irq = entry->irq;
567 static void __iomem *msix_map_region(struct pci_dev *dev, unsigned pos,
570 resource_size_t phys_addr;
574 pci_read_config_dword(dev, msix_table_offset_reg(pos), &table_offset);
575 bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK);
576 table_offset &= ~PCI_MSIX_FLAGS_BIRMASK;
577 phys_addr = pci_resource_start(dev, bir) + table_offset;
579 return ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE);
582 static int msix_setup_entries(struct pci_dev *dev, unsigned pos,
583 void __iomem *base, struct msix_entry *entries,
586 struct msi_desc *entry;
589 for (i = 0; i < nvec; i++) {
590 entry = alloc_msi_entry(dev);
596 /* No enough memory. Don't try again */
600 entry->msi_attrib.is_msix = 1;
601 entry->msi_attrib.is_64 = 1;
602 entry->msi_attrib.entry_nr = entries[i].entry;
603 entry->msi_attrib.default_irq = dev->irq;
604 entry->msi_attrib.pos = pos;
605 entry->mask_base = base;
607 list_add_tail(&entry->list, &dev->msi_list);
613 static void msix_program_entries(struct pci_dev *dev,
614 struct msix_entry *entries)
616 struct msi_desc *entry;
619 list_for_each_entry(entry, &dev->msi_list, list) {
620 int offset = entries[i].entry * PCI_MSIX_ENTRY_SIZE +
621 PCI_MSIX_ENTRY_VECTOR_CTRL;
623 entries[i].vector = entry->irq;
624 irq_set_msi_desc(entry->irq, entry);
625 entry->masked = readl(entry->mask_base + offset);
626 msix_mask_irq(entry, 1);
632 * msix_capability_init - configure device's MSI-X capability
633 * @dev: pointer to the pci_dev data structure of MSI-X device function
634 * @entries: pointer to an array of struct msix_entry entries
635 * @nvec: number of @entries
637 * Setup the MSI-X capability structure of device function with a
638 * single MSI-X irq. A return of zero indicates the successful setup of
639 * requested MSI-X entries with allocated irqs or non-zero for otherwise.
641 static int msix_capability_init(struct pci_dev *dev,
642 struct msix_entry *entries, int nvec)
648 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
649 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
651 /* Ensure MSI-X is disabled while it is set up */
652 control &= ~PCI_MSIX_FLAGS_ENABLE;
653 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
655 /* Request & Map MSI-X table region */
656 base = msix_map_region(dev, pos, multi_msix_capable(control));
660 ret = msix_setup_entries(dev, pos, base, entries, nvec);
664 ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX);
669 * Some devices require MSI-X to be enabled before we can touch the
670 * MSI-X registers. We need to mask all the vectors to prevent
671 * interrupts coming in before they're fully set up.
673 control |= PCI_MSIX_FLAGS_MASKALL | PCI_MSIX_FLAGS_ENABLE;
674 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
676 msix_program_entries(dev, entries);
678 ret = populate_msi_sysfs(dev);
684 /* Set MSI-X enabled bits and unmask the function */
685 pci_intx_for_msi(dev, 0);
686 dev->msix_enabled = 1;
688 control &= ~PCI_MSIX_FLAGS_MASKALL;
689 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
696 * If we had some success, report the number of irqs
697 * we succeeded in setting up.
699 struct msi_desc *entry;
702 list_for_each_entry(entry, &dev->msi_list, list) {
716 * pci_msi_check_device - check whether MSI may be enabled on a device
717 * @dev: pointer to the pci_dev data structure of MSI device function
718 * @nvec: how many MSIs have been requested ?
719 * @type: are we checking for MSI or MSI-X ?
721 * Look at global flags, the device itself, and its parent busses
722 * to determine if MSI/-X are supported for the device. If MSI/-X is
723 * supported return 0, else return an error code.
725 static int pci_msi_check_device(struct pci_dev *dev, int nvec, int type)
730 /* MSI must be globally enabled and supported by the device */
731 if (!pci_msi_enable || !dev || dev->no_msi)
735 * You can't ask to have 0 or less MSIs configured.
737 * b) the list manipulation code assumes nvec >= 1.
743 * Any bridge which does NOT route MSI transactions from its
744 * secondary bus to its primary bus must set NO_MSI flag on
745 * the secondary pci_bus.
746 * We expect only arch-specific PCI host bus controller driver
747 * or quirks for specific PCI bridges to be setting NO_MSI.
749 for (bus = dev->bus; bus; bus = bus->parent)
750 if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI)
753 ret = arch_msi_check_device(dev, nvec, type);
757 if (!pci_find_capability(dev, type))
764 * pci_enable_msi_block - configure device's MSI capability structure
765 * @dev: device to configure
766 * @nvec: number of interrupts to configure
768 * Allocate IRQs for a device with the MSI capability.
769 * This function returns a negative errno if an error occurs. If it
770 * is unable to allocate the number of interrupts requested, it returns
771 * the number of interrupts it might be able to allocate. If it successfully
772 * allocates at least the number of interrupts requested, it returns 0 and
773 * updates the @dev's irq member to the lowest new interrupt number; the
774 * other interrupt numbers allocated to this device are consecutive.
776 int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec)
778 int status, pos, maxvec;
781 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
784 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl);
785 maxvec = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1);
789 status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSI);
793 WARN_ON(!!dev->msi_enabled);
795 /* Check whether driver already requested MSI-X irqs */
796 if (dev->msix_enabled) {
797 dev_info(&dev->dev, "can't enable MSI "
798 "(MSI-X already enabled)\n");
802 status = msi_capability_init(dev, nvec);
805 EXPORT_SYMBOL(pci_enable_msi_block);
807 void pci_msi_shutdown(struct pci_dev *dev)
809 struct msi_desc *desc;
814 if (!pci_msi_enable || !dev || !dev->msi_enabled)
817 BUG_ON(list_empty(&dev->msi_list));
818 desc = list_first_entry(&dev->msi_list, struct msi_desc, list);
819 pos = desc->msi_attrib.pos;
821 msi_set_enable(dev, pos, 0);
822 pci_intx_for_msi(dev, 1);
823 dev->msi_enabled = 0;
825 /* Return the device with MSI unmasked as initial states */
826 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &ctrl);
827 mask = msi_capable_mask(ctrl);
828 /* Keep cached state to be restored */
829 __msi_mask_irq(desc, mask, ~mask);
831 /* Restore dev->irq to its default pin-assertion irq */
832 dev->irq = desc->msi_attrib.default_irq;
835 void pci_disable_msi(struct pci_dev *dev)
837 if (!pci_msi_enable || !dev || !dev->msi_enabled)
840 pci_msi_shutdown(dev);
842 kset_unregister(dev->msi_kset);
843 dev->msi_kset = NULL;
845 EXPORT_SYMBOL(pci_disable_msi);
848 * pci_msix_table_size - return the number of device's MSI-X table entries
849 * @dev: pointer to the pci_dev data structure of MSI-X device function
851 int pci_msix_table_size(struct pci_dev *dev)
856 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
860 pci_read_config_word(dev, msi_control_reg(pos), &control);
861 return multi_msix_capable(control);
865 * pci_enable_msix - configure device's MSI-X capability structure
866 * @dev: pointer to the pci_dev data structure of MSI-X device function
867 * @entries: pointer to an array of MSI-X entries
868 * @nvec: number of MSI-X irqs requested for allocation by device driver
870 * Setup the MSI-X capability structure of device function with the number
871 * of requested irqs upon its software driver call to request for
872 * MSI-X mode enabled on its hardware device function. A return of zero
873 * indicates the successful configuration of MSI-X capability structure
874 * with new allocated MSI-X irqs. A return of < 0 indicates a failure.
875 * Or a return of > 0 indicates that driver request is exceeding the number
876 * of irqs or MSI-X vectors available. Driver should use the returned value to
877 * re-send its request.
879 int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec)
881 int status, nr_entries;
887 status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSIX);
891 nr_entries = pci_msix_table_size(dev);
892 if (nvec > nr_entries)
895 /* Check for any invalid entries */
896 for (i = 0; i < nvec; i++) {
897 if (entries[i].entry >= nr_entries)
898 return -EINVAL; /* invalid entry */
899 for (j = i + 1; j < nvec; j++) {
900 if (entries[i].entry == entries[j].entry)
901 return -EINVAL; /* duplicate entry */
904 WARN_ON(!!dev->msix_enabled);
906 /* Check whether driver already requested for MSI irq */
907 if (dev->msi_enabled) {
908 dev_info(&dev->dev, "can't enable MSI-X "
909 "(MSI IRQ already assigned)\n");
912 status = msix_capability_init(dev, entries, nvec);
915 EXPORT_SYMBOL(pci_enable_msix);
917 void pci_msix_shutdown(struct pci_dev *dev)
919 struct msi_desc *entry;
921 if (!pci_msi_enable || !dev || !dev->msix_enabled)
924 /* Return the device with MSI-X masked as initial states */
925 list_for_each_entry(entry, &dev->msi_list, list) {
926 /* Keep cached states to be restored */
927 __msix_mask_irq(entry, 1);
930 msix_set_enable(dev, 0);
931 pci_intx_for_msi(dev, 1);
932 dev->msix_enabled = 0;
935 void pci_disable_msix(struct pci_dev *dev)
937 if (!pci_msi_enable || !dev || !dev->msix_enabled)
940 pci_msix_shutdown(dev);
942 kset_unregister(dev->msi_kset);
943 dev->msi_kset = NULL;
945 EXPORT_SYMBOL(pci_disable_msix);
948 * msi_remove_pci_irq_vectors - reclaim MSI(X) irqs to unused state
949 * @dev: pointer to the pci_dev data structure of MSI(X) device function
951 * Being called during hotplug remove, from which the device function
952 * is hot-removed. All previous assigned MSI/MSI-X irqs, if
953 * allocated for this device function, are reclaimed to unused state,
954 * which may be used later on.
956 void msi_remove_pci_irq_vectors(struct pci_dev *dev)
958 if (!pci_msi_enable || !dev)
961 if (dev->msi_enabled || dev->msix_enabled)
965 void pci_no_msi(void)
971 * pci_msi_enabled - is MSI enabled?
973 * Returns true if MSI has not been disabled by the command-line option
976 int pci_msi_enabled(void)
978 return pci_msi_enable;
980 EXPORT_SYMBOL(pci_msi_enabled);
982 void pci_msi_init_pci_dev(struct pci_dev *dev)
985 INIT_LIST_HEAD(&dev->msi_list);
987 /* Disable the msi hardware to avoid screaming interrupts
988 * during boot. This is the power on reset default so
989 * usually this should be a noop.
991 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
993 msi_set_enable(dev, pos, 0);
994 msix_set_enable(dev, 0);