2 * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
3 * Andreas Heppel <aheppel@sysgo.de>
5 * (C) Copyright 2002, 2003
6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 * SPDX-License-Identifier: GPL-2.0+
19 #include <asm/processor.h>
23 DECLARE_GLOBAL_DATA_PTR;
25 #define PCI_HOSE_OP(rw, size, type) \
26 int pci_hose_##rw##_config_##size(struct pci_controller *hose, \
28 int offset, type value) \
30 return hose->rw##_##size(hose, dev, offset, value); \
33 PCI_HOSE_OP(read, byte, u8 *)
34 PCI_HOSE_OP(read, word, u16 *)
35 PCI_HOSE_OP(read, dword, u32 *)
36 PCI_HOSE_OP(write, byte, u8)
37 PCI_HOSE_OP(write, word, u16)
38 PCI_HOSE_OP(write, dword, u32)
40 #define PCI_OP(rw, size, type, error_code) \
41 int pci_##rw##_config_##size(pci_dev_t dev, int offset, type value) \
43 struct pci_controller *hose = pci_bus_to_hose(PCI_BUS(dev)); \
51 return pci_hose_##rw##_config_##size(hose, dev, offset, value); \
54 PCI_OP(read, byte, u8 *, *value = 0xff)
55 PCI_OP(read, word, u16 *, *value = 0xffff)
56 PCI_OP(read, dword, u32 *, *value = 0xffffffff)
57 PCI_OP(write, byte, u8, )
58 PCI_OP(write, word, u16, )
59 PCI_OP(write, dword, u32, )
61 #define PCI_READ_VIA_DWORD_OP(size, type, off_mask) \
62 int pci_hose_read_config_##size##_via_dword(struct pci_controller *hose,\
64 int offset, type val) \
68 if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0) { \
73 *val = (val32 >> ((offset & (int)off_mask) * 8)); \
78 #define PCI_WRITE_VIA_DWORD_OP(size, type, off_mask, val_mask) \
79 int pci_hose_write_config_##size##_via_dword(struct pci_controller *hose,\
81 int offset, type val) \
83 u32 val32, mask, ldata, shift; \
85 if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0)\
88 shift = ((offset & (int)off_mask) * 8); \
89 ldata = (((unsigned long)val) & val_mask) << shift; \
90 mask = val_mask << shift; \
91 val32 = (val32 & ~mask) | ldata; \
93 if (pci_hose_write_config_dword(hose, dev, offset & 0xfc, val32) < 0)\
99 PCI_READ_VIA_DWORD_OP(byte, u8 *, 0x03)
100 PCI_READ_VIA_DWORD_OP(word, u16 *, 0x02)
101 PCI_WRITE_VIA_DWORD_OP(byte, u8, 0x03, 0x000000ff)
102 PCI_WRITE_VIA_DWORD_OP(word, u16, 0x02, 0x0000ffff)
108 static struct pci_controller* hose_head;
110 struct pci_controller *pci_get_hose_head(void)
118 void pci_register_hose(struct pci_controller* hose)
120 struct pci_controller **phose = &hose_head;
123 phose = &(*phose)->next;
130 struct pci_controller *pci_bus_to_hose(int bus)
132 struct pci_controller *hose;
134 for (hose = pci_get_hose_head(); hose; hose = hose->next) {
135 if (bus >= hose->first_busno && bus <= hose->last_busno)
139 printf("pci_bus_to_hose() failed\n");
143 struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr)
145 struct pci_controller *hose;
147 for (hose = pci_get_hose_head(); hose; hose = hose->next) {
148 if (hose->cfg_addr == cfg_addr)
155 int pci_last_busno(void)
157 struct pci_controller *hose = pci_get_hose_head();
165 return hose->last_busno;
168 pci_dev_t pci_find_devices(struct pci_device_id *ids, int index)
170 struct pci_controller * hose;
174 for (hose = pci_get_hose_head(); hose; hose = hose->next) {
175 #ifdef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE
176 for (bus = hose->last_busno; bus >= hose->first_busno; bus--) {
178 for (bus = hose->first_busno; bus <= hose->last_busno; bus++) {
180 bdf = pci_hose_find_devices(hose, bus, ids, &index);
193 int __pci_hose_phys_to_bus(struct pci_controller *hose,
194 phys_addr_t phys_addr,
196 unsigned long skip_mask,
199 struct pci_region *res;
203 for (i = 0; i < hose->region_count; i++) {
204 res = &hose->regions[i];
206 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
209 if (res->flags & skip_mask)
212 bus_addr = phys_addr - res->phys_start + res->bus_start;
214 if (bus_addr >= res->bus_start &&
215 bus_addr < res->bus_start + res->size) {
224 pci_addr_t pci_hose_phys_to_bus (struct pci_controller *hose,
225 phys_addr_t phys_addr,
228 pci_addr_t bus_addr = 0;
232 puts("pci_hose_phys_to_bus: invalid hose\n");
237 * if PCI_REGION_MEM is set we do a two pass search with preference
238 * on matches that don't have PCI_REGION_SYS_MEMORY set
240 if ((flags & PCI_REGION_MEM) == PCI_REGION_MEM) {
241 ret = __pci_hose_phys_to_bus(hose, phys_addr,
242 flags, PCI_REGION_SYS_MEMORY, &bus_addr);
247 ret = __pci_hose_phys_to_bus(hose, phys_addr, flags, 0, &bus_addr);
250 puts("pci_hose_phys_to_bus: invalid physical address\n");
255 int pci_hose_config_device(struct pci_controller *hose,
259 unsigned long command)
262 unsigned int old_command;
263 pci_addr_t bar_value;
266 int bar, found_mem64;
268 debug("PCI Config: I/O=0x%lx, Memory=0x%llx, Command=0x%lx\n", io,
271 pci_hose_write_config_dword(hose, dev, PCI_COMMAND, 0);
273 for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_5; bar += 4) {
274 pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
275 pci_hose_read_config_dword(hose, dev, bar, &bar_response);
282 /* Check the BAR type and set our address mask */
283 if (bar_response & PCI_BASE_ADDRESS_SPACE) {
284 bar_size = ~(bar_response & PCI_BASE_ADDRESS_IO_MASK) + 1;
285 /* round up region base address to a multiple of size */
286 io = ((io - 1) | (bar_size - 1)) + 1;
288 /* compute new region base address */
291 if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
292 PCI_BASE_ADDRESS_MEM_TYPE_64) {
293 u32 bar_response_upper;
295 pci_hose_write_config_dword(hose, dev, bar + 4,
297 pci_hose_read_config_dword(hose, dev, bar + 4,
298 &bar_response_upper);
300 bar64 = ((u64)bar_response_upper << 32) | bar_response;
302 bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1;
305 bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1);
308 /* round up region base address to multiple of size */
309 mem = ((mem - 1) | (bar_size - 1)) + 1;
311 /* compute new region base address */
312 mem = mem + bar_size;
315 /* Write it out and update our limit */
316 pci_hose_write_config_dword (hose, dev, bar, (u32)bar_value);
320 #ifdef CONFIG_SYS_PCI_64BIT
321 pci_hose_write_config_dword(hose, dev, bar,
322 (u32)(bar_value >> 32));
324 pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
329 /* Configure Cache Line Size Register */
330 pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
332 /* Configure Latency Timer */
333 pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
335 /* Disable interrupt line, if device says it wants to use interrupts */
336 pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &pin);
338 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 0xff);
341 pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &old_command);
342 pci_hose_write_config_dword(hose, dev, PCI_COMMAND,
343 (old_command & 0xffff0000) | command);
352 struct pci_config_table *pci_find_config(struct pci_controller *hose,
353 unsigned short class,
360 struct pci_config_table *table;
362 for (table = hose->config_table; table && table->vendor; table++) {
363 if ((table->vendor == PCI_ANY_ID || table->vendor == vendor) &&
364 (table->device == PCI_ANY_ID || table->device == device) &&
365 (table->class == PCI_ANY_ID || table->class == class) &&
366 (table->bus == PCI_ANY_ID || table->bus == bus) &&
367 (table->dev == PCI_ANY_ID || table->dev == dev) &&
368 (table->func == PCI_ANY_ID || table->func == func)) {
376 void pci_cfgfunc_config_device(struct pci_controller *hose,
378 struct pci_config_table *entry)
380 pci_hose_config_device(hose, dev, entry->priv[0], entry->priv[1],
384 void pci_cfgfunc_do_nothing(struct pci_controller *hose,
385 pci_dev_t dev, struct pci_config_table *entry)
390 * HJF: Changed this to return int. I think this is required
391 * to get the correct result when scanning bridges
393 extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
395 #ifdef CONFIG_PCI_SCAN_SHOW
396 __weak int pci_print_dev(struct pci_controller *hose, pci_dev_t dev)
398 if (dev == PCI_BDF(hose->first_busno, 0, 0))
403 #endif /* CONFIG_PCI_SCAN_SHOW */
405 int pci_hose_scan_bus(struct pci_controller *hose, int bus)
407 unsigned int sub_bus, found_multi = 0;
408 unsigned short vendor, device, class;
409 unsigned char header_type;
410 #ifndef CONFIG_PCI_PNP
411 struct pci_config_table *cfg;
414 #ifdef CONFIG_PCI_SCAN_SHOW
415 static int indent = 0;
420 for (dev = PCI_BDF(bus,0,0);
421 dev < PCI_BDF(bus, PCI_MAX_PCI_DEVICES - 1,
422 PCI_MAX_PCI_FUNCTIONS - 1);
423 dev += PCI_BDF(0, 0, 1)) {
425 if (pci_skip_dev(hose, dev))
428 if (PCI_FUNC(dev) && !found_multi)
431 pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type);
433 pci_hose_read_config_word(hose, dev, PCI_VENDOR_ID, &vendor);
435 if (vendor == 0xffff || vendor == 0x0000)
439 found_multi = header_type & 0x80;
441 debug("PCI Scan: Found Bus %d, Device %d, Function %d\n",
442 PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
444 pci_hose_read_config_word(hose, dev, PCI_DEVICE_ID, &device);
445 pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
447 #ifdef CONFIG_PCI_FIXUP_DEV
448 board_pci_fixup_dev(hose, dev, vendor, device, class);
451 #ifdef CONFIG_PCI_SCAN_SHOW
454 /* Print leading space, including bus indentation */
455 printf("%*c", indent + 1, ' ');
457 if (pci_print_dev(hose, dev)) {
458 printf("%02x:%02x.%-*x - %04x:%04x - %s\n",
459 PCI_BUS(dev), PCI_DEV(dev), 6 - indent, PCI_FUNC(dev),
460 vendor, device, pci_class_str(class >> 8));
464 #ifdef CONFIG_PCI_PNP
465 sub_bus = max((unsigned int)pciauto_config_device(hose, dev),
468 cfg = pci_find_config(hose, class, vendor, device,
469 PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
471 cfg->config_device(hose, dev, cfg);
472 sub_bus = max(sub_bus,
473 (unsigned int)hose->current_busno);
477 #ifdef CONFIG_PCI_SCAN_SHOW
482 hose->fixup_irq(hose, dev);
488 int pci_hose_scan(struct pci_controller *hose)
490 #if defined(CONFIG_PCI_BOOTDELAY)
494 if (!gd->pcidelay_done) {
495 /* wait "pcidelay" ms (if defined)... */
496 s = getenv("pcidelay");
498 int val = simple_strtoul(s, NULL, 10);
499 for (i = 0; i < val; i++)
502 gd->pcidelay_done = 1;
504 #endif /* CONFIG_PCI_BOOTDELAY */
507 * Start scan at current_busno.
508 * PCIe will start scan at first_busno+1.
510 /* For legacy support, ensure current >= first */
511 if (hose->first_busno > hose->current_busno)
512 hose->current_busno = hose->first_busno;
513 #ifdef CONFIG_PCI_PNP
514 pciauto_config_init(hose);
516 return pci_hose_scan_bus(hose, hose->current_busno);
523 /* now call board specific pci_init()... */
527 /* Returns the address of the requested capability structure within the
528 * device's PCI configuration space or 0 in case the device does not
531 int pci_hose_find_capability(struct pci_controller *hose, pci_dev_t dev,
537 pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &hdr_type);
539 pos = pci_hose_find_cap_start(hose, dev, hdr_type & 0x7F);
542 pos = pci_find_cap(hose, dev, pos, cap);
547 /* Find the header pointer to the Capabilities*/
548 int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev,
553 pci_hose_read_config_word(hose, dev, PCI_STATUS, &status);
555 if (!(status & PCI_STATUS_CAP_LIST))
559 case PCI_HEADER_TYPE_NORMAL:
560 case PCI_HEADER_TYPE_BRIDGE:
561 return PCI_CAPABILITY_LIST;
562 case PCI_HEADER_TYPE_CARDBUS:
563 return PCI_CB_CAPABILITY_LIST;
569 int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos, int cap)
571 int ttl = PCI_FIND_CAP_TTL;
576 pci_hose_read_config_byte(hose, dev, pos, &next_pos);
577 if (next_pos < CAP_START_POS)
580 pos = (int) next_pos;
581 pci_hose_read_config_byte(hose, dev,
582 pos + PCI_CAP_LIST_ID, &id);
587 pos += PCI_CAP_LIST_NEXT;