2 * PCI Bus Services, see include/linux/pci.h for further explanation.
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
10 #include <linux/kernel.h>
11 #include <linux/delay.h>
12 #include <linux/init.h>
13 #include <linux/pci.h>
15 #include <linux/slab.h>
16 #include <linux/module.h>
17 #include <linux/spinlock.h>
18 #include <linux/string.h>
19 #include <linux/log2.h>
20 #include <linux/pci-aspm.h>
21 #include <linux/pm_wakeup.h>
22 #include <linux/interrupt.h>
23 #include <linux/device.h>
24 #include <linux/pm_runtime.h>
25 #include <linux/pci_hotplug.h>
26 #include <asm-generic/pci-bridge.h>
27 #include <asm/setup.h>
30 const char *pci_power_names[] = {
31 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
33 EXPORT_SYMBOL_GPL(pci_power_names);
35 int isa_dma_bridge_buggy;
36 EXPORT_SYMBOL(isa_dma_bridge_buggy);
39 EXPORT_SYMBOL(pci_pci_problems);
41 unsigned int pci_pm_d3_delay;
43 static void pci_pme_list_scan(struct work_struct *work);
45 static LIST_HEAD(pci_pme_list);
46 static DEFINE_MUTEX(pci_pme_list_mutex);
47 static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan);
49 struct pci_pme_device {
50 struct list_head list;
54 #define PME_TIMEOUT 1000 /* How long between PME checks */
56 static void pci_dev_d3_sleep(struct pci_dev *dev)
58 unsigned int delay = dev->d3_delay;
60 if (delay < pci_pm_d3_delay)
61 delay = pci_pm_d3_delay;
66 #ifdef CONFIG_PCI_DOMAINS
67 int pci_domains_supported = 1;
70 #define DEFAULT_CARDBUS_IO_SIZE (256)
71 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
72 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
73 unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
74 unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
76 #define DEFAULT_HOTPLUG_IO_SIZE (256)
77 #define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024)
78 /* pci=hpmemsize=nnM,hpiosize=nn can override this */
79 unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE;
80 unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE;
82 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_TUNE_OFF;
85 * The default CLS is used if arch didn't set CLS explicitly and not
86 * all pci devices agree on the same value. Arch can override either
87 * the dfl or actual value as it sees fit. Don't forget this is
88 * measured in 32-bit words, not bytes.
90 u8 pci_dfl_cache_line_size = L1_CACHE_BYTES >> 2;
91 u8 pci_cache_line_size;
94 * If we set up a device for bus mastering, we need to check the latency
95 * timer as certain BIOSes forget to set it properly.
97 unsigned int pcibios_max_latency = 255;
99 /* If set, the PCIe ARI capability will not be used. */
100 static bool pcie_ari_disabled;
103 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
104 * @bus: pointer to PCI bus structure to search
106 * Given a PCI bus, returns the highest PCI bus number present in the set
107 * including the given PCI bus and its list of child PCI buses.
109 unsigned char pci_bus_max_busnr(struct pci_bus* bus)
112 unsigned char max, n;
114 max = bus->busn_res.end;
115 list_for_each_entry(tmp, &bus->children, node) {
116 n = pci_bus_max_busnr(tmp);
122 EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
124 #ifdef CONFIG_HAS_IOMEM
125 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
128 * Make sure the BAR is actually a memory resource, not an IO resource
130 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
134 return ioremap_nocache(pci_resource_start(pdev, bar),
135 pci_resource_len(pdev, bar));
137 EXPORT_SYMBOL_GPL(pci_ioremap_bar);
140 #define PCI_FIND_CAP_TTL 48
142 static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
143 u8 pos, int cap, int *ttl)
148 pci_bus_read_config_byte(bus, devfn, pos, &pos);
152 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID,
158 pos += PCI_CAP_LIST_NEXT;
163 static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
166 int ttl = PCI_FIND_CAP_TTL;
168 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
171 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
173 return __pci_find_next_cap(dev->bus, dev->devfn,
174 pos + PCI_CAP_LIST_NEXT, cap);
176 EXPORT_SYMBOL_GPL(pci_find_next_capability);
178 static int __pci_bus_find_cap_start(struct pci_bus *bus,
179 unsigned int devfn, u8 hdr_type)
183 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
184 if (!(status & PCI_STATUS_CAP_LIST))
188 case PCI_HEADER_TYPE_NORMAL:
189 case PCI_HEADER_TYPE_BRIDGE:
190 return PCI_CAPABILITY_LIST;
191 case PCI_HEADER_TYPE_CARDBUS:
192 return PCI_CB_CAPABILITY_LIST;
201 * pci_find_capability - query for devices' capabilities
202 * @dev: PCI device to query
203 * @cap: capability code
205 * Tell if a device supports a given PCI capability.
206 * Returns the address of the requested capability structure within the
207 * device's PCI configuration space or 0 in case the device does not
208 * support it. Possible values for @cap:
210 * %PCI_CAP_ID_PM Power Management
211 * %PCI_CAP_ID_AGP Accelerated Graphics Port
212 * %PCI_CAP_ID_VPD Vital Product Data
213 * %PCI_CAP_ID_SLOTID Slot Identification
214 * %PCI_CAP_ID_MSI Message Signalled Interrupts
215 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
216 * %PCI_CAP_ID_PCIX PCI-X
217 * %PCI_CAP_ID_EXP PCI Express
219 int pci_find_capability(struct pci_dev *dev, int cap)
223 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
225 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
231 * pci_bus_find_capability - query for devices' capabilities
232 * @bus: the PCI bus to query
233 * @devfn: PCI device to query
234 * @cap: capability code
236 * Like pci_find_capability() but works for pci devices that do not have a
237 * pci_dev structure set up yet.
239 * Returns the address of the requested capability structure within the
240 * device's PCI configuration space or 0 in case the device does not
243 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
248 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
250 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
252 pos = __pci_find_next_cap(bus, devfn, pos, cap);
258 * pci_find_next_ext_capability - Find an extended capability
259 * @dev: PCI device to query
260 * @start: address at which to start looking (0 to start at beginning of list)
261 * @cap: capability code
263 * Returns the address of the next matching extended capability structure
264 * within the device's PCI configuration space or 0 if the device does
265 * not support it. Some capabilities can occur several times, e.g., the
266 * vendor-specific capability, and this provides a way to find them all.
268 int pci_find_next_ext_capability(struct pci_dev *dev, int start, int cap)
272 int pos = PCI_CFG_SPACE_SIZE;
274 /* minimum 8 bytes per capability */
275 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
277 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
283 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
287 * If we have no capabilities, this is indicated by cap ID,
288 * cap version and next pointer all being 0.
294 if (PCI_EXT_CAP_ID(header) == cap && pos != start)
297 pos = PCI_EXT_CAP_NEXT(header);
298 if (pos < PCI_CFG_SPACE_SIZE)
301 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
307 EXPORT_SYMBOL_GPL(pci_find_next_ext_capability);
310 * pci_find_ext_capability - Find an extended capability
311 * @dev: PCI device to query
312 * @cap: capability code
314 * Returns the address of the requested extended capability structure
315 * within the device's PCI configuration space or 0 if the device does
316 * not support it. Possible values for @cap:
318 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
319 * %PCI_EXT_CAP_ID_VC Virtual Channel
320 * %PCI_EXT_CAP_ID_DSN Device Serial Number
321 * %PCI_EXT_CAP_ID_PWR Power Budgeting
323 int pci_find_ext_capability(struct pci_dev *dev, int cap)
325 return pci_find_next_ext_capability(dev, 0, cap);
327 EXPORT_SYMBOL_GPL(pci_find_ext_capability);
329 static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
331 int rc, ttl = PCI_FIND_CAP_TTL;
334 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
335 mask = HT_3BIT_CAP_MASK;
337 mask = HT_5BIT_CAP_MASK;
339 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
340 PCI_CAP_ID_HT, &ttl);
342 rc = pci_read_config_byte(dev, pos + 3, &cap);
343 if (rc != PCIBIOS_SUCCESSFUL)
346 if ((cap & mask) == ht_cap)
349 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
350 pos + PCI_CAP_LIST_NEXT,
351 PCI_CAP_ID_HT, &ttl);
357 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
358 * @dev: PCI device to query
359 * @pos: Position from which to continue searching
360 * @ht_cap: Hypertransport capability code
362 * To be used in conjunction with pci_find_ht_capability() to search for
363 * all capabilities matching @ht_cap. @pos should always be a value returned
364 * from pci_find_ht_capability().
366 * NB. To be 100% safe against broken PCI devices, the caller should take
367 * steps to avoid an infinite loop.
369 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
371 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
373 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
376 * pci_find_ht_capability - query a device's Hypertransport capabilities
377 * @dev: PCI device to query
378 * @ht_cap: Hypertransport capability code
380 * Tell if a device supports a given Hypertransport capability.
381 * Returns an address within the device's PCI configuration space
382 * or 0 in case the device does not support the request capability.
383 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
384 * which has a Hypertransport capability matching @ht_cap.
386 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
390 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
392 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
396 EXPORT_SYMBOL_GPL(pci_find_ht_capability);
399 * pci_find_parent_resource - return resource region of parent bus of given region
400 * @dev: PCI device structure contains resources to be searched
401 * @res: child resource record for which parent is sought
403 * For given resource region of given device, return the resource
404 * region of parent bus the given region is contained in.
407 pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
409 const struct pci_bus *bus = dev->bus;
413 pci_bus_for_each_resource(bus, r, i) {
416 if (res->start && resource_contains(r, res)) {
419 * If the window is prefetchable but the BAR is
420 * not, the allocator made a mistake.
422 if (r->flags & IORESOURCE_PREFETCH &&
423 !(res->flags & IORESOURCE_PREFETCH))
427 * If we're below a transparent bridge, there may
428 * be both a positively-decoded aperture and a
429 * subtractively-decoded region that contain the BAR.
430 * We want the positively-decoded one, so this depends
431 * on pci_bus_for_each_resource() giving us those
441 * pci_wait_for_pending - wait for @mask bit(s) to clear in status word @pos
442 * @dev: the PCI device to operate on
443 * @pos: config space offset of status word
444 * @mask: mask of bit(s) to care about in status word
446 * Return 1 when mask bit(s) in status word clear, 0 otherwise.
448 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask)
452 /* Wait for Transaction Pending bit clean */
453 for (i = 0; i < 4; i++) {
456 msleep((1 << (i - 1)) * 100);
458 pci_read_config_word(dev, pos, &status);
459 if (!(status & mask))
467 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
468 * @dev: PCI device to have its BARs restored
470 * Restore the BAR values for a given device, so as to make it
471 * accessible by its driver.
474 pci_restore_bars(struct pci_dev *dev)
478 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
479 pci_update_resource(dev, i);
482 static struct pci_platform_pm_ops *pci_platform_pm;
484 int pci_set_platform_pm(struct pci_platform_pm_ops *ops)
486 if (!ops->is_manageable || !ops->set_state || !ops->choose_state
489 pci_platform_pm = ops;
493 static inline bool platform_pci_power_manageable(struct pci_dev *dev)
495 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
498 static inline int platform_pci_set_power_state(struct pci_dev *dev,
501 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
504 static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
506 return pci_platform_pm ?
507 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
510 static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable)
512 return pci_platform_pm ?
513 pci_platform_pm->sleep_wake(dev, enable) : -ENODEV;
516 static inline int platform_pci_run_wake(struct pci_dev *dev, bool enable)
518 return pci_platform_pm ?
519 pci_platform_pm->run_wake(dev, enable) : -ENODEV;
523 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
525 * @dev: PCI device to handle.
526 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
529 * -EINVAL if the requested state is invalid.
530 * -EIO if device does not support PCI PM or its PM capabilities register has a
531 * wrong version, or device doesn't support the requested state.
532 * 0 if device already is in the requested state.
533 * 0 if device's power state has been successfully changed.
535 static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
538 bool need_restore = false;
540 /* Check if we're already there */
541 if (dev->current_state == state)
547 if (state < PCI_D0 || state > PCI_D3hot)
550 /* Validate current state:
551 * Can enter D0 from any state, but if we can only go deeper
552 * to sleep if we're already in a low power state
554 if (state != PCI_D0 && dev->current_state <= PCI_D3cold
555 && dev->current_state > state) {
556 dev_err(&dev->dev, "invalid power transition "
557 "(from state %d to %d)\n", dev->current_state, state);
561 /* check if this device supports the desired state */
562 if ((state == PCI_D1 && !dev->d1_support)
563 || (state == PCI_D2 && !dev->d2_support))
566 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
568 /* If we're (effectively) in D3, force entire word to 0.
569 * This doesn't affect PME_Status, disables PME_En, and
570 * sets PowerState to 0.
572 switch (dev->current_state) {
576 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
581 case PCI_UNKNOWN: /* Boot-up */
582 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
583 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
585 /* Fall-through: force to D0 */
591 /* enter specified state */
592 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
594 /* Mandatory power management transition delays */
595 /* see PCI PM 1.1 5.6.1 table 18 */
596 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
597 pci_dev_d3_sleep(dev);
598 else if (state == PCI_D2 || dev->current_state == PCI_D2)
599 udelay(PCI_PM_D2_DELAY);
601 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
602 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
603 if (dev->current_state != state && printk_ratelimit())
604 dev_info(&dev->dev, "Refused to change power state, "
605 "currently in D%d\n", dev->current_state);
608 * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
609 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
610 * from D3hot to D0 _may_ perform an internal reset, thereby
611 * going to "D0 Uninitialized" rather than "D0 Initialized".
612 * For example, at least some versions of the 3c905B and the
613 * 3c556B exhibit this behaviour.
615 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
616 * devices in a D3hot state at boot. Consequently, we need to
617 * restore at least the BARs so that the device will be
618 * accessible to its driver.
621 pci_restore_bars(dev);
624 pcie_aspm_pm_state_change(dev->bus->self);
630 * pci_update_current_state - Read PCI power state of given device from its
631 * PCI PM registers and cache it
632 * @dev: PCI device to handle.
633 * @state: State to cache in case the device doesn't have the PM capability
635 void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
641 * Configuration space is not accessible for device in
642 * D3cold, so just keep or set D3cold for safety
644 if (dev->current_state == PCI_D3cold)
646 if (state == PCI_D3cold) {
647 dev->current_state = PCI_D3cold;
650 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
651 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
653 dev->current_state = state;
658 * pci_power_up - Put the given device into D0 forcibly
659 * @dev: PCI device to power up
661 void pci_power_up(struct pci_dev *dev)
663 if (platform_pci_power_manageable(dev))
664 platform_pci_set_power_state(dev, PCI_D0);
666 pci_raw_set_power_state(dev, PCI_D0);
667 pci_update_current_state(dev, PCI_D0);
671 * pci_platform_power_transition - Use platform to change device power state
672 * @dev: PCI device to handle.
673 * @state: State to put the device into.
675 static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
679 if (platform_pci_power_manageable(dev)) {
680 error = platform_pci_set_power_state(dev, state);
682 pci_update_current_state(dev, state);
686 if (error && !dev->pm_cap) /* Fall back to PCI_D0 */
687 dev->current_state = PCI_D0;
693 * pci_wakeup - Wake up a PCI device
694 * @pci_dev: Device to handle.
695 * @ign: ignored parameter
697 static int pci_wakeup(struct pci_dev *pci_dev, void *ign)
699 pci_wakeup_event(pci_dev);
700 pm_request_resume(&pci_dev->dev);
705 * pci_wakeup_bus - Walk given bus and wake up devices on it
706 * @bus: Top bus of the subtree to walk.
708 static void pci_wakeup_bus(struct pci_bus *bus)
711 pci_walk_bus(bus, pci_wakeup, NULL);
715 * __pci_start_power_transition - Start power transition of a PCI device
716 * @dev: PCI device to handle.
717 * @state: State to put the device into.
719 static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state)
721 if (state == PCI_D0) {
722 pci_platform_power_transition(dev, PCI_D0);
724 * Mandatory power management transition delays, see
725 * PCI Express Base Specification Revision 2.0 Section
726 * 6.6.1: Conventional Reset. Do not delay for
727 * devices powered on/off by corresponding bridge,
728 * because have already delayed for the bridge.
730 if (dev->runtime_d3cold) {
731 msleep(dev->d3cold_delay);
733 * When powering on a bridge from D3cold, the
734 * whole hierarchy may be powered on into
735 * D0uninitialized state, resume them to give
736 * them a chance to suspend again
738 pci_wakeup_bus(dev->subordinate);
744 * __pci_dev_set_current_state - Set current state of a PCI device
745 * @dev: Device to handle
746 * @data: pointer to state to be set
748 static int __pci_dev_set_current_state(struct pci_dev *dev, void *data)
750 pci_power_t state = *(pci_power_t *)data;
752 dev->current_state = state;
757 * __pci_bus_set_current_state - Walk given bus and set current state of devices
758 * @bus: Top bus of the subtree to walk.
759 * @state: state to be set
761 static void __pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state)
764 pci_walk_bus(bus, __pci_dev_set_current_state, &state);
768 * __pci_complete_power_transition - Complete power transition of a PCI device
769 * @dev: PCI device to handle.
770 * @state: State to put the device into.
772 * This function should not be called directly by device drivers.
774 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state)
780 ret = pci_platform_power_transition(dev, state);
781 /* Power off the bridge may power off the whole hierarchy */
782 if (!ret && state == PCI_D3cold)
783 __pci_bus_set_current_state(dev->subordinate, PCI_D3cold);
786 EXPORT_SYMBOL_GPL(__pci_complete_power_transition);
789 * pci_set_power_state - Set the power state of a PCI device
790 * @dev: PCI device to handle.
791 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
793 * Transition a device to a new power state, using the platform firmware and/or
794 * the device's PCI PM registers.
797 * -EINVAL if the requested state is invalid.
798 * -EIO if device does not support PCI PM or its PM capabilities register has a
799 * wrong version, or device doesn't support the requested state.
800 * 0 if device already is in the requested state.
801 * 0 if device's power state has been successfully changed.
803 int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
807 /* bound the state we're entering */
808 if (state > PCI_D3cold)
810 else if (state < PCI_D0)
812 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
814 * If the device or the parent bridge do not support PCI PM,
815 * ignore the request if we're doing anything other than putting
816 * it into D0 (which would only happen on boot).
820 /* Check if we're already there */
821 if (dev->current_state == state)
824 __pci_start_power_transition(dev, state);
826 /* This device is quirked not to be put into D3, so
827 don't put it in D3 */
828 if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
832 * To put device in D3cold, we put device into D3hot in native
833 * way, then put device into D3cold with platform ops
835 error = pci_raw_set_power_state(dev, state > PCI_D3hot ?
838 if (!__pci_complete_power_transition(dev, state))
841 * When aspm_policy is "powersave" this call ensures
842 * that ASPM is configured.
844 if (!error && dev->bus->self)
845 pcie_aspm_powersave_config_link(dev->bus->self);
851 * pci_choose_state - Choose the power state of a PCI device
852 * @dev: PCI device to be suspended
853 * @state: target sleep state for the whole system. This is the value
854 * that is passed to suspend() function.
856 * Returns PCI power state suitable for given device and given system
860 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
867 ret = platform_pci_choose_state(dev);
868 if (ret != PCI_POWER_ERROR)
871 switch (state.event) {
874 case PM_EVENT_FREEZE:
875 case PM_EVENT_PRETHAW:
876 /* REVISIT both freeze and pre-thaw "should" use D0 */
877 case PM_EVENT_SUSPEND:
878 case PM_EVENT_HIBERNATE:
881 dev_info(&dev->dev, "unrecognized suspend event %d\n",
888 EXPORT_SYMBOL(pci_choose_state);
890 #define PCI_EXP_SAVE_REGS 7
893 static struct pci_cap_saved_state *_pci_find_saved_cap(struct pci_dev *pci_dev,
894 u16 cap, bool extended)
896 struct pci_cap_saved_state *tmp;
898 hlist_for_each_entry(tmp, &pci_dev->saved_cap_space, next) {
899 if (tmp->cap.cap_extended == extended && tmp->cap.cap_nr == cap)
905 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap)
907 return _pci_find_saved_cap(dev, cap, false);
910 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, u16 cap)
912 return _pci_find_saved_cap(dev, cap, true);
915 static int pci_save_pcie_state(struct pci_dev *dev)
918 struct pci_cap_saved_state *save_state;
921 if (!pci_is_pcie(dev))
924 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
926 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
930 cap = (u16 *)&save_state->cap.data[0];
931 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &cap[i++]);
932 pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &cap[i++]);
933 pcie_capability_read_word(dev, PCI_EXP_SLTCTL, &cap[i++]);
934 pcie_capability_read_word(dev, PCI_EXP_RTCTL, &cap[i++]);
935 pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &cap[i++]);
936 pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]);
937 pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]);
942 static void pci_restore_pcie_state(struct pci_dev *dev)
945 struct pci_cap_saved_state *save_state;
948 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
952 cap = (u16 *)&save_state->cap.data[0];
953 pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]);
954 pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]);
955 pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]);
956 pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]);
957 pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]);
958 pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]);
959 pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]);
963 static int pci_save_pcix_state(struct pci_dev *dev)
966 struct pci_cap_saved_state *save_state;
968 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
972 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
974 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
978 pci_read_config_word(dev, pos + PCI_X_CMD,
979 (u16 *)save_state->cap.data);
984 static void pci_restore_pcix_state(struct pci_dev *dev)
987 struct pci_cap_saved_state *save_state;
990 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
991 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
992 if (!save_state || pos <= 0)
994 cap = (u16 *)&save_state->cap.data[0];
996 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
1001 * pci_save_state - save the PCI configuration space of a device before suspending
1002 * @dev: - PCI device that we're dealing with
1005 pci_save_state(struct pci_dev *dev)
1008 /* XXX: 100% dword access ok here? */
1009 for (i = 0; i < 16; i++)
1010 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
1011 dev->state_saved = true;
1012 if ((i = pci_save_pcie_state(dev)) != 0)
1014 if ((i = pci_save_pcix_state(dev)) != 0)
1016 if ((i = pci_save_vc_state(dev)) != 0)
1021 static void pci_restore_config_dword(struct pci_dev *pdev, int offset,
1022 u32 saved_val, int retry)
1026 pci_read_config_dword(pdev, offset, &val);
1027 if (val == saved_val)
1031 dev_dbg(&pdev->dev, "restoring config space at offset "
1032 "%#x (was %#x, writing %#x)\n", offset, val, saved_val);
1033 pci_write_config_dword(pdev, offset, saved_val);
1037 pci_read_config_dword(pdev, offset, &val);
1038 if (val == saved_val)
1045 static void pci_restore_config_space_range(struct pci_dev *pdev,
1046 int start, int end, int retry)
1050 for (index = end; index >= start; index--)
1051 pci_restore_config_dword(pdev, 4 * index,
1052 pdev->saved_config_space[index],
1056 static void pci_restore_config_space(struct pci_dev *pdev)
1058 if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) {
1059 pci_restore_config_space_range(pdev, 10, 15, 0);
1060 /* Restore BARs before the command register. */
1061 pci_restore_config_space_range(pdev, 4, 9, 10);
1062 pci_restore_config_space_range(pdev, 0, 3, 0);
1064 pci_restore_config_space_range(pdev, 0, 15, 0);
1069 * pci_restore_state - Restore the saved state of a PCI device
1070 * @dev: - PCI device that we're dealing with
1072 void pci_restore_state(struct pci_dev *dev)
1074 if (!dev->state_saved)
1077 /* PCI Express register must be restored first */
1078 pci_restore_pcie_state(dev);
1079 pci_restore_ats_state(dev);
1080 pci_restore_vc_state(dev);
1082 pci_restore_config_space(dev);
1084 pci_restore_pcix_state(dev);
1085 pci_restore_msi_state(dev);
1086 pci_restore_iov_state(dev);
1088 dev->state_saved = false;
1091 struct pci_saved_state {
1092 u32 config_space[16];
1093 struct pci_cap_saved_data cap[0];
1097 * pci_store_saved_state - Allocate and return an opaque struct containing
1098 * the device saved state.
1099 * @dev: PCI device that we're dealing with
1101 * Return NULL if no state or error.
1103 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev)
1105 struct pci_saved_state *state;
1106 struct pci_cap_saved_state *tmp;
1107 struct pci_cap_saved_data *cap;
1110 if (!dev->state_saved)
1113 size = sizeof(*state) + sizeof(struct pci_cap_saved_data);
1115 hlist_for_each_entry(tmp, &dev->saved_cap_space, next)
1116 size += sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1118 state = kzalloc(size, GFP_KERNEL);
1122 memcpy(state->config_space, dev->saved_config_space,
1123 sizeof(state->config_space));
1126 hlist_for_each_entry(tmp, &dev->saved_cap_space, next) {
1127 size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1128 memcpy(cap, &tmp->cap, len);
1129 cap = (struct pci_cap_saved_data *)((u8 *)cap + len);
1131 /* Empty cap_save terminates list */
1135 EXPORT_SYMBOL_GPL(pci_store_saved_state);
1138 * pci_load_saved_state - Reload the provided save state into struct pci_dev.
1139 * @dev: PCI device that we're dealing with
1140 * @state: Saved state returned from pci_store_saved_state()
1142 static int pci_load_saved_state(struct pci_dev *dev,
1143 struct pci_saved_state *state)
1145 struct pci_cap_saved_data *cap;
1147 dev->state_saved = false;
1152 memcpy(dev->saved_config_space, state->config_space,
1153 sizeof(state->config_space));
1157 struct pci_cap_saved_state *tmp;
1159 tmp = _pci_find_saved_cap(dev, cap->cap_nr, cap->cap_extended);
1160 if (!tmp || tmp->cap.size != cap->size)
1163 memcpy(tmp->cap.data, cap->data, tmp->cap.size);
1164 cap = (struct pci_cap_saved_data *)((u8 *)cap +
1165 sizeof(struct pci_cap_saved_data) + cap->size);
1168 dev->state_saved = true;
1173 * pci_load_and_free_saved_state - Reload the save state pointed to by state,
1174 * and free the memory allocated for it.
1175 * @dev: PCI device that we're dealing with
1176 * @state: Pointer to saved state returned from pci_store_saved_state()
1178 int pci_load_and_free_saved_state(struct pci_dev *dev,
1179 struct pci_saved_state **state)
1181 int ret = pci_load_saved_state(dev, *state);
1186 EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state);
1188 int __weak pcibios_enable_device(struct pci_dev *dev, int bars)
1190 return pci_enable_resources(dev, bars);
1193 static int do_pci_enable_device(struct pci_dev *dev, int bars)
1199 err = pci_set_power_state(dev, PCI_D0);
1200 if (err < 0 && err != -EIO)
1202 err = pcibios_enable_device(dev, bars);
1205 pci_fixup_device(pci_fixup_enable, dev);
1207 if (dev->msi_enabled || dev->msix_enabled)
1210 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
1212 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1213 if (cmd & PCI_COMMAND_INTX_DISABLE)
1214 pci_write_config_word(dev, PCI_COMMAND,
1215 cmd & ~PCI_COMMAND_INTX_DISABLE);
1222 * pci_reenable_device - Resume abandoned device
1223 * @dev: PCI device to be resumed
1225 * Note this function is a backend of pci_default_resume and is not supposed
1226 * to be called by normal code, write proper resume handler and use it instead.
1228 int pci_reenable_device(struct pci_dev *dev)
1230 if (pci_is_enabled(dev))
1231 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
1235 static void pci_enable_bridge(struct pci_dev *dev)
1237 struct pci_dev *bridge;
1240 bridge = pci_upstream_bridge(dev);
1242 pci_enable_bridge(bridge);
1244 if (pci_is_enabled(dev)) {
1245 if (!dev->is_busmaster)
1246 pci_set_master(dev);
1250 retval = pci_enable_device(dev);
1252 dev_err(&dev->dev, "Error enabling bridge (%d), continuing\n",
1254 pci_set_master(dev);
1257 static int pci_enable_device_flags(struct pci_dev *dev, unsigned long flags)
1259 struct pci_dev *bridge;
1264 * Power state could be unknown at this point, either due to a fresh
1265 * boot or a device removal call. So get the current power state
1266 * so that things like MSI message writing will behave as expected
1267 * (e.g. if the device really is in D0 at enable time).
1271 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1272 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
1275 if (atomic_inc_return(&dev->enable_cnt) > 1)
1276 return 0; /* already enabled */
1278 bridge = pci_upstream_bridge(dev);
1280 pci_enable_bridge(bridge);
1282 /* only skip sriov related */
1283 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
1284 if (dev->resource[i].flags & flags)
1286 for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++)
1287 if (dev->resource[i].flags & flags)
1290 err = do_pci_enable_device(dev, bars);
1292 atomic_dec(&dev->enable_cnt);
1297 * pci_enable_device_io - Initialize a device for use with IO space
1298 * @dev: PCI device to be initialized
1300 * Initialize device before it's used by a driver. Ask low-level code
1301 * to enable I/O resources. Wake up the device if it was suspended.
1302 * Beware, this function can fail.
1304 int pci_enable_device_io(struct pci_dev *dev)
1306 return pci_enable_device_flags(dev, IORESOURCE_IO);
1310 * pci_enable_device_mem - Initialize a device for use with Memory space
1311 * @dev: PCI device to be initialized
1313 * Initialize device before it's used by a driver. Ask low-level code
1314 * to enable Memory resources. Wake up the device if it was suspended.
1315 * Beware, this function can fail.
1317 int pci_enable_device_mem(struct pci_dev *dev)
1319 return pci_enable_device_flags(dev, IORESOURCE_MEM);
1323 * pci_enable_device - Initialize device before it's used by a driver.
1324 * @dev: PCI device to be initialized
1326 * Initialize device before it's used by a driver. Ask low-level code
1327 * to enable I/O and memory. Wake up the device if it was suspended.
1328 * Beware, this function can fail.
1330 * Note we don't actually enable the device many times if we call
1331 * this function repeatedly (we just increment the count).
1333 int pci_enable_device(struct pci_dev *dev)
1335 return pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
1339 * Managed PCI resources. This manages device on/off, intx/msi/msix
1340 * on/off and BAR regions. pci_dev itself records msi/msix status, so
1341 * there's no need to track it separately. pci_devres is initialized
1342 * when a device is enabled using managed PCI device enable interface.
1345 unsigned int enabled:1;
1346 unsigned int pinned:1;
1347 unsigned int orig_intx:1;
1348 unsigned int restore_intx:1;
1352 static void pcim_release(struct device *gendev, void *res)
1354 struct pci_dev *dev = container_of(gendev, struct pci_dev, dev);
1355 struct pci_devres *this = res;
1358 if (dev->msi_enabled)
1359 pci_disable_msi(dev);
1360 if (dev->msix_enabled)
1361 pci_disable_msix(dev);
1363 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
1364 if (this->region_mask & (1 << i))
1365 pci_release_region(dev, i);
1367 if (this->restore_intx)
1368 pci_intx(dev, this->orig_intx);
1370 if (this->enabled && !this->pinned)
1371 pci_disable_device(dev);
1374 static struct pci_devres * get_pci_dr(struct pci_dev *pdev)
1376 struct pci_devres *dr, *new_dr;
1378 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
1382 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
1385 return devres_get(&pdev->dev, new_dr, NULL, NULL);
1388 static struct pci_devres * find_pci_dr(struct pci_dev *pdev)
1390 if (pci_is_managed(pdev))
1391 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
1396 * pcim_enable_device - Managed pci_enable_device()
1397 * @pdev: PCI device to be initialized
1399 * Managed pci_enable_device().
1401 int pcim_enable_device(struct pci_dev *pdev)
1403 struct pci_devres *dr;
1406 dr = get_pci_dr(pdev);
1412 rc = pci_enable_device(pdev);
1414 pdev->is_managed = 1;
1421 * pcim_pin_device - Pin managed PCI device
1422 * @pdev: PCI device to pin
1424 * Pin managed PCI device @pdev. Pinned device won't be disabled on
1425 * driver detach. @pdev must have been enabled with
1426 * pcim_enable_device().
1428 void pcim_pin_device(struct pci_dev *pdev)
1430 struct pci_devres *dr;
1432 dr = find_pci_dr(pdev);
1433 WARN_ON(!dr || !dr->enabled);
1439 * pcibios_add_device - provide arch specific hooks when adding device dev
1440 * @dev: the PCI device being added
1442 * Permits the platform to provide architecture specific functionality when
1443 * devices are added. This is the default implementation. Architecture
1444 * implementations can override this.
1446 int __weak pcibios_add_device (struct pci_dev *dev)
1452 * pcibios_release_device - provide arch specific hooks when releasing device dev
1453 * @dev: the PCI device being released
1455 * Permits the platform to provide architecture specific functionality when
1456 * devices are released. This is the default implementation. Architecture
1457 * implementations can override this.
1459 void __weak pcibios_release_device(struct pci_dev *dev) {}
1462 * pcibios_disable_device - disable arch specific PCI resources for device dev
1463 * @dev: the PCI device to disable
1465 * Disables architecture specific PCI resources for the device. This
1466 * is the default implementation. Architecture implementations can
1469 void __weak pcibios_disable_device (struct pci_dev *dev) {}
1471 static void do_pci_disable_device(struct pci_dev *dev)
1475 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
1476 if (pci_command & PCI_COMMAND_MASTER) {
1477 pci_command &= ~PCI_COMMAND_MASTER;
1478 pci_write_config_word(dev, PCI_COMMAND, pci_command);
1481 pcibios_disable_device(dev);
1485 * pci_disable_enabled_device - Disable device without updating enable_cnt
1486 * @dev: PCI device to disable
1488 * NOTE: This function is a backend of PCI power management routines and is
1489 * not supposed to be called drivers.
1491 void pci_disable_enabled_device(struct pci_dev *dev)
1493 if (pci_is_enabled(dev))
1494 do_pci_disable_device(dev);
1498 * pci_disable_device - Disable PCI device after use
1499 * @dev: PCI device to be disabled
1501 * Signal to the system that the PCI device is not in use by the system
1502 * anymore. This only involves disabling PCI bus-mastering, if active.
1504 * Note we don't actually disable the device until all callers of
1505 * pci_enable_device() have called pci_disable_device().
1508 pci_disable_device(struct pci_dev *dev)
1510 struct pci_devres *dr;
1512 dr = find_pci_dr(dev);
1516 dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <= 0,
1517 "disabling already-disabled device");
1519 if (atomic_dec_return(&dev->enable_cnt) != 0)
1522 do_pci_disable_device(dev);
1524 dev->is_busmaster = 0;
1528 * pcibios_set_pcie_reset_state - set reset state for device dev
1529 * @dev: the PCIe device reset
1530 * @state: Reset state to enter into
1533 * Sets the PCIe reset state for the device. This is the default
1534 * implementation. Architecture implementations can override this.
1536 int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev,
1537 enum pcie_reset_state state)
1543 * pci_set_pcie_reset_state - set reset state for device dev
1544 * @dev: the PCIe device reset
1545 * @state: Reset state to enter into
1548 * Sets the PCI reset state for the device.
1550 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
1552 return pcibios_set_pcie_reset_state(dev, state);
1556 * pci_check_pme_status - Check if given device has generated PME.
1557 * @dev: Device to check.
1559 * Check the PME status of the device and if set, clear it and clear PME enable
1560 * (if set). Return 'true' if PME status and PME enable were both set or
1561 * 'false' otherwise.
1563 bool pci_check_pme_status(struct pci_dev *dev)
1572 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL;
1573 pci_read_config_word(dev, pmcsr_pos, &pmcsr);
1574 if (!(pmcsr & PCI_PM_CTRL_PME_STATUS))
1577 /* Clear PME status. */
1578 pmcsr |= PCI_PM_CTRL_PME_STATUS;
1579 if (pmcsr & PCI_PM_CTRL_PME_ENABLE) {
1580 /* Disable PME to avoid interrupt flood. */
1581 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1585 pci_write_config_word(dev, pmcsr_pos, pmcsr);
1591 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
1592 * @dev: Device to handle.
1593 * @pme_poll_reset: Whether or not to reset the device's pme_poll flag.
1595 * Check if @dev has generated PME and queue a resume request for it in that
1598 static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset)
1600 if (pme_poll_reset && dev->pme_poll)
1601 dev->pme_poll = false;
1603 if (pci_check_pme_status(dev)) {
1604 pci_wakeup_event(dev);
1605 pm_request_resume(&dev->dev);
1611 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
1612 * @bus: Top bus of the subtree to walk.
1614 void pci_pme_wakeup_bus(struct pci_bus *bus)
1617 pci_walk_bus(bus, pci_pme_wakeup, (void *)true);
1622 * pci_pme_capable - check the capability of PCI device to generate PME#
1623 * @dev: PCI device to handle.
1624 * @state: PCI state from which device will issue PME#.
1626 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
1631 return !!(dev->pme_support & (1 << state));
1634 static void pci_pme_list_scan(struct work_struct *work)
1636 struct pci_pme_device *pme_dev, *n;
1638 mutex_lock(&pci_pme_list_mutex);
1639 list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) {
1640 if (pme_dev->dev->pme_poll) {
1641 struct pci_dev *bridge;
1643 bridge = pme_dev->dev->bus->self;
1645 * If bridge is in low power state, the
1646 * configuration space of subordinate devices
1647 * may be not accessible
1649 if (bridge && bridge->current_state != PCI_D0)
1651 pci_pme_wakeup(pme_dev->dev, NULL);
1653 list_del(&pme_dev->list);
1657 if (!list_empty(&pci_pme_list))
1658 schedule_delayed_work(&pci_pme_work,
1659 msecs_to_jiffies(PME_TIMEOUT));
1660 mutex_unlock(&pci_pme_list_mutex);
1664 * pci_pme_active - enable or disable PCI device's PME# function
1665 * @dev: PCI device to handle.
1666 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1668 * The caller must verify that the device is capable of generating PME# before
1669 * calling this function with @enable equal to 'true'.
1671 void pci_pme_active(struct pci_dev *dev, bool enable)
1675 if (!dev->pme_support)
1678 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1679 /* Clear PME_Status by writing 1 to it and enable PME# */
1680 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
1682 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1684 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1687 * PCI (as opposed to PCIe) PME requires that the device have
1688 * its PME# line hooked up correctly. Not all hardware vendors
1689 * do this, so the PME never gets delivered and the device
1690 * remains asleep. The easiest way around this is to
1691 * periodically walk the list of suspended devices and check
1692 * whether any have their PME flag set. The assumption is that
1693 * we'll wake up often enough anyway that this won't be a huge
1694 * hit, and the power savings from the devices will still be a
1697 * Although PCIe uses in-band PME message instead of PME# line
1698 * to report PME, PME does not work for some PCIe devices in
1699 * reality. For example, there are devices that set their PME
1700 * status bits, but don't really bother to send a PME message;
1701 * there are PCI Express Root Ports that don't bother to
1702 * trigger interrupts when they receive PME messages from the
1703 * devices below. So PME poll is used for PCIe devices too.
1706 if (dev->pme_poll) {
1707 struct pci_pme_device *pme_dev;
1709 pme_dev = kmalloc(sizeof(struct pci_pme_device),
1712 dev_warn(&dev->dev, "can't enable PME#\n");
1716 mutex_lock(&pci_pme_list_mutex);
1717 list_add(&pme_dev->list, &pci_pme_list);
1718 if (list_is_singular(&pci_pme_list))
1719 schedule_delayed_work(&pci_pme_work,
1720 msecs_to_jiffies(PME_TIMEOUT));
1721 mutex_unlock(&pci_pme_list_mutex);
1723 mutex_lock(&pci_pme_list_mutex);
1724 list_for_each_entry(pme_dev, &pci_pme_list, list) {
1725 if (pme_dev->dev == dev) {
1726 list_del(&pme_dev->list);
1731 mutex_unlock(&pci_pme_list_mutex);
1735 dev_dbg(&dev->dev, "PME# %s\n", enable ? "enabled" : "disabled");
1739 * __pci_enable_wake - enable PCI device as wakeup event source
1740 * @dev: PCI device affected
1741 * @state: PCI state from which device will issue wakeup events
1742 * @runtime: True if the events are to be generated at run time
1743 * @enable: True to enable event generation; false to disable
1745 * This enables the device as a wakeup event source, or disables it.
1746 * When such events involves platform-specific hooks, those hooks are
1747 * called automatically by this routine.
1749 * Devices with legacy power management (no standard PCI PM capabilities)
1750 * always require such platform hooks.
1753 * 0 is returned on success
1754 * -EINVAL is returned if device is not supposed to wake up the system
1755 * Error code depending on the platform is returned if both the platform and
1756 * the native mechanism fail to enable the generation of wake-up events
1758 int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1759 bool runtime, bool enable)
1763 if (enable && !runtime && !device_may_wakeup(&dev->dev))
1766 /* Don't do the same thing twice in a row for one device. */
1767 if (!!enable == !!dev->wakeup_prepared)
1771 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1772 * Anderson we should be doing PME# wake enable followed by ACPI wake
1773 * enable. To disable wake-up we call the platform first, for symmetry.
1779 if (pci_pme_capable(dev, state))
1780 pci_pme_active(dev, true);
1783 error = runtime ? platform_pci_run_wake(dev, true) :
1784 platform_pci_sleep_wake(dev, true);
1788 dev->wakeup_prepared = true;
1791 platform_pci_run_wake(dev, false);
1793 platform_pci_sleep_wake(dev, false);
1794 pci_pme_active(dev, false);
1795 dev->wakeup_prepared = false;
1800 EXPORT_SYMBOL(__pci_enable_wake);
1803 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
1804 * @dev: PCI device to prepare
1805 * @enable: True to enable wake-up event generation; false to disable
1807 * Many drivers want the device to wake up the system from D3_hot or D3_cold
1808 * and this function allows them to set that up cleanly - pci_enable_wake()
1809 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
1810 * ordering constraints.
1812 * This function only returns error code if the device is not capable of
1813 * generating PME# from both D3_hot and D3_cold, and the platform is unable to
1814 * enable wake-up power for it.
1816 int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1818 return pci_pme_capable(dev, PCI_D3cold) ?
1819 pci_enable_wake(dev, PCI_D3cold, enable) :
1820 pci_enable_wake(dev, PCI_D3hot, enable);
1824 * pci_target_state - find an appropriate low power state for a given PCI dev
1827 * Use underlying platform code to find a supported low power state for @dev.
1828 * If the platform can't manage @dev, return the deepest state from which it
1829 * can generate wake events, based on any available PME info.
1831 static pci_power_t pci_target_state(struct pci_dev *dev)
1833 pci_power_t target_state = PCI_D3hot;
1835 if (platform_pci_power_manageable(dev)) {
1837 * Call the platform to choose the target state of the device
1838 * and enable wake-up from this state if supported.
1840 pci_power_t state = platform_pci_choose_state(dev);
1843 case PCI_POWER_ERROR:
1848 if (pci_no_d1d2(dev))
1851 target_state = state;
1853 } else if (!dev->pm_cap) {
1854 target_state = PCI_D0;
1855 } else if (device_may_wakeup(&dev->dev)) {
1857 * Find the deepest state from which the device can generate
1858 * wake-up events, make it the target state and enable device
1861 if (dev->pme_support) {
1863 && !(dev->pme_support & (1 << target_state)))
1868 return target_state;
1872 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
1873 * @dev: Device to handle.
1875 * Choose the power state appropriate for the device depending on whether
1876 * it can wake up the system and/or is power manageable by the platform
1877 * (PCI_D3hot is the default) and put the device into that state.
1879 int pci_prepare_to_sleep(struct pci_dev *dev)
1881 pci_power_t target_state = pci_target_state(dev);
1884 if (target_state == PCI_POWER_ERROR)
1887 /* D3cold during system suspend/hibernate is not supported */
1888 if (target_state > PCI_D3hot)
1889 target_state = PCI_D3hot;
1891 pci_enable_wake(dev, target_state, device_may_wakeup(&dev->dev));
1893 error = pci_set_power_state(dev, target_state);
1896 pci_enable_wake(dev, target_state, false);
1902 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
1903 * @dev: Device to handle.
1905 * Disable device's system wake-up capability and put it into D0.
1907 int pci_back_from_sleep(struct pci_dev *dev)
1909 pci_enable_wake(dev, PCI_D0, false);
1910 return pci_set_power_state(dev, PCI_D0);
1914 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
1915 * @dev: PCI device being suspended.
1917 * Prepare @dev to generate wake-up events at run time and put it into a low
1920 int pci_finish_runtime_suspend(struct pci_dev *dev)
1922 pci_power_t target_state = pci_target_state(dev);
1925 if (target_state == PCI_POWER_ERROR)
1928 dev->runtime_d3cold = target_state == PCI_D3cold;
1930 __pci_enable_wake(dev, target_state, true, pci_dev_run_wake(dev));
1932 error = pci_set_power_state(dev, target_state);
1935 __pci_enable_wake(dev, target_state, true, false);
1936 dev->runtime_d3cold = false;
1943 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
1944 * @dev: Device to check.
1946 * Return true if the device itself is capable of generating wake-up events
1947 * (through the platform or using the native PCIe PME) or if the device supports
1948 * PME and one of its upstream bridges can generate wake-up events.
1950 bool pci_dev_run_wake(struct pci_dev *dev)
1952 struct pci_bus *bus = dev->bus;
1954 if (device_run_wake(&dev->dev))
1957 if (!dev->pme_support)
1960 while (bus->parent) {
1961 struct pci_dev *bridge = bus->self;
1963 if (device_run_wake(&bridge->dev))
1969 /* We have reached the root bus. */
1971 return device_run_wake(bus->bridge);
1975 EXPORT_SYMBOL_GPL(pci_dev_run_wake);
1977 void pci_config_pm_runtime_get(struct pci_dev *pdev)
1979 struct device *dev = &pdev->dev;
1980 struct device *parent = dev->parent;
1983 pm_runtime_get_sync(parent);
1984 pm_runtime_get_noresume(dev);
1986 * pdev->current_state is set to PCI_D3cold during suspending,
1987 * so wait until suspending completes
1989 pm_runtime_barrier(dev);
1991 * Only need to resume devices in D3cold, because config
1992 * registers are still accessible for devices suspended but
1995 if (pdev->current_state == PCI_D3cold)
1996 pm_runtime_resume(dev);
1999 void pci_config_pm_runtime_put(struct pci_dev *pdev)
2001 struct device *dev = &pdev->dev;
2002 struct device *parent = dev->parent;
2004 pm_runtime_put(dev);
2006 pm_runtime_put_sync(parent);
2010 * pci_pm_init - Initialize PM functions of given PCI device
2011 * @dev: PCI device to handle.
2013 void pci_pm_init(struct pci_dev *dev)
2018 pm_runtime_forbid(&dev->dev);
2019 pm_runtime_set_active(&dev->dev);
2020 pm_runtime_enable(&dev->dev);
2021 device_enable_async_suspend(&dev->dev);
2022 dev->wakeup_prepared = false;
2025 dev->pme_support = 0;
2027 /* find PCI PM capability in list */
2028 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
2031 /* Check device's ability to generate PME# */
2032 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
2034 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
2035 dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n",
2036 pmc & PCI_PM_CAP_VER_MASK);
2041 dev->d3_delay = PCI_PM_D3_WAIT;
2042 dev->d3cold_delay = PCI_PM_D3COLD_WAIT;
2043 dev->d3cold_allowed = true;
2045 dev->d1_support = false;
2046 dev->d2_support = false;
2047 if (!pci_no_d1d2(dev)) {
2048 if (pmc & PCI_PM_CAP_D1)
2049 dev->d1_support = true;
2050 if (pmc & PCI_PM_CAP_D2)
2051 dev->d2_support = true;
2053 if (dev->d1_support || dev->d2_support)
2054 dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n",
2055 dev->d1_support ? " D1" : "",
2056 dev->d2_support ? " D2" : "");
2059 pmc &= PCI_PM_CAP_PME_MASK;
2061 dev_printk(KERN_DEBUG, &dev->dev,
2062 "PME# supported from%s%s%s%s%s\n",
2063 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
2064 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
2065 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
2066 (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "",
2067 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
2068 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
2069 dev->pme_poll = true;
2071 * Make device's PM flags reflect the wake-up capability, but
2072 * let the user space enable it to wake up the system as needed.
2074 device_set_wakeup_capable(&dev->dev, true);
2075 /* Disable the PME# generation functionality */
2076 pci_pme_active(dev, false);
2080 static void pci_add_saved_cap(struct pci_dev *pci_dev,
2081 struct pci_cap_saved_state *new_cap)
2083 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
2087 * _pci_add_cap_save_buffer - allocate buffer for saving given
2088 * capability registers
2089 * @dev: the PCI device
2090 * @cap: the capability to allocate the buffer for
2091 * @extended: Standard or Extended capability ID
2092 * @size: requested size of the buffer
2094 static int _pci_add_cap_save_buffer(struct pci_dev *dev, u16 cap,
2095 bool extended, unsigned int size)
2098 struct pci_cap_saved_state *save_state;
2101 pos = pci_find_ext_capability(dev, cap);
2103 pos = pci_find_capability(dev, cap);
2108 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
2112 save_state->cap.cap_nr = cap;
2113 save_state->cap.cap_extended = extended;
2114 save_state->cap.size = size;
2115 pci_add_saved_cap(dev, save_state);
2120 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size)
2122 return _pci_add_cap_save_buffer(dev, cap, false, size);
2125 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, u16 cap, unsigned int size)
2127 return _pci_add_cap_save_buffer(dev, cap, true, size);
2131 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
2132 * @dev: the PCI device
2134 void pci_allocate_cap_save_buffers(struct pci_dev *dev)
2138 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
2139 PCI_EXP_SAVE_REGS * sizeof(u16));
2142 "unable to preallocate PCI Express save buffer\n");
2144 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
2147 "unable to preallocate PCI-X save buffer\n");
2149 pci_allocate_vc_save_buffers(dev);
2152 void pci_free_cap_save_buffers(struct pci_dev *dev)
2154 struct pci_cap_saved_state *tmp;
2155 struct hlist_node *n;
2157 hlist_for_each_entry_safe(tmp, n, &dev->saved_cap_space, next)
2162 * pci_configure_ari - enable or disable ARI forwarding
2163 * @dev: the PCI device
2165 * If @dev and its upstream bridge both support ARI, enable ARI in the
2166 * bridge. Otherwise, disable ARI in the bridge.
2168 void pci_configure_ari(struct pci_dev *dev)
2171 struct pci_dev *bridge;
2173 if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn)
2176 bridge = dev->bus->self;
2180 pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
2181 if (!(cap & PCI_EXP_DEVCAP2_ARI))
2184 if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) {
2185 pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2,
2186 PCI_EXP_DEVCTL2_ARI);
2187 bridge->ari_enabled = 1;
2189 pcie_capability_clear_word(bridge, PCI_EXP_DEVCTL2,
2190 PCI_EXP_DEVCTL2_ARI);
2191 bridge->ari_enabled = 0;
2195 static int pci_acs_enable;
2198 * pci_request_acs - ask for ACS to be enabled if supported
2200 void pci_request_acs(void)
2206 * pci_std_enable_acs - enable ACS on devices using standard ACS capabilites
2207 * @dev: the PCI device
2209 static int pci_std_enable_acs(struct pci_dev *dev)
2215 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
2219 pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
2220 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
2222 /* Source Validation */
2223 ctrl |= (cap & PCI_ACS_SV);
2225 /* P2P Request Redirect */
2226 ctrl |= (cap & PCI_ACS_RR);
2228 /* P2P Completion Redirect */
2229 ctrl |= (cap & PCI_ACS_CR);
2231 /* Upstream Forwarding */
2232 ctrl |= (cap & PCI_ACS_UF);
2234 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
2240 * pci_enable_acs - enable ACS if hardware support it
2241 * @dev: the PCI device
2243 void pci_enable_acs(struct pci_dev *dev)
2245 if (!pci_acs_enable)
2248 if (!pci_std_enable_acs(dev))
2251 pci_dev_specific_enable_acs(dev);
2254 static bool pci_acs_flags_enabled(struct pci_dev *pdev, u16 acs_flags)
2259 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ACS);
2264 * Except for egress control, capabilities are either required
2265 * or only required if controllable. Features missing from the
2266 * capability field can therefore be assumed as hard-wired enabled.
2268 pci_read_config_word(pdev, pos + PCI_ACS_CAP, &cap);
2269 acs_flags &= (cap | PCI_ACS_EC);
2271 pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl);
2272 return (ctrl & acs_flags) == acs_flags;
2276 * pci_acs_enabled - test ACS against required flags for a given device
2277 * @pdev: device to test
2278 * @acs_flags: required PCI ACS flags
2280 * Return true if the device supports the provided flags. Automatically
2281 * filters out flags that are not implemented on multifunction devices.
2283 * Note that this interface checks the effective ACS capabilities of the
2284 * device rather than the actual capabilities. For instance, most single
2285 * function endpoints are not required to support ACS because they have no
2286 * opportunity for peer-to-peer access. We therefore return 'true'
2287 * regardless of whether the device exposes an ACS capability. This makes
2288 * it much easier for callers of this function to ignore the actual type
2289 * or topology of the device when testing ACS support.
2291 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
2295 ret = pci_dev_specific_acs_enabled(pdev, acs_flags);
2300 * Conventional PCI and PCI-X devices never support ACS, either
2301 * effectively or actually. The shared bus topology implies that
2302 * any device on the bus can receive or snoop DMA.
2304 if (!pci_is_pcie(pdev))
2307 switch (pci_pcie_type(pdev)) {
2309 * PCI/X-to-PCIe bridges are not specifically mentioned by the spec,
2310 * but since their primary interface is PCI/X, we conservatively
2311 * handle them as we would a non-PCIe device.
2313 case PCI_EXP_TYPE_PCIE_BRIDGE:
2315 * PCIe 3.0, 6.12.1 excludes ACS on these devices. "ACS is never
2316 * applicable... must never implement an ACS Extended Capability...".
2317 * This seems arbitrary, but we take a conservative interpretation
2318 * of this statement.
2320 case PCI_EXP_TYPE_PCI_BRIDGE:
2321 case PCI_EXP_TYPE_RC_EC:
2324 * PCIe 3.0, 6.12.1.1 specifies that downstream and root ports should
2325 * implement ACS in order to indicate their peer-to-peer capabilities,
2326 * regardless of whether they are single- or multi-function devices.
2328 case PCI_EXP_TYPE_DOWNSTREAM:
2329 case PCI_EXP_TYPE_ROOT_PORT:
2330 return pci_acs_flags_enabled(pdev, acs_flags);
2332 * PCIe 3.0, 6.12.1.2 specifies ACS capabilities that should be
2333 * implemented by the remaining PCIe types to indicate peer-to-peer
2334 * capabilities, but only when they are part of a multifunction
2335 * device. The footnote for section 6.12 indicates the specific
2336 * PCIe types included here.
2338 case PCI_EXP_TYPE_ENDPOINT:
2339 case PCI_EXP_TYPE_UPSTREAM:
2340 case PCI_EXP_TYPE_LEG_END:
2341 case PCI_EXP_TYPE_RC_END:
2342 if (!pdev->multifunction)
2345 return pci_acs_flags_enabled(pdev, acs_flags);
2349 * PCIe 3.0, 6.12.1.3 specifies no ACS capabilities are applicable
2350 * to single function devices with the exception of downstream ports.
2356 * pci_acs_path_enable - test ACS flags from start to end in a hierarchy
2357 * @start: starting downstream device
2358 * @end: ending upstream device or NULL to search to the root bus
2359 * @acs_flags: required flags
2361 * Walk up a device tree from start to end testing PCI ACS support. If
2362 * any step along the way does not support the required flags, return false.
2364 bool pci_acs_path_enabled(struct pci_dev *start,
2365 struct pci_dev *end, u16 acs_flags)
2367 struct pci_dev *pdev, *parent = start;
2372 if (!pci_acs_enabled(pdev, acs_flags))
2375 if (pci_is_root_bus(pdev->bus))
2376 return (end == NULL);
2378 parent = pdev->bus->self;
2379 } while (pdev != end);
2385 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
2386 * @dev: the PCI device
2387 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD)
2389 * Perform INTx swizzling for a device behind one level of bridge. This is
2390 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
2391 * behind bridges on add-in cards. For devices with ARI enabled, the slot
2392 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
2393 * the PCI Express Base Specification, Revision 2.1)
2395 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin)
2399 if (pci_ari_enabled(dev->bus))
2402 slot = PCI_SLOT(dev->devfn);
2404 return (((pin - 1) + slot) % 4) + 1;
2408 pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
2416 while (!pci_is_root_bus(dev->bus)) {
2417 pin = pci_swizzle_interrupt_pin(dev, pin);
2418 dev = dev->bus->self;
2425 * pci_common_swizzle - swizzle INTx all the way to root bridge
2426 * @dev: the PCI device
2427 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
2429 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
2430 * bridges all the way up to a PCI root bus.
2432 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
2436 while (!pci_is_root_bus(dev->bus)) {
2437 pin = pci_swizzle_interrupt_pin(dev, pin);
2438 dev = dev->bus->self;
2441 return PCI_SLOT(dev->devfn);
2445 * pci_release_region - Release a PCI bar
2446 * @pdev: PCI device whose resources were previously reserved by pci_request_region
2447 * @bar: BAR to release
2449 * Releases the PCI I/O and memory resources previously reserved by a
2450 * successful call to pci_request_region. Call this function only
2451 * after all use of the PCI regions has ceased.
2453 void pci_release_region(struct pci_dev *pdev, int bar)
2455 struct pci_devres *dr;
2457 if (pci_resource_len(pdev, bar) == 0)
2459 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
2460 release_region(pci_resource_start(pdev, bar),
2461 pci_resource_len(pdev, bar));
2462 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
2463 release_mem_region(pci_resource_start(pdev, bar),
2464 pci_resource_len(pdev, bar));
2466 dr = find_pci_dr(pdev);
2468 dr->region_mask &= ~(1 << bar);
2472 * __pci_request_region - Reserved PCI I/O and memory resource
2473 * @pdev: PCI device whose resources are to be reserved
2474 * @bar: BAR to be reserved
2475 * @res_name: Name to be associated with resource.
2476 * @exclusive: whether the region access is exclusive or not
2478 * Mark the PCI region associated with PCI device @pdev BR @bar as
2479 * being reserved by owner @res_name. Do not access any
2480 * address inside the PCI regions unless this call returns
2483 * If @exclusive is set, then the region is marked so that userspace
2484 * is explicitly not allowed to map the resource via /dev/mem or
2485 * sysfs MMIO access.
2487 * Returns 0 on success, or %EBUSY on error. A warning
2488 * message is also printed on failure.
2490 static int __pci_request_region(struct pci_dev *pdev, int bar, const char *res_name,
2493 struct pci_devres *dr;
2495 if (pci_resource_len(pdev, bar) == 0)
2498 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
2499 if (!request_region(pci_resource_start(pdev, bar),
2500 pci_resource_len(pdev, bar), res_name))
2503 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
2504 if (!__request_mem_region(pci_resource_start(pdev, bar),
2505 pci_resource_len(pdev, bar), res_name,
2510 dr = find_pci_dr(pdev);
2512 dr->region_mask |= 1 << bar;
2517 dev_warn(&pdev->dev, "BAR %d: can't reserve %pR\n", bar,
2518 &pdev->resource[bar]);
2523 * pci_request_region - Reserve PCI I/O and memory resource
2524 * @pdev: PCI device whose resources are to be reserved
2525 * @bar: BAR to be reserved
2526 * @res_name: Name to be associated with resource
2528 * Mark the PCI region associated with PCI device @pdev BAR @bar as
2529 * being reserved by owner @res_name. Do not access any
2530 * address inside the PCI regions unless this call returns
2533 * Returns 0 on success, or %EBUSY on error. A warning
2534 * message is also printed on failure.
2536 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
2538 return __pci_request_region(pdev, bar, res_name, 0);
2542 * pci_request_region_exclusive - Reserved PCI I/O and memory resource
2543 * @pdev: PCI device whose resources are to be reserved
2544 * @bar: BAR to be reserved
2545 * @res_name: Name to be associated with resource.
2547 * Mark the PCI region associated with PCI device @pdev BR @bar as
2548 * being reserved by owner @res_name. Do not access any
2549 * address inside the PCI regions unless this call returns
2552 * Returns 0 on success, or %EBUSY on error. A warning
2553 * message is also printed on failure.
2555 * The key difference that _exclusive makes it that userspace is
2556 * explicitly not allowed to map the resource via /dev/mem or
2559 int pci_request_region_exclusive(struct pci_dev *pdev, int bar, const char *res_name)
2561 return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE);
2564 * pci_release_selected_regions - Release selected PCI I/O and memory resources
2565 * @pdev: PCI device whose resources were previously reserved
2566 * @bars: Bitmask of BARs to be released
2568 * Release selected PCI I/O and memory resources previously reserved.
2569 * Call this function only after all use of the PCI regions has ceased.
2571 void pci_release_selected_regions(struct pci_dev *pdev, int bars)
2575 for (i = 0; i < 6; i++)
2576 if (bars & (1 << i))
2577 pci_release_region(pdev, i);
2580 static int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
2581 const char *res_name, int excl)
2585 for (i = 0; i < 6; i++)
2586 if (bars & (1 << i))
2587 if (__pci_request_region(pdev, i, res_name, excl))
2593 if (bars & (1 << i))
2594 pci_release_region(pdev, i);
2601 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
2602 * @pdev: PCI device whose resources are to be reserved
2603 * @bars: Bitmask of BARs to be requested
2604 * @res_name: Name to be associated with resource
2606 int pci_request_selected_regions(struct pci_dev *pdev, int bars,
2607 const char *res_name)
2609 return __pci_request_selected_regions(pdev, bars, res_name, 0);
2612 int pci_request_selected_regions_exclusive(struct pci_dev *pdev,
2613 int bars, const char *res_name)
2615 return __pci_request_selected_regions(pdev, bars, res_name,
2616 IORESOURCE_EXCLUSIVE);
2620 * pci_release_regions - Release reserved PCI I/O and memory resources
2621 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
2623 * Releases all PCI I/O and memory resources previously reserved by a
2624 * successful call to pci_request_regions. Call this function only
2625 * after all use of the PCI regions has ceased.
2628 void pci_release_regions(struct pci_dev *pdev)
2630 pci_release_selected_regions(pdev, (1 << 6) - 1);
2634 * pci_request_regions - Reserved PCI I/O and memory resources
2635 * @pdev: PCI device whose resources are to be reserved
2636 * @res_name: Name to be associated with resource.
2638 * Mark all PCI regions associated with PCI device @pdev as
2639 * being reserved by owner @res_name. Do not access any
2640 * address inside the PCI regions unless this call returns
2643 * Returns 0 on success, or %EBUSY on error. A warning
2644 * message is also printed on failure.
2646 int pci_request_regions(struct pci_dev *pdev, const char *res_name)
2648 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
2652 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
2653 * @pdev: PCI device whose resources are to be reserved
2654 * @res_name: Name to be associated with resource.
2656 * Mark all PCI regions associated with PCI device @pdev as
2657 * being reserved by owner @res_name. Do not access any
2658 * address inside the PCI regions unless this call returns
2661 * pci_request_regions_exclusive() will mark the region so that
2662 * /dev/mem and the sysfs MMIO access will not be allowed.
2664 * Returns 0 on success, or %EBUSY on error. A warning
2665 * message is also printed on failure.
2667 int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
2669 return pci_request_selected_regions_exclusive(pdev,
2670 ((1 << 6) - 1), res_name);
2673 static void __pci_set_master(struct pci_dev *dev, bool enable)
2677 pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
2679 cmd = old_cmd | PCI_COMMAND_MASTER;
2681 cmd = old_cmd & ~PCI_COMMAND_MASTER;
2682 if (cmd != old_cmd) {
2683 dev_dbg(&dev->dev, "%s bus mastering\n",
2684 enable ? "enabling" : "disabling");
2685 pci_write_config_word(dev, PCI_COMMAND, cmd);
2687 dev->is_busmaster = enable;
2691 * pcibios_setup - process "pci=" kernel boot arguments
2692 * @str: string used to pass in "pci=" kernel boot arguments
2694 * Process kernel boot arguments. This is the default implementation.
2695 * Architecture specific implementations can override this as necessary.
2697 char * __weak __init pcibios_setup(char *str)
2703 * pcibios_set_master - enable PCI bus-mastering for device dev
2704 * @dev: the PCI device to enable
2706 * Enables PCI bus-mastering for the device. This is the default
2707 * implementation. Architecture specific implementations can override
2708 * this if necessary.
2710 void __weak pcibios_set_master(struct pci_dev *dev)
2714 /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */
2715 if (pci_is_pcie(dev))
2718 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
2720 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
2721 else if (lat > pcibios_max_latency)
2722 lat = pcibios_max_latency;
2726 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
2730 * pci_set_master - enables bus-mastering for device dev
2731 * @dev: the PCI device to enable
2733 * Enables bus-mastering on the device and calls pcibios_set_master()
2734 * to do the needed arch specific settings.
2736 void pci_set_master(struct pci_dev *dev)
2738 __pci_set_master(dev, true);
2739 pcibios_set_master(dev);
2743 * pci_clear_master - disables bus-mastering for device dev
2744 * @dev: the PCI device to disable
2746 void pci_clear_master(struct pci_dev *dev)
2748 __pci_set_master(dev, false);
2752 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
2753 * @dev: the PCI device for which MWI is to be enabled
2755 * Helper function for pci_set_mwi.
2756 * Originally copied from drivers/net/acenic.c.
2757 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
2759 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2761 int pci_set_cacheline_size(struct pci_dev *dev)
2765 if (!pci_cache_line_size)
2768 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
2769 equal to or multiple of the right value. */
2770 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
2771 if (cacheline_size >= pci_cache_line_size &&
2772 (cacheline_size % pci_cache_line_size) == 0)
2775 /* Write the correct value. */
2776 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
2778 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
2779 if (cacheline_size == pci_cache_line_size)
2782 dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not "
2783 "supported\n", pci_cache_line_size << 2);
2787 EXPORT_SYMBOL_GPL(pci_set_cacheline_size);
2789 #ifdef PCI_DISABLE_MWI
2790 int pci_set_mwi(struct pci_dev *dev)
2795 int pci_try_set_mwi(struct pci_dev *dev)
2800 void pci_clear_mwi(struct pci_dev *dev)
2807 * pci_set_mwi - enables memory-write-invalidate PCI transaction
2808 * @dev: the PCI device for which MWI is enabled
2810 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
2812 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2815 pci_set_mwi(struct pci_dev *dev)
2820 rc = pci_set_cacheline_size(dev);
2824 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2825 if (! (cmd & PCI_COMMAND_INVALIDATE)) {
2826 dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n");
2827 cmd |= PCI_COMMAND_INVALIDATE;
2828 pci_write_config_word(dev, PCI_COMMAND, cmd);
2835 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
2836 * @dev: the PCI device for which MWI is enabled
2838 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
2839 * Callers are not required to check the return value.
2841 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2843 int pci_try_set_mwi(struct pci_dev *dev)
2845 int rc = pci_set_mwi(dev);
2850 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
2851 * @dev: the PCI device to disable
2853 * Disables PCI Memory-Write-Invalidate transaction on the device
2856 pci_clear_mwi(struct pci_dev *dev)
2860 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2861 if (cmd & PCI_COMMAND_INVALIDATE) {
2862 cmd &= ~PCI_COMMAND_INVALIDATE;
2863 pci_write_config_word(dev, PCI_COMMAND, cmd);
2866 #endif /* ! PCI_DISABLE_MWI */
2869 * pci_intx - enables/disables PCI INTx for device dev
2870 * @pdev: the PCI device to operate on
2871 * @enable: boolean: whether to enable or disable PCI INTx
2873 * Enables/disables PCI INTx for device dev
2876 pci_intx(struct pci_dev *pdev, int enable)
2878 u16 pci_command, new;
2880 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
2883 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
2885 new = pci_command | PCI_COMMAND_INTX_DISABLE;
2888 if (new != pci_command) {
2889 struct pci_devres *dr;
2891 pci_write_config_word(pdev, PCI_COMMAND, new);
2893 dr = find_pci_dr(pdev);
2894 if (dr && !dr->restore_intx) {
2895 dr->restore_intx = 1;
2896 dr->orig_intx = !enable;
2902 * pci_intx_mask_supported - probe for INTx masking support
2903 * @dev: the PCI device to operate on
2905 * Check if the device dev support INTx masking via the config space
2908 bool pci_intx_mask_supported(struct pci_dev *dev)
2910 bool mask_supported = false;
2913 if (dev->broken_intx_masking)
2916 pci_cfg_access_lock(dev);
2918 pci_read_config_word(dev, PCI_COMMAND, &orig);
2919 pci_write_config_word(dev, PCI_COMMAND,
2920 orig ^ PCI_COMMAND_INTX_DISABLE);
2921 pci_read_config_word(dev, PCI_COMMAND, &new);
2924 * There's no way to protect against hardware bugs or detect them
2925 * reliably, but as long as we know what the value should be, let's
2926 * go ahead and check it.
2928 if ((new ^ orig) & ~PCI_COMMAND_INTX_DISABLE) {
2929 dev_err(&dev->dev, "Command register changed from "
2930 "0x%x to 0x%x: driver or hardware bug?\n", orig, new);
2931 } else if ((new ^ orig) & PCI_COMMAND_INTX_DISABLE) {
2932 mask_supported = true;
2933 pci_write_config_word(dev, PCI_COMMAND, orig);
2936 pci_cfg_access_unlock(dev);
2937 return mask_supported;
2939 EXPORT_SYMBOL_GPL(pci_intx_mask_supported);
2941 static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask)
2943 struct pci_bus *bus = dev->bus;
2944 bool mask_updated = true;
2945 u32 cmd_status_dword;
2946 u16 origcmd, newcmd;
2947 unsigned long flags;
2951 * We do a single dword read to retrieve both command and status.
2952 * Document assumptions that make this possible.
2954 BUILD_BUG_ON(PCI_COMMAND % 4);
2955 BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS);
2957 raw_spin_lock_irqsave(&pci_lock, flags);
2959 bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword);
2961 irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT;
2964 * Check interrupt status register to see whether our device
2965 * triggered the interrupt (when masking) or the next IRQ is
2966 * already pending (when unmasking).
2968 if (mask != irq_pending) {
2969 mask_updated = false;
2973 origcmd = cmd_status_dword;
2974 newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE;
2976 newcmd |= PCI_COMMAND_INTX_DISABLE;
2977 if (newcmd != origcmd)
2978 bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd);
2981 raw_spin_unlock_irqrestore(&pci_lock, flags);
2983 return mask_updated;
2987 * pci_check_and_mask_intx - mask INTx on pending interrupt
2988 * @dev: the PCI device to operate on
2990 * Check if the device dev has its INTx line asserted, mask it and
2991 * return true in that case. False is returned if not interrupt was
2994 bool pci_check_and_mask_intx(struct pci_dev *dev)
2996 return pci_check_and_set_intx_mask(dev, true);
2998 EXPORT_SYMBOL_GPL(pci_check_and_mask_intx);
3001 * pci_check_and_unmask_intx - unmask INTx if no interrupt is pending
3002 * @dev: the PCI device to operate on
3004 * Check if the device dev has its INTx line asserted, unmask it if not
3005 * and return true. False is returned and the mask remains active if
3006 * there was still an interrupt pending.
3008 bool pci_check_and_unmask_intx(struct pci_dev *dev)
3010 return pci_check_and_set_intx_mask(dev, false);
3012 EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx);
3015 * pci_msi_off - disables any MSI or MSI-X capabilities
3016 * @dev: the PCI device to operate on
3018 * If you want to use MSI, see pci_enable_msi() and friends.
3019 * This is a lower-level primitive that allows us to disable
3020 * MSI operation at the device level.
3022 void pci_msi_off(struct pci_dev *dev)
3028 * This looks like it could go in msi.c, but we need it even when
3029 * CONFIG_PCI_MSI=n. For the same reason, we can't use
3030 * dev->msi_cap or dev->msix_cap here.
3032 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
3034 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
3035 control &= ~PCI_MSI_FLAGS_ENABLE;
3036 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
3038 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
3040 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
3041 control &= ~PCI_MSIX_FLAGS_ENABLE;
3042 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
3045 EXPORT_SYMBOL_GPL(pci_msi_off);
3047 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size)
3049 return dma_set_max_seg_size(&dev->dev, size);
3051 EXPORT_SYMBOL(pci_set_dma_max_seg_size);
3053 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask)
3055 return dma_set_seg_boundary(&dev->dev, mask);
3057 EXPORT_SYMBOL(pci_set_dma_seg_boundary);
3060 * pci_wait_for_pending_transaction - waits for pending transaction
3061 * @dev: the PCI device to operate on
3063 * Return 0 if transaction is pending 1 otherwise.
3065 int pci_wait_for_pending_transaction(struct pci_dev *dev)
3067 if (!pci_is_pcie(dev))
3070 return pci_wait_for_pending(dev, pci_pcie_cap(dev) + PCI_EXP_DEVSTA,
3071 PCI_EXP_DEVSTA_TRPND);
3073 EXPORT_SYMBOL(pci_wait_for_pending_transaction);
3075 static int pcie_flr(struct pci_dev *dev, int probe)
3079 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
3080 if (!(cap & PCI_EXP_DEVCAP_FLR))
3086 if (!pci_wait_for_pending_transaction(dev))
3087 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
3089 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
3096 static int pci_af_flr(struct pci_dev *dev, int probe)
3101 pos = pci_find_capability(dev, PCI_CAP_ID_AF);
3105 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
3106 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
3112 /* Wait for Transaction Pending bit clean */
3113 if (pci_wait_for_pending(dev, pos + PCI_AF_STATUS, PCI_AF_STATUS_TP))
3116 dev_err(&dev->dev, "transaction is not cleared; "
3117 "proceeding with reset anyway\n");
3120 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
3127 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
3128 * @dev: Device to reset.
3129 * @probe: If set, only check if the device can be reset this way.
3131 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
3132 * unset, it will be reinitialized internally when going from PCI_D3hot to
3133 * PCI_D0. If that's the case and the device is not in a low-power state
3134 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
3136 * NOTE: This causes the caller to sleep for twice the device power transition
3137 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
3138 * by default (i.e. unless the @dev's d3_delay field has a different value).
3139 * Moreover, only devices in D0 can be reset by this function.
3141 static int pci_pm_reset(struct pci_dev *dev, int probe)
3148 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
3149 if (csr & PCI_PM_CTRL_NO_SOFT_RESET)
3155 if (dev->current_state != PCI_D0)
3158 csr &= ~PCI_PM_CTRL_STATE_MASK;
3160 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
3161 pci_dev_d3_sleep(dev);
3163 csr &= ~PCI_PM_CTRL_STATE_MASK;
3165 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
3166 pci_dev_d3_sleep(dev);
3172 * pci_reset_bridge_secondary_bus - Reset the secondary bus on a PCI bridge.
3173 * @dev: Bridge device
3175 * Use the bridge control register to assert reset on the secondary bus.
3176 * Devices on the secondary bus are left in power-on state.
3178 void pci_reset_bridge_secondary_bus(struct pci_dev *dev)
3182 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl);
3183 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
3184 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
3186 * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double
3187 * this to 2ms to ensure that we meet the minimum requirement.
3191 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
3192 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
3195 * Trhfa for conventional PCI is 2^25 clock cycles.
3196 * Assuming a minimum 33MHz clock this results in a 1s
3197 * delay before we can consider subordinate devices to
3198 * be re-initialized. PCIe has some ways to shorten this,
3199 * but we don't make use of them yet.
3203 EXPORT_SYMBOL_GPL(pci_reset_bridge_secondary_bus);
3205 static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
3207 struct pci_dev *pdev;
3209 if (pci_is_root_bus(dev->bus) || dev->subordinate || !dev->bus->self)
3212 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
3219 pci_reset_bridge_secondary_bus(dev->bus->self);
3224 static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, int probe)
3228 if (!hotplug || !try_module_get(hotplug->ops->owner))
3231 if (hotplug->ops->reset_slot)
3232 rc = hotplug->ops->reset_slot(hotplug, probe);
3234 module_put(hotplug->ops->owner);
3239 static int pci_dev_reset_slot_function(struct pci_dev *dev, int probe)
3241 struct pci_dev *pdev;
3243 if (dev->subordinate || !dev->slot)
3246 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
3247 if (pdev != dev && pdev->slot == dev->slot)
3250 return pci_reset_hotplug_slot(dev->slot->hotplug, probe);
3253 static int __pci_dev_reset(struct pci_dev *dev, int probe)
3259 rc = pci_dev_specific_reset(dev, probe);
3263 rc = pcie_flr(dev, probe);
3267 rc = pci_af_flr(dev, probe);
3271 rc = pci_pm_reset(dev, probe);
3275 rc = pci_dev_reset_slot_function(dev, probe);
3279 rc = pci_parent_bus_reset(dev, probe);
3284 static void pci_dev_lock(struct pci_dev *dev)
3286 pci_cfg_access_lock(dev);
3287 /* block PM suspend, driver probe, etc. */
3288 device_lock(&dev->dev);
3291 /* Return 1 on successful lock, 0 on contention */
3292 static int pci_dev_trylock(struct pci_dev *dev)
3294 if (pci_cfg_access_trylock(dev)) {
3295 if (device_trylock(&dev->dev))
3297 pci_cfg_access_unlock(dev);
3303 static void pci_dev_unlock(struct pci_dev *dev)
3305 device_unlock(&dev->dev);
3306 pci_cfg_access_unlock(dev);
3309 static void pci_dev_save_and_disable(struct pci_dev *dev)
3312 * Wake-up device prior to save. PM registers default to D0 after
3313 * reset and a simple register restore doesn't reliably return
3314 * to a non-D0 state anyway.
3316 pci_set_power_state(dev, PCI_D0);
3318 pci_save_state(dev);
3320 * Disable the device by clearing the Command register, except for
3321 * INTx-disable which is set. This not only disables MMIO and I/O port
3322 * BARs, but also prevents the device from being Bus Master, preventing
3323 * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3
3324 * compliant devices, INTx-disable prevents legacy interrupts.
3326 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
3329 static void pci_dev_restore(struct pci_dev *dev)
3331 pci_restore_state(dev);
3334 static int pci_dev_reset(struct pci_dev *dev, int probe)
3341 rc = __pci_dev_reset(dev, probe);
3344 pci_dev_unlock(dev);
3349 * __pci_reset_function - reset a PCI device function
3350 * @dev: PCI device to reset
3352 * Some devices allow an individual function to be reset without affecting
3353 * other functions in the same device. The PCI device must be responsive
3354 * to PCI config space in order to use this function.
3356 * The device function is presumed to be unused when this function is called.
3357 * Resetting the device will make the contents of PCI configuration space
3358 * random, so any caller of this must be prepared to reinitialise the
3359 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
3362 * Returns 0 if the device function was successfully reset or negative if the
3363 * device doesn't support resetting a single function.
3365 int __pci_reset_function(struct pci_dev *dev)
3367 return pci_dev_reset(dev, 0);
3369 EXPORT_SYMBOL_GPL(__pci_reset_function);
3372 * __pci_reset_function_locked - reset a PCI device function while holding
3373 * the @dev mutex lock.
3374 * @dev: PCI device to reset
3376 * Some devices allow an individual function to be reset without affecting
3377 * other functions in the same device. The PCI device must be responsive
3378 * to PCI config space in order to use this function.
3380 * The device function is presumed to be unused and the caller is holding
3381 * the device mutex lock when this function is called.
3382 * Resetting the device will make the contents of PCI configuration space
3383 * random, so any caller of this must be prepared to reinitialise the
3384 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
3387 * Returns 0 if the device function was successfully reset or negative if the
3388 * device doesn't support resetting a single function.
3390 int __pci_reset_function_locked(struct pci_dev *dev)
3392 return __pci_dev_reset(dev, 0);
3394 EXPORT_SYMBOL_GPL(__pci_reset_function_locked);
3397 * pci_probe_reset_function - check whether the device can be safely reset
3398 * @dev: PCI device to reset
3400 * Some devices allow an individual function to be reset without affecting
3401 * other functions in the same device. The PCI device must be responsive
3402 * to PCI config space in order to use this function.
3404 * Returns 0 if the device function can be reset or negative if the
3405 * device doesn't support resetting a single function.
3407 int pci_probe_reset_function(struct pci_dev *dev)
3409 return pci_dev_reset(dev, 1);
3413 * pci_reset_function - quiesce and reset a PCI device function
3414 * @dev: PCI device to reset
3416 * Some devices allow an individual function to be reset without affecting
3417 * other functions in the same device. The PCI device must be responsive
3418 * to PCI config space in order to use this function.
3420 * This function does not just reset the PCI portion of a device, but
3421 * clears all the state associated with the device. This function differs
3422 * from __pci_reset_function in that it saves and restores device state
3425 * Returns 0 if the device function was successfully reset or negative if the
3426 * device doesn't support resetting a single function.
3428 int pci_reset_function(struct pci_dev *dev)
3432 rc = pci_dev_reset(dev, 1);
3436 pci_dev_save_and_disable(dev);
3438 rc = pci_dev_reset(dev, 0);
3440 pci_dev_restore(dev);
3444 EXPORT_SYMBOL_GPL(pci_reset_function);
3447 * pci_try_reset_function - quiesce and reset a PCI device function
3448 * @dev: PCI device to reset
3450 * Same as above, except return -EAGAIN if unable to lock device.
3452 int pci_try_reset_function(struct pci_dev *dev)
3456 rc = pci_dev_reset(dev, 1);
3460 pci_dev_save_and_disable(dev);
3462 if (pci_dev_trylock(dev)) {
3463 rc = __pci_dev_reset(dev, 0);
3464 pci_dev_unlock(dev);
3468 pci_dev_restore(dev);
3472 EXPORT_SYMBOL_GPL(pci_try_reset_function);
3474 /* Lock devices from the top of the tree down */
3475 static void pci_bus_lock(struct pci_bus *bus)
3477 struct pci_dev *dev;
3479 list_for_each_entry(dev, &bus->devices, bus_list) {
3481 if (dev->subordinate)
3482 pci_bus_lock(dev->subordinate);
3486 /* Unlock devices from the bottom of the tree up */
3487 static void pci_bus_unlock(struct pci_bus *bus)
3489 struct pci_dev *dev;
3491 list_for_each_entry(dev, &bus->devices, bus_list) {
3492 if (dev->subordinate)
3493 pci_bus_unlock(dev->subordinate);
3494 pci_dev_unlock(dev);
3498 /* Return 1 on successful lock, 0 on contention */
3499 static int pci_bus_trylock(struct pci_bus *bus)
3501 struct pci_dev *dev;
3503 list_for_each_entry(dev, &bus->devices, bus_list) {
3504 if (!pci_dev_trylock(dev))
3506 if (dev->subordinate) {
3507 if (!pci_bus_trylock(dev->subordinate)) {
3508 pci_dev_unlock(dev);
3516 list_for_each_entry_continue_reverse(dev, &bus->devices, bus_list) {
3517 if (dev->subordinate)
3518 pci_bus_unlock(dev->subordinate);
3519 pci_dev_unlock(dev);
3524 /* Lock devices from the top of the tree down */
3525 static void pci_slot_lock(struct pci_slot *slot)
3527 struct pci_dev *dev;
3529 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
3530 if (!dev->slot || dev->slot != slot)
3533 if (dev->subordinate)
3534 pci_bus_lock(dev->subordinate);
3538 /* Unlock devices from the bottom of the tree up */
3539 static void pci_slot_unlock(struct pci_slot *slot)
3541 struct pci_dev *dev;
3543 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
3544 if (!dev->slot || dev->slot != slot)
3546 if (dev->subordinate)
3547 pci_bus_unlock(dev->subordinate);
3548 pci_dev_unlock(dev);
3552 /* Return 1 on successful lock, 0 on contention */
3553 static int pci_slot_trylock(struct pci_slot *slot)
3555 struct pci_dev *dev;
3557 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
3558 if (!dev->slot || dev->slot != slot)
3560 if (!pci_dev_trylock(dev))
3562 if (dev->subordinate) {
3563 if (!pci_bus_trylock(dev->subordinate)) {
3564 pci_dev_unlock(dev);
3572 list_for_each_entry_continue_reverse(dev,
3573 &slot->bus->devices, bus_list) {
3574 if (!dev->slot || dev->slot != slot)
3576 if (dev->subordinate)
3577 pci_bus_unlock(dev->subordinate);
3578 pci_dev_unlock(dev);
3583 /* Save and disable devices from the top of the tree down */
3584 static void pci_bus_save_and_disable(struct pci_bus *bus)
3586 struct pci_dev *dev;
3588 list_for_each_entry(dev, &bus->devices, bus_list) {
3589 pci_dev_save_and_disable(dev);
3590 if (dev->subordinate)
3591 pci_bus_save_and_disable(dev->subordinate);
3596 * Restore devices from top of the tree down - parent bridges need to be
3597 * restored before we can get to subordinate devices.
3599 static void pci_bus_restore(struct pci_bus *bus)
3601 struct pci_dev *dev;
3603 list_for_each_entry(dev, &bus->devices, bus_list) {
3604 pci_dev_restore(dev);
3605 if (dev->subordinate)
3606 pci_bus_restore(dev->subordinate);
3610 /* Save and disable devices from the top of the tree down */
3611 static void pci_slot_save_and_disable(struct pci_slot *slot)
3613 struct pci_dev *dev;
3615 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
3616 if (!dev->slot || dev->slot != slot)
3618 pci_dev_save_and_disable(dev);
3619 if (dev->subordinate)
3620 pci_bus_save_and_disable(dev->subordinate);
3625 * Restore devices from top of the tree down - parent bridges need to be
3626 * restored before we can get to subordinate devices.
3628 static void pci_slot_restore(struct pci_slot *slot)
3630 struct pci_dev *dev;
3632 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
3633 if (!dev->slot || dev->slot != slot)
3635 pci_dev_restore(dev);
3636 if (dev->subordinate)
3637 pci_bus_restore(dev->subordinate);
3641 static int pci_slot_reset(struct pci_slot *slot, int probe)
3649 pci_slot_lock(slot);
3653 rc = pci_reset_hotplug_slot(slot->hotplug, probe);
3656 pci_slot_unlock(slot);
3662 * pci_probe_reset_slot - probe whether a PCI slot can be reset
3663 * @slot: PCI slot to probe
3665 * Return 0 if slot can be reset, negative if a slot reset is not supported.
3667 int pci_probe_reset_slot(struct pci_slot *slot)
3669 return pci_slot_reset(slot, 1);
3671 EXPORT_SYMBOL_GPL(pci_probe_reset_slot);
3674 * pci_reset_slot - reset a PCI slot
3675 * @slot: PCI slot to reset
3677 * A PCI bus may host multiple slots, each slot may support a reset mechanism
3678 * independent of other slots. For instance, some slots may support slot power
3679 * control. In the case of a 1:1 bus to slot architecture, this function may
3680 * wrap the bus reset to avoid spurious slot related events such as hotplug.
3681 * Generally a slot reset should be attempted before a bus reset. All of the
3682 * function of the slot and any subordinate buses behind the slot are reset
3683 * through this function. PCI config space of all devices in the slot and
3684 * behind the slot is saved before and restored after reset.
3686 * Return 0 on success, non-zero on error.
3688 int pci_reset_slot(struct pci_slot *slot)
3692 rc = pci_slot_reset(slot, 1);
3696 pci_slot_save_and_disable(slot);
3698 rc = pci_slot_reset(slot, 0);
3700 pci_slot_restore(slot);
3704 EXPORT_SYMBOL_GPL(pci_reset_slot);
3707 * pci_try_reset_slot - Try to reset a PCI slot
3708 * @slot: PCI slot to reset
3710 * Same as above except return -EAGAIN if the slot cannot be locked
3712 int pci_try_reset_slot(struct pci_slot *slot)
3716 rc = pci_slot_reset(slot, 1);
3720 pci_slot_save_and_disable(slot);
3722 if (pci_slot_trylock(slot)) {
3724 rc = pci_reset_hotplug_slot(slot->hotplug, 0);
3725 pci_slot_unlock(slot);
3729 pci_slot_restore(slot);
3733 EXPORT_SYMBOL_GPL(pci_try_reset_slot);
3735 static int pci_bus_reset(struct pci_bus *bus, int probe)
3747 pci_reset_bridge_secondary_bus(bus->self);
3749 pci_bus_unlock(bus);
3755 * pci_probe_reset_bus - probe whether a PCI bus can be reset
3756 * @bus: PCI bus to probe
3758 * Return 0 if bus can be reset, negative if a bus reset is not supported.
3760 int pci_probe_reset_bus(struct pci_bus *bus)
3762 return pci_bus_reset(bus, 1);
3764 EXPORT_SYMBOL_GPL(pci_probe_reset_bus);
3767 * pci_reset_bus - reset a PCI bus
3768 * @bus: top level PCI bus to reset
3770 * Do a bus reset on the given bus and any subordinate buses, saving
3771 * and restoring state of all devices.
3773 * Return 0 on success, non-zero on error.
3775 int pci_reset_bus(struct pci_bus *bus)
3779 rc = pci_bus_reset(bus, 1);
3783 pci_bus_save_and_disable(bus);
3785 rc = pci_bus_reset(bus, 0);
3787 pci_bus_restore(bus);
3791 EXPORT_SYMBOL_GPL(pci_reset_bus);
3794 * pci_try_reset_bus - Try to reset a PCI bus
3795 * @bus: top level PCI bus to reset
3797 * Same as above except return -EAGAIN if the bus cannot be locked
3799 int pci_try_reset_bus(struct pci_bus *bus)
3803 rc = pci_bus_reset(bus, 1);
3807 pci_bus_save_and_disable(bus);
3809 if (pci_bus_trylock(bus)) {
3811 pci_reset_bridge_secondary_bus(bus->self);
3812 pci_bus_unlock(bus);
3816 pci_bus_restore(bus);
3820 EXPORT_SYMBOL_GPL(pci_try_reset_bus);
3823 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
3824 * @dev: PCI device to query
3826 * Returns mmrbc: maximum designed memory read count in bytes
3827 * or appropriate error value.
3829 int pcix_get_max_mmrbc(struct pci_dev *dev)
3834 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
3838 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
3841 return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21);
3843 EXPORT_SYMBOL(pcix_get_max_mmrbc);
3846 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
3847 * @dev: PCI device to query
3849 * Returns mmrbc: maximum memory read count in bytes
3850 * or appropriate error value.
3852 int pcix_get_mmrbc(struct pci_dev *dev)
3857 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
3861 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
3864 return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
3866 EXPORT_SYMBOL(pcix_get_mmrbc);
3869 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
3870 * @dev: PCI device to query
3871 * @mmrbc: maximum memory read count in bytes
3872 * valid values are 512, 1024, 2048, 4096
3874 * If possible sets maximum memory read byte count, some bridges have erratas
3875 * that prevent this.
3877 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
3883 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
3886 v = ffs(mmrbc) - 10;
3888 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
3892 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
3895 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
3898 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
3901 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
3903 if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
3906 cmd &= ~PCI_X_CMD_MAX_READ;
3908 if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd))
3913 EXPORT_SYMBOL(pcix_set_mmrbc);
3916 * pcie_get_readrq - get PCI Express read request size
3917 * @dev: PCI device to query
3919 * Returns maximum memory read request in bytes
3920 * or appropriate error value.
3922 int pcie_get_readrq(struct pci_dev *dev)
3926 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
3928 return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
3930 EXPORT_SYMBOL(pcie_get_readrq);
3933 * pcie_set_readrq - set PCI Express maximum memory read request
3934 * @dev: PCI device to query
3935 * @rq: maximum memory read count in bytes
3936 * valid values are 128, 256, 512, 1024, 2048, 4096
3938 * If possible sets maximum memory read request in bytes
3940 int pcie_set_readrq(struct pci_dev *dev, int rq)
3944 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
3948 * If using the "performance" PCIe config, we clamp the
3949 * read rq size to the max packet size to prevent the
3950 * host bridge generating requests larger than we can
3953 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
3954 int mps = pcie_get_mps(dev);
3960 v = (ffs(rq) - 8) << 12;
3962 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
3963 PCI_EXP_DEVCTL_READRQ, v);
3965 EXPORT_SYMBOL(pcie_set_readrq);
3968 * pcie_get_mps - get PCI Express maximum payload size
3969 * @dev: PCI device to query
3971 * Returns maximum payload size in bytes
3973 int pcie_get_mps(struct pci_dev *dev)
3977 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
3979 return 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
3981 EXPORT_SYMBOL(pcie_get_mps);
3984 * pcie_set_mps - set PCI Express maximum payload size
3985 * @dev: PCI device to query
3986 * @mps: maximum payload size in bytes
3987 * valid values are 128, 256, 512, 1024, 2048, 4096
3989 * If possible sets maximum payload size
3991 int pcie_set_mps(struct pci_dev *dev, int mps)
3995 if (mps < 128 || mps > 4096 || !is_power_of_2(mps))
3999 if (v > dev->pcie_mpss)
4003 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
4004 PCI_EXP_DEVCTL_PAYLOAD, v);
4006 EXPORT_SYMBOL(pcie_set_mps);
4009 * pcie_get_minimum_link - determine minimum link settings of a PCI device
4010 * @dev: PCI device to query
4011 * @speed: storage for minimum speed
4012 * @width: storage for minimum width
4014 * This function will walk up the PCI device chain and determine the minimum
4015 * link width and speed of the device.
4017 int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed,
4018 enum pcie_link_width *width)
4022 *speed = PCI_SPEED_UNKNOWN;
4023 *width = PCIE_LNK_WIDTH_UNKNOWN;
4027 enum pci_bus_speed next_speed;
4028 enum pcie_link_width next_width;
4030 ret = pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta);
4034 next_speed = pcie_link_speed[lnksta & PCI_EXP_LNKSTA_CLS];
4035 next_width = (lnksta & PCI_EXP_LNKSTA_NLW) >>
4036 PCI_EXP_LNKSTA_NLW_SHIFT;
4038 if (next_speed < *speed)
4039 *speed = next_speed;
4041 if (next_width < *width)
4042 *width = next_width;
4044 dev = dev->bus->self;
4049 EXPORT_SYMBOL(pcie_get_minimum_link);
4052 * pci_select_bars - Make BAR mask from the type of resource
4053 * @dev: the PCI device for which BAR mask is made
4054 * @flags: resource type mask to be selected
4056 * This helper routine makes bar mask from the type of resource.
4058 int pci_select_bars(struct pci_dev *dev, unsigned long flags)
4061 for (i = 0; i < PCI_NUM_RESOURCES; i++)
4062 if (pci_resource_flags(dev, i) & flags)
4068 * pci_resource_bar - get position of the BAR associated with a resource
4069 * @dev: the PCI device
4070 * @resno: the resource number
4071 * @type: the BAR type to be filled in
4073 * Returns BAR position in config space, or 0 if the BAR is invalid.
4075 int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type)
4079 if (resno < PCI_ROM_RESOURCE) {
4080 *type = pci_bar_unknown;
4081 return PCI_BASE_ADDRESS_0 + 4 * resno;
4082 } else if (resno == PCI_ROM_RESOURCE) {
4083 *type = pci_bar_mem32;
4084 return dev->rom_base_reg;
4085 } else if (resno < PCI_BRIDGE_RESOURCES) {
4086 /* device specific resource */
4087 reg = pci_iov_resource_bar(dev, resno, type);
4092 dev_err(&dev->dev, "BAR %d: invalid resource\n", resno);
4096 /* Some architectures require additional programming to enable VGA */
4097 static arch_set_vga_state_t arch_set_vga_state;
4099 void __init pci_register_set_vga_state(arch_set_vga_state_t func)
4101 arch_set_vga_state = func; /* NULL disables */
4104 static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode,
4105 unsigned int command_bits, u32 flags)
4107 if (arch_set_vga_state)
4108 return arch_set_vga_state(dev, decode, command_bits,
4114 * pci_set_vga_state - set VGA decode state on device and parents if requested
4115 * @dev: the PCI device
4116 * @decode: true = enable decoding, false = disable decoding
4117 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
4118 * @flags: traverse ancestors and change bridges
4119 * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE
4121 int pci_set_vga_state(struct pci_dev *dev, bool decode,
4122 unsigned int command_bits, u32 flags)
4124 struct pci_bus *bus;
4125 struct pci_dev *bridge;
4129 WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) & (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY)));
4131 /* ARCH specific VGA enables */
4132 rc = pci_set_vga_state_arch(dev, decode, command_bits, flags);
4136 if (flags & PCI_VGA_STATE_CHANGE_DECODES) {
4137 pci_read_config_word(dev, PCI_COMMAND, &cmd);
4139 cmd |= command_bits;
4141 cmd &= ~command_bits;
4142 pci_write_config_word(dev, PCI_COMMAND, cmd);
4145 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
4152 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
4155 cmd |= PCI_BRIDGE_CTL_VGA;
4157 cmd &= ~PCI_BRIDGE_CTL_VGA;
4158 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL,
4166 bool pci_device_is_present(struct pci_dev *pdev)
4170 return pci_bus_read_dev_vendor_id(pdev->bus, pdev->devfn, &v, 0);
4172 EXPORT_SYMBOL_GPL(pci_device_is_present);
4174 #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
4175 static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0};
4176 static DEFINE_SPINLOCK(resource_alignment_lock);
4179 * pci_specified_resource_alignment - get resource alignment specified by user.
4180 * @dev: the PCI device to get
4182 * RETURNS: Resource alignment if it is specified.
4183 * Zero if it is not specified.
4185 static resource_size_t pci_specified_resource_alignment(struct pci_dev *dev)
4187 int seg, bus, slot, func, align_order, count;
4188 resource_size_t align = 0;
4191 spin_lock(&resource_alignment_lock);
4192 p = resource_alignment_param;
4195 if (sscanf(p, "%d%n", &align_order, &count) == 1 &&
4201 if (sscanf(p, "%x:%x:%x.%x%n",
4202 &seg, &bus, &slot, &func, &count) != 4) {
4204 if (sscanf(p, "%x:%x.%x%n",
4205 &bus, &slot, &func, &count) != 3) {
4206 /* Invalid format */
4207 printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: %s\n",
4213 if (seg == pci_domain_nr(dev->bus) &&
4214 bus == dev->bus->number &&
4215 slot == PCI_SLOT(dev->devfn) &&
4216 func == PCI_FUNC(dev->devfn)) {
4217 if (align_order == -1) {
4220 align = 1 << align_order;
4225 if (*p != ';' && *p != ',') {
4226 /* End of param or invalid format */
4231 spin_unlock(&resource_alignment_lock);
4236 * This function disables memory decoding and releases memory resources
4237 * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
4238 * It also rounds up size to specified alignment.
4239 * Later on, the kernel will assign page-aligned memory resource back
4242 void pci_reassigndev_resource_alignment(struct pci_dev *dev)
4246 resource_size_t align, size;
4249 /* check if specified PCI is target device to reassign */
4250 align = pci_specified_resource_alignment(dev);
4254 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
4255 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
4257 "Can't reassign resources to host bridge.\n");
4262 "Disabling memory decoding and releasing memory resources.\n");
4263 pci_read_config_word(dev, PCI_COMMAND, &command);
4264 command &= ~PCI_COMMAND_MEMORY;
4265 pci_write_config_word(dev, PCI_COMMAND, command);
4267 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) {
4268 r = &dev->resource[i];
4269 if (!(r->flags & IORESOURCE_MEM))
4271 size = resource_size(r);
4275 "Rounding up size of resource #%d to %#llx.\n",
4276 i, (unsigned long long)size);
4278 r->flags |= IORESOURCE_UNSET;
4282 /* Need to disable bridge's resource window,
4283 * to enable the kernel to reassign new resource
4286 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
4287 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
4288 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
4289 r = &dev->resource[i];
4290 if (!(r->flags & IORESOURCE_MEM))
4292 r->flags |= IORESOURCE_UNSET;
4293 r->end = resource_size(r) - 1;
4296 pci_disable_bridge_window(dev);
4300 static ssize_t pci_set_resource_alignment_param(const char *buf, size_t count)
4302 if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1)
4303 count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1;
4304 spin_lock(&resource_alignment_lock);
4305 strncpy(resource_alignment_param, buf, count);
4306 resource_alignment_param[count] = '\0';
4307 spin_unlock(&resource_alignment_lock);
4311 static ssize_t pci_get_resource_alignment_param(char *buf, size_t size)
4314 spin_lock(&resource_alignment_lock);
4315 count = snprintf(buf, size, "%s", resource_alignment_param);
4316 spin_unlock(&resource_alignment_lock);
4320 static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf)
4322 return pci_get_resource_alignment_param(buf, PAGE_SIZE);
4325 static ssize_t pci_resource_alignment_store(struct bus_type *bus,
4326 const char *buf, size_t count)
4328 return pci_set_resource_alignment_param(buf, count);
4331 BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show,
4332 pci_resource_alignment_store);
4334 static int __init pci_resource_alignment_sysfs_init(void)
4336 return bus_create_file(&pci_bus_type,
4337 &bus_attr_resource_alignment);
4340 late_initcall(pci_resource_alignment_sysfs_init);
4342 static void pci_no_domains(void)
4344 #ifdef CONFIG_PCI_DOMAINS
4345 pci_domains_supported = 0;
4350 * pci_ext_cfg_avail - can we access extended PCI config space?
4352 * Returns 1 if we can access PCI extended config space (offsets
4353 * greater than 0xff). This is the default implementation. Architecture
4354 * implementations can override this.
4356 int __weak pci_ext_cfg_avail(void)
4361 void __weak pci_fixup_cardbus(struct pci_bus *bus)
4364 EXPORT_SYMBOL(pci_fixup_cardbus);
4366 static int __init pci_setup(char *str)
4369 char *k = strchr(str, ',');
4372 if (*str && (str = pcibios_setup(str)) && *str) {
4373 if (!strcmp(str, "nomsi")) {
4375 } else if (!strcmp(str, "noaer")) {
4377 } else if (!strncmp(str, "realloc=", 8)) {
4378 pci_realloc_get_opt(str + 8);
4379 } else if (!strncmp(str, "realloc", 7)) {
4380 pci_realloc_get_opt("on");
4381 } else if (!strcmp(str, "nodomains")) {
4383 } else if (!strncmp(str, "noari", 5)) {
4384 pcie_ari_disabled = true;
4385 } else if (!strncmp(str, "cbiosize=", 9)) {
4386 pci_cardbus_io_size = memparse(str + 9, &str);
4387 } else if (!strncmp(str, "cbmemsize=", 10)) {
4388 pci_cardbus_mem_size = memparse(str + 10, &str);
4389 } else if (!strncmp(str, "resource_alignment=", 19)) {
4390 pci_set_resource_alignment_param(str + 19,
4392 } else if (!strncmp(str, "ecrc=", 5)) {
4393 pcie_ecrc_get_policy(str + 5);
4394 } else if (!strncmp(str, "hpiosize=", 9)) {
4395 pci_hotplug_io_size = memparse(str + 9, &str);
4396 } else if (!strncmp(str, "hpmemsize=", 10)) {
4397 pci_hotplug_mem_size = memparse(str + 10, &str);
4398 } else if (!strncmp(str, "pcie_bus_tune_off", 17)) {
4399 pcie_bus_config = PCIE_BUS_TUNE_OFF;
4400 } else if (!strncmp(str, "pcie_bus_safe", 13)) {
4401 pcie_bus_config = PCIE_BUS_SAFE;
4402 } else if (!strncmp(str, "pcie_bus_perf", 13)) {
4403 pcie_bus_config = PCIE_BUS_PERFORMANCE;
4404 } else if (!strncmp(str, "pcie_bus_peer2peer", 18)) {
4405 pcie_bus_config = PCIE_BUS_PEER2PEER;
4406 } else if (!strncmp(str, "pcie_scan_all", 13)) {
4407 pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS);
4409 printk(KERN_ERR "PCI: Unknown option `%s'\n",
4417 early_param("pci", pci_setup);
4419 EXPORT_SYMBOL(pci_reenable_device);
4420 EXPORT_SYMBOL(pci_enable_device_io);
4421 EXPORT_SYMBOL(pci_enable_device_mem);
4422 EXPORT_SYMBOL(pci_enable_device);
4423 EXPORT_SYMBOL(pcim_enable_device);
4424 EXPORT_SYMBOL(pcim_pin_device);
4425 EXPORT_SYMBOL(pci_disable_device);
4426 EXPORT_SYMBOL(pci_find_capability);
4427 EXPORT_SYMBOL(pci_bus_find_capability);
4428 EXPORT_SYMBOL(pci_release_regions);
4429 EXPORT_SYMBOL(pci_request_regions);
4430 EXPORT_SYMBOL(pci_request_regions_exclusive);
4431 EXPORT_SYMBOL(pci_release_region);
4432 EXPORT_SYMBOL(pci_request_region);
4433 EXPORT_SYMBOL(pci_request_region_exclusive);
4434 EXPORT_SYMBOL(pci_release_selected_regions);
4435 EXPORT_SYMBOL(pci_request_selected_regions);
4436 EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
4437 EXPORT_SYMBOL(pci_set_master);
4438 EXPORT_SYMBOL(pci_clear_master);
4439 EXPORT_SYMBOL(pci_set_mwi);
4440 EXPORT_SYMBOL(pci_try_set_mwi);
4441 EXPORT_SYMBOL(pci_clear_mwi);
4442 EXPORT_SYMBOL_GPL(pci_intx);
4443 EXPORT_SYMBOL(pci_assign_resource);
4444 EXPORT_SYMBOL(pci_find_parent_resource);
4445 EXPORT_SYMBOL(pci_select_bars);
4447 EXPORT_SYMBOL(pci_set_power_state);
4448 EXPORT_SYMBOL(pci_save_state);
4449 EXPORT_SYMBOL(pci_restore_state);
4450 EXPORT_SYMBOL(pci_pme_capable);
4451 EXPORT_SYMBOL(pci_pme_active);
4452 EXPORT_SYMBOL(pci_wake_from_d3);
4453 EXPORT_SYMBOL(pci_prepare_to_sleep);
4454 EXPORT_SYMBOL(pci_back_from_sleep);
4455 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);