2 * PCI Bus Services, see include/linux/pci.h for further explanation.
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
10 #include <linux/kernel.h>
11 #include <linux/delay.h>
12 #include <linux/init.h>
13 #include <linux/pci.h>
15 #include <linux/module.h>
16 #include <linux/spinlock.h>
17 #include <linux/string.h>
18 #include <linux/log2.h>
19 #include <linux/pci-aspm.h>
20 #include <linux/pm_wakeup.h>
21 #include <linux/interrupt.h>
22 #include <asm/dma.h> /* isa_dma_bridge_buggy */
23 #include <linux/device.h>
24 #include <asm/setup.h>
27 const char *pci_power_names[] = {
28 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
30 EXPORT_SYMBOL_GPL(pci_power_names);
32 unsigned int pci_pm_d3_delay = PCI_PM_D3_WAIT;
34 #ifdef CONFIG_PCI_DOMAINS
35 int pci_domains_supported = 1;
38 #define DEFAULT_CARDBUS_IO_SIZE (256)
39 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
40 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
41 unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
42 unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
44 #define DEFAULT_HOTPLUG_IO_SIZE (256)
45 #define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024)
46 /* pci=hpmemsize=nnM,hpiosize=nn can override this */
47 unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE;
48 unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE;
51 * The default CLS is used if arch didn't set CLS explicitly and not
52 * all pci devices agree on the same value. Arch can override either
53 * the dfl or actual value as it sees fit. Don't forget this is
54 * measured in 32-bit words, not bytes.
56 u8 pci_dfl_cache_line_size __devinitdata = L1_CACHE_BYTES >> 2;
57 u8 pci_cache_line_size;
60 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
61 * @bus: pointer to PCI bus structure to search
63 * Given a PCI bus, returns the highest PCI bus number present in the set
64 * including the given PCI bus and its list of child PCI buses.
66 unsigned char pci_bus_max_busnr(struct pci_bus* bus)
68 struct list_head *tmp;
71 max = bus->subordinate;
72 list_for_each(tmp, &bus->children) {
73 n = pci_bus_max_busnr(pci_bus_b(tmp));
79 EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
81 #ifdef CONFIG_HAS_IOMEM
82 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
85 * Make sure the BAR is actually a memory resource, not an IO resource
87 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
91 return ioremap_nocache(pci_resource_start(pdev, bar),
92 pci_resource_len(pdev, bar));
94 EXPORT_SYMBOL_GPL(pci_ioremap_bar);
99 * pci_max_busnr - returns maximum PCI bus number
101 * Returns the highest PCI bus number present in the system global list of
104 unsigned char __devinit
107 struct pci_bus *bus = NULL;
108 unsigned char max, n;
111 while ((bus = pci_find_next_bus(bus)) != NULL) {
112 n = pci_bus_max_busnr(bus);
121 #define PCI_FIND_CAP_TTL 48
123 static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
124 u8 pos, int cap, int *ttl)
129 pci_bus_read_config_byte(bus, devfn, pos, &pos);
133 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID,
139 pos += PCI_CAP_LIST_NEXT;
144 static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
147 int ttl = PCI_FIND_CAP_TTL;
149 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
152 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
154 return __pci_find_next_cap(dev->bus, dev->devfn,
155 pos + PCI_CAP_LIST_NEXT, cap);
157 EXPORT_SYMBOL_GPL(pci_find_next_capability);
159 static int __pci_bus_find_cap_start(struct pci_bus *bus,
160 unsigned int devfn, u8 hdr_type)
164 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
165 if (!(status & PCI_STATUS_CAP_LIST))
169 case PCI_HEADER_TYPE_NORMAL:
170 case PCI_HEADER_TYPE_BRIDGE:
171 return PCI_CAPABILITY_LIST;
172 case PCI_HEADER_TYPE_CARDBUS:
173 return PCI_CB_CAPABILITY_LIST;
182 * pci_find_capability - query for devices' capabilities
183 * @dev: PCI device to query
184 * @cap: capability code
186 * Tell if a device supports a given PCI capability.
187 * Returns the address of the requested capability structure within the
188 * device's PCI configuration space or 0 in case the device does not
189 * support it. Possible values for @cap:
191 * %PCI_CAP_ID_PM Power Management
192 * %PCI_CAP_ID_AGP Accelerated Graphics Port
193 * %PCI_CAP_ID_VPD Vital Product Data
194 * %PCI_CAP_ID_SLOTID Slot Identification
195 * %PCI_CAP_ID_MSI Message Signalled Interrupts
196 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
197 * %PCI_CAP_ID_PCIX PCI-X
198 * %PCI_CAP_ID_EXP PCI Express
200 int pci_find_capability(struct pci_dev *dev, int cap)
204 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
206 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
212 * pci_bus_find_capability - query for devices' capabilities
213 * @bus: the PCI bus to query
214 * @devfn: PCI device to query
215 * @cap: capability code
217 * Like pci_find_capability() but works for pci devices that do not have a
218 * pci_dev structure set up yet.
220 * Returns the address of the requested capability structure within the
221 * device's PCI configuration space or 0 in case the device does not
224 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
229 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
231 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
233 pos = __pci_find_next_cap(bus, devfn, pos, cap);
239 * pci_find_ext_capability - Find an extended capability
240 * @dev: PCI device to query
241 * @cap: capability code
243 * Returns the address of the requested extended capability structure
244 * within the device's PCI configuration space or 0 if the device does
245 * not support it. Possible values for @cap:
247 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
248 * %PCI_EXT_CAP_ID_VC Virtual Channel
249 * %PCI_EXT_CAP_ID_DSN Device Serial Number
250 * %PCI_EXT_CAP_ID_PWR Power Budgeting
252 int pci_find_ext_capability(struct pci_dev *dev, int cap)
256 int pos = PCI_CFG_SPACE_SIZE;
258 /* minimum 8 bytes per capability */
259 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
261 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
264 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
268 * If we have no capabilities, this is indicated by cap ID,
269 * cap version and next pointer all being 0.
275 if (PCI_EXT_CAP_ID(header) == cap)
278 pos = PCI_EXT_CAP_NEXT(header);
279 if (pos < PCI_CFG_SPACE_SIZE)
282 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
288 EXPORT_SYMBOL_GPL(pci_find_ext_capability);
290 static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
292 int rc, ttl = PCI_FIND_CAP_TTL;
295 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
296 mask = HT_3BIT_CAP_MASK;
298 mask = HT_5BIT_CAP_MASK;
300 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
301 PCI_CAP_ID_HT, &ttl);
303 rc = pci_read_config_byte(dev, pos + 3, &cap);
304 if (rc != PCIBIOS_SUCCESSFUL)
307 if ((cap & mask) == ht_cap)
310 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
311 pos + PCI_CAP_LIST_NEXT,
312 PCI_CAP_ID_HT, &ttl);
318 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
319 * @dev: PCI device to query
320 * @pos: Position from which to continue searching
321 * @ht_cap: Hypertransport capability code
323 * To be used in conjunction with pci_find_ht_capability() to search for
324 * all capabilities matching @ht_cap. @pos should always be a value returned
325 * from pci_find_ht_capability().
327 * NB. To be 100% safe against broken PCI devices, the caller should take
328 * steps to avoid an infinite loop.
330 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
332 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
334 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
337 * pci_find_ht_capability - query a device's Hypertransport capabilities
338 * @dev: PCI device to query
339 * @ht_cap: Hypertransport capability code
341 * Tell if a device supports a given Hypertransport capability.
342 * Returns an address within the device's PCI configuration space
343 * or 0 in case the device does not support the request capability.
344 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
345 * which has a Hypertransport capability matching @ht_cap.
347 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
351 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
353 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
357 EXPORT_SYMBOL_GPL(pci_find_ht_capability);
360 * pci_find_parent_resource - return resource region of parent bus of given region
361 * @dev: PCI device structure contains resources to be searched
362 * @res: child resource record for which parent is sought
364 * For given resource region of given device, return the resource
365 * region of parent bus the given region is contained in or where
366 * it should be allocated from.
369 pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
371 const struct pci_bus *bus = dev->bus;
373 struct resource *best = NULL;
375 for(i = 0; i < PCI_BUS_NUM_RESOURCES; i++) {
376 struct resource *r = bus->resource[i];
379 if (res->start && !(res->start >= r->start && res->end <= r->end))
380 continue; /* Not contained */
381 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
382 continue; /* Wrong type */
383 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH))
384 return r; /* Exact match */
385 if ((res->flags & IORESOURCE_PREFETCH) && !(r->flags & IORESOURCE_PREFETCH))
386 best = r; /* Approximating prefetchable by non-prefetchable */
392 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
393 * @dev: PCI device to have its BARs restored
395 * Restore the BAR values for a given device, so as to make it
396 * accessible by its driver.
399 pci_restore_bars(struct pci_dev *dev)
403 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
404 pci_update_resource(dev, i);
407 static struct pci_platform_pm_ops *pci_platform_pm;
409 int pci_set_platform_pm(struct pci_platform_pm_ops *ops)
411 if (!ops->is_manageable || !ops->set_state || !ops->choose_state
412 || !ops->sleep_wake || !ops->can_wakeup)
414 pci_platform_pm = ops;
418 static inline bool platform_pci_power_manageable(struct pci_dev *dev)
420 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
423 static inline int platform_pci_set_power_state(struct pci_dev *dev,
426 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
429 static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
431 return pci_platform_pm ?
432 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
435 static inline bool platform_pci_can_wakeup(struct pci_dev *dev)
437 return pci_platform_pm ? pci_platform_pm->can_wakeup(dev) : false;
440 static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable)
442 return pci_platform_pm ?
443 pci_platform_pm->sleep_wake(dev, enable) : -ENODEV;
447 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
449 * @dev: PCI device to handle.
450 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
453 * -EINVAL if the requested state is invalid.
454 * -EIO if device does not support PCI PM or its PM capabilities register has a
455 * wrong version, or device doesn't support the requested state.
456 * 0 if device already is in the requested state.
457 * 0 if device's power state has been successfully changed.
459 static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
462 bool need_restore = false;
464 /* Check if we're already there */
465 if (dev->current_state == state)
471 if (state < PCI_D0 || state > PCI_D3hot)
474 /* Validate current state:
475 * Can enter D0 from any state, but if we can only go deeper
476 * to sleep if we're already in a low power state
478 if (state != PCI_D0 && dev->current_state <= PCI_D3cold
479 && dev->current_state > state) {
480 dev_err(&dev->dev, "invalid power transition "
481 "(from state %d to %d)\n", dev->current_state, state);
485 /* check if this device supports the desired state */
486 if ((state == PCI_D1 && !dev->d1_support)
487 || (state == PCI_D2 && !dev->d2_support))
490 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
492 /* If we're (effectively) in D3, force entire word to 0.
493 * This doesn't affect PME_Status, disables PME_En, and
494 * sets PowerState to 0.
496 switch (dev->current_state) {
500 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
505 case PCI_UNKNOWN: /* Boot-up */
506 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
507 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
509 /* Fall-through: force to D0 */
515 /* enter specified state */
516 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
518 /* Mandatory power management transition delays */
519 /* see PCI PM 1.1 5.6.1 table 18 */
520 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
521 msleep(pci_pm_d3_delay);
522 else if (state == PCI_D2 || dev->current_state == PCI_D2)
523 udelay(PCI_PM_D2_DELAY);
525 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
526 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
527 if (dev->current_state != state && printk_ratelimit())
528 dev_info(&dev->dev, "Refused to change power state, "
529 "currently in D%d\n", dev->current_state);
531 /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
532 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
533 * from D3hot to D0 _may_ perform an internal reset, thereby
534 * going to "D0 Uninitialized" rather than "D0 Initialized".
535 * For example, at least some versions of the 3c905B and the
536 * 3c556B exhibit this behaviour.
538 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
539 * devices in a D3hot state at boot. Consequently, we need to
540 * restore at least the BARs so that the device will be
541 * accessible to its driver.
544 pci_restore_bars(dev);
547 pcie_aspm_pm_state_change(dev->bus->self);
553 * pci_update_current_state - Read PCI power state of given device from its
554 * PCI PM registers and cache it
555 * @dev: PCI device to handle.
556 * @state: State to cache in case the device doesn't have the PM capability
558 void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
563 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
564 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
566 dev->current_state = state;
571 * pci_platform_power_transition - Use platform to change device power state
572 * @dev: PCI device to handle.
573 * @state: State to put the device into.
575 static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
579 if (platform_pci_power_manageable(dev)) {
580 error = platform_pci_set_power_state(dev, state);
582 pci_update_current_state(dev, state);
585 /* Fall back to PCI_D0 if native PM is not supported */
587 dev->current_state = PCI_D0;
594 * __pci_start_power_transition - Start power transition of a PCI device
595 * @dev: PCI device to handle.
596 * @state: State to put the device into.
598 static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state)
601 pci_platform_power_transition(dev, PCI_D0);
605 * __pci_complete_power_transition - Complete power transition of a PCI device
606 * @dev: PCI device to handle.
607 * @state: State to put the device into.
609 * This function should not be called directly by device drivers.
611 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state)
613 return state > PCI_D0 ?
614 pci_platform_power_transition(dev, state) : -EINVAL;
616 EXPORT_SYMBOL_GPL(__pci_complete_power_transition);
619 * pci_set_power_state - Set the power state of a PCI device
620 * @dev: PCI device to handle.
621 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
623 * Transition a device to a new power state, using the platform firmware and/or
624 * the device's PCI PM registers.
627 * -EINVAL if the requested state is invalid.
628 * -EIO if device does not support PCI PM or its PM capabilities register has a
629 * wrong version, or device doesn't support the requested state.
630 * 0 if device already is in the requested state.
631 * 0 if device's power state has been successfully changed.
633 int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
637 /* bound the state we're entering */
638 if (state > PCI_D3hot)
640 else if (state < PCI_D0)
642 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
644 * If the device or the parent bridge do not support PCI PM,
645 * ignore the request if we're doing anything other than putting
646 * it into D0 (which would only happen on boot).
650 /* Check if we're already there */
651 if (dev->current_state == state)
654 __pci_start_power_transition(dev, state);
656 /* This device is quirked not to be put into D3, so
657 don't put it in D3 */
658 if (state == PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
661 error = pci_raw_set_power_state(dev, state);
663 if (!__pci_complete_power_transition(dev, state))
670 * pci_choose_state - Choose the power state of a PCI device
671 * @dev: PCI device to be suspended
672 * @state: target sleep state for the whole system. This is the value
673 * that is passed to suspend() function.
675 * Returns PCI power state suitable for given device and given system
679 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
683 if (!pci_find_capability(dev, PCI_CAP_ID_PM))
686 ret = platform_pci_choose_state(dev);
687 if (ret != PCI_POWER_ERROR)
690 switch (state.event) {
693 case PM_EVENT_FREEZE:
694 case PM_EVENT_PRETHAW:
695 /* REVISIT both freeze and pre-thaw "should" use D0 */
696 case PM_EVENT_SUSPEND:
697 case PM_EVENT_HIBERNATE:
700 dev_info(&dev->dev, "unrecognized suspend event %d\n",
707 EXPORT_SYMBOL(pci_choose_state);
709 #define PCI_EXP_SAVE_REGS 7
711 #define pcie_cap_has_devctl(type, flags) 1
712 #define pcie_cap_has_lnkctl(type, flags) \
713 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
714 (type == PCI_EXP_TYPE_ROOT_PORT || \
715 type == PCI_EXP_TYPE_ENDPOINT || \
716 type == PCI_EXP_TYPE_LEG_END))
717 #define pcie_cap_has_sltctl(type, flags) \
718 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
719 ((type == PCI_EXP_TYPE_ROOT_PORT) || \
720 (type == PCI_EXP_TYPE_DOWNSTREAM && \
721 (flags & PCI_EXP_FLAGS_SLOT))))
722 #define pcie_cap_has_rtctl(type, flags) \
723 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
724 (type == PCI_EXP_TYPE_ROOT_PORT || \
725 type == PCI_EXP_TYPE_RC_EC))
726 #define pcie_cap_has_devctl2(type, flags) \
727 ((flags & PCI_EXP_FLAGS_VERS) > 1)
728 #define pcie_cap_has_lnkctl2(type, flags) \
729 ((flags & PCI_EXP_FLAGS_VERS) > 1)
730 #define pcie_cap_has_sltctl2(type, flags) \
731 ((flags & PCI_EXP_FLAGS_VERS) > 1)
733 static int pci_save_pcie_state(struct pci_dev *dev)
736 struct pci_cap_saved_state *save_state;
740 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
744 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
746 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
749 cap = (u16 *)&save_state->data[0];
751 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);
753 if (pcie_cap_has_devctl(dev->pcie_type, flags))
754 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &cap[i++]);
755 if (pcie_cap_has_lnkctl(dev->pcie_type, flags))
756 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]);
757 if (pcie_cap_has_sltctl(dev->pcie_type, flags))
758 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]);
759 if (pcie_cap_has_rtctl(dev->pcie_type, flags))
760 pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]);
761 if (pcie_cap_has_devctl2(dev->pcie_type, flags))
762 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &cap[i++]);
763 if (pcie_cap_has_lnkctl2(dev->pcie_type, flags))
764 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL2, &cap[i++]);
765 if (pcie_cap_has_sltctl2(dev->pcie_type, flags))
766 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL2, &cap[i++]);
771 static void pci_restore_pcie_state(struct pci_dev *dev)
774 struct pci_cap_saved_state *save_state;
778 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
779 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
780 if (!save_state || pos <= 0)
782 cap = (u16 *)&save_state->data[0];
784 pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);
786 if (pcie_cap_has_devctl(dev->pcie_type, flags))
787 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, cap[i++]);
788 if (pcie_cap_has_lnkctl(dev->pcie_type, flags))
789 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL, cap[i++]);
790 if (pcie_cap_has_sltctl(dev->pcie_type, flags))
791 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL, cap[i++]);
792 if (pcie_cap_has_rtctl(dev->pcie_type, flags))
793 pci_write_config_word(dev, pos + PCI_EXP_RTCTL, cap[i++]);
794 if (pcie_cap_has_devctl2(dev->pcie_type, flags))
795 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, cap[i++]);
796 if (pcie_cap_has_lnkctl2(dev->pcie_type, flags))
797 pci_write_config_word(dev, pos + PCI_EXP_LNKCTL2, cap[i++]);
798 if (pcie_cap_has_sltctl2(dev->pcie_type, flags))
799 pci_write_config_word(dev, pos + PCI_EXP_SLTCTL2, cap[i++]);
803 static int pci_save_pcix_state(struct pci_dev *dev)
806 struct pci_cap_saved_state *save_state;
808 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
812 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
814 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
818 pci_read_config_word(dev, pos + PCI_X_CMD, (u16 *)save_state->data);
823 static void pci_restore_pcix_state(struct pci_dev *dev)
826 struct pci_cap_saved_state *save_state;
829 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
830 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
831 if (!save_state || pos <= 0)
833 cap = (u16 *)&save_state->data[0];
835 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
840 * pci_save_state - save the PCI configuration space of a device before suspending
841 * @dev: - PCI device that we're dealing with
844 pci_save_state(struct pci_dev *dev)
847 /* XXX: 100% dword access ok here? */
848 for (i = 0; i < 16; i++)
849 pci_read_config_dword(dev, i * 4,&dev->saved_config_space[i]);
850 dev->state_saved = true;
851 if ((i = pci_save_pcie_state(dev)) != 0)
853 if ((i = pci_save_pcix_state(dev)) != 0)
859 * pci_restore_state - Restore the saved state of a PCI device
860 * @dev: - PCI device that we're dealing with
863 pci_restore_state(struct pci_dev *dev)
868 if (!dev->state_saved)
871 /* PCI Express register must be restored first */
872 pci_restore_pcie_state(dev);
875 * The Base Address register should be programmed before the command
878 for (i = 15; i >= 0; i--) {
879 pci_read_config_dword(dev, i * 4, &val);
880 if (val != dev->saved_config_space[i]) {
881 dev_printk(KERN_DEBUG, &dev->dev, "restoring config "
882 "space at offset %#x (was %#x, writing %#x)\n",
883 i, val, (int)dev->saved_config_space[i]);
884 pci_write_config_dword(dev,i * 4,
885 dev->saved_config_space[i]);
888 pci_restore_pcix_state(dev);
889 pci_restore_msi_state(dev);
890 pci_restore_iov_state(dev);
892 dev->state_saved = false;
897 static int do_pci_enable_device(struct pci_dev *dev, int bars)
901 err = pci_set_power_state(dev, PCI_D0);
902 if (err < 0 && err != -EIO)
904 err = pcibios_enable_device(dev, bars);
907 pci_fixup_device(pci_fixup_enable, dev);
913 * pci_reenable_device - Resume abandoned device
914 * @dev: PCI device to be resumed
916 * Note this function is a backend of pci_default_resume and is not supposed
917 * to be called by normal code, write proper resume handler and use it instead.
919 int pci_reenable_device(struct pci_dev *dev)
921 if (pci_is_enabled(dev))
922 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
926 static int __pci_enable_device_flags(struct pci_dev *dev,
927 resource_size_t flags)
932 if (atomic_add_return(1, &dev->enable_cnt) > 1)
933 return 0; /* already enabled */
935 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
936 if (dev->resource[i].flags & flags)
939 err = do_pci_enable_device(dev, bars);
941 atomic_dec(&dev->enable_cnt);
946 * pci_enable_device_io - Initialize a device for use with IO space
947 * @dev: PCI device to be initialized
949 * Initialize device before it's used by a driver. Ask low-level code
950 * to enable I/O resources. Wake up the device if it was suspended.
951 * Beware, this function can fail.
953 int pci_enable_device_io(struct pci_dev *dev)
955 return __pci_enable_device_flags(dev, IORESOURCE_IO);
959 * pci_enable_device_mem - Initialize a device for use with Memory space
960 * @dev: PCI device to be initialized
962 * Initialize device before it's used by a driver. Ask low-level code
963 * to enable Memory resources. Wake up the device if it was suspended.
964 * Beware, this function can fail.
966 int pci_enable_device_mem(struct pci_dev *dev)
968 return __pci_enable_device_flags(dev, IORESOURCE_MEM);
972 * pci_enable_device - Initialize device before it's used by a driver.
973 * @dev: PCI device to be initialized
975 * Initialize device before it's used by a driver. Ask low-level code
976 * to enable I/O and memory. Wake up the device if it was suspended.
977 * Beware, this function can fail.
979 * Note we don't actually enable the device many times if we call
980 * this function repeatedly (we just increment the count).
982 int pci_enable_device(struct pci_dev *dev)
984 return __pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
988 * Managed PCI resources. This manages device on/off, intx/msi/msix
989 * on/off and BAR regions. pci_dev itself records msi/msix status, so
990 * there's no need to track it separately. pci_devres is initialized
991 * when a device is enabled using managed PCI device enable interface.
994 unsigned int enabled:1;
995 unsigned int pinned:1;
996 unsigned int orig_intx:1;
997 unsigned int restore_intx:1;
1001 static void pcim_release(struct device *gendev, void *res)
1003 struct pci_dev *dev = container_of(gendev, struct pci_dev, dev);
1004 struct pci_devres *this = res;
1007 if (dev->msi_enabled)
1008 pci_disable_msi(dev);
1009 if (dev->msix_enabled)
1010 pci_disable_msix(dev);
1012 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
1013 if (this->region_mask & (1 << i))
1014 pci_release_region(dev, i);
1016 if (this->restore_intx)
1017 pci_intx(dev, this->orig_intx);
1019 if (this->enabled && !this->pinned)
1020 pci_disable_device(dev);
1023 static struct pci_devres * get_pci_dr(struct pci_dev *pdev)
1025 struct pci_devres *dr, *new_dr;
1027 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
1031 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
1034 return devres_get(&pdev->dev, new_dr, NULL, NULL);
1037 static struct pci_devres * find_pci_dr(struct pci_dev *pdev)
1039 if (pci_is_managed(pdev))
1040 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
1045 * pcim_enable_device - Managed pci_enable_device()
1046 * @pdev: PCI device to be initialized
1048 * Managed pci_enable_device().
1050 int pcim_enable_device(struct pci_dev *pdev)
1052 struct pci_devres *dr;
1055 dr = get_pci_dr(pdev);
1061 rc = pci_enable_device(pdev);
1063 pdev->is_managed = 1;
1070 * pcim_pin_device - Pin managed PCI device
1071 * @pdev: PCI device to pin
1073 * Pin managed PCI device @pdev. Pinned device won't be disabled on
1074 * driver detach. @pdev must have been enabled with
1075 * pcim_enable_device().
1077 void pcim_pin_device(struct pci_dev *pdev)
1079 struct pci_devres *dr;
1081 dr = find_pci_dr(pdev);
1082 WARN_ON(!dr || !dr->enabled);
1088 * pcibios_disable_device - disable arch specific PCI resources for device dev
1089 * @dev: the PCI device to disable
1091 * Disables architecture specific PCI resources for the device. This
1092 * is the default implementation. Architecture implementations can
1095 void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {}
1097 static void do_pci_disable_device(struct pci_dev *dev)
1101 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
1102 if (pci_command & PCI_COMMAND_MASTER) {
1103 pci_command &= ~PCI_COMMAND_MASTER;
1104 pci_write_config_word(dev, PCI_COMMAND, pci_command);
1107 pcibios_disable_device(dev);
1111 * pci_disable_enabled_device - Disable device without updating enable_cnt
1112 * @dev: PCI device to disable
1114 * NOTE: This function is a backend of PCI power management routines and is
1115 * not supposed to be called drivers.
1117 void pci_disable_enabled_device(struct pci_dev *dev)
1119 if (pci_is_enabled(dev))
1120 do_pci_disable_device(dev);
1124 * pci_disable_device - Disable PCI device after use
1125 * @dev: PCI device to be disabled
1127 * Signal to the system that the PCI device is not in use by the system
1128 * anymore. This only involves disabling PCI bus-mastering, if active.
1130 * Note we don't actually disable the device until all callers of
1131 * pci_device_enable() have called pci_device_disable().
1134 pci_disable_device(struct pci_dev *dev)
1136 struct pci_devres *dr;
1138 dr = find_pci_dr(dev);
1142 if (atomic_sub_return(1, &dev->enable_cnt) != 0)
1145 do_pci_disable_device(dev);
1147 dev->is_busmaster = 0;
1151 * pcibios_set_pcie_reset_state - set reset state for device dev
1152 * @dev: the PCI-E device reset
1153 * @state: Reset state to enter into
1156 * Sets the PCI-E reset state for the device. This is the default
1157 * implementation. Architecture implementations can override this.
1159 int __attribute__ ((weak)) pcibios_set_pcie_reset_state(struct pci_dev *dev,
1160 enum pcie_reset_state state)
1166 * pci_set_pcie_reset_state - set reset state for device dev
1167 * @dev: the PCI-E device reset
1168 * @state: Reset state to enter into
1171 * Sets the PCI reset state for the device.
1173 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
1175 return pcibios_set_pcie_reset_state(dev, state);
1179 * pci_pme_capable - check the capability of PCI device to generate PME#
1180 * @dev: PCI device to handle.
1181 * @state: PCI state from which device will issue PME#.
1183 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
1188 return !!(dev->pme_support & (1 << state));
1192 * pci_pme_active - enable or disable PCI device's PME# function
1193 * @dev: PCI device to handle.
1194 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1196 * The caller must verify that the device is capable of generating PME# before
1197 * calling this function with @enable equal to 'true'.
1199 void pci_pme_active(struct pci_dev *dev, bool enable)
1206 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1207 /* Clear PME_Status by writing 1 to it and enable PME# */
1208 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
1210 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1212 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1214 dev_printk(KERN_INFO, &dev->dev, "PME# %s\n",
1215 enable ? "enabled" : "disabled");
1219 * pci_enable_wake - enable PCI device as wakeup event source
1220 * @dev: PCI device affected
1221 * @state: PCI state from which device will issue wakeup events
1222 * @enable: True to enable event generation; false to disable
1224 * This enables the device as a wakeup event source, or disables it.
1225 * When such events involves platform-specific hooks, those hooks are
1226 * called automatically by this routine.
1228 * Devices with legacy power management (no standard PCI PM capabilities)
1229 * always require such platform hooks.
1232 * 0 is returned on success
1233 * -EINVAL is returned if device is not supposed to wake up the system
1234 * Error code depending on the platform is returned if both the platform and
1235 * the native mechanism fail to enable the generation of wake-up events
1237 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable)
1241 if (enable && !device_may_wakeup(&dev->dev))
1244 /* Don't do the same thing twice in a row for one device. */
1245 if (!!enable == !!dev->wakeup_prepared)
1249 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1250 * Anderson we should be doing PME# wake enable followed by ACPI wake
1251 * enable. To disable wake-up we call the platform first, for symmetry.
1257 if (pci_pme_capable(dev, state))
1258 pci_pme_active(dev, true);
1261 error = platform_pci_sleep_wake(dev, true);
1265 dev->wakeup_prepared = true;
1267 platform_pci_sleep_wake(dev, false);
1268 pci_pme_active(dev, false);
1269 dev->wakeup_prepared = false;
1276 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
1277 * @dev: PCI device to prepare
1278 * @enable: True to enable wake-up event generation; false to disable
1280 * Many drivers want the device to wake up the system from D3_hot or D3_cold
1281 * and this function allows them to set that up cleanly - pci_enable_wake()
1282 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
1283 * ordering constraints.
1285 * This function only returns error code if the device is not capable of
1286 * generating PME# from both D3_hot and D3_cold, and the platform is unable to
1287 * enable wake-up power for it.
1289 int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1291 return pci_pme_capable(dev, PCI_D3cold) ?
1292 pci_enable_wake(dev, PCI_D3cold, enable) :
1293 pci_enable_wake(dev, PCI_D3hot, enable);
1297 * pci_target_state - find an appropriate low power state for a given PCI dev
1300 * Use underlying platform code to find a supported low power state for @dev.
1301 * If the platform can't manage @dev, return the deepest state from which it
1302 * can generate wake events, based on any available PME info.
1304 pci_power_t pci_target_state(struct pci_dev *dev)
1306 pci_power_t target_state = PCI_D3hot;
1308 if (platform_pci_power_manageable(dev)) {
1310 * Call the platform to choose the target state of the device
1311 * and enable wake-up from this state if supported.
1313 pci_power_t state = platform_pci_choose_state(dev);
1316 case PCI_POWER_ERROR:
1321 if (pci_no_d1d2(dev))
1324 target_state = state;
1326 } else if (!dev->pm_cap) {
1327 target_state = PCI_D0;
1328 } else if (device_may_wakeup(&dev->dev)) {
1330 * Find the deepest state from which the device can generate
1331 * wake-up events, make it the target state and enable device
1334 if (dev->pme_support) {
1336 && !(dev->pme_support & (1 << target_state)))
1341 return target_state;
1345 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
1346 * @dev: Device to handle.
1348 * Choose the power state appropriate for the device depending on whether
1349 * it can wake up the system and/or is power manageable by the platform
1350 * (PCI_D3hot is the default) and put the device into that state.
1352 int pci_prepare_to_sleep(struct pci_dev *dev)
1354 pci_power_t target_state = pci_target_state(dev);
1357 if (target_state == PCI_POWER_ERROR)
1360 pci_enable_wake(dev, target_state, device_may_wakeup(&dev->dev));
1362 error = pci_set_power_state(dev, target_state);
1365 pci_enable_wake(dev, target_state, false);
1371 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
1372 * @dev: Device to handle.
1374 * Disable device's sytem wake-up capability and put it into D0.
1376 int pci_back_from_sleep(struct pci_dev *dev)
1378 pci_enable_wake(dev, PCI_D0, false);
1379 return pci_set_power_state(dev, PCI_D0);
1383 * pci_pm_init - Initialize PM functions of given PCI device
1384 * @dev: PCI device to handle.
1386 void pci_pm_init(struct pci_dev *dev)
1391 dev->wakeup_prepared = false;
1394 /* find PCI PM capability in list */
1395 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
1398 /* Check device's ability to generate PME# */
1399 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
1401 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
1402 dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n",
1403 pmc & PCI_PM_CAP_VER_MASK);
1409 dev->d1_support = false;
1410 dev->d2_support = false;
1411 if (!pci_no_d1d2(dev)) {
1412 if (pmc & PCI_PM_CAP_D1)
1413 dev->d1_support = true;
1414 if (pmc & PCI_PM_CAP_D2)
1415 dev->d2_support = true;
1417 if (dev->d1_support || dev->d2_support)
1418 dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n",
1419 dev->d1_support ? " D1" : "",
1420 dev->d2_support ? " D2" : "");
1423 pmc &= PCI_PM_CAP_PME_MASK;
1425 dev_info(&dev->dev, "PME# supported from%s%s%s%s%s\n",
1426 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
1427 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
1428 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
1429 (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "",
1430 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
1431 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
1433 * Make device's PM flags reflect the wake-up capability, but
1434 * let the user space enable it to wake up the system as needed.
1436 device_set_wakeup_capable(&dev->dev, true);
1437 device_set_wakeup_enable(&dev->dev, false);
1438 /* Disable the PME# generation functionality */
1439 pci_pme_active(dev, false);
1441 dev->pme_support = 0;
1446 * platform_pci_wakeup_init - init platform wakeup if present
1449 * Some devices don't have PCI PM caps but can still generate wakeup
1450 * events through platform methods (like ACPI events). If @dev supports
1451 * platform wakeup events, set the device flag to indicate as much. This
1452 * may be redundant if the device also supports PCI PM caps, but double
1453 * initialization should be safe in that case.
1455 void platform_pci_wakeup_init(struct pci_dev *dev)
1457 if (!platform_pci_can_wakeup(dev))
1460 device_set_wakeup_capable(&dev->dev, true);
1461 device_set_wakeup_enable(&dev->dev, false);
1462 platform_pci_sleep_wake(dev, false);
1466 * pci_add_save_buffer - allocate buffer for saving given capability registers
1467 * @dev: the PCI device
1468 * @cap: the capability to allocate the buffer for
1469 * @size: requested size of the buffer
1471 static int pci_add_cap_save_buffer(
1472 struct pci_dev *dev, char cap, unsigned int size)
1475 struct pci_cap_saved_state *save_state;
1477 pos = pci_find_capability(dev, cap);
1481 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
1485 save_state->cap_nr = cap;
1486 pci_add_saved_cap(dev, save_state);
1492 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
1493 * @dev: the PCI device
1495 void pci_allocate_cap_save_buffers(struct pci_dev *dev)
1499 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
1500 PCI_EXP_SAVE_REGS * sizeof(u16));
1503 "unable to preallocate PCI Express save buffer\n");
1505 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
1508 "unable to preallocate PCI-X save buffer\n");
1512 * pci_enable_ari - enable ARI forwarding if hardware support it
1513 * @dev: the PCI device
1515 void pci_enable_ari(struct pci_dev *dev)
1520 struct pci_dev *bridge;
1522 if (!dev->is_pcie || dev->devfn)
1525 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
1529 bridge = dev->bus->self;
1530 if (!bridge || !bridge->is_pcie)
1533 pos = pci_find_capability(bridge, PCI_CAP_ID_EXP);
1537 pci_read_config_dword(bridge, pos + PCI_EXP_DEVCAP2, &cap);
1538 if (!(cap & PCI_EXP_DEVCAP2_ARI))
1541 pci_read_config_word(bridge, pos + PCI_EXP_DEVCTL2, &ctrl);
1542 ctrl |= PCI_EXP_DEVCTL2_ARI;
1543 pci_write_config_word(bridge, pos + PCI_EXP_DEVCTL2, ctrl);
1545 bridge->ari_enabled = 1;
1549 * pci_enable_acs - enable ACS if hardware support it
1550 * @dev: the PCI device
1552 void pci_enable_acs(struct pci_dev *dev)
1561 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
1565 pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
1566 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
1568 /* Source Validation */
1569 ctrl |= (cap & PCI_ACS_SV);
1571 /* P2P Request Redirect */
1572 ctrl |= (cap & PCI_ACS_RR);
1574 /* P2P Completion Redirect */
1575 ctrl |= (cap & PCI_ACS_CR);
1577 /* Upstream Forwarding */
1578 ctrl |= (cap & PCI_ACS_UF);
1580 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
1584 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
1585 * @dev: the PCI device
1586 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTD, 4=INTD)
1588 * Perform INTx swizzling for a device behind one level of bridge. This is
1589 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
1590 * behind bridges on add-in cards. For devices with ARI enabled, the slot
1591 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
1592 * the PCI Express Base Specification, Revision 2.1)
1594 u8 pci_swizzle_interrupt_pin(struct pci_dev *dev, u8 pin)
1598 if (pci_ari_enabled(dev->bus))
1601 slot = PCI_SLOT(dev->devfn);
1603 return (((pin - 1) + slot) % 4) + 1;
1607 pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
1615 while (!pci_is_root_bus(dev->bus)) {
1616 pin = pci_swizzle_interrupt_pin(dev, pin);
1617 dev = dev->bus->self;
1624 * pci_common_swizzle - swizzle INTx all the way to root bridge
1625 * @dev: the PCI device
1626 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
1628 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
1629 * bridges all the way up to a PCI root bus.
1631 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
1635 while (!pci_is_root_bus(dev->bus)) {
1636 pin = pci_swizzle_interrupt_pin(dev, pin);
1637 dev = dev->bus->self;
1640 return PCI_SLOT(dev->devfn);
1644 * pci_release_region - Release a PCI bar
1645 * @pdev: PCI device whose resources were previously reserved by pci_request_region
1646 * @bar: BAR to release
1648 * Releases the PCI I/O and memory resources previously reserved by a
1649 * successful call to pci_request_region. Call this function only
1650 * after all use of the PCI regions has ceased.
1652 void pci_release_region(struct pci_dev *pdev, int bar)
1654 struct pci_devres *dr;
1656 if (pci_resource_len(pdev, bar) == 0)
1658 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
1659 release_region(pci_resource_start(pdev, bar),
1660 pci_resource_len(pdev, bar));
1661 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
1662 release_mem_region(pci_resource_start(pdev, bar),
1663 pci_resource_len(pdev, bar));
1665 dr = find_pci_dr(pdev);
1667 dr->region_mask &= ~(1 << bar);
1671 * __pci_request_region - Reserved PCI I/O and memory resource
1672 * @pdev: PCI device whose resources are to be reserved
1673 * @bar: BAR to be reserved
1674 * @res_name: Name to be associated with resource.
1675 * @exclusive: whether the region access is exclusive or not
1677 * Mark the PCI region associated with PCI device @pdev BR @bar as
1678 * being reserved by owner @res_name. Do not access any
1679 * address inside the PCI regions unless this call returns
1682 * If @exclusive is set, then the region is marked so that userspace
1683 * is explicitly not allowed to map the resource via /dev/mem or
1684 * sysfs MMIO access.
1686 * Returns 0 on success, or %EBUSY on error. A warning
1687 * message is also printed on failure.
1689 static int __pci_request_region(struct pci_dev *pdev, int bar, const char *res_name,
1692 struct pci_devres *dr;
1694 if (pci_resource_len(pdev, bar) == 0)
1697 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
1698 if (!request_region(pci_resource_start(pdev, bar),
1699 pci_resource_len(pdev, bar), res_name))
1702 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
1703 if (!__request_mem_region(pci_resource_start(pdev, bar),
1704 pci_resource_len(pdev, bar), res_name,
1709 dr = find_pci_dr(pdev);
1711 dr->region_mask |= 1 << bar;
1716 dev_warn(&pdev->dev, "BAR %d: can't reserve %pRt\n", bar,
1717 &pdev->resource[bar]);
1722 * pci_request_region - Reserve PCI I/O and memory resource
1723 * @pdev: PCI device whose resources are to be reserved
1724 * @bar: BAR to be reserved
1725 * @res_name: Name to be associated with resource
1727 * Mark the PCI region associated with PCI device @pdev BAR @bar as
1728 * being reserved by owner @res_name. Do not access any
1729 * address inside the PCI regions unless this call returns
1732 * Returns 0 on success, or %EBUSY on error. A warning
1733 * message is also printed on failure.
1735 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
1737 return __pci_request_region(pdev, bar, res_name, 0);
1741 * pci_request_region_exclusive - Reserved PCI I/O and memory resource
1742 * @pdev: PCI device whose resources are to be reserved
1743 * @bar: BAR to be reserved
1744 * @res_name: Name to be associated with resource.
1746 * Mark the PCI region associated with PCI device @pdev BR @bar as
1747 * being reserved by owner @res_name. Do not access any
1748 * address inside the PCI regions unless this call returns
1751 * Returns 0 on success, or %EBUSY on error. A warning
1752 * message is also printed on failure.
1754 * The key difference that _exclusive makes it that userspace is
1755 * explicitly not allowed to map the resource via /dev/mem or
1758 int pci_request_region_exclusive(struct pci_dev *pdev, int bar, const char *res_name)
1760 return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE);
1763 * pci_release_selected_regions - Release selected PCI I/O and memory resources
1764 * @pdev: PCI device whose resources were previously reserved
1765 * @bars: Bitmask of BARs to be released
1767 * Release selected PCI I/O and memory resources previously reserved.
1768 * Call this function only after all use of the PCI regions has ceased.
1770 void pci_release_selected_regions(struct pci_dev *pdev, int bars)
1774 for (i = 0; i < 6; i++)
1775 if (bars & (1 << i))
1776 pci_release_region(pdev, i);
1779 int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
1780 const char *res_name, int excl)
1784 for (i = 0; i < 6; i++)
1785 if (bars & (1 << i))
1786 if (__pci_request_region(pdev, i, res_name, excl))
1792 if (bars & (1 << i))
1793 pci_release_region(pdev, i);
1800 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
1801 * @pdev: PCI device whose resources are to be reserved
1802 * @bars: Bitmask of BARs to be requested
1803 * @res_name: Name to be associated with resource
1805 int pci_request_selected_regions(struct pci_dev *pdev, int bars,
1806 const char *res_name)
1808 return __pci_request_selected_regions(pdev, bars, res_name, 0);
1811 int pci_request_selected_regions_exclusive(struct pci_dev *pdev,
1812 int bars, const char *res_name)
1814 return __pci_request_selected_regions(pdev, bars, res_name,
1815 IORESOURCE_EXCLUSIVE);
1819 * pci_release_regions - Release reserved PCI I/O and memory resources
1820 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
1822 * Releases all PCI I/O and memory resources previously reserved by a
1823 * successful call to pci_request_regions. Call this function only
1824 * after all use of the PCI regions has ceased.
1827 void pci_release_regions(struct pci_dev *pdev)
1829 pci_release_selected_regions(pdev, (1 << 6) - 1);
1833 * pci_request_regions - Reserved PCI I/O and memory resources
1834 * @pdev: PCI device whose resources are to be reserved
1835 * @res_name: Name to be associated with resource.
1837 * Mark all PCI regions associated with PCI device @pdev as
1838 * being reserved by owner @res_name. Do not access any
1839 * address inside the PCI regions unless this call returns
1842 * Returns 0 on success, or %EBUSY on error. A warning
1843 * message is also printed on failure.
1845 int pci_request_regions(struct pci_dev *pdev, const char *res_name)
1847 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
1851 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
1852 * @pdev: PCI device whose resources are to be reserved
1853 * @res_name: Name to be associated with resource.
1855 * Mark all PCI regions associated with PCI device @pdev as
1856 * being reserved by owner @res_name. Do not access any
1857 * address inside the PCI regions unless this call returns
1860 * pci_request_regions_exclusive() will mark the region so that
1861 * /dev/mem and the sysfs MMIO access will not be allowed.
1863 * Returns 0 on success, or %EBUSY on error. A warning
1864 * message is also printed on failure.
1866 int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
1868 return pci_request_selected_regions_exclusive(pdev,
1869 ((1 << 6) - 1), res_name);
1872 static void __pci_set_master(struct pci_dev *dev, bool enable)
1876 pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
1878 cmd = old_cmd | PCI_COMMAND_MASTER;
1880 cmd = old_cmd & ~PCI_COMMAND_MASTER;
1881 if (cmd != old_cmd) {
1882 dev_dbg(&dev->dev, "%s bus mastering\n",
1883 enable ? "enabling" : "disabling");
1884 pci_write_config_word(dev, PCI_COMMAND, cmd);
1886 dev->is_busmaster = enable;
1890 * pci_set_master - enables bus-mastering for device dev
1891 * @dev: the PCI device to enable
1893 * Enables bus-mastering on the device and calls pcibios_set_master()
1894 * to do the needed arch specific settings.
1896 void pci_set_master(struct pci_dev *dev)
1898 __pci_set_master(dev, true);
1899 pcibios_set_master(dev);
1903 * pci_clear_master - disables bus-mastering for device dev
1904 * @dev: the PCI device to disable
1906 void pci_clear_master(struct pci_dev *dev)
1908 __pci_set_master(dev, false);
1912 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
1913 * @dev: the PCI device for which MWI is to be enabled
1915 * Helper function for pci_set_mwi.
1916 * Originally copied from drivers/net/acenic.c.
1917 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
1919 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1921 int pci_set_cacheline_size(struct pci_dev *dev)
1925 if (!pci_cache_line_size)
1928 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
1929 equal to or multiple of the right value. */
1930 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
1931 if (cacheline_size >= pci_cache_line_size &&
1932 (cacheline_size % pci_cache_line_size) == 0)
1935 /* Write the correct value. */
1936 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
1938 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
1939 if (cacheline_size == pci_cache_line_size)
1942 dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not "
1943 "supported\n", pci_cache_line_size << 2);
1947 EXPORT_SYMBOL_GPL(pci_set_cacheline_size);
1949 #ifdef PCI_DISABLE_MWI
1950 int pci_set_mwi(struct pci_dev *dev)
1955 int pci_try_set_mwi(struct pci_dev *dev)
1960 void pci_clear_mwi(struct pci_dev *dev)
1967 * pci_set_mwi - enables memory-write-invalidate PCI transaction
1968 * @dev: the PCI device for which MWI is enabled
1970 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
1972 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1975 pci_set_mwi(struct pci_dev *dev)
1980 rc = pci_set_cacheline_size(dev);
1984 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1985 if (! (cmd & PCI_COMMAND_INVALIDATE)) {
1986 dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n");
1987 cmd |= PCI_COMMAND_INVALIDATE;
1988 pci_write_config_word(dev, PCI_COMMAND, cmd);
1995 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
1996 * @dev: the PCI device for which MWI is enabled
1998 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
1999 * Callers are not required to check the return value.
2001 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2003 int pci_try_set_mwi(struct pci_dev *dev)
2005 int rc = pci_set_mwi(dev);
2010 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
2011 * @dev: the PCI device to disable
2013 * Disables PCI Memory-Write-Invalidate transaction on the device
2016 pci_clear_mwi(struct pci_dev *dev)
2020 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2021 if (cmd & PCI_COMMAND_INVALIDATE) {
2022 cmd &= ~PCI_COMMAND_INVALIDATE;
2023 pci_write_config_word(dev, PCI_COMMAND, cmd);
2026 #endif /* ! PCI_DISABLE_MWI */
2029 * pci_intx - enables/disables PCI INTx for device dev
2030 * @pdev: the PCI device to operate on
2031 * @enable: boolean: whether to enable or disable PCI INTx
2033 * Enables/disables PCI INTx for device dev
2036 pci_intx(struct pci_dev *pdev, int enable)
2038 u16 pci_command, new;
2040 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
2043 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
2045 new = pci_command | PCI_COMMAND_INTX_DISABLE;
2048 if (new != pci_command) {
2049 struct pci_devres *dr;
2051 pci_write_config_word(pdev, PCI_COMMAND, new);
2053 dr = find_pci_dr(pdev);
2054 if (dr && !dr->restore_intx) {
2055 dr->restore_intx = 1;
2056 dr->orig_intx = !enable;
2062 * pci_msi_off - disables any msi or msix capabilities
2063 * @dev: the PCI device to operate on
2065 * If you want to use msi see pci_enable_msi and friends.
2066 * This is a lower level primitive that allows us to disable
2067 * msi operation at the device level.
2069 void pci_msi_off(struct pci_dev *dev)
2074 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
2076 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
2077 control &= ~PCI_MSI_FLAGS_ENABLE;
2078 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
2080 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
2082 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
2083 control &= ~PCI_MSIX_FLAGS_ENABLE;
2084 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
2088 #ifndef HAVE_ARCH_PCI_SET_DMA_MASK
2090 * These can be overridden by arch-specific implementations
2093 pci_set_dma_mask(struct pci_dev *dev, u64 mask)
2095 if (!pci_dma_supported(dev, mask))
2098 dev->dma_mask = mask;
2104 pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
2106 if (!pci_dma_supported(dev, mask))
2109 dev->dev.coherent_dma_mask = mask;
2115 #ifndef HAVE_ARCH_PCI_SET_DMA_MAX_SEGMENT_SIZE
2116 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size)
2118 return dma_set_max_seg_size(&dev->dev, size);
2120 EXPORT_SYMBOL(pci_set_dma_max_seg_size);
2123 #ifndef HAVE_ARCH_PCI_SET_DMA_SEGMENT_BOUNDARY
2124 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask)
2126 return dma_set_seg_boundary(&dev->dev, mask);
2128 EXPORT_SYMBOL(pci_set_dma_seg_boundary);
2131 static int pcie_flr(struct pci_dev *dev, int probe)
2138 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
2142 pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP, &cap);
2143 if (!(cap & PCI_EXP_DEVCAP_FLR))
2149 /* Wait for Transaction Pending bit clean */
2150 for (i = 0; i < 4; i++) {
2152 msleep((1 << (i - 1)) * 100);
2154 pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status);
2155 if (!(status & PCI_EXP_DEVSTA_TRPND))
2159 dev_err(&dev->dev, "transaction is not cleared; "
2160 "proceeding with reset anyway\n");
2163 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL,
2164 PCI_EXP_DEVCTL_BCR_FLR);
2170 static int pci_af_flr(struct pci_dev *dev, int probe)
2177 pos = pci_find_capability(dev, PCI_CAP_ID_AF);
2181 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
2182 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
2188 /* Wait for Transaction Pending bit clean */
2189 for (i = 0; i < 4; i++) {
2191 msleep((1 << (i - 1)) * 100);
2193 pci_read_config_byte(dev, pos + PCI_AF_STATUS, &status);
2194 if (!(status & PCI_AF_STATUS_TP))
2198 dev_err(&dev->dev, "transaction is not cleared; "
2199 "proceeding with reset anyway\n");
2202 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
2208 static int pci_pm_reset(struct pci_dev *dev, int probe)
2215 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
2216 if (csr & PCI_PM_CTRL_NO_SOFT_RESET)
2222 if (dev->current_state != PCI_D0)
2225 csr &= ~PCI_PM_CTRL_STATE_MASK;
2227 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
2228 msleep(pci_pm_d3_delay);
2230 csr &= ~PCI_PM_CTRL_STATE_MASK;
2232 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
2233 msleep(pci_pm_d3_delay);
2238 static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
2241 struct pci_dev *pdev;
2243 if (pci_is_root_bus(dev->bus) || dev->subordinate || !dev->bus->self)
2246 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
2253 pci_read_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, &ctrl);
2254 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
2255 pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl);
2258 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
2259 pci_write_config_word(dev->bus->self, PCI_BRIDGE_CONTROL, ctrl);
2265 static int pci_dev_reset(struct pci_dev *dev, int probe)
2272 pci_block_user_cfg_access(dev);
2273 /* block PM suspend, driver probe, etc. */
2274 down(&dev->dev.sem);
2277 rc = pcie_flr(dev, probe);
2281 rc = pci_af_flr(dev, probe);
2285 rc = pci_pm_reset(dev, probe);
2289 rc = pci_parent_bus_reset(dev, probe);
2293 pci_unblock_user_cfg_access(dev);
2300 * __pci_reset_function - reset a PCI device function
2301 * @dev: PCI device to reset
2303 * Some devices allow an individual function to be reset without affecting
2304 * other functions in the same device. The PCI device must be responsive
2305 * to PCI config space in order to use this function.
2307 * The device function is presumed to be unused when this function is called.
2308 * Resetting the device will make the contents of PCI configuration space
2309 * random, so any caller of this must be prepared to reinitialise the
2310 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
2313 * Returns 0 if the device function was successfully reset or negative if the
2314 * device doesn't support resetting a single function.
2316 int __pci_reset_function(struct pci_dev *dev)
2318 return pci_dev_reset(dev, 0);
2320 EXPORT_SYMBOL_GPL(__pci_reset_function);
2323 * pci_probe_reset_function - check whether the device can be safely reset
2324 * @dev: PCI device to reset
2326 * Some devices allow an individual function to be reset without affecting
2327 * other functions in the same device. The PCI device must be responsive
2328 * to PCI config space in order to use this function.
2330 * Returns 0 if the device function can be reset or negative if the
2331 * device doesn't support resetting a single function.
2333 int pci_probe_reset_function(struct pci_dev *dev)
2335 return pci_dev_reset(dev, 1);
2339 * pci_reset_function - quiesce and reset a PCI device function
2340 * @dev: PCI device to reset
2342 * Some devices allow an individual function to be reset without affecting
2343 * other functions in the same device. The PCI device must be responsive
2344 * to PCI config space in order to use this function.
2346 * This function does not just reset the PCI portion of a device, but
2347 * clears all the state associated with the device. This function differs
2348 * from __pci_reset_function in that it saves and restores device state
2351 * Returns 0 if the device function was successfully reset or negative if the
2352 * device doesn't support resetting a single function.
2354 int pci_reset_function(struct pci_dev *dev)
2358 rc = pci_dev_reset(dev, 1);
2362 pci_save_state(dev);
2365 * both INTx and MSI are disabled after the Interrupt Disable bit
2366 * is set and the Bus Master bit is cleared.
2368 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
2370 rc = pci_dev_reset(dev, 0);
2372 pci_restore_state(dev);
2376 EXPORT_SYMBOL_GPL(pci_reset_function);
2379 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
2380 * @dev: PCI device to query
2382 * Returns mmrbc: maximum designed memory read count in bytes
2383 * or appropriate error value.
2385 int pcix_get_max_mmrbc(struct pci_dev *dev)
2390 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
2394 err = pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat);
2398 return (stat & PCI_X_STATUS_MAX_READ) >> 12;
2400 EXPORT_SYMBOL(pcix_get_max_mmrbc);
2403 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
2404 * @dev: PCI device to query
2406 * Returns mmrbc: maximum memory read count in bytes
2407 * or appropriate error value.
2409 int pcix_get_mmrbc(struct pci_dev *dev)
2414 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
2418 ret = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd);
2420 ret = 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
2424 EXPORT_SYMBOL(pcix_get_mmrbc);
2427 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
2428 * @dev: PCI device to query
2429 * @mmrbc: maximum memory read count in bytes
2430 * valid values are 512, 1024, 2048, 4096
2432 * If possible sets maximum memory read byte count, some bridges have erratas
2433 * that prevent this.
2435 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
2437 int cap, err = -EINVAL;
2438 u32 stat, cmd, v, o;
2440 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
2443 v = ffs(mmrbc) - 10;
2445 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
2449 err = pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat);
2453 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
2456 err = pci_read_config_dword(dev, cap + PCI_X_CMD, &cmd);
2460 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
2462 if (v > o && dev->bus &&
2463 (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
2466 cmd &= ~PCI_X_CMD_MAX_READ;
2468 err = pci_write_config_dword(dev, cap + PCI_X_CMD, cmd);
2473 EXPORT_SYMBOL(pcix_set_mmrbc);
2476 * pcie_get_readrq - get PCI Express read request size
2477 * @dev: PCI device to query
2479 * Returns maximum memory read request in bytes
2480 * or appropriate error value.
2482 int pcie_get_readrq(struct pci_dev *dev)
2487 cap = pci_find_capability(dev, PCI_CAP_ID_EXP);
2491 ret = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
2493 ret = 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
2497 EXPORT_SYMBOL(pcie_get_readrq);
2500 * pcie_set_readrq - set PCI Express maximum memory read request
2501 * @dev: PCI device to query
2502 * @rq: maximum memory read count in bytes
2503 * valid values are 128, 256, 512, 1024, 2048, 4096
2505 * If possible sets maximum read byte count
2507 int pcie_set_readrq(struct pci_dev *dev, int rq)
2509 int cap, err = -EINVAL;
2512 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
2515 v = (ffs(rq) - 8) << 12;
2517 cap = pci_find_capability(dev, PCI_CAP_ID_EXP);
2521 err = pci_read_config_word(dev, cap + PCI_EXP_DEVCTL, &ctl);
2525 if ((ctl & PCI_EXP_DEVCTL_READRQ) != v) {
2526 ctl &= ~PCI_EXP_DEVCTL_READRQ;
2528 err = pci_write_config_dword(dev, cap + PCI_EXP_DEVCTL, ctl);
2534 EXPORT_SYMBOL(pcie_set_readrq);
2537 * pci_select_bars - Make BAR mask from the type of resource
2538 * @dev: the PCI device for which BAR mask is made
2539 * @flags: resource type mask to be selected
2541 * This helper routine makes bar mask from the type of resource.
2543 int pci_select_bars(struct pci_dev *dev, unsigned long flags)
2546 for (i = 0; i < PCI_NUM_RESOURCES; i++)
2547 if (pci_resource_flags(dev, i) & flags)
2553 * pci_resource_bar - get position of the BAR associated with a resource
2554 * @dev: the PCI device
2555 * @resno: the resource number
2556 * @type: the BAR type to be filled in
2558 * Returns BAR position in config space, or 0 if the BAR is invalid.
2560 int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type)
2564 if (resno < PCI_ROM_RESOURCE) {
2565 *type = pci_bar_unknown;
2566 return PCI_BASE_ADDRESS_0 + 4 * resno;
2567 } else if (resno == PCI_ROM_RESOURCE) {
2568 *type = pci_bar_mem32;
2569 return dev->rom_base_reg;
2570 } else if (resno < PCI_BRIDGE_RESOURCES) {
2571 /* device specific resource */
2572 reg = pci_iov_resource_bar(dev, resno, type);
2577 dev_err(&dev->dev, "BAR: invalid resource #%d\n", resno);
2582 * pci_set_vga_state - set VGA decode state on device and parents if requested
2583 * @dev: the PCI device
2584 * @decode: true = enable decoding, false = disable decoding
2585 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
2586 * @change_bridge: traverse ancestors and change bridges
2588 int pci_set_vga_state(struct pci_dev *dev, bool decode,
2589 unsigned int command_bits, bool change_bridge)
2591 struct pci_bus *bus;
2592 struct pci_dev *bridge;
2595 WARN_ON(command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY));
2597 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2599 cmd |= command_bits;
2601 cmd &= ~command_bits;
2602 pci_write_config_word(dev, PCI_COMMAND, cmd);
2604 if (change_bridge == false)
2611 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
2614 cmd |= PCI_BRIDGE_CTL_VGA;
2616 cmd &= ~PCI_BRIDGE_CTL_VGA;
2617 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL,
2625 #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
2626 static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0};
2627 spinlock_t resource_alignment_lock = SPIN_LOCK_UNLOCKED;
2630 * pci_specified_resource_alignment - get resource alignment specified by user.
2631 * @dev: the PCI device to get
2633 * RETURNS: Resource alignment if it is specified.
2634 * Zero if it is not specified.
2636 resource_size_t pci_specified_resource_alignment(struct pci_dev *dev)
2638 int seg, bus, slot, func, align_order, count;
2639 resource_size_t align = 0;
2642 spin_lock(&resource_alignment_lock);
2643 p = resource_alignment_param;
2646 if (sscanf(p, "%d%n", &align_order, &count) == 1 &&
2652 if (sscanf(p, "%x:%x:%x.%x%n",
2653 &seg, &bus, &slot, &func, &count) != 4) {
2655 if (sscanf(p, "%x:%x.%x%n",
2656 &bus, &slot, &func, &count) != 3) {
2657 /* Invalid format */
2658 printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: %s\n",
2664 if (seg == pci_domain_nr(dev->bus) &&
2665 bus == dev->bus->number &&
2666 slot == PCI_SLOT(dev->devfn) &&
2667 func == PCI_FUNC(dev->devfn)) {
2668 if (align_order == -1) {
2671 align = 1 << align_order;
2676 if (*p != ';' && *p != ',') {
2677 /* End of param or invalid format */
2682 spin_unlock(&resource_alignment_lock);
2687 * pci_is_reassigndev - check if specified PCI is target device to reassign
2688 * @dev: the PCI device to check
2690 * RETURNS: non-zero for PCI device is a target device to reassign,
2693 int pci_is_reassigndev(struct pci_dev *dev)
2695 return (pci_specified_resource_alignment(dev) != 0);
2698 ssize_t pci_set_resource_alignment_param(const char *buf, size_t count)
2700 if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1)
2701 count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1;
2702 spin_lock(&resource_alignment_lock);
2703 strncpy(resource_alignment_param, buf, count);
2704 resource_alignment_param[count] = '\0';
2705 spin_unlock(&resource_alignment_lock);
2709 ssize_t pci_get_resource_alignment_param(char *buf, size_t size)
2712 spin_lock(&resource_alignment_lock);
2713 count = snprintf(buf, size, "%s", resource_alignment_param);
2714 spin_unlock(&resource_alignment_lock);
2718 static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf)
2720 return pci_get_resource_alignment_param(buf, PAGE_SIZE);
2723 static ssize_t pci_resource_alignment_store(struct bus_type *bus,
2724 const char *buf, size_t count)
2726 return pci_set_resource_alignment_param(buf, count);
2729 BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show,
2730 pci_resource_alignment_store);
2732 static int __init pci_resource_alignment_sysfs_init(void)
2734 return bus_create_file(&pci_bus_type,
2735 &bus_attr_resource_alignment);
2738 late_initcall(pci_resource_alignment_sysfs_init);
2740 static void __devinit pci_no_domains(void)
2742 #ifdef CONFIG_PCI_DOMAINS
2743 pci_domains_supported = 0;
2748 * pci_ext_cfg_enabled - can we access extended PCI config space?
2749 * @dev: The PCI device of the root bridge.
2751 * Returns 1 if we can access PCI extended config space (offsets
2752 * greater than 0xff). This is the default implementation. Architecture
2753 * implementations can override this.
2755 int __attribute__ ((weak)) pci_ext_cfg_avail(struct pci_dev *dev)
2760 static int __init pci_setup(char *str)
2763 char *k = strchr(str, ',');
2766 if (*str && (str = pcibios_setup(str)) && *str) {
2767 if (!strcmp(str, "nomsi")) {
2769 } else if (!strcmp(str, "noaer")) {
2771 } else if (!strcmp(str, "nodomains")) {
2773 } else if (!strncmp(str, "cbiosize=", 9)) {
2774 pci_cardbus_io_size = memparse(str + 9, &str);
2775 } else if (!strncmp(str, "cbmemsize=", 10)) {
2776 pci_cardbus_mem_size = memparse(str + 10, &str);
2777 } else if (!strncmp(str, "resource_alignment=", 19)) {
2778 pci_set_resource_alignment_param(str + 19,
2780 } else if (!strncmp(str, "ecrc=", 5)) {
2781 pcie_ecrc_get_policy(str + 5);
2782 } else if (!strncmp(str, "hpiosize=", 9)) {
2783 pci_hotplug_io_size = memparse(str + 9, &str);
2784 } else if (!strncmp(str, "hpmemsize=", 10)) {
2785 pci_hotplug_mem_size = memparse(str + 10, &str);
2787 printk(KERN_ERR "PCI: Unknown option `%s'\n",
2795 early_param("pci", pci_setup);
2797 EXPORT_SYMBOL(pci_reenable_device);
2798 EXPORT_SYMBOL(pci_enable_device_io);
2799 EXPORT_SYMBOL(pci_enable_device_mem);
2800 EXPORT_SYMBOL(pci_enable_device);
2801 EXPORT_SYMBOL(pcim_enable_device);
2802 EXPORT_SYMBOL(pcim_pin_device);
2803 EXPORT_SYMBOL(pci_disable_device);
2804 EXPORT_SYMBOL(pci_find_capability);
2805 EXPORT_SYMBOL(pci_bus_find_capability);
2806 EXPORT_SYMBOL(pci_release_regions);
2807 EXPORT_SYMBOL(pci_request_regions);
2808 EXPORT_SYMBOL(pci_request_regions_exclusive);
2809 EXPORT_SYMBOL(pci_release_region);
2810 EXPORT_SYMBOL(pci_request_region);
2811 EXPORT_SYMBOL(pci_request_region_exclusive);
2812 EXPORT_SYMBOL(pci_release_selected_regions);
2813 EXPORT_SYMBOL(pci_request_selected_regions);
2814 EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
2815 EXPORT_SYMBOL(pci_set_master);
2816 EXPORT_SYMBOL(pci_clear_master);
2817 EXPORT_SYMBOL(pci_set_mwi);
2818 EXPORT_SYMBOL(pci_try_set_mwi);
2819 EXPORT_SYMBOL(pci_clear_mwi);
2820 EXPORT_SYMBOL_GPL(pci_intx);
2821 EXPORT_SYMBOL(pci_set_dma_mask);
2822 EXPORT_SYMBOL(pci_set_consistent_dma_mask);
2823 EXPORT_SYMBOL(pci_assign_resource);
2824 EXPORT_SYMBOL(pci_find_parent_resource);
2825 EXPORT_SYMBOL(pci_select_bars);
2827 EXPORT_SYMBOL(pci_set_power_state);
2828 EXPORT_SYMBOL(pci_save_state);
2829 EXPORT_SYMBOL(pci_restore_state);
2830 EXPORT_SYMBOL(pci_pme_capable);
2831 EXPORT_SYMBOL(pci_pme_active);
2832 EXPORT_SYMBOL(pci_enable_wake);
2833 EXPORT_SYMBOL(pci_wake_from_d3);
2834 EXPORT_SYMBOL(pci_target_state);
2835 EXPORT_SYMBOL(pci_prepare_to_sleep);
2836 EXPORT_SYMBOL(pci_back_from_sleep);
2837 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);