2 * PCI Bus Services, see include/linux/pci.h for further explanation.
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
10 #include <linux/kernel.h>
11 #include <linux/delay.h>
12 #include <linux/init.h>
13 #include <linux/pci.h>
15 #include <linux/slab.h>
16 #include <linux/module.h>
17 #include <linux/spinlock.h>
18 #include <linux/string.h>
19 #include <linux/log2.h>
20 #include <linux/pci-aspm.h>
21 #include <linux/pm_wakeup.h>
22 #include <linux/interrupt.h>
23 #include <linux/device.h>
24 #include <linux/pm_runtime.h>
25 #include <linux/pci_hotplug.h>
26 #include <asm-generic/pci-bridge.h>
27 #include <asm/setup.h>
30 const char *pci_power_names[] = {
31 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
33 EXPORT_SYMBOL_GPL(pci_power_names);
35 int isa_dma_bridge_buggy;
36 EXPORT_SYMBOL(isa_dma_bridge_buggy);
39 EXPORT_SYMBOL(pci_pci_problems);
41 unsigned int pci_pm_d3_delay;
43 static void pci_pme_list_scan(struct work_struct *work);
45 static LIST_HEAD(pci_pme_list);
46 static DEFINE_MUTEX(pci_pme_list_mutex);
47 static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan);
49 struct pci_pme_device {
50 struct list_head list;
54 #define PME_TIMEOUT 1000 /* How long between PME checks */
56 static void pci_dev_d3_sleep(struct pci_dev *dev)
58 unsigned int delay = dev->d3_delay;
60 if (delay < pci_pm_d3_delay)
61 delay = pci_pm_d3_delay;
66 #ifdef CONFIG_PCI_DOMAINS
67 int pci_domains_supported = 1;
70 #define DEFAULT_CARDBUS_IO_SIZE (256)
71 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
72 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
73 unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
74 unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
76 #define DEFAULT_HOTPLUG_IO_SIZE (256)
77 #define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024)
78 /* pci=hpmemsize=nnM,hpiosize=nn can override this */
79 unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE;
80 unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE;
82 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_TUNE_OFF;
85 * The default CLS is used if arch didn't set CLS explicitly and not
86 * all pci devices agree on the same value. Arch can override either
87 * the dfl or actual value as it sees fit. Don't forget this is
88 * measured in 32-bit words, not bytes.
90 u8 pci_dfl_cache_line_size = L1_CACHE_BYTES >> 2;
91 u8 pci_cache_line_size;
94 * If we set up a device for bus mastering, we need to check the latency
95 * timer as certain BIOSes forget to set it properly.
97 unsigned int pcibios_max_latency = 255;
99 /* If set, the PCIe ARI capability will not be used. */
100 static bool pcie_ari_disabled;
103 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
104 * @bus: pointer to PCI bus structure to search
106 * Given a PCI bus, returns the highest PCI bus number present in the set
107 * including the given PCI bus and its list of child PCI buses.
109 unsigned char pci_bus_max_busnr(struct pci_bus* bus)
112 unsigned char max, n;
114 max = bus->busn_res.end;
115 list_for_each_entry(tmp, &bus->children, node) {
116 n = pci_bus_max_busnr(tmp);
122 EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
124 #ifdef CONFIG_HAS_IOMEM
125 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
128 * Make sure the BAR is actually a memory resource, not an IO resource
130 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
134 return ioremap_nocache(pci_resource_start(pdev, bar),
135 pci_resource_len(pdev, bar));
137 EXPORT_SYMBOL_GPL(pci_ioremap_bar);
140 #define PCI_FIND_CAP_TTL 48
142 static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
143 u8 pos, int cap, int *ttl)
148 pci_bus_read_config_byte(bus, devfn, pos, &pos);
152 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID,
158 pos += PCI_CAP_LIST_NEXT;
163 static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
166 int ttl = PCI_FIND_CAP_TTL;
168 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
171 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
173 return __pci_find_next_cap(dev->bus, dev->devfn,
174 pos + PCI_CAP_LIST_NEXT, cap);
176 EXPORT_SYMBOL_GPL(pci_find_next_capability);
178 static int __pci_bus_find_cap_start(struct pci_bus *bus,
179 unsigned int devfn, u8 hdr_type)
183 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
184 if (!(status & PCI_STATUS_CAP_LIST))
188 case PCI_HEADER_TYPE_NORMAL:
189 case PCI_HEADER_TYPE_BRIDGE:
190 return PCI_CAPABILITY_LIST;
191 case PCI_HEADER_TYPE_CARDBUS:
192 return PCI_CB_CAPABILITY_LIST;
201 * pci_find_capability - query for devices' capabilities
202 * @dev: PCI device to query
203 * @cap: capability code
205 * Tell if a device supports a given PCI capability.
206 * Returns the address of the requested capability structure within the
207 * device's PCI configuration space or 0 in case the device does not
208 * support it. Possible values for @cap:
210 * %PCI_CAP_ID_PM Power Management
211 * %PCI_CAP_ID_AGP Accelerated Graphics Port
212 * %PCI_CAP_ID_VPD Vital Product Data
213 * %PCI_CAP_ID_SLOTID Slot Identification
214 * %PCI_CAP_ID_MSI Message Signalled Interrupts
215 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
216 * %PCI_CAP_ID_PCIX PCI-X
217 * %PCI_CAP_ID_EXP PCI Express
219 int pci_find_capability(struct pci_dev *dev, int cap)
223 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
225 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
229 EXPORT_SYMBOL(pci_find_capability);
232 * pci_bus_find_capability - query for devices' capabilities
233 * @bus: the PCI bus to query
234 * @devfn: PCI device to query
235 * @cap: capability code
237 * Like pci_find_capability() but works for pci devices that do not have a
238 * pci_dev structure set up yet.
240 * Returns the address of the requested capability structure within the
241 * device's PCI configuration space or 0 in case the device does not
244 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
249 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
251 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
253 pos = __pci_find_next_cap(bus, devfn, pos, cap);
257 EXPORT_SYMBOL(pci_bus_find_capability);
260 * pci_find_next_ext_capability - Find an extended capability
261 * @dev: PCI device to query
262 * @start: address at which to start looking (0 to start at beginning of list)
263 * @cap: capability code
265 * Returns the address of the next matching extended capability structure
266 * within the device's PCI configuration space or 0 if the device does
267 * not support it. Some capabilities can occur several times, e.g., the
268 * vendor-specific capability, and this provides a way to find them all.
270 int pci_find_next_ext_capability(struct pci_dev *dev, int start, int cap)
274 int pos = PCI_CFG_SPACE_SIZE;
276 /* minimum 8 bytes per capability */
277 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
279 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
285 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
289 * If we have no capabilities, this is indicated by cap ID,
290 * cap version and next pointer all being 0.
296 if (PCI_EXT_CAP_ID(header) == cap && pos != start)
299 pos = PCI_EXT_CAP_NEXT(header);
300 if (pos < PCI_CFG_SPACE_SIZE)
303 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
309 EXPORT_SYMBOL_GPL(pci_find_next_ext_capability);
312 * pci_find_ext_capability - Find an extended capability
313 * @dev: PCI device to query
314 * @cap: capability code
316 * Returns the address of the requested extended capability structure
317 * within the device's PCI configuration space or 0 if the device does
318 * not support it. Possible values for @cap:
320 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
321 * %PCI_EXT_CAP_ID_VC Virtual Channel
322 * %PCI_EXT_CAP_ID_DSN Device Serial Number
323 * %PCI_EXT_CAP_ID_PWR Power Budgeting
325 int pci_find_ext_capability(struct pci_dev *dev, int cap)
327 return pci_find_next_ext_capability(dev, 0, cap);
329 EXPORT_SYMBOL_GPL(pci_find_ext_capability);
331 static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
333 int rc, ttl = PCI_FIND_CAP_TTL;
336 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
337 mask = HT_3BIT_CAP_MASK;
339 mask = HT_5BIT_CAP_MASK;
341 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
342 PCI_CAP_ID_HT, &ttl);
344 rc = pci_read_config_byte(dev, pos + 3, &cap);
345 if (rc != PCIBIOS_SUCCESSFUL)
348 if ((cap & mask) == ht_cap)
351 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
352 pos + PCI_CAP_LIST_NEXT,
353 PCI_CAP_ID_HT, &ttl);
359 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
360 * @dev: PCI device to query
361 * @pos: Position from which to continue searching
362 * @ht_cap: Hypertransport capability code
364 * To be used in conjunction with pci_find_ht_capability() to search for
365 * all capabilities matching @ht_cap. @pos should always be a value returned
366 * from pci_find_ht_capability().
368 * NB. To be 100% safe against broken PCI devices, the caller should take
369 * steps to avoid an infinite loop.
371 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
373 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
375 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
378 * pci_find_ht_capability - query a device's Hypertransport capabilities
379 * @dev: PCI device to query
380 * @ht_cap: Hypertransport capability code
382 * Tell if a device supports a given Hypertransport capability.
383 * Returns an address within the device's PCI configuration space
384 * or 0 in case the device does not support the request capability.
385 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
386 * which has a Hypertransport capability matching @ht_cap.
388 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
392 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
394 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
398 EXPORT_SYMBOL_GPL(pci_find_ht_capability);
401 * pci_find_parent_resource - return resource region of parent bus of given region
402 * @dev: PCI device structure contains resources to be searched
403 * @res: child resource record for which parent is sought
405 * For given resource region of given device, return the resource
406 * region of parent bus the given region is contained in.
409 pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
411 const struct pci_bus *bus = dev->bus;
415 pci_bus_for_each_resource(bus, r, i) {
418 if (res->start && resource_contains(r, res)) {
421 * If the window is prefetchable but the BAR is
422 * not, the allocator made a mistake.
424 if (r->flags & IORESOURCE_PREFETCH &&
425 !(res->flags & IORESOURCE_PREFETCH))
429 * If we're below a transparent bridge, there may
430 * be both a positively-decoded aperture and a
431 * subtractively-decoded region that contain the BAR.
432 * We want the positively-decoded one, so this depends
433 * on pci_bus_for_each_resource() giving us those
441 EXPORT_SYMBOL(pci_find_parent_resource);
444 * pci_wait_for_pending - wait for @mask bit(s) to clear in status word @pos
445 * @dev: the PCI device to operate on
446 * @pos: config space offset of status word
447 * @mask: mask of bit(s) to care about in status word
449 * Return 1 when mask bit(s) in status word clear, 0 otherwise.
451 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask)
455 /* Wait for Transaction Pending bit clean */
456 for (i = 0; i < 4; i++) {
459 msleep((1 << (i - 1)) * 100);
461 pci_read_config_word(dev, pos, &status);
462 if (!(status & mask))
470 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
471 * @dev: PCI device to have its BARs restored
473 * Restore the BAR values for a given device, so as to make it
474 * accessible by its driver.
477 pci_restore_bars(struct pci_dev *dev)
481 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
482 pci_update_resource(dev, i);
485 static struct pci_platform_pm_ops *pci_platform_pm;
487 int pci_set_platform_pm(struct pci_platform_pm_ops *ops)
489 if (!ops->is_manageable || !ops->set_state || !ops->choose_state
492 pci_platform_pm = ops;
496 static inline bool platform_pci_power_manageable(struct pci_dev *dev)
498 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
501 static inline int platform_pci_set_power_state(struct pci_dev *dev,
504 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
507 static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
509 return pci_platform_pm ?
510 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
513 static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable)
515 return pci_platform_pm ?
516 pci_platform_pm->sleep_wake(dev, enable) : -ENODEV;
519 static inline int platform_pci_run_wake(struct pci_dev *dev, bool enable)
521 return pci_platform_pm ?
522 pci_platform_pm->run_wake(dev, enable) : -ENODEV;
526 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
528 * @dev: PCI device to handle.
529 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
532 * -EINVAL if the requested state is invalid.
533 * -EIO if device does not support PCI PM or its PM capabilities register has a
534 * wrong version, or device doesn't support the requested state.
535 * 0 if device already is in the requested state.
536 * 0 if device's power state has been successfully changed.
538 static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
541 bool need_restore = false;
543 /* Check if we're already there */
544 if (dev->current_state == state)
550 if (state < PCI_D0 || state > PCI_D3hot)
553 /* Validate current state:
554 * Can enter D0 from any state, but if we can only go deeper
555 * to sleep if we're already in a low power state
557 if (state != PCI_D0 && dev->current_state <= PCI_D3cold
558 && dev->current_state > state) {
559 dev_err(&dev->dev, "invalid power transition "
560 "(from state %d to %d)\n", dev->current_state, state);
564 /* check if this device supports the desired state */
565 if ((state == PCI_D1 && !dev->d1_support)
566 || (state == PCI_D2 && !dev->d2_support))
569 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
571 /* If we're (effectively) in D3, force entire word to 0.
572 * This doesn't affect PME_Status, disables PME_En, and
573 * sets PowerState to 0.
575 switch (dev->current_state) {
579 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
584 case PCI_UNKNOWN: /* Boot-up */
585 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
586 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
588 /* Fall-through: force to D0 */
594 /* enter specified state */
595 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
597 /* Mandatory power management transition delays */
598 /* see PCI PM 1.1 5.6.1 table 18 */
599 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
600 pci_dev_d3_sleep(dev);
601 else if (state == PCI_D2 || dev->current_state == PCI_D2)
602 udelay(PCI_PM_D2_DELAY);
604 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
605 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
606 if (dev->current_state != state && printk_ratelimit())
607 dev_info(&dev->dev, "Refused to change power state, "
608 "currently in D%d\n", dev->current_state);
611 * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
612 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
613 * from D3hot to D0 _may_ perform an internal reset, thereby
614 * going to "D0 Uninitialized" rather than "D0 Initialized".
615 * For example, at least some versions of the 3c905B and the
616 * 3c556B exhibit this behaviour.
618 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
619 * devices in a D3hot state at boot. Consequently, we need to
620 * restore at least the BARs so that the device will be
621 * accessible to its driver.
624 pci_restore_bars(dev);
627 pcie_aspm_pm_state_change(dev->bus->self);
633 * pci_update_current_state - Read PCI power state of given device from its
634 * PCI PM registers and cache it
635 * @dev: PCI device to handle.
636 * @state: State to cache in case the device doesn't have the PM capability
638 void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
644 * Configuration space is not accessible for device in
645 * D3cold, so just keep or set D3cold for safety
647 if (dev->current_state == PCI_D3cold)
649 if (state == PCI_D3cold) {
650 dev->current_state = PCI_D3cold;
653 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
654 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
656 dev->current_state = state;
661 * pci_power_up - Put the given device into D0 forcibly
662 * @dev: PCI device to power up
664 void pci_power_up(struct pci_dev *dev)
666 if (platform_pci_power_manageable(dev))
667 platform_pci_set_power_state(dev, PCI_D0);
669 pci_raw_set_power_state(dev, PCI_D0);
670 pci_update_current_state(dev, PCI_D0);
674 * pci_platform_power_transition - Use platform to change device power state
675 * @dev: PCI device to handle.
676 * @state: State to put the device into.
678 static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
682 if (platform_pci_power_manageable(dev)) {
683 error = platform_pci_set_power_state(dev, state);
685 pci_update_current_state(dev, state);
689 if (error && !dev->pm_cap) /* Fall back to PCI_D0 */
690 dev->current_state = PCI_D0;
696 * pci_wakeup - Wake up a PCI device
697 * @pci_dev: Device to handle.
698 * @ign: ignored parameter
700 static int pci_wakeup(struct pci_dev *pci_dev, void *ign)
702 pci_wakeup_event(pci_dev);
703 pm_request_resume(&pci_dev->dev);
708 * pci_wakeup_bus - Walk given bus and wake up devices on it
709 * @bus: Top bus of the subtree to walk.
711 static void pci_wakeup_bus(struct pci_bus *bus)
714 pci_walk_bus(bus, pci_wakeup, NULL);
718 * __pci_start_power_transition - Start power transition of a PCI device
719 * @dev: PCI device to handle.
720 * @state: State to put the device into.
722 static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state)
724 if (state == PCI_D0) {
725 pci_platform_power_transition(dev, PCI_D0);
727 * Mandatory power management transition delays, see
728 * PCI Express Base Specification Revision 2.0 Section
729 * 6.6.1: Conventional Reset. Do not delay for
730 * devices powered on/off by corresponding bridge,
731 * because have already delayed for the bridge.
733 if (dev->runtime_d3cold) {
734 msleep(dev->d3cold_delay);
736 * When powering on a bridge from D3cold, the
737 * whole hierarchy may be powered on into
738 * D0uninitialized state, resume them to give
739 * them a chance to suspend again
741 pci_wakeup_bus(dev->subordinate);
747 * __pci_dev_set_current_state - Set current state of a PCI device
748 * @dev: Device to handle
749 * @data: pointer to state to be set
751 static int __pci_dev_set_current_state(struct pci_dev *dev, void *data)
753 pci_power_t state = *(pci_power_t *)data;
755 dev->current_state = state;
760 * __pci_bus_set_current_state - Walk given bus and set current state of devices
761 * @bus: Top bus of the subtree to walk.
762 * @state: state to be set
764 static void __pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state)
767 pci_walk_bus(bus, __pci_dev_set_current_state, &state);
771 * __pci_complete_power_transition - Complete power transition of a PCI device
772 * @dev: PCI device to handle.
773 * @state: State to put the device into.
775 * This function should not be called directly by device drivers.
777 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state)
783 ret = pci_platform_power_transition(dev, state);
784 /* Power off the bridge may power off the whole hierarchy */
785 if (!ret && state == PCI_D3cold)
786 __pci_bus_set_current_state(dev->subordinate, PCI_D3cold);
789 EXPORT_SYMBOL_GPL(__pci_complete_power_transition);
792 * pci_set_power_state - Set the power state of a PCI device
793 * @dev: PCI device to handle.
794 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
796 * Transition a device to a new power state, using the platform firmware and/or
797 * the device's PCI PM registers.
800 * -EINVAL if the requested state is invalid.
801 * -EIO if device does not support PCI PM or its PM capabilities register has a
802 * wrong version, or device doesn't support the requested state.
803 * 0 if device already is in the requested state.
804 * 0 if device's power state has been successfully changed.
806 int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
810 /* bound the state we're entering */
811 if (state > PCI_D3cold)
813 else if (state < PCI_D0)
815 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
817 * If the device or the parent bridge do not support PCI PM,
818 * ignore the request if we're doing anything other than putting
819 * it into D0 (which would only happen on boot).
823 /* Check if we're already there */
824 if (dev->current_state == state)
827 __pci_start_power_transition(dev, state);
829 /* This device is quirked not to be put into D3, so
830 don't put it in D3 */
831 if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
835 * To put device in D3cold, we put device into D3hot in native
836 * way, then put device into D3cold with platform ops
838 error = pci_raw_set_power_state(dev, state > PCI_D3hot ?
841 if (!__pci_complete_power_transition(dev, state))
844 * When aspm_policy is "powersave" this call ensures
845 * that ASPM is configured.
847 if (!error && dev->bus->self)
848 pcie_aspm_powersave_config_link(dev->bus->self);
852 EXPORT_SYMBOL(pci_set_power_state);
855 * pci_choose_state - Choose the power state of a PCI device
856 * @dev: PCI device to be suspended
857 * @state: target sleep state for the whole system. This is the value
858 * that is passed to suspend() function.
860 * Returns PCI power state suitable for given device and given system
864 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
871 ret = platform_pci_choose_state(dev);
872 if (ret != PCI_POWER_ERROR)
875 switch (state.event) {
878 case PM_EVENT_FREEZE:
879 case PM_EVENT_PRETHAW:
880 /* REVISIT both freeze and pre-thaw "should" use D0 */
881 case PM_EVENT_SUSPEND:
882 case PM_EVENT_HIBERNATE:
885 dev_info(&dev->dev, "unrecognized suspend event %d\n",
892 EXPORT_SYMBOL(pci_choose_state);
894 #define PCI_EXP_SAVE_REGS 7
897 static struct pci_cap_saved_state *_pci_find_saved_cap(struct pci_dev *pci_dev,
898 u16 cap, bool extended)
900 struct pci_cap_saved_state *tmp;
902 hlist_for_each_entry(tmp, &pci_dev->saved_cap_space, next) {
903 if (tmp->cap.cap_extended == extended && tmp->cap.cap_nr == cap)
909 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap)
911 return _pci_find_saved_cap(dev, cap, false);
914 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, u16 cap)
916 return _pci_find_saved_cap(dev, cap, true);
919 static int pci_save_pcie_state(struct pci_dev *dev)
922 struct pci_cap_saved_state *save_state;
925 if (!pci_is_pcie(dev))
928 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
930 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
934 cap = (u16 *)&save_state->cap.data[0];
935 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &cap[i++]);
936 pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &cap[i++]);
937 pcie_capability_read_word(dev, PCI_EXP_SLTCTL, &cap[i++]);
938 pcie_capability_read_word(dev, PCI_EXP_RTCTL, &cap[i++]);
939 pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &cap[i++]);
940 pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]);
941 pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]);
946 static void pci_restore_pcie_state(struct pci_dev *dev)
949 struct pci_cap_saved_state *save_state;
952 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
956 cap = (u16 *)&save_state->cap.data[0];
957 pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]);
958 pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]);
959 pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]);
960 pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]);
961 pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]);
962 pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]);
963 pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]);
967 static int pci_save_pcix_state(struct pci_dev *dev)
970 struct pci_cap_saved_state *save_state;
972 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
976 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
978 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
982 pci_read_config_word(dev, pos + PCI_X_CMD,
983 (u16 *)save_state->cap.data);
988 static void pci_restore_pcix_state(struct pci_dev *dev)
991 struct pci_cap_saved_state *save_state;
994 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
995 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
996 if (!save_state || pos <= 0)
998 cap = (u16 *)&save_state->cap.data[0];
1000 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
1005 * pci_save_state - save the PCI configuration space of a device before suspending
1006 * @dev: - PCI device that we're dealing with
1009 pci_save_state(struct pci_dev *dev)
1012 /* XXX: 100% dword access ok here? */
1013 for (i = 0; i < 16; i++)
1014 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
1015 dev->state_saved = true;
1016 if ((i = pci_save_pcie_state(dev)) != 0)
1018 if ((i = pci_save_pcix_state(dev)) != 0)
1020 if ((i = pci_save_vc_state(dev)) != 0)
1024 EXPORT_SYMBOL(pci_save_state);
1026 static void pci_restore_config_dword(struct pci_dev *pdev, int offset,
1027 u32 saved_val, int retry)
1031 pci_read_config_dword(pdev, offset, &val);
1032 if (val == saved_val)
1036 dev_dbg(&pdev->dev, "restoring config space at offset "
1037 "%#x (was %#x, writing %#x)\n", offset, val, saved_val);
1038 pci_write_config_dword(pdev, offset, saved_val);
1042 pci_read_config_dword(pdev, offset, &val);
1043 if (val == saved_val)
1050 static void pci_restore_config_space_range(struct pci_dev *pdev,
1051 int start, int end, int retry)
1055 for (index = end; index >= start; index--)
1056 pci_restore_config_dword(pdev, 4 * index,
1057 pdev->saved_config_space[index],
1061 static void pci_restore_config_space(struct pci_dev *pdev)
1063 if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) {
1064 pci_restore_config_space_range(pdev, 10, 15, 0);
1065 /* Restore BARs before the command register. */
1066 pci_restore_config_space_range(pdev, 4, 9, 10);
1067 pci_restore_config_space_range(pdev, 0, 3, 0);
1069 pci_restore_config_space_range(pdev, 0, 15, 0);
1074 * pci_restore_state - Restore the saved state of a PCI device
1075 * @dev: - PCI device that we're dealing with
1077 void pci_restore_state(struct pci_dev *dev)
1079 if (!dev->state_saved)
1082 /* PCI Express register must be restored first */
1083 pci_restore_pcie_state(dev);
1084 pci_restore_ats_state(dev);
1085 pci_restore_vc_state(dev);
1087 pci_restore_config_space(dev);
1089 pci_restore_pcix_state(dev);
1090 pci_restore_msi_state(dev);
1091 pci_restore_iov_state(dev);
1093 dev->state_saved = false;
1095 EXPORT_SYMBOL(pci_restore_state);
1097 struct pci_saved_state {
1098 u32 config_space[16];
1099 struct pci_cap_saved_data cap[0];
1103 * pci_store_saved_state - Allocate and return an opaque struct containing
1104 * the device saved state.
1105 * @dev: PCI device that we're dealing with
1107 * Return NULL if no state or error.
1109 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev)
1111 struct pci_saved_state *state;
1112 struct pci_cap_saved_state *tmp;
1113 struct pci_cap_saved_data *cap;
1116 if (!dev->state_saved)
1119 size = sizeof(*state) + sizeof(struct pci_cap_saved_data);
1121 hlist_for_each_entry(tmp, &dev->saved_cap_space, next)
1122 size += sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1124 state = kzalloc(size, GFP_KERNEL);
1128 memcpy(state->config_space, dev->saved_config_space,
1129 sizeof(state->config_space));
1132 hlist_for_each_entry(tmp, &dev->saved_cap_space, next) {
1133 size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1134 memcpy(cap, &tmp->cap, len);
1135 cap = (struct pci_cap_saved_data *)((u8 *)cap + len);
1137 /* Empty cap_save terminates list */
1141 EXPORT_SYMBOL_GPL(pci_store_saved_state);
1144 * pci_load_saved_state - Reload the provided save state into struct pci_dev.
1145 * @dev: PCI device that we're dealing with
1146 * @state: Saved state returned from pci_store_saved_state()
1148 static int pci_load_saved_state(struct pci_dev *dev,
1149 struct pci_saved_state *state)
1151 struct pci_cap_saved_data *cap;
1153 dev->state_saved = false;
1158 memcpy(dev->saved_config_space, state->config_space,
1159 sizeof(state->config_space));
1163 struct pci_cap_saved_state *tmp;
1165 tmp = _pci_find_saved_cap(dev, cap->cap_nr, cap->cap_extended);
1166 if (!tmp || tmp->cap.size != cap->size)
1169 memcpy(tmp->cap.data, cap->data, tmp->cap.size);
1170 cap = (struct pci_cap_saved_data *)((u8 *)cap +
1171 sizeof(struct pci_cap_saved_data) + cap->size);
1174 dev->state_saved = true;
1179 * pci_load_and_free_saved_state - Reload the save state pointed to by state,
1180 * and free the memory allocated for it.
1181 * @dev: PCI device that we're dealing with
1182 * @state: Pointer to saved state returned from pci_store_saved_state()
1184 int pci_load_and_free_saved_state(struct pci_dev *dev,
1185 struct pci_saved_state **state)
1187 int ret = pci_load_saved_state(dev, *state);
1192 EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state);
1194 int __weak pcibios_enable_device(struct pci_dev *dev, int bars)
1196 return pci_enable_resources(dev, bars);
1199 static int do_pci_enable_device(struct pci_dev *dev, int bars)
1205 err = pci_set_power_state(dev, PCI_D0);
1206 if (err < 0 && err != -EIO)
1208 err = pcibios_enable_device(dev, bars);
1211 pci_fixup_device(pci_fixup_enable, dev);
1213 if (dev->msi_enabled || dev->msix_enabled)
1216 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
1218 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1219 if (cmd & PCI_COMMAND_INTX_DISABLE)
1220 pci_write_config_word(dev, PCI_COMMAND,
1221 cmd & ~PCI_COMMAND_INTX_DISABLE);
1228 * pci_reenable_device - Resume abandoned device
1229 * @dev: PCI device to be resumed
1231 * Note this function is a backend of pci_default_resume and is not supposed
1232 * to be called by normal code, write proper resume handler and use it instead.
1234 int pci_reenable_device(struct pci_dev *dev)
1236 if (pci_is_enabled(dev))
1237 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
1240 EXPORT_SYMBOL(pci_reenable_device);
1242 static void pci_enable_bridge(struct pci_dev *dev)
1244 struct pci_dev *bridge;
1247 bridge = pci_upstream_bridge(dev);
1249 pci_enable_bridge(bridge);
1251 if (pci_is_enabled(dev)) {
1252 if (!dev->is_busmaster)
1253 pci_set_master(dev);
1257 retval = pci_enable_device(dev);
1259 dev_err(&dev->dev, "Error enabling bridge (%d), continuing\n",
1261 pci_set_master(dev);
1264 static int pci_enable_device_flags(struct pci_dev *dev, unsigned long flags)
1266 struct pci_dev *bridge;
1271 * Power state could be unknown at this point, either due to a fresh
1272 * boot or a device removal call. So get the current power state
1273 * so that things like MSI message writing will behave as expected
1274 * (e.g. if the device really is in D0 at enable time).
1278 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1279 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
1282 if (atomic_inc_return(&dev->enable_cnt) > 1)
1283 return 0; /* already enabled */
1285 bridge = pci_upstream_bridge(dev);
1287 pci_enable_bridge(bridge);
1289 /* only skip sriov related */
1290 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
1291 if (dev->resource[i].flags & flags)
1293 for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++)
1294 if (dev->resource[i].flags & flags)
1297 err = do_pci_enable_device(dev, bars);
1299 atomic_dec(&dev->enable_cnt);
1304 * pci_enable_device_io - Initialize a device for use with IO space
1305 * @dev: PCI device to be initialized
1307 * Initialize device before it's used by a driver. Ask low-level code
1308 * to enable I/O resources. Wake up the device if it was suspended.
1309 * Beware, this function can fail.
1311 int pci_enable_device_io(struct pci_dev *dev)
1313 return pci_enable_device_flags(dev, IORESOURCE_IO);
1315 EXPORT_SYMBOL(pci_enable_device_io);
1318 * pci_enable_device_mem - Initialize a device for use with Memory space
1319 * @dev: PCI device to be initialized
1321 * Initialize device before it's used by a driver. Ask low-level code
1322 * to enable Memory resources. Wake up the device if it was suspended.
1323 * Beware, this function can fail.
1325 int pci_enable_device_mem(struct pci_dev *dev)
1327 return pci_enable_device_flags(dev, IORESOURCE_MEM);
1329 EXPORT_SYMBOL(pci_enable_device_mem);
1332 * pci_enable_device - Initialize device before it's used by a driver.
1333 * @dev: PCI device to be initialized
1335 * Initialize device before it's used by a driver. Ask low-level code
1336 * to enable I/O and memory. Wake up the device if it was suspended.
1337 * Beware, this function can fail.
1339 * Note we don't actually enable the device many times if we call
1340 * this function repeatedly (we just increment the count).
1342 int pci_enable_device(struct pci_dev *dev)
1344 return pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
1346 EXPORT_SYMBOL(pci_enable_device);
1349 * Managed PCI resources. This manages device on/off, intx/msi/msix
1350 * on/off and BAR regions. pci_dev itself records msi/msix status, so
1351 * there's no need to track it separately. pci_devres is initialized
1352 * when a device is enabled using managed PCI device enable interface.
1355 unsigned int enabled:1;
1356 unsigned int pinned:1;
1357 unsigned int orig_intx:1;
1358 unsigned int restore_intx:1;
1362 static void pcim_release(struct device *gendev, void *res)
1364 struct pci_dev *dev = container_of(gendev, struct pci_dev, dev);
1365 struct pci_devres *this = res;
1368 if (dev->msi_enabled)
1369 pci_disable_msi(dev);
1370 if (dev->msix_enabled)
1371 pci_disable_msix(dev);
1373 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
1374 if (this->region_mask & (1 << i))
1375 pci_release_region(dev, i);
1377 if (this->restore_intx)
1378 pci_intx(dev, this->orig_intx);
1380 if (this->enabled && !this->pinned)
1381 pci_disable_device(dev);
1384 static struct pci_devres * get_pci_dr(struct pci_dev *pdev)
1386 struct pci_devres *dr, *new_dr;
1388 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
1392 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
1395 return devres_get(&pdev->dev, new_dr, NULL, NULL);
1398 static struct pci_devres * find_pci_dr(struct pci_dev *pdev)
1400 if (pci_is_managed(pdev))
1401 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
1406 * pcim_enable_device - Managed pci_enable_device()
1407 * @pdev: PCI device to be initialized
1409 * Managed pci_enable_device().
1411 int pcim_enable_device(struct pci_dev *pdev)
1413 struct pci_devres *dr;
1416 dr = get_pci_dr(pdev);
1422 rc = pci_enable_device(pdev);
1424 pdev->is_managed = 1;
1429 EXPORT_SYMBOL(pcim_enable_device);
1432 * pcim_pin_device - Pin managed PCI device
1433 * @pdev: PCI device to pin
1435 * Pin managed PCI device @pdev. Pinned device won't be disabled on
1436 * driver detach. @pdev must have been enabled with
1437 * pcim_enable_device().
1439 void pcim_pin_device(struct pci_dev *pdev)
1441 struct pci_devres *dr;
1443 dr = find_pci_dr(pdev);
1444 WARN_ON(!dr || !dr->enabled);
1448 EXPORT_SYMBOL(pcim_pin_device);
1451 * pcibios_add_device - provide arch specific hooks when adding device dev
1452 * @dev: the PCI device being added
1454 * Permits the platform to provide architecture specific functionality when
1455 * devices are added. This is the default implementation. Architecture
1456 * implementations can override this.
1458 int __weak pcibios_add_device (struct pci_dev *dev)
1464 * pcibios_release_device - provide arch specific hooks when releasing device dev
1465 * @dev: the PCI device being released
1467 * Permits the platform to provide architecture specific functionality when
1468 * devices are released. This is the default implementation. Architecture
1469 * implementations can override this.
1471 void __weak pcibios_release_device(struct pci_dev *dev) {}
1474 * pcibios_disable_device - disable arch specific PCI resources for device dev
1475 * @dev: the PCI device to disable
1477 * Disables architecture specific PCI resources for the device. This
1478 * is the default implementation. Architecture implementations can
1481 void __weak pcibios_disable_device (struct pci_dev *dev) {}
1484 * pcibios_penalize_isa_irq - penalize an ISA IRQ
1485 * @irq: ISA IRQ to penalize
1486 * @active: IRQ active or not
1488 * Permits the platform to provide architecture-specific functionality when
1489 * penalizing ISA IRQs. This is the default implementation. Architecture
1490 * implementations can override this.
1492 void __weak pcibios_penalize_isa_irq(int irq, int active) {}
1494 static void do_pci_disable_device(struct pci_dev *dev)
1498 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
1499 if (pci_command & PCI_COMMAND_MASTER) {
1500 pci_command &= ~PCI_COMMAND_MASTER;
1501 pci_write_config_word(dev, PCI_COMMAND, pci_command);
1504 pcibios_disable_device(dev);
1508 * pci_disable_enabled_device - Disable device without updating enable_cnt
1509 * @dev: PCI device to disable
1511 * NOTE: This function is a backend of PCI power management routines and is
1512 * not supposed to be called drivers.
1514 void pci_disable_enabled_device(struct pci_dev *dev)
1516 if (pci_is_enabled(dev))
1517 do_pci_disable_device(dev);
1521 * pci_disable_device - Disable PCI device after use
1522 * @dev: PCI device to be disabled
1524 * Signal to the system that the PCI device is not in use by the system
1525 * anymore. This only involves disabling PCI bus-mastering, if active.
1527 * Note we don't actually disable the device until all callers of
1528 * pci_enable_device() have called pci_disable_device().
1531 pci_disable_device(struct pci_dev *dev)
1533 struct pci_devres *dr;
1535 dr = find_pci_dr(dev);
1539 dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <= 0,
1540 "disabling already-disabled device");
1542 if (atomic_dec_return(&dev->enable_cnt) != 0)
1545 do_pci_disable_device(dev);
1547 dev->is_busmaster = 0;
1549 EXPORT_SYMBOL(pci_disable_device);
1552 * pcibios_set_pcie_reset_state - set reset state for device dev
1553 * @dev: the PCIe device reset
1554 * @state: Reset state to enter into
1557 * Sets the PCIe reset state for the device. This is the default
1558 * implementation. Architecture implementations can override this.
1560 int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev,
1561 enum pcie_reset_state state)
1567 * pci_set_pcie_reset_state - set reset state for device dev
1568 * @dev: the PCIe device reset
1569 * @state: Reset state to enter into
1572 * Sets the PCI reset state for the device.
1574 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
1576 return pcibios_set_pcie_reset_state(dev, state);
1578 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);
1581 * pci_check_pme_status - Check if given device has generated PME.
1582 * @dev: Device to check.
1584 * Check the PME status of the device and if set, clear it and clear PME enable
1585 * (if set). Return 'true' if PME status and PME enable were both set or
1586 * 'false' otherwise.
1588 bool pci_check_pme_status(struct pci_dev *dev)
1597 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL;
1598 pci_read_config_word(dev, pmcsr_pos, &pmcsr);
1599 if (!(pmcsr & PCI_PM_CTRL_PME_STATUS))
1602 /* Clear PME status. */
1603 pmcsr |= PCI_PM_CTRL_PME_STATUS;
1604 if (pmcsr & PCI_PM_CTRL_PME_ENABLE) {
1605 /* Disable PME to avoid interrupt flood. */
1606 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1610 pci_write_config_word(dev, pmcsr_pos, pmcsr);
1616 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
1617 * @dev: Device to handle.
1618 * @pme_poll_reset: Whether or not to reset the device's pme_poll flag.
1620 * Check if @dev has generated PME and queue a resume request for it in that
1623 static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset)
1625 if (pme_poll_reset && dev->pme_poll)
1626 dev->pme_poll = false;
1628 if (pci_check_pme_status(dev)) {
1629 pci_wakeup_event(dev);
1630 pm_request_resume(&dev->dev);
1636 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
1637 * @bus: Top bus of the subtree to walk.
1639 void pci_pme_wakeup_bus(struct pci_bus *bus)
1642 pci_walk_bus(bus, pci_pme_wakeup, (void *)true);
1647 * pci_pme_capable - check the capability of PCI device to generate PME#
1648 * @dev: PCI device to handle.
1649 * @state: PCI state from which device will issue PME#.
1651 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
1656 return !!(dev->pme_support & (1 << state));
1658 EXPORT_SYMBOL(pci_pme_capable);
1660 static void pci_pme_list_scan(struct work_struct *work)
1662 struct pci_pme_device *pme_dev, *n;
1664 mutex_lock(&pci_pme_list_mutex);
1665 list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) {
1666 if (pme_dev->dev->pme_poll) {
1667 struct pci_dev *bridge;
1669 bridge = pme_dev->dev->bus->self;
1671 * If bridge is in low power state, the
1672 * configuration space of subordinate devices
1673 * may be not accessible
1675 if (bridge && bridge->current_state != PCI_D0)
1677 pci_pme_wakeup(pme_dev->dev, NULL);
1679 list_del(&pme_dev->list);
1683 if (!list_empty(&pci_pme_list))
1684 schedule_delayed_work(&pci_pme_work,
1685 msecs_to_jiffies(PME_TIMEOUT));
1686 mutex_unlock(&pci_pme_list_mutex);
1690 * pci_pme_active - enable or disable PCI device's PME# function
1691 * @dev: PCI device to handle.
1692 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1694 * The caller must verify that the device is capable of generating PME# before
1695 * calling this function with @enable equal to 'true'.
1697 void pci_pme_active(struct pci_dev *dev, bool enable)
1701 if (!dev->pme_support)
1704 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1705 /* Clear PME_Status by writing 1 to it and enable PME# */
1706 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
1708 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1710 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1713 * PCI (as opposed to PCIe) PME requires that the device have
1714 * its PME# line hooked up correctly. Not all hardware vendors
1715 * do this, so the PME never gets delivered and the device
1716 * remains asleep. The easiest way around this is to
1717 * periodically walk the list of suspended devices and check
1718 * whether any have their PME flag set. The assumption is that
1719 * we'll wake up often enough anyway that this won't be a huge
1720 * hit, and the power savings from the devices will still be a
1723 * Although PCIe uses in-band PME message instead of PME# line
1724 * to report PME, PME does not work for some PCIe devices in
1725 * reality. For example, there are devices that set their PME
1726 * status bits, but don't really bother to send a PME message;
1727 * there are PCI Express Root Ports that don't bother to
1728 * trigger interrupts when they receive PME messages from the
1729 * devices below. So PME poll is used for PCIe devices too.
1732 if (dev->pme_poll) {
1733 struct pci_pme_device *pme_dev;
1735 pme_dev = kmalloc(sizeof(struct pci_pme_device),
1738 dev_warn(&dev->dev, "can't enable PME#\n");
1742 mutex_lock(&pci_pme_list_mutex);
1743 list_add(&pme_dev->list, &pci_pme_list);
1744 if (list_is_singular(&pci_pme_list))
1745 schedule_delayed_work(&pci_pme_work,
1746 msecs_to_jiffies(PME_TIMEOUT));
1747 mutex_unlock(&pci_pme_list_mutex);
1749 mutex_lock(&pci_pme_list_mutex);
1750 list_for_each_entry(pme_dev, &pci_pme_list, list) {
1751 if (pme_dev->dev == dev) {
1752 list_del(&pme_dev->list);
1757 mutex_unlock(&pci_pme_list_mutex);
1761 dev_dbg(&dev->dev, "PME# %s\n", enable ? "enabled" : "disabled");
1763 EXPORT_SYMBOL(pci_pme_active);
1766 * __pci_enable_wake - enable PCI device as wakeup event source
1767 * @dev: PCI device affected
1768 * @state: PCI state from which device will issue wakeup events
1769 * @runtime: True if the events are to be generated at run time
1770 * @enable: True to enable event generation; false to disable
1772 * This enables the device as a wakeup event source, or disables it.
1773 * When such events involves platform-specific hooks, those hooks are
1774 * called automatically by this routine.
1776 * Devices with legacy power management (no standard PCI PM capabilities)
1777 * always require such platform hooks.
1780 * 0 is returned on success
1781 * -EINVAL is returned if device is not supposed to wake up the system
1782 * Error code depending on the platform is returned if both the platform and
1783 * the native mechanism fail to enable the generation of wake-up events
1785 int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1786 bool runtime, bool enable)
1790 if (enable && !runtime && !device_may_wakeup(&dev->dev))
1793 /* Don't do the same thing twice in a row for one device. */
1794 if (!!enable == !!dev->wakeup_prepared)
1798 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1799 * Anderson we should be doing PME# wake enable followed by ACPI wake
1800 * enable. To disable wake-up we call the platform first, for symmetry.
1806 if (pci_pme_capable(dev, state))
1807 pci_pme_active(dev, true);
1810 error = runtime ? platform_pci_run_wake(dev, true) :
1811 platform_pci_sleep_wake(dev, true);
1815 dev->wakeup_prepared = true;
1818 platform_pci_run_wake(dev, false);
1820 platform_pci_sleep_wake(dev, false);
1821 pci_pme_active(dev, false);
1822 dev->wakeup_prepared = false;
1827 EXPORT_SYMBOL(__pci_enable_wake);
1830 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
1831 * @dev: PCI device to prepare
1832 * @enable: True to enable wake-up event generation; false to disable
1834 * Many drivers want the device to wake up the system from D3_hot or D3_cold
1835 * and this function allows them to set that up cleanly - pci_enable_wake()
1836 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
1837 * ordering constraints.
1839 * This function only returns error code if the device is not capable of
1840 * generating PME# from both D3_hot and D3_cold, and the platform is unable to
1841 * enable wake-up power for it.
1843 int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1845 return pci_pme_capable(dev, PCI_D3cold) ?
1846 pci_enable_wake(dev, PCI_D3cold, enable) :
1847 pci_enable_wake(dev, PCI_D3hot, enable);
1849 EXPORT_SYMBOL(pci_wake_from_d3);
1852 * pci_target_state - find an appropriate low power state for a given PCI dev
1855 * Use underlying platform code to find a supported low power state for @dev.
1856 * If the platform can't manage @dev, return the deepest state from which it
1857 * can generate wake events, based on any available PME info.
1859 static pci_power_t pci_target_state(struct pci_dev *dev)
1861 pci_power_t target_state = PCI_D3hot;
1863 if (platform_pci_power_manageable(dev)) {
1865 * Call the platform to choose the target state of the device
1866 * and enable wake-up from this state if supported.
1868 pci_power_t state = platform_pci_choose_state(dev);
1871 case PCI_POWER_ERROR:
1876 if (pci_no_d1d2(dev))
1879 target_state = state;
1881 } else if (!dev->pm_cap) {
1882 target_state = PCI_D0;
1883 } else if (device_may_wakeup(&dev->dev)) {
1885 * Find the deepest state from which the device can generate
1886 * wake-up events, make it the target state and enable device
1889 if (dev->pme_support) {
1891 && !(dev->pme_support & (1 << target_state)))
1896 return target_state;
1900 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
1901 * @dev: Device to handle.
1903 * Choose the power state appropriate for the device depending on whether
1904 * it can wake up the system and/or is power manageable by the platform
1905 * (PCI_D3hot is the default) and put the device into that state.
1907 int pci_prepare_to_sleep(struct pci_dev *dev)
1909 pci_power_t target_state = pci_target_state(dev);
1912 if (target_state == PCI_POWER_ERROR)
1915 /* D3cold during system suspend/hibernate is not supported */
1916 if (target_state > PCI_D3hot)
1917 target_state = PCI_D3hot;
1919 pci_enable_wake(dev, target_state, device_may_wakeup(&dev->dev));
1921 error = pci_set_power_state(dev, target_state);
1924 pci_enable_wake(dev, target_state, false);
1928 EXPORT_SYMBOL(pci_prepare_to_sleep);
1931 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
1932 * @dev: Device to handle.
1934 * Disable device's system wake-up capability and put it into D0.
1936 int pci_back_from_sleep(struct pci_dev *dev)
1938 pci_enable_wake(dev, PCI_D0, false);
1939 return pci_set_power_state(dev, PCI_D0);
1941 EXPORT_SYMBOL(pci_back_from_sleep);
1944 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
1945 * @dev: PCI device being suspended.
1947 * Prepare @dev to generate wake-up events at run time and put it into a low
1950 int pci_finish_runtime_suspend(struct pci_dev *dev)
1952 pci_power_t target_state = pci_target_state(dev);
1955 if (target_state == PCI_POWER_ERROR)
1958 dev->runtime_d3cold = target_state == PCI_D3cold;
1960 __pci_enable_wake(dev, target_state, true, pci_dev_run_wake(dev));
1962 error = pci_set_power_state(dev, target_state);
1965 __pci_enable_wake(dev, target_state, true, false);
1966 dev->runtime_d3cold = false;
1973 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
1974 * @dev: Device to check.
1976 * Return true if the device itself is capable of generating wake-up events
1977 * (through the platform or using the native PCIe PME) or if the device supports
1978 * PME and one of its upstream bridges can generate wake-up events.
1980 bool pci_dev_run_wake(struct pci_dev *dev)
1982 struct pci_bus *bus = dev->bus;
1984 if (device_run_wake(&dev->dev))
1987 if (!dev->pme_support)
1990 while (bus->parent) {
1991 struct pci_dev *bridge = bus->self;
1993 if (device_run_wake(&bridge->dev))
1999 /* We have reached the root bus. */
2001 return device_run_wake(bus->bridge);
2005 EXPORT_SYMBOL_GPL(pci_dev_run_wake);
2007 void pci_config_pm_runtime_get(struct pci_dev *pdev)
2009 struct device *dev = &pdev->dev;
2010 struct device *parent = dev->parent;
2013 pm_runtime_get_sync(parent);
2014 pm_runtime_get_noresume(dev);
2016 * pdev->current_state is set to PCI_D3cold during suspending,
2017 * so wait until suspending completes
2019 pm_runtime_barrier(dev);
2021 * Only need to resume devices in D3cold, because config
2022 * registers are still accessible for devices suspended but
2025 if (pdev->current_state == PCI_D3cold)
2026 pm_runtime_resume(dev);
2029 void pci_config_pm_runtime_put(struct pci_dev *pdev)
2031 struct device *dev = &pdev->dev;
2032 struct device *parent = dev->parent;
2034 pm_runtime_put(dev);
2036 pm_runtime_put_sync(parent);
2040 * pci_pm_init - Initialize PM functions of given PCI device
2041 * @dev: PCI device to handle.
2043 void pci_pm_init(struct pci_dev *dev)
2048 pm_runtime_forbid(&dev->dev);
2049 pm_runtime_set_active(&dev->dev);
2050 pm_runtime_enable(&dev->dev);
2051 device_enable_async_suspend(&dev->dev);
2052 dev->wakeup_prepared = false;
2055 dev->pme_support = 0;
2057 /* find PCI PM capability in list */
2058 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
2061 /* Check device's ability to generate PME# */
2062 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
2064 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
2065 dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n",
2066 pmc & PCI_PM_CAP_VER_MASK);
2071 dev->d3_delay = PCI_PM_D3_WAIT;
2072 dev->d3cold_delay = PCI_PM_D3COLD_WAIT;
2073 dev->d3cold_allowed = true;
2075 dev->d1_support = false;
2076 dev->d2_support = false;
2077 if (!pci_no_d1d2(dev)) {
2078 if (pmc & PCI_PM_CAP_D1)
2079 dev->d1_support = true;
2080 if (pmc & PCI_PM_CAP_D2)
2081 dev->d2_support = true;
2083 if (dev->d1_support || dev->d2_support)
2084 dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n",
2085 dev->d1_support ? " D1" : "",
2086 dev->d2_support ? " D2" : "");
2089 pmc &= PCI_PM_CAP_PME_MASK;
2091 dev_printk(KERN_DEBUG, &dev->dev,
2092 "PME# supported from%s%s%s%s%s\n",
2093 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
2094 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
2095 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
2096 (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "",
2097 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
2098 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
2099 dev->pme_poll = true;
2101 * Make device's PM flags reflect the wake-up capability, but
2102 * let the user space enable it to wake up the system as needed.
2104 device_set_wakeup_capable(&dev->dev, true);
2105 /* Disable the PME# generation functionality */
2106 pci_pme_active(dev, false);
2110 static void pci_add_saved_cap(struct pci_dev *pci_dev,
2111 struct pci_cap_saved_state *new_cap)
2113 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
2117 * _pci_add_cap_save_buffer - allocate buffer for saving given
2118 * capability registers
2119 * @dev: the PCI device
2120 * @cap: the capability to allocate the buffer for
2121 * @extended: Standard or Extended capability ID
2122 * @size: requested size of the buffer
2124 static int _pci_add_cap_save_buffer(struct pci_dev *dev, u16 cap,
2125 bool extended, unsigned int size)
2128 struct pci_cap_saved_state *save_state;
2131 pos = pci_find_ext_capability(dev, cap);
2133 pos = pci_find_capability(dev, cap);
2138 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
2142 save_state->cap.cap_nr = cap;
2143 save_state->cap.cap_extended = extended;
2144 save_state->cap.size = size;
2145 pci_add_saved_cap(dev, save_state);
2150 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size)
2152 return _pci_add_cap_save_buffer(dev, cap, false, size);
2155 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, u16 cap, unsigned int size)
2157 return _pci_add_cap_save_buffer(dev, cap, true, size);
2161 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
2162 * @dev: the PCI device
2164 void pci_allocate_cap_save_buffers(struct pci_dev *dev)
2168 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
2169 PCI_EXP_SAVE_REGS * sizeof(u16));
2172 "unable to preallocate PCI Express save buffer\n");
2174 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
2177 "unable to preallocate PCI-X save buffer\n");
2179 pci_allocate_vc_save_buffers(dev);
2182 void pci_free_cap_save_buffers(struct pci_dev *dev)
2184 struct pci_cap_saved_state *tmp;
2185 struct hlist_node *n;
2187 hlist_for_each_entry_safe(tmp, n, &dev->saved_cap_space, next)
2192 * pci_configure_ari - enable or disable ARI forwarding
2193 * @dev: the PCI device
2195 * If @dev and its upstream bridge both support ARI, enable ARI in the
2196 * bridge. Otherwise, disable ARI in the bridge.
2198 void pci_configure_ari(struct pci_dev *dev)
2201 struct pci_dev *bridge;
2203 if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn)
2206 bridge = dev->bus->self;
2210 pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
2211 if (!(cap & PCI_EXP_DEVCAP2_ARI))
2214 if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) {
2215 pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2,
2216 PCI_EXP_DEVCTL2_ARI);
2217 bridge->ari_enabled = 1;
2219 pcie_capability_clear_word(bridge, PCI_EXP_DEVCTL2,
2220 PCI_EXP_DEVCTL2_ARI);
2221 bridge->ari_enabled = 0;
2225 static int pci_acs_enable;
2228 * pci_request_acs - ask for ACS to be enabled if supported
2230 void pci_request_acs(void)
2236 * pci_std_enable_acs - enable ACS on devices using standard ACS capabilites
2237 * @dev: the PCI device
2239 static int pci_std_enable_acs(struct pci_dev *dev)
2245 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
2249 pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
2250 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
2252 /* Source Validation */
2253 ctrl |= (cap & PCI_ACS_SV);
2255 /* P2P Request Redirect */
2256 ctrl |= (cap & PCI_ACS_RR);
2258 /* P2P Completion Redirect */
2259 ctrl |= (cap & PCI_ACS_CR);
2261 /* Upstream Forwarding */
2262 ctrl |= (cap & PCI_ACS_UF);
2264 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
2270 * pci_enable_acs - enable ACS if hardware support it
2271 * @dev: the PCI device
2273 void pci_enable_acs(struct pci_dev *dev)
2275 if (!pci_acs_enable)
2278 if (!pci_std_enable_acs(dev))
2281 pci_dev_specific_enable_acs(dev);
2284 static bool pci_acs_flags_enabled(struct pci_dev *pdev, u16 acs_flags)
2289 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ACS);
2294 * Except for egress control, capabilities are either required
2295 * or only required if controllable. Features missing from the
2296 * capability field can therefore be assumed as hard-wired enabled.
2298 pci_read_config_word(pdev, pos + PCI_ACS_CAP, &cap);
2299 acs_flags &= (cap | PCI_ACS_EC);
2301 pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl);
2302 return (ctrl & acs_flags) == acs_flags;
2306 * pci_acs_enabled - test ACS against required flags for a given device
2307 * @pdev: device to test
2308 * @acs_flags: required PCI ACS flags
2310 * Return true if the device supports the provided flags. Automatically
2311 * filters out flags that are not implemented on multifunction devices.
2313 * Note that this interface checks the effective ACS capabilities of the
2314 * device rather than the actual capabilities. For instance, most single
2315 * function endpoints are not required to support ACS because they have no
2316 * opportunity for peer-to-peer access. We therefore return 'true'
2317 * regardless of whether the device exposes an ACS capability. This makes
2318 * it much easier for callers of this function to ignore the actual type
2319 * or topology of the device when testing ACS support.
2321 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
2325 ret = pci_dev_specific_acs_enabled(pdev, acs_flags);
2330 * Conventional PCI and PCI-X devices never support ACS, either
2331 * effectively or actually. The shared bus topology implies that
2332 * any device on the bus can receive or snoop DMA.
2334 if (!pci_is_pcie(pdev))
2337 switch (pci_pcie_type(pdev)) {
2339 * PCI/X-to-PCIe bridges are not specifically mentioned by the spec,
2340 * but since their primary interface is PCI/X, we conservatively
2341 * handle them as we would a non-PCIe device.
2343 case PCI_EXP_TYPE_PCIE_BRIDGE:
2345 * PCIe 3.0, 6.12.1 excludes ACS on these devices. "ACS is never
2346 * applicable... must never implement an ACS Extended Capability...".
2347 * This seems arbitrary, but we take a conservative interpretation
2348 * of this statement.
2350 case PCI_EXP_TYPE_PCI_BRIDGE:
2351 case PCI_EXP_TYPE_RC_EC:
2354 * PCIe 3.0, 6.12.1.1 specifies that downstream and root ports should
2355 * implement ACS in order to indicate their peer-to-peer capabilities,
2356 * regardless of whether they are single- or multi-function devices.
2358 case PCI_EXP_TYPE_DOWNSTREAM:
2359 case PCI_EXP_TYPE_ROOT_PORT:
2360 return pci_acs_flags_enabled(pdev, acs_flags);
2362 * PCIe 3.0, 6.12.1.2 specifies ACS capabilities that should be
2363 * implemented by the remaining PCIe types to indicate peer-to-peer
2364 * capabilities, but only when they are part of a multifunction
2365 * device. The footnote for section 6.12 indicates the specific
2366 * PCIe types included here.
2368 case PCI_EXP_TYPE_ENDPOINT:
2369 case PCI_EXP_TYPE_UPSTREAM:
2370 case PCI_EXP_TYPE_LEG_END:
2371 case PCI_EXP_TYPE_RC_END:
2372 if (!pdev->multifunction)
2375 return pci_acs_flags_enabled(pdev, acs_flags);
2379 * PCIe 3.0, 6.12.1.3 specifies no ACS capabilities are applicable
2380 * to single function devices with the exception of downstream ports.
2386 * pci_acs_path_enable - test ACS flags from start to end in a hierarchy
2387 * @start: starting downstream device
2388 * @end: ending upstream device or NULL to search to the root bus
2389 * @acs_flags: required flags
2391 * Walk up a device tree from start to end testing PCI ACS support. If
2392 * any step along the way does not support the required flags, return false.
2394 bool pci_acs_path_enabled(struct pci_dev *start,
2395 struct pci_dev *end, u16 acs_flags)
2397 struct pci_dev *pdev, *parent = start;
2402 if (!pci_acs_enabled(pdev, acs_flags))
2405 if (pci_is_root_bus(pdev->bus))
2406 return (end == NULL);
2408 parent = pdev->bus->self;
2409 } while (pdev != end);
2415 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
2416 * @dev: the PCI device
2417 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD)
2419 * Perform INTx swizzling for a device behind one level of bridge. This is
2420 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
2421 * behind bridges on add-in cards. For devices with ARI enabled, the slot
2422 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
2423 * the PCI Express Base Specification, Revision 2.1)
2425 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin)
2429 if (pci_ari_enabled(dev->bus))
2432 slot = PCI_SLOT(dev->devfn);
2434 return (((pin - 1) + slot) % 4) + 1;
2438 pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
2446 while (!pci_is_root_bus(dev->bus)) {
2447 pin = pci_swizzle_interrupt_pin(dev, pin);
2448 dev = dev->bus->self;
2455 * pci_common_swizzle - swizzle INTx all the way to root bridge
2456 * @dev: the PCI device
2457 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
2459 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
2460 * bridges all the way up to a PCI root bus.
2462 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
2466 while (!pci_is_root_bus(dev->bus)) {
2467 pin = pci_swizzle_interrupt_pin(dev, pin);
2468 dev = dev->bus->self;
2471 return PCI_SLOT(dev->devfn);
2475 * pci_release_region - Release a PCI bar
2476 * @pdev: PCI device whose resources were previously reserved by pci_request_region
2477 * @bar: BAR to release
2479 * Releases the PCI I/O and memory resources previously reserved by a
2480 * successful call to pci_request_region. Call this function only
2481 * after all use of the PCI regions has ceased.
2483 void pci_release_region(struct pci_dev *pdev, int bar)
2485 struct pci_devres *dr;
2487 if (pci_resource_len(pdev, bar) == 0)
2489 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
2490 release_region(pci_resource_start(pdev, bar),
2491 pci_resource_len(pdev, bar));
2492 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
2493 release_mem_region(pci_resource_start(pdev, bar),
2494 pci_resource_len(pdev, bar));
2496 dr = find_pci_dr(pdev);
2498 dr->region_mask &= ~(1 << bar);
2500 EXPORT_SYMBOL(pci_release_region);
2503 * __pci_request_region - Reserved PCI I/O and memory resource
2504 * @pdev: PCI device whose resources are to be reserved
2505 * @bar: BAR to be reserved
2506 * @res_name: Name to be associated with resource.
2507 * @exclusive: whether the region access is exclusive or not
2509 * Mark the PCI region associated with PCI device @pdev BR @bar as
2510 * being reserved by owner @res_name. Do not access any
2511 * address inside the PCI regions unless this call returns
2514 * If @exclusive is set, then the region is marked so that userspace
2515 * is explicitly not allowed to map the resource via /dev/mem or
2516 * sysfs MMIO access.
2518 * Returns 0 on success, or %EBUSY on error. A warning
2519 * message is also printed on failure.
2521 static int __pci_request_region(struct pci_dev *pdev, int bar, const char *res_name,
2524 struct pci_devres *dr;
2526 if (pci_resource_len(pdev, bar) == 0)
2529 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
2530 if (!request_region(pci_resource_start(pdev, bar),
2531 pci_resource_len(pdev, bar), res_name))
2534 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
2535 if (!__request_mem_region(pci_resource_start(pdev, bar),
2536 pci_resource_len(pdev, bar), res_name,
2541 dr = find_pci_dr(pdev);
2543 dr->region_mask |= 1 << bar;
2548 dev_warn(&pdev->dev, "BAR %d: can't reserve %pR\n", bar,
2549 &pdev->resource[bar]);
2554 * pci_request_region - Reserve PCI I/O and memory resource
2555 * @pdev: PCI device whose resources are to be reserved
2556 * @bar: BAR to be reserved
2557 * @res_name: Name to be associated with resource
2559 * Mark the PCI region associated with PCI device @pdev BAR @bar as
2560 * being reserved by owner @res_name. Do not access any
2561 * address inside the PCI regions unless this call returns
2564 * Returns 0 on success, or %EBUSY on error. A warning
2565 * message is also printed on failure.
2567 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
2569 return __pci_request_region(pdev, bar, res_name, 0);
2571 EXPORT_SYMBOL(pci_request_region);
2574 * pci_request_region_exclusive - Reserved PCI I/O and memory resource
2575 * @pdev: PCI device whose resources are to be reserved
2576 * @bar: BAR to be reserved
2577 * @res_name: Name to be associated with resource.
2579 * Mark the PCI region associated with PCI device @pdev BR @bar as
2580 * being reserved by owner @res_name. Do not access any
2581 * address inside the PCI regions unless this call returns
2584 * Returns 0 on success, or %EBUSY on error. A warning
2585 * message is also printed on failure.
2587 * The key difference that _exclusive makes it that userspace is
2588 * explicitly not allowed to map the resource via /dev/mem or
2591 int pci_request_region_exclusive(struct pci_dev *pdev, int bar, const char *res_name)
2593 return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE);
2595 EXPORT_SYMBOL(pci_request_region_exclusive);
2598 * pci_release_selected_regions - Release selected PCI I/O and memory resources
2599 * @pdev: PCI device whose resources were previously reserved
2600 * @bars: Bitmask of BARs to be released
2602 * Release selected PCI I/O and memory resources previously reserved.
2603 * Call this function only after all use of the PCI regions has ceased.
2605 void pci_release_selected_regions(struct pci_dev *pdev, int bars)
2609 for (i = 0; i < 6; i++)
2610 if (bars & (1 << i))
2611 pci_release_region(pdev, i);
2613 EXPORT_SYMBOL(pci_release_selected_regions);
2615 static int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
2616 const char *res_name, int excl)
2620 for (i = 0; i < 6; i++)
2621 if (bars & (1 << i))
2622 if (__pci_request_region(pdev, i, res_name, excl))
2628 if (bars & (1 << i))
2629 pci_release_region(pdev, i);
2636 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
2637 * @pdev: PCI device whose resources are to be reserved
2638 * @bars: Bitmask of BARs to be requested
2639 * @res_name: Name to be associated with resource
2641 int pci_request_selected_regions(struct pci_dev *pdev, int bars,
2642 const char *res_name)
2644 return __pci_request_selected_regions(pdev, bars, res_name, 0);
2646 EXPORT_SYMBOL(pci_request_selected_regions);
2648 int pci_request_selected_regions_exclusive(struct pci_dev *pdev,
2649 int bars, const char *res_name)
2651 return __pci_request_selected_regions(pdev, bars, res_name,
2652 IORESOURCE_EXCLUSIVE);
2654 EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
2657 * pci_release_regions - Release reserved PCI I/O and memory resources
2658 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
2660 * Releases all PCI I/O and memory resources previously reserved by a
2661 * successful call to pci_request_regions. Call this function only
2662 * after all use of the PCI regions has ceased.
2665 void pci_release_regions(struct pci_dev *pdev)
2667 pci_release_selected_regions(pdev, (1 << 6) - 1);
2669 EXPORT_SYMBOL(pci_release_regions);
2672 * pci_request_regions - Reserved PCI I/O and memory resources
2673 * @pdev: PCI device whose resources are to be reserved
2674 * @res_name: Name to be associated with resource.
2676 * Mark all PCI regions associated with PCI device @pdev as
2677 * being reserved by owner @res_name. Do not access any
2678 * address inside the PCI regions unless this call returns
2681 * Returns 0 on success, or %EBUSY on error. A warning
2682 * message is also printed on failure.
2684 int pci_request_regions(struct pci_dev *pdev, const char *res_name)
2686 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
2688 EXPORT_SYMBOL(pci_request_regions);
2691 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
2692 * @pdev: PCI device whose resources are to be reserved
2693 * @res_name: Name to be associated with resource.
2695 * Mark all PCI regions associated with PCI device @pdev as
2696 * being reserved by owner @res_name. Do not access any
2697 * address inside the PCI regions unless this call returns
2700 * pci_request_regions_exclusive() will mark the region so that
2701 * /dev/mem and the sysfs MMIO access will not be allowed.
2703 * Returns 0 on success, or %EBUSY on error. A warning
2704 * message is also printed on failure.
2706 int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
2708 return pci_request_selected_regions_exclusive(pdev,
2709 ((1 << 6) - 1), res_name);
2711 EXPORT_SYMBOL(pci_request_regions_exclusive);
2713 static void __pci_set_master(struct pci_dev *dev, bool enable)
2717 pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
2719 cmd = old_cmd | PCI_COMMAND_MASTER;
2721 cmd = old_cmd & ~PCI_COMMAND_MASTER;
2722 if (cmd != old_cmd) {
2723 dev_dbg(&dev->dev, "%s bus mastering\n",
2724 enable ? "enabling" : "disabling");
2725 pci_write_config_word(dev, PCI_COMMAND, cmd);
2727 dev->is_busmaster = enable;
2731 * pcibios_setup - process "pci=" kernel boot arguments
2732 * @str: string used to pass in "pci=" kernel boot arguments
2734 * Process kernel boot arguments. This is the default implementation.
2735 * Architecture specific implementations can override this as necessary.
2737 char * __weak __init pcibios_setup(char *str)
2743 * pcibios_set_master - enable PCI bus-mastering for device dev
2744 * @dev: the PCI device to enable
2746 * Enables PCI bus-mastering for the device. This is the default
2747 * implementation. Architecture specific implementations can override
2748 * this if necessary.
2750 void __weak pcibios_set_master(struct pci_dev *dev)
2754 /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */
2755 if (pci_is_pcie(dev))
2758 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
2760 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
2761 else if (lat > pcibios_max_latency)
2762 lat = pcibios_max_latency;
2766 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
2770 * pci_set_master - enables bus-mastering for device dev
2771 * @dev: the PCI device to enable
2773 * Enables bus-mastering on the device and calls pcibios_set_master()
2774 * to do the needed arch specific settings.
2776 void pci_set_master(struct pci_dev *dev)
2778 __pci_set_master(dev, true);
2779 pcibios_set_master(dev);
2781 EXPORT_SYMBOL(pci_set_master);
2784 * pci_clear_master - disables bus-mastering for device dev
2785 * @dev: the PCI device to disable
2787 void pci_clear_master(struct pci_dev *dev)
2789 __pci_set_master(dev, false);
2791 EXPORT_SYMBOL(pci_clear_master);
2794 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
2795 * @dev: the PCI device for which MWI is to be enabled
2797 * Helper function for pci_set_mwi.
2798 * Originally copied from drivers/net/acenic.c.
2799 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
2801 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2803 int pci_set_cacheline_size(struct pci_dev *dev)
2807 if (!pci_cache_line_size)
2810 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
2811 equal to or multiple of the right value. */
2812 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
2813 if (cacheline_size >= pci_cache_line_size &&
2814 (cacheline_size % pci_cache_line_size) == 0)
2817 /* Write the correct value. */
2818 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
2820 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
2821 if (cacheline_size == pci_cache_line_size)
2824 dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not "
2825 "supported\n", pci_cache_line_size << 2);
2829 EXPORT_SYMBOL_GPL(pci_set_cacheline_size);
2832 * pci_set_mwi - enables memory-write-invalidate PCI transaction
2833 * @dev: the PCI device for which MWI is enabled
2835 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
2837 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2840 pci_set_mwi(struct pci_dev *dev)
2842 #ifdef PCI_DISABLE_MWI
2848 rc = pci_set_cacheline_size(dev);
2852 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2853 if (! (cmd & PCI_COMMAND_INVALIDATE)) {
2854 dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n");
2855 cmd |= PCI_COMMAND_INVALIDATE;
2856 pci_write_config_word(dev, PCI_COMMAND, cmd);
2861 EXPORT_SYMBOL(pci_set_mwi);
2864 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
2865 * @dev: the PCI device for which MWI is enabled
2867 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
2868 * Callers are not required to check the return value.
2870 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
2872 int pci_try_set_mwi(struct pci_dev *dev)
2874 #ifdef PCI_DISABLE_MWI
2877 return pci_set_mwi(dev);
2880 EXPORT_SYMBOL(pci_try_set_mwi);
2883 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
2884 * @dev: the PCI device to disable
2886 * Disables PCI Memory-Write-Invalidate transaction on the device
2889 pci_clear_mwi(struct pci_dev *dev)
2891 #ifndef PCI_DISABLE_MWI
2894 pci_read_config_word(dev, PCI_COMMAND, &cmd);
2895 if (cmd & PCI_COMMAND_INVALIDATE) {
2896 cmd &= ~PCI_COMMAND_INVALIDATE;
2897 pci_write_config_word(dev, PCI_COMMAND, cmd);
2901 EXPORT_SYMBOL(pci_clear_mwi);
2904 * pci_intx - enables/disables PCI INTx for device dev
2905 * @pdev: the PCI device to operate on
2906 * @enable: boolean: whether to enable or disable PCI INTx
2908 * Enables/disables PCI INTx for device dev
2911 pci_intx(struct pci_dev *pdev, int enable)
2913 u16 pci_command, new;
2915 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
2918 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
2920 new = pci_command | PCI_COMMAND_INTX_DISABLE;
2923 if (new != pci_command) {
2924 struct pci_devres *dr;
2926 pci_write_config_word(pdev, PCI_COMMAND, new);
2928 dr = find_pci_dr(pdev);
2929 if (dr && !dr->restore_intx) {
2930 dr->restore_intx = 1;
2931 dr->orig_intx = !enable;
2935 EXPORT_SYMBOL_GPL(pci_intx);
2938 * pci_intx_mask_supported - probe for INTx masking support
2939 * @dev: the PCI device to operate on
2941 * Check if the device dev support INTx masking via the config space
2944 bool pci_intx_mask_supported(struct pci_dev *dev)
2946 bool mask_supported = false;
2949 if (dev->broken_intx_masking)
2952 pci_cfg_access_lock(dev);
2954 pci_read_config_word(dev, PCI_COMMAND, &orig);
2955 pci_write_config_word(dev, PCI_COMMAND,
2956 orig ^ PCI_COMMAND_INTX_DISABLE);
2957 pci_read_config_word(dev, PCI_COMMAND, &new);
2960 * There's no way to protect against hardware bugs or detect them
2961 * reliably, but as long as we know what the value should be, let's
2962 * go ahead and check it.
2964 if ((new ^ orig) & ~PCI_COMMAND_INTX_DISABLE) {
2965 dev_err(&dev->dev, "Command register changed from "
2966 "0x%x to 0x%x: driver or hardware bug?\n", orig, new);
2967 } else if ((new ^ orig) & PCI_COMMAND_INTX_DISABLE) {
2968 mask_supported = true;
2969 pci_write_config_word(dev, PCI_COMMAND, orig);
2972 pci_cfg_access_unlock(dev);
2973 return mask_supported;
2975 EXPORT_SYMBOL_GPL(pci_intx_mask_supported);
2977 static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask)
2979 struct pci_bus *bus = dev->bus;
2980 bool mask_updated = true;
2981 u32 cmd_status_dword;
2982 u16 origcmd, newcmd;
2983 unsigned long flags;
2987 * We do a single dword read to retrieve both command and status.
2988 * Document assumptions that make this possible.
2990 BUILD_BUG_ON(PCI_COMMAND % 4);
2991 BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS);
2993 raw_spin_lock_irqsave(&pci_lock, flags);
2995 bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword);
2997 irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT;
3000 * Check interrupt status register to see whether our device
3001 * triggered the interrupt (when masking) or the next IRQ is
3002 * already pending (when unmasking).
3004 if (mask != irq_pending) {
3005 mask_updated = false;
3009 origcmd = cmd_status_dword;
3010 newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE;
3012 newcmd |= PCI_COMMAND_INTX_DISABLE;
3013 if (newcmd != origcmd)
3014 bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd);
3017 raw_spin_unlock_irqrestore(&pci_lock, flags);
3019 return mask_updated;
3023 * pci_check_and_mask_intx - mask INTx on pending interrupt
3024 * @dev: the PCI device to operate on
3026 * Check if the device dev has its INTx line asserted, mask it and
3027 * return true in that case. False is returned if not interrupt was
3030 bool pci_check_and_mask_intx(struct pci_dev *dev)
3032 return pci_check_and_set_intx_mask(dev, true);
3034 EXPORT_SYMBOL_GPL(pci_check_and_mask_intx);
3037 * pci_check_and_unmask_intx - unmask INTx if no interrupt is pending
3038 * @dev: the PCI device to operate on
3040 * Check if the device dev has its INTx line asserted, unmask it if not
3041 * and return true. False is returned and the mask remains active if
3042 * there was still an interrupt pending.
3044 bool pci_check_and_unmask_intx(struct pci_dev *dev)
3046 return pci_check_and_set_intx_mask(dev, false);
3048 EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx);
3051 * pci_msi_off - disables any MSI or MSI-X capabilities
3052 * @dev: the PCI device to operate on
3054 * If you want to use MSI, see pci_enable_msi() and friends.
3055 * This is a lower-level primitive that allows us to disable
3056 * MSI operation at the device level.
3058 void pci_msi_off(struct pci_dev *dev)
3064 * This looks like it could go in msi.c, but we need it even when
3065 * CONFIG_PCI_MSI=n. For the same reason, we can't use
3066 * dev->msi_cap or dev->msix_cap here.
3068 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
3070 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
3071 control &= ~PCI_MSI_FLAGS_ENABLE;
3072 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
3074 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
3076 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
3077 control &= ~PCI_MSIX_FLAGS_ENABLE;
3078 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
3081 EXPORT_SYMBOL_GPL(pci_msi_off);
3083 int pci_set_dma_max_seg_size(struct pci_dev *dev, unsigned int size)
3085 return dma_set_max_seg_size(&dev->dev, size);
3087 EXPORT_SYMBOL(pci_set_dma_max_seg_size);
3089 int pci_set_dma_seg_boundary(struct pci_dev *dev, unsigned long mask)
3091 return dma_set_seg_boundary(&dev->dev, mask);
3093 EXPORT_SYMBOL(pci_set_dma_seg_boundary);
3096 * pci_wait_for_pending_transaction - waits for pending transaction
3097 * @dev: the PCI device to operate on
3099 * Return 0 if transaction is pending 1 otherwise.
3101 int pci_wait_for_pending_transaction(struct pci_dev *dev)
3103 if (!pci_is_pcie(dev))
3106 return pci_wait_for_pending(dev, PCI_EXP_DEVSTA, PCI_EXP_DEVSTA_TRPND);
3108 EXPORT_SYMBOL(pci_wait_for_pending_transaction);
3110 static int pcie_flr(struct pci_dev *dev, int probe)
3114 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
3115 if (!(cap & PCI_EXP_DEVCAP_FLR))
3121 if (!pci_wait_for_pending_transaction(dev))
3122 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
3124 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
3131 static int pci_af_flr(struct pci_dev *dev, int probe)
3136 pos = pci_find_capability(dev, PCI_CAP_ID_AF);
3140 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
3141 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
3147 /* Wait for Transaction Pending bit clean */
3148 if (pci_wait_for_pending(dev, PCI_AF_STATUS, PCI_AF_STATUS_TP))
3151 dev_err(&dev->dev, "transaction is not cleared; "
3152 "proceeding with reset anyway\n");
3155 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
3162 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
3163 * @dev: Device to reset.
3164 * @probe: If set, only check if the device can be reset this way.
3166 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
3167 * unset, it will be reinitialized internally when going from PCI_D3hot to
3168 * PCI_D0. If that's the case and the device is not in a low-power state
3169 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
3171 * NOTE: This causes the caller to sleep for twice the device power transition
3172 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
3173 * by default (i.e. unless the @dev's d3_delay field has a different value).
3174 * Moreover, only devices in D0 can be reset by this function.
3176 static int pci_pm_reset(struct pci_dev *dev, int probe)
3183 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
3184 if (csr & PCI_PM_CTRL_NO_SOFT_RESET)
3190 if (dev->current_state != PCI_D0)
3193 csr &= ~PCI_PM_CTRL_STATE_MASK;
3195 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
3196 pci_dev_d3_sleep(dev);
3198 csr &= ~PCI_PM_CTRL_STATE_MASK;
3200 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
3201 pci_dev_d3_sleep(dev);
3207 * pci_reset_bridge_secondary_bus - Reset the secondary bus on a PCI bridge.
3208 * @dev: Bridge device
3210 * Use the bridge control register to assert reset on the secondary bus.
3211 * Devices on the secondary bus are left in power-on state.
3213 void pci_reset_bridge_secondary_bus(struct pci_dev *dev)
3217 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl);
3218 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
3219 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
3221 * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double
3222 * this to 2ms to ensure that we meet the minimum requirement.
3226 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
3227 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
3230 * Trhfa for conventional PCI is 2^25 clock cycles.
3231 * Assuming a minimum 33MHz clock this results in a 1s
3232 * delay before we can consider subordinate devices to
3233 * be re-initialized. PCIe has some ways to shorten this,
3234 * but we don't make use of them yet.
3238 EXPORT_SYMBOL_GPL(pci_reset_bridge_secondary_bus);
3240 static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
3242 struct pci_dev *pdev;
3244 if (pci_is_root_bus(dev->bus) || dev->subordinate || !dev->bus->self)
3247 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
3254 pci_reset_bridge_secondary_bus(dev->bus->self);
3259 static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, int probe)
3263 if (!hotplug || !try_module_get(hotplug->ops->owner))
3266 if (hotplug->ops->reset_slot)
3267 rc = hotplug->ops->reset_slot(hotplug, probe);
3269 module_put(hotplug->ops->owner);
3274 static int pci_dev_reset_slot_function(struct pci_dev *dev, int probe)
3276 struct pci_dev *pdev;
3278 if (dev->subordinate || !dev->slot)
3281 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
3282 if (pdev != dev && pdev->slot == dev->slot)
3285 return pci_reset_hotplug_slot(dev->slot->hotplug, probe);
3288 static int __pci_dev_reset(struct pci_dev *dev, int probe)
3294 rc = pci_dev_specific_reset(dev, probe);
3298 rc = pcie_flr(dev, probe);
3302 rc = pci_af_flr(dev, probe);
3306 rc = pci_pm_reset(dev, probe);
3310 rc = pci_dev_reset_slot_function(dev, probe);
3314 rc = pci_parent_bus_reset(dev, probe);
3319 static void pci_dev_lock(struct pci_dev *dev)
3321 pci_cfg_access_lock(dev);
3322 /* block PM suspend, driver probe, etc. */
3323 device_lock(&dev->dev);
3326 /* Return 1 on successful lock, 0 on contention */
3327 static int pci_dev_trylock(struct pci_dev *dev)
3329 if (pci_cfg_access_trylock(dev)) {
3330 if (device_trylock(&dev->dev))
3332 pci_cfg_access_unlock(dev);
3338 static void pci_dev_unlock(struct pci_dev *dev)
3340 device_unlock(&dev->dev);
3341 pci_cfg_access_unlock(dev);
3345 * pci_reset_notify - notify device driver of reset
3346 * @dev: device to be notified of reset
3347 * @prepare: 'true' if device is about to be reset; 'false' if reset attempt
3350 * Must be called prior to device access being disabled and after device
3351 * access is restored.
3353 static void pci_reset_notify(struct pci_dev *dev, bool prepare)
3355 const struct pci_error_handlers *err_handler =
3356 dev->driver ? dev->driver->err_handler : NULL;
3357 if (err_handler && err_handler->reset_notify)
3358 err_handler->reset_notify(dev, prepare);
3361 static void pci_dev_save_and_disable(struct pci_dev *dev)
3363 pci_reset_notify(dev, true);
3366 * Wake-up device prior to save. PM registers default to D0 after
3367 * reset and a simple register restore doesn't reliably return
3368 * to a non-D0 state anyway.
3370 pci_set_power_state(dev, PCI_D0);
3372 pci_save_state(dev);
3374 * Disable the device by clearing the Command register, except for
3375 * INTx-disable which is set. This not only disables MMIO and I/O port
3376 * BARs, but also prevents the device from being Bus Master, preventing
3377 * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3
3378 * compliant devices, INTx-disable prevents legacy interrupts.
3380 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
3383 static void pci_dev_restore(struct pci_dev *dev)
3385 pci_restore_state(dev);
3386 pci_reset_notify(dev, false);
3389 static int pci_dev_reset(struct pci_dev *dev, int probe)
3396 rc = __pci_dev_reset(dev, probe);
3399 pci_dev_unlock(dev);
3405 * __pci_reset_function - reset a PCI device function
3406 * @dev: PCI device to reset
3408 * Some devices allow an individual function to be reset without affecting
3409 * other functions in the same device. The PCI device must be responsive
3410 * to PCI config space in order to use this function.
3412 * The device function is presumed to be unused when this function is called.
3413 * Resetting the device will make the contents of PCI configuration space
3414 * random, so any caller of this must be prepared to reinitialise the
3415 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
3418 * Returns 0 if the device function was successfully reset or negative if the
3419 * device doesn't support resetting a single function.
3421 int __pci_reset_function(struct pci_dev *dev)
3423 return pci_dev_reset(dev, 0);
3425 EXPORT_SYMBOL_GPL(__pci_reset_function);
3428 * __pci_reset_function_locked - reset a PCI device function while holding
3429 * the @dev mutex lock.
3430 * @dev: PCI device to reset
3432 * Some devices allow an individual function to be reset without affecting
3433 * other functions in the same device. The PCI device must be responsive
3434 * to PCI config space in order to use this function.
3436 * The device function is presumed to be unused and the caller is holding
3437 * the device mutex lock when this function is called.
3438 * Resetting the device will make the contents of PCI configuration space
3439 * random, so any caller of this must be prepared to reinitialise the
3440 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
3443 * Returns 0 if the device function was successfully reset or negative if the
3444 * device doesn't support resetting a single function.
3446 int __pci_reset_function_locked(struct pci_dev *dev)
3448 return __pci_dev_reset(dev, 0);
3450 EXPORT_SYMBOL_GPL(__pci_reset_function_locked);
3453 * pci_probe_reset_function - check whether the device can be safely reset
3454 * @dev: PCI device to reset
3456 * Some devices allow an individual function to be reset without affecting
3457 * other functions in the same device. The PCI device must be responsive
3458 * to PCI config space in order to use this function.
3460 * Returns 0 if the device function can be reset or negative if the
3461 * device doesn't support resetting a single function.
3463 int pci_probe_reset_function(struct pci_dev *dev)
3465 return pci_dev_reset(dev, 1);
3469 * pci_reset_function - quiesce and reset a PCI device function
3470 * @dev: PCI device to reset
3472 * Some devices allow an individual function to be reset without affecting
3473 * other functions in the same device. The PCI device must be responsive
3474 * to PCI config space in order to use this function.
3476 * This function does not just reset the PCI portion of a device, but
3477 * clears all the state associated with the device. This function differs
3478 * from __pci_reset_function in that it saves and restores device state
3481 * Returns 0 if the device function was successfully reset or negative if the
3482 * device doesn't support resetting a single function.
3484 int pci_reset_function(struct pci_dev *dev)
3488 rc = pci_dev_reset(dev, 1);
3492 pci_dev_save_and_disable(dev);
3494 rc = pci_dev_reset(dev, 0);
3496 pci_dev_restore(dev);
3500 EXPORT_SYMBOL_GPL(pci_reset_function);
3503 * pci_try_reset_function - quiesce and reset a PCI device function
3504 * @dev: PCI device to reset
3506 * Same as above, except return -EAGAIN if unable to lock device.
3508 int pci_try_reset_function(struct pci_dev *dev)
3512 rc = pci_dev_reset(dev, 1);
3516 pci_dev_save_and_disable(dev);
3518 if (pci_dev_trylock(dev)) {
3519 rc = __pci_dev_reset(dev, 0);
3520 pci_dev_unlock(dev);
3524 pci_dev_restore(dev);
3528 EXPORT_SYMBOL_GPL(pci_try_reset_function);
3530 /* Lock devices from the top of the tree down */
3531 static void pci_bus_lock(struct pci_bus *bus)
3533 struct pci_dev *dev;
3535 list_for_each_entry(dev, &bus->devices, bus_list) {
3537 if (dev->subordinate)
3538 pci_bus_lock(dev->subordinate);
3542 /* Unlock devices from the bottom of the tree up */
3543 static void pci_bus_unlock(struct pci_bus *bus)
3545 struct pci_dev *dev;
3547 list_for_each_entry(dev, &bus->devices, bus_list) {
3548 if (dev->subordinate)
3549 pci_bus_unlock(dev->subordinate);
3550 pci_dev_unlock(dev);
3554 /* Return 1 on successful lock, 0 on contention */
3555 static int pci_bus_trylock(struct pci_bus *bus)
3557 struct pci_dev *dev;
3559 list_for_each_entry(dev, &bus->devices, bus_list) {
3560 if (!pci_dev_trylock(dev))
3562 if (dev->subordinate) {
3563 if (!pci_bus_trylock(dev->subordinate)) {
3564 pci_dev_unlock(dev);
3572 list_for_each_entry_continue_reverse(dev, &bus->devices, bus_list) {
3573 if (dev->subordinate)
3574 pci_bus_unlock(dev->subordinate);
3575 pci_dev_unlock(dev);
3580 /* Lock devices from the top of the tree down */
3581 static void pci_slot_lock(struct pci_slot *slot)
3583 struct pci_dev *dev;
3585 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
3586 if (!dev->slot || dev->slot != slot)
3589 if (dev->subordinate)
3590 pci_bus_lock(dev->subordinate);
3594 /* Unlock devices from the bottom of the tree up */
3595 static void pci_slot_unlock(struct pci_slot *slot)
3597 struct pci_dev *dev;
3599 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
3600 if (!dev->slot || dev->slot != slot)
3602 if (dev->subordinate)
3603 pci_bus_unlock(dev->subordinate);
3604 pci_dev_unlock(dev);
3608 /* Return 1 on successful lock, 0 on contention */
3609 static int pci_slot_trylock(struct pci_slot *slot)
3611 struct pci_dev *dev;
3613 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
3614 if (!dev->slot || dev->slot != slot)
3616 if (!pci_dev_trylock(dev))
3618 if (dev->subordinate) {
3619 if (!pci_bus_trylock(dev->subordinate)) {
3620 pci_dev_unlock(dev);
3628 list_for_each_entry_continue_reverse(dev,
3629 &slot->bus->devices, bus_list) {
3630 if (!dev->slot || dev->slot != slot)
3632 if (dev->subordinate)
3633 pci_bus_unlock(dev->subordinate);
3634 pci_dev_unlock(dev);
3639 /* Save and disable devices from the top of the tree down */
3640 static void pci_bus_save_and_disable(struct pci_bus *bus)
3642 struct pci_dev *dev;
3644 list_for_each_entry(dev, &bus->devices, bus_list) {
3645 pci_dev_save_and_disable(dev);
3646 if (dev->subordinate)
3647 pci_bus_save_and_disable(dev->subordinate);
3652 * Restore devices from top of the tree down - parent bridges need to be
3653 * restored before we can get to subordinate devices.
3655 static void pci_bus_restore(struct pci_bus *bus)
3657 struct pci_dev *dev;
3659 list_for_each_entry(dev, &bus->devices, bus_list) {
3660 pci_dev_restore(dev);
3661 if (dev->subordinate)
3662 pci_bus_restore(dev->subordinate);
3666 /* Save and disable devices from the top of the tree down */
3667 static void pci_slot_save_and_disable(struct pci_slot *slot)
3669 struct pci_dev *dev;
3671 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
3672 if (!dev->slot || dev->slot != slot)
3674 pci_dev_save_and_disable(dev);
3675 if (dev->subordinate)
3676 pci_bus_save_and_disable(dev->subordinate);
3681 * Restore devices from top of the tree down - parent bridges need to be
3682 * restored before we can get to subordinate devices.
3684 static void pci_slot_restore(struct pci_slot *slot)
3686 struct pci_dev *dev;
3688 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
3689 if (!dev->slot || dev->slot != slot)
3691 pci_dev_restore(dev);
3692 if (dev->subordinate)
3693 pci_bus_restore(dev->subordinate);
3697 static int pci_slot_reset(struct pci_slot *slot, int probe)
3705 pci_slot_lock(slot);
3709 rc = pci_reset_hotplug_slot(slot->hotplug, probe);
3712 pci_slot_unlock(slot);
3718 * pci_probe_reset_slot - probe whether a PCI slot can be reset
3719 * @slot: PCI slot to probe
3721 * Return 0 if slot can be reset, negative if a slot reset is not supported.
3723 int pci_probe_reset_slot(struct pci_slot *slot)
3725 return pci_slot_reset(slot, 1);
3727 EXPORT_SYMBOL_GPL(pci_probe_reset_slot);
3730 * pci_reset_slot - reset a PCI slot
3731 * @slot: PCI slot to reset
3733 * A PCI bus may host multiple slots, each slot may support a reset mechanism
3734 * independent of other slots. For instance, some slots may support slot power
3735 * control. In the case of a 1:1 bus to slot architecture, this function may
3736 * wrap the bus reset to avoid spurious slot related events such as hotplug.
3737 * Generally a slot reset should be attempted before a bus reset. All of the
3738 * function of the slot and any subordinate buses behind the slot are reset
3739 * through this function. PCI config space of all devices in the slot and
3740 * behind the slot is saved before and restored after reset.
3742 * Return 0 on success, non-zero on error.
3744 int pci_reset_slot(struct pci_slot *slot)
3748 rc = pci_slot_reset(slot, 1);
3752 pci_slot_save_and_disable(slot);
3754 rc = pci_slot_reset(slot, 0);
3756 pci_slot_restore(slot);
3760 EXPORT_SYMBOL_GPL(pci_reset_slot);
3763 * pci_try_reset_slot - Try to reset a PCI slot
3764 * @slot: PCI slot to reset
3766 * Same as above except return -EAGAIN if the slot cannot be locked
3768 int pci_try_reset_slot(struct pci_slot *slot)
3772 rc = pci_slot_reset(slot, 1);
3776 pci_slot_save_and_disable(slot);
3778 if (pci_slot_trylock(slot)) {
3780 rc = pci_reset_hotplug_slot(slot->hotplug, 0);
3781 pci_slot_unlock(slot);
3785 pci_slot_restore(slot);
3789 EXPORT_SYMBOL_GPL(pci_try_reset_slot);
3791 static int pci_bus_reset(struct pci_bus *bus, int probe)
3803 pci_reset_bridge_secondary_bus(bus->self);
3805 pci_bus_unlock(bus);
3811 * pci_probe_reset_bus - probe whether a PCI bus can be reset
3812 * @bus: PCI bus to probe
3814 * Return 0 if bus can be reset, negative if a bus reset is not supported.
3816 int pci_probe_reset_bus(struct pci_bus *bus)
3818 return pci_bus_reset(bus, 1);
3820 EXPORT_SYMBOL_GPL(pci_probe_reset_bus);
3823 * pci_reset_bus - reset a PCI bus
3824 * @bus: top level PCI bus to reset
3826 * Do a bus reset on the given bus and any subordinate buses, saving
3827 * and restoring state of all devices.
3829 * Return 0 on success, non-zero on error.
3831 int pci_reset_bus(struct pci_bus *bus)
3835 rc = pci_bus_reset(bus, 1);
3839 pci_bus_save_and_disable(bus);
3841 rc = pci_bus_reset(bus, 0);
3843 pci_bus_restore(bus);
3847 EXPORT_SYMBOL_GPL(pci_reset_bus);
3850 * pci_try_reset_bus - Try to reset a PCI bus
3851 * @bus: top level PCI bus to reset
3853 * Same as above except return -EAGAIN if the bus cannot be locked
3855 int pci_try_reset_bus(struct pci_bus *bus)
3859 rc = pci_bus_reset(bus, 1);
3863 pci_bus_save_and_disable(bus);
3865 if (pci_bus_trylock(bus)) {
3867 pci_reset_bridge_secondary_bus(bus->self);
3868 pci_bus_unlock(bus);
3872 pci_bus_restore(bus);
3876 EXPORT_SYMBOL_GPL(pci_try_reset_bus);
3879 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
3880 * @dev: PCI device to query
3882 * Returns mmrbc: maximum designed memory read count in bytes
3883 * or appropriate error value.
3885 int pcix_get_max_mmrbc(struct pci_dev *dev)
3890 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
3894 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
3897 return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21);
3899 EXPORT_SYMBOL(pcix_get_max_mmrbc);
3902 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
3903 * @dev: PCI device to query
3905 * Returns mmrbc: maximum memory read count in bytes
3906 * or appropriate error value.
3908 int pcix_get_mmrbc(struct pci_dev *dev)
3913 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
3917 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
3920 return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
3922 EXPORT_SYMBOL(pcix_get_mmrbc);
3925 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
3926 * @dev: PCI device to query
3927 * @mmrbc: maximum memory read count in bytes
3928 * valid values are 512, 1024, 2048, 4096
3930 * If possible sets maximum memory read byte count, some bridges have erratas
3931 * that prevent this.
3933 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
3939 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
3942 v = ffs(mmrbc) - 10;
3944 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
3948 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
3951 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
3954 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
3957 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
3959 if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
3962 cmd &= ~PCI_X_CMD_MAX_READ;
3964 if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd))
3969 EXPORT_SYMBOL(pcix_set_mmrbc);
3972 * pcie_get_readrq - get PCI Express read request size
3973 * @dev: PCI device to query
3975 * Returns maximum memory read request in bytes
3976 * or appropriate error value.
3978 int pcie_get_readrq(struct pci_dev *dev)
3982 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
3984 return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
3986 EXPORT_SYMBOL(pcie_get_readrq);
3989 * pcie_set_readrq - set PCI Express maximum memory read request
3990 * @dev: PCI device to query
3991 * @rq: maximum memory read count in bytes
3992 * valid values are 128, 256, 512, 1024, 2048, 4096
3994 * If possible sets maximum memory read request in bytes
3996 int pcie_set_readrq(struct pci_dev *dev, int rq)
4000 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
4004 * If using the "performance" PCIe config, we clamp the
4005 * read rq size to the max packet size to prevent the
4006 * host bridge generating requests larger than we can
4009 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
4010 int mps = pcie_get_mps(dev);
4016 v = (ffs(rq) - 8) << 12;
4018 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
4019 PCI_EXP_DEVCTL_READRQ, v);
4021 EXPORT_SYMBOL(pcie_set_readrq);
4024 * pcie_get_mps - get PCI Express maximum payload size
4025 * @dev: PCI device to query
4027 * Returns maximum payload size in bytes
4029 int pcie_get_mps(struct pci_dev *dev)
4033 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
4035 return 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
4037 EXPORT_SYMBOL(pcie_get_mps);
4040 * pcie_set_mps - set PCI Express maximum payload size
4041 * @dev: PCI device to query
4042 * @mps: maximum payload size in bytes
4043 * valid values are 128, 256, 512, 1024, 2048, 4096
4045 * If possible sets maximum payload size
4047 int pcie_set_mps(struct pci_dev *dev, int mps)
4051 if (mps < 128 || mps > 4096 || !is_power_of_2(mps))
4055 if (v > dev->pcie_mpss)
4059 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
4060 PCI_EXP_DEVCTL_PAYLOAD, v);
4062 EXPORT_SYMBOL(pcie_set_mps);
4065 * pcie_get_minimum_link - determine minimum link settings of a PCI device
4066 * @dev: PCI device to query
4067 * @speed: storage for minimum speed
4068 * @width: storage for minimum width
4070 * This function will walk up the PCI device chain and determine the minimum
4071 * link width and speed of the device.
4073 int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed,
4074 enum pcie_link_width *width)
4078 *speed = PCI_SPEED_UNKNOWN;
4079 *width = PCIE_LNK_WIDTH_UNKNOWN;
4083 enum pci_bus_speed next_speed;
4084 enum pcie_link_width next_width;
4086 ret = pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta);
4090 next_speed = pcie_link_speed[lnksta & PCI_EXP_LNKSTA_CLS];
4091 next_width = (lnksta & PCI_EXP_LNKSTA_NLW) >>
4092 PCI_EXP_LNKSTA_NLW_SHIFT;
4094 if (next_speed < *speed)
4095 *speed = next_speed;
4097 if (next_width < *width)
4098 *width = next_width;
4100 dev = dev->bus->self;
4105 EXPORT_SYMBOL(pcie_get_minimum_link);
4108 * pci_select_bars - Make BAR mask from the type of resource
4109 * @dev: the PCI device for which BAR mask is made
4110 * @flags: resource type mask to be selected
4112 * This helper routine makes bar mask from the type of resource.
4114 int pci_select_bars(struct pci_dev *dev, unsigned long flags)
4117 for (i = 0; i < PCI_NUM_RESOURCES; i++)
4118 if (pci_resource_flags(dev, i) & flags)
4122 EXPORT_SYMBOL(pci_select_bars);
4125 * pci_resource_bar - get position of the BAR associated with a resource
4126 * @dev: the PCI device
4127 * @resno: the resource number
4128 * @type: the BAR type to be filled in
4130 * Returns BAR position in config space, or 0 if the BAR is invalid.
4132 int pci_resource_bar(struct pci_dev *dev, int resno, enum pci_bar_type *type)
4136 if (resno < PCI_ROM_RESOURCE) {
4137 *type = pci_bar_unknown;
4138 return PCI_BASE_ADDRESS_0 + 4 * resno;
4139 } else if (resno == PCI_ROM_RESOURCE) {
4140 *type = pci_bar_mem32;
4141 return dev->rom_base_reg;
4142 } else if (resno < PCI_BRIDGE_RESOURCES) {
4143 /* device specific resource */
4144 reg = pci_iov_resource_bar(dev, resno, type);
4149 dev_err(&dev->dev, "BAR %d: invalid resource\n", resno);
4153 /* Some architectures require additional programming to enable VGA */
4154 static arch_set_vga_state_t arch_set_vga_state;
4156 void __init pci_register_set_vga_state(arch_set_vga_state_t func)
4158 arch_set_vga_state = func; /* NULL disables */
4161 static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode,
4162 unsigned int command_bits, u32 flags)
4164 if (arch_set_vga_state)
4165 return arch_set_vga_state(dev, decode, command_bits,
4171 * pci_set_vga_state - set VGA decode state on device and parents if requested
4172 * @dev: the PCI device
4173 * @decode: true = enable decoding, false = disable decoding
4174 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
4175 * @flags: traverse ancestors and change bridges
4176 * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE
4178 int pci_set_vga_state(struct pci_dev *dev, bool decode,
4179 unsigned int command_bits, u32 flags)
4181 struct pci_bus *bus;
4182 struct pci_dev *bridge;
4186 WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) && (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY)));
4188 /* ARCH specific VGA enables */
4189 rc = pci_set_vga_state_arch(dev, decode, command_bits, flags);
4193 if (flags & PCI_VGA_STATE_CHANGE_DECODES) {
4194 pci_read_config_word(dev, PCI_COMMAND, &cmd);
4196 cmd |= command_bits;
4198 cmd &= ~command_bits;
4199 pci_write_config_word(dev, PCI_COMMAND, cmd);
4202 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
4209 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
4212 cmd |= PCI_BRIDGE_CTL_VGA;
4214 cmd &= ~PCI_BRIDGE_CTL_VGA;
4215 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL,
4223 bool pci_device_is_present(struct pci_dev *pdev)
4227 return pci_bus_read_dev_vendor_id(pdev->bus, pdev->devfn, &v, 0);
4229 EXPORT_SYMBOL_GPL(pci_device_is_present);
4231 #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
4232 static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0};
4233 static DEFINE_SPINLOCK(resource_alignment_lock);
4236 * pci_specified_resource_alignment - get resource alignment specified by user.
4237 * @dev: the PCI device to get
4239 * RETURNS: Resource alignment if it is specified.
4240 * Zero if it is not specified.
4242 static resource_size_t pci_specified_resource_alignment(struct pci_dev *dev)
4244 int seg, bus, slot, func, align_order, count;
4245 resource_size_t align = 0;
4248 spin_lock(&resource_alignment_lock);
4249 p = resource_alignment_param;
4252 if (sscanf(p, "%d%n", &align_order, &count) == 1 &&
4258 if (sscanf(p, "%x:%x:%x.%x%n",
4259 &seg, &bus, &slot, &func, &count) != 4) {
4261 if (sscanf(p, "%x:%x.%x%n",
4262 &bus, &slot, &func, &count) != 3) {
4263 /* Invalid format */
4264 printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: %s\n",
4270 if (seg == pci_domain_nr(dev->bus) &&
4271 bus == dev->bus->number &&
4272 slot == PCI_SLOT(dev->devfn) &&
4273 func == PCI_FUNC(dev->devfn)) {
4274 if (align_order == -1) {
4277 align = 1 << align_order;
4282 if (*p != ';' && *p != ',') {
4283 /* End of param or invalid format */
4288 spin_unlock(&resource_alignment_lock);
4293 * This function disables memory decoding and releases memory resources
4294 * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
4295 * It also rounds up size to specified alignment.
4296 * Later on, the kernel will assign page-aligned memory resource back
4299 void pci_reassigndev_resource_alignment(struct pci_dev *dev)
4303 resource_size_t align, size;
4306 /* check if specified PCI is target device to reassign */
4307 align = pci_specified_resource_alignment(dev);
4311 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
4312 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
4314 "Can't reassign resources to host bridge.\n");
4319 "Disabling memory decoding and releasing memory resources.\n");
4320 pci_read_config_word(dev, PCI_COMMAND, &command);
4321 command &= ~PCI_COMMAND_MEMORY;
4322 pci_write_config_word(dev, PCI_COMMAND, command);
4324 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) {
4325 r = &dev->resource[i];
4326 if (!(r->flags & IORESOURCE_MEM))
4328 size = resource_size(r);
4332 "Rounding up size of resource #%d to %#llx.\n",
4333 i, (unsigned long long)size);
4335 r->flags |= IORESOURCE_UNSET;
4339 /* Need to disable bridge's resource window,
4340 * to enable the kernel to reassign new resource
4343 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
4344 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
4345 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
4346 r = &dev->resource[i];
4347 if (!(r->flags & IORESOURCE_MEM))
4349 r->flags |= IORESOURCE_UNSET;
4350 r->end = resource_size(r) - 1;
4353 pci_disable_bridge_window(dev);
4357 static ssize_t pci_set_resource_alignment_param(const char *buf, size_t count)
4359 if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1)
4360 count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1;
4361 spin_lock(&resource_alignment_lock);
4362 strncpy(resource_alignment_param, buf, count);
4363 resource_alignment_param[count] = '\0';
4364 spin_unlock(&resource_alignment_lock);
4368 static ssize_t pci_get_resource_alignment_param(char *buf, size_t size)
4371 spin_lock(&resource_alignment_lock);
4372 count = snprintf(buf, size, "%s", resource_alignment_param);
4373 spin_unlock(&resource_alignment_lock);
4377 static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf)
4379 return pci_get_resource_alignment_param(buf, PAGE_SIZE);
4382 static ssize_t pci_resource_alignment_store(struct bus_type *bus,
4383 const char *buf, size_t count)
4385 return pci_set_resource_alignment_param(buf, count);
4388 BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show,
4389 pci_resource_alignment_store);
4391 static int __init pci_resource_alignment_sysfs_init(void)
4393 return bus_create_file(&pci_bus_type,
4394 &bus_attr_resource_alignment);
4397 late_initcall(pci_resource_alignment_sysfs_init);
4399 static void pci_no_domains(void)
4401 #ifdef CONFIG_PCI_DOMAINS
4402 pci_domains_supported = 0;
4407 * pci_ext_cfg_avail - can we access extended PCI config space?
4409 * Returns 1 if we can access PCI extended config space (offsets
4410 * greater than 0xff). This is the default implementation. Architecture
4411 * implementations can override this.
4413 int __weak pci_ext_cfg_avail(void)
4418 void __weak pci_fixup_cardbus(struct pci_bus *bus)
4421 EXPORT_SYMBOL(pci_fixup_cardbus);
4423 static int __init pci_setup(char *str)
4426 char *k = strchr(str, ',');
4429 if (*str && (str = pcibios_setup(str)) && *str) {
4430 if (!strcmp(str, "nomsi")) {
4432 } else if (!strcmp(str, "noaer")) {
4434 } else if (!strncmp(str, "realloc=", 8)) {
4435 pci_realloc_get_opt(str + 8);
4436 } else if (!strncmp(str, "realloc", 7)) {
4437 pci_realloc_get_opt("on");
4438 } else if (!strcmp(str, "nodomains")) {
4440 } else if (!strncmp(str, "noari", 5)) {
4441 pcie_ari_disabled = true;
4442 } else if (!strncmp(str, "cbiosize=", 9)) {
4443 pci_cardbus_io_size = memparse(str + 9, &str);
4444 } else if (!strncmp(str, "cbmemsize=", 10)) {
4445 pci_cardbus_mem_size = memparse(str + 10, &str);
4446 } else if (!strncmp(str, "resource_alignment=", 19)) {
4447 pci_set_resource_alignment_param(str + 19,
4449 } else if (!strncmp(str, "ecrc=", 5)) {
4450 pcie_ecrc_get_policy(str + 5);
4451 } else if (!strncmp(str, "hpiosize=", 9)) {
4452 pci_hotplug_io_size = memparse(str + 9, &str);
4453 } else if (!strncmp(str, "hpmemsize=", 10)) {
4454 pci_hotplug_mem_size = memparse(str + 10, &str);
4455 } else if (!strncmp(str, "pcie_bus_tune_off", 17)) {
4456 pcie_bus_config = PCIE_BUS_TUNE_OFF;
4457 } else if (!strncmp(str, "pcie_bus_safe", 13)) {
4458 pcie_bus_config = PCIE_BUS_SAFE;
4459 } else if (!strncmp(str, "pcie_bus_perf", 13)) {
4460 pcie_bus_config = PCIE_BUS_PERFORMANCE;
4461 } else if (!strncmp(str, "pcie_bus_peer2peer", 18)) {
4462 pcie_bus_config = PCIE_BUS_PEER2PEER;
4463 } else if (!strncmp(str, "pcie_scan_all", 13)) {
4464 pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS);
4466 printk(KERN_ERR "PCI: Unknown option `%s'\n",
4474 early_param("pci", pci_setup);