2 * probe.c - PCI detection and setup code
5 #include <linux/kernel.h>
6 #include <linux/delay.h>
7 #include <linux/init.h>
9 #include <linux/of_device.h>
10 #include <linux/of_pci.h>
11 #include <linux/pci_hotplug.h>
12 #include <linux/slab.h>
13 #include <linux/module.h>
14 #include <linux/cpumask.h>
15 #include <linux/pci-aspm.h>
16 #include <linux/aer.h>
17 #include <linux/acpi.h>
18 #include <linux/irqdomain.h>
19 #include <linux/pm_runtime.h>
22 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
23 #define CARDBUS_RESERVE_BUSNR 3
25 static struct resource busn_resource = {
29 .flags = IORESOURCE_BUS,
32 /* Ugh. Need to stop exporting this to modules. */
33 LIST_HEAD(pci_root_buses);
34 EXPORT_SYMBOL(pci_root_buses);
36 static LIST_HEAD(pci_domain_busn_res_list);
38 struct pci_domain_busn_res {
39 struct list_head list;
44 static struct resource *get_pci_domain_busn_res(int domain_nr)
46 struct pci_domain_busn_res *r;
48 list_for_each_entry(r, &pci_domain_busn_res_list, list)
49 if (r->domain_nr == domain_nr)
52 r = kzalloc(sizeof(*r), GFP_KERNEL);
56 r->domain_nr = domain_nr;
59 r->res.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED;
61 list_add_tail(&r->list, &pci_domain_busn_res_list);
66 static int find_anything(struct device *dev, void *data)
72 * Some device drivers need know if pci is initiated.
73 * Basically, we think pci is not initiated when there
74 * is no device to be found on the pci_bus_type.
76 int no_pci_devices(void)
81 dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything);
82 no_devices = (dev == NULL);
86 EXPORT_SYMBOL(no_pci_devices);
91 static void release_pcibus_dev(struct device *dev)
93 struct pci_bus *pci_bus = to_pci_bus(dev);
95 put_device(pci_bus->bridge);
96 pci_bus_remove_resources(pci_bus);
97 pci_release_bus_of_node(pci_bus);
101 static struct class pcibus_class = {
103 .dev_release = &release_pcibus_dev,
104 .dev_groups = pcibus_groups,
107 static int __init pcibus_class_init(void)
109 return class_register(&pcibus_class);
111 postcore_initcall(pcibus_class_init);
113 static u64 pci_size(u64 base, u64 maxbase, u64 mask)
115 u64 size = mask & maxbase; /* Find the significant bits */
119 /* Get the lowest of them to find the decode size, and
120 from that the extent. */
121 size = (size & ~(size-1)) - 1;
123 /* base == maxbase can be valid only if the BAR has
124 already been programmed with all 1s. */
125 if (base == maxbase && ((base | size) & mask) != mask)
131 static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar)
136 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
137 flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
138 flags |= IORESOURCE_IO;
142 flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
143 flags |= IORESOURCE_MEM;
144 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
145 flags |= IORESOURCE_PREFETCH;
147 mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
149 case PCI_BASE_ADDRESS_MEM_TYPE_32:
151 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
152 /* 1M mem BAR treated as 32-bit BAR */
154 case PCI_BASE_ADDRESS_MEM_TYPE_64:
155 flags |= IORESOURCE_MEM_64;
158 /* mem unknown type treated as 32-bit BAR */
164 #define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)
167 * pci_read_base - read a PCI BAR
168 * @dev: the PCI device
169 * @type: type of the BAR
170 * @res: resource buffer to be filled in
171 * @pos: BAR position in the config space
173 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
175 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
176 struct resource *res, unsigned int pos)
179 u64 l64, sz64, mask64;
181 struct pci_bus_region region, inverted_region;
183 mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
185 /* No printks while decoding is disabled! */
186 if (!dev->mmio_always_on) {
187 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);
188 if (orig_cmd & PCI_COMMAND_DECODE_ENABLE) {
189 pci_write_config_word(dev, PCI_COMMAND,
190 orig_cmd & ~PCI_COMMAND_DECODE_ENABLE);
194 res->name = pci_name(dev);
196 pci_read_config_dword(dev, pos, &l);
197 pci_write_config_dword(dev, pos, l | mask);
198 pci_read_config_dword(dev, pos, &sz);
199 pci_write_config_dword(dev, pos, l);
202 * All bits set in sz means the device isn't working properly.
203 * If the BAR isn't implemented, all bits must be 0. If it's a
204 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
207 if (sz == 0xffffffff)
211 * I don't know how l can have all bits set. Copied from old code.
212 * Maybe it fixes a bug on some ancient platform.
217 if (type == pci_bar_unknown) {
218 res->flags = decode_bar(dev, l);
219 res->flags |= IORESOURCE_SIZEALIGN;
220 if (res->flags & IORESOURCE_IO) {
221 l64 = l & PCI_BASE_ADDRESS_IO_MASK;
222 sz64 = sz & PCI_BASE_ADDRESS_IO_MASK;
223 mask64 = PCI_BASE_ADDRESS_IO_MASK & (u32)IO_SPACE_LIMIT;
225 l64 = l & PCI_BASE_ADDRESS_MEM_MASK;
226 sz64 = sz & PCI_BASE_ADDRESS_MEM_MASK;
227 mask64 = (u32)PCI_BASE_ADDRESS_MEM_MASK;
230 res->flags |= (l & IORESOURCE_ROM_ENABLE);
231 l64 = l & PCI_ROM_ADDRESS_MASK;
232 sz64 = sz & PCI_ROM_ADDRESS_MASK;
233 mask64 = (u32)PCI_ROM_ADDRESS_MASK;
236 if (res->flags & IORESOURCE_MEM_64) {
237 pci_read_config_dword(dev, pos + 4, &l);
238 pci_write_config_dword(dev, pos + 4, ~0);
239 pci_read_config_dword(dev, pos + 4, &sz);
240 pci_write_config_dword(dev, pos + 4, l);
242 l64 |= ((u64)l << 32);
243 sz64 |= ((u64)sz << 32);
244 mask64 |= ((u64)~0 << 32);
247 if (!dev->mmio_always_on && (orig_cmd & PCI_COMMAND_DECODE_ENABLE))
248 pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
253 sz64 = pci_size(l64, sz64, mask64);
255 dev_info(&dev->dev, FW_BUG "reg 0x%x: invalid BAR (can't size)\n",
260 if (res->flags & IORESOURCE_MEM_64) {
261 if ((sizeof(pci_bus_addr_t) < 8 || sizeof(resource_size_t) < 8)
262 && sz64 > 0x100000000ULL) {
263 res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED;
266 dev_err(&dev->dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n",
267 pos, (unsigned long long)sz64);
271 if ((sizeof(pci_bus_addr_t) < 8) && l) {
272 /* Above 32-bit boundary; try to reallocate */
273 res->flags |= IORESOURCE_UNSET;
276 dev_info(&dev->dev, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n",
277 pos, (unsigned long long)l64);
283 region.end = l64 + sz64;
285 pcibios_bus_to_resource(dev->bus, res, ®ion);
286 pcibios_resource_to_bus(dev->bus, &inverted_region, res);
289 * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is
290 * the corresponding resource address (the physical address used by
291 * the CPU. Converting that resource address back to a bus address
292 * should yield the original BAR value:
294 * resource_to_bus(bus_to_resource(A)) == A
296 * If it doesn't, CPU accesses to "bus_to_resource(A)" will not
297 * be claimed by the device.
299 if (inverted_region.start != region.start) {
300 res->flags |= IORESOURCE_UNSET;
302 res->end = region.end - region.start;
303 dev_info(&dev->dev, "reg 0x%x: initial BAR value %#010llx invalid\n",
304 pos, (unsigned long long)region.start);
314 dev_printk(KERN_DEBUG, &dev->dev, "reg 0x%x: %pR\n", pos, res);
316 return (res->flags & IORESOURCE_MEM_64) ? 1 : 0;
319 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
321 unsigned int pos, reg;
323 if (dev->non_compliant_bars)
326 for (pos = 0; pos < howmany; pos++) {
327 struct resource *res = &dev->resource[pos];
328 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
329 pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
333 struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
334 dev->rom_base_reg = rom;
335 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
336 IORESOURCE_READONLY | IORESOURCE_SIZEALIGN;
337 __pci_read_base(dev, pci_bar_mem32, res, rom);
341 static void pci_read_bridge_io(struct pci_bus *child)
343 struct pci_dev *dev = child->self;
344 u8 io_base_lo, io_limit_lo;
345 unsigned long io_mask, io_granularity, base, limit;
346 struct pci_bus_region region;
347 struct resource *res;
349 io_mask = PCI_IO_RANGE_MASK;
350 io_granularity = 0x1000;
351 if (dev->io_window_1k) {
352 /* Support 1K I/O space granularity */
353 io_mask = PCI_IO_1K_RANGE_MASK;
354 io_granularity = 0x400;
357 res = child->resource[0];
358 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
359 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
360 base = (io_base_lo & io_mask) << 8;
361 limit = (io_limit_lo & io_mask) << 8;
363 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
364 u16 io_base_hi, io_limit_hi;
366 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
367 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
368 base |= ((unsigned long) io_base_hi << 16);
369 limit |= ((unsigned long) io_limit_hi << 16);
373 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
375 region.end = limit + io_granularity - 1;
376 pcibios_bus_to_resource(dev->bus, res, ®ion);
377 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
381 static void pci_read_bridge_mmio(struct pci_bus *child)
383 struct pci_dev *dev = child->self;
384 u16 mem_base_lo, mem_limit_lo;
385 unsigned long base, limit;
386 struct pci_bus_region region;
387 struct resource *res;
389 res = child->resource[1];
390 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
391 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
392 base = ((unsigned long) mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
393 limit = ((unsigned long) mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
395 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
397 region.end = limit + 0xfffff;
398 pcibios_bus_to_resource(dev->bus, res, ®ion);
399 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
403 static void pci_read_bridge_mmio_pref(struct pci_bus *child)
405 struct pci_dev *dev = child->self;
406 u16 mem_base_lo, mem_limit_lo;
408 pci_bus_addr_t base, limit;
409 struct pci_bus_region region;
410 struct resource *res;
412 res = child->resource[2];
413 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
414 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
415 base64 = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
416 limit64 = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
418 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
419 u32 mem_base_hi, mem_limit_hi;
421 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
422 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
425 * Some bridges set the base > limit by default, and some
426 * (broken) BIOSes do not initialize them. If we find
427 * this, just assume they are not being used.
429 if (mem_base_hi <= mem_limit_hi) {
430 base64 |= (u64) mem_base_hi << 32;
431 limit64 |= (u64) mem_limit_hi << 32;
435 base = (pci_bus_addr_t) base64;
436 limit = (pci_bus_addr_t) limit64;
438 if (base != base64) {
439 dev_err(&dev->dev, "can't handle bridge window above 4GB (bus address %#010llx)\n",
440 (unsigned long long) base64);
445 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) |
446 IORESOURCE_MEM | IORESOURCE_PREFETCH;
447 if (res->flags & PCI_PREF_RANGE_TYPE_64)
448 res->flags |= IORESOURCE_MEM_64;
450 region.end = limit + 0xfffff;
451 pcibios_bus_to_resource(dev->bus, res, ®ion);
452 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
456 void pci_read_bridge_bases(struct pci_bus *child)
458 struct pci_dev *dev = child->self;
459 struct resource *res;
462 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */
465 dev_info(&dev->dev, "PCI bridge to %pR%s\n",
467 dev->transparent ? " (subtractive decode)" : "");
469 pci_bus_remove_resources(child);
470 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
471 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
473 pci_read_bridge_io(child);
474 pci_read_bridge_mmio(child);
475 pci_read_bridge_mmio_pref(child);
477 if (dev->transparent) {
478 pci_bus_for_each_resource(child->parent, res, i) {
479 if (res && res->flags) {
480 pci_bus_add_resource(child, res,
481 PCI_SUBTRACTIVE_DECODE);
482 dev_printk(KERN_DEBUG, &dev->dev,
483 " bridge window %pR (subtractive decode)\n",
490 static struct pci_bus *pci_alloc_bus(struct pci_bus *parent)
494 b = kzalloc(sizeof(*b), GFP_KERNEL);
498 INIT_LIST_HEAD(&b->node);
499 INIT_LIST_HEAD(&b->children);
500 INIT_LIST_HEAD(&b->devices);
501 INIT_LIST_HEAD(&b->slots);
502 INIT_LIST_HEAD(&b->resources);
503 b->max_bus_speed = PCI_SPEED_UNKNOWN;
504 b->cur_bus_speed = PCI_SPEED_UNKNOWN;
505 #ifdef CONFIG_PCI_DOMAINS_GENERIC
507 b->domain_nr = parent->domain_nr;
512 static void pci_release_host_bridge_dev(struct device *dev)
514 struct pci_host_bridge *bridge = to_pci_host_bridge(dev);
516 if (bridge->release_fn)
517 bridge->release_fn(bridge);
519 pci_free_resource_list(&bridge->windows);
524 static struct pci_host_bridge *pci_alloc_host_bridge(struct pci_bus *b)
526 struct pci_host_bridge *bridge;
528 bridge = kzalloc(sizeof(*bridge), GFP_KERNEL);
532 INIT_LIST_HEAD(&bridge->windows);
537 static const unsigned char pcix_bus_speed[] = {
538 PCI_SPEED_UNKNOWN, /* 0 */
539 PCI_SPEED_66MHz_PCIX, /* 1 */
540 PCI_SPEED_100MHz_PCIX, /* 2 */
541 PCI_SPEED_133MHz_PCIX, /* 3 */
542 PCI_SPEED_UNKNOWN, /* 4 */
543 PCI_SPEED_66MHz_PCIX_ECC, /* 5 */
544 PCI_SPEED_100MHz_PCIX_ECC, /* 6 */
545 PCI_SPEED_133MHz_PCIX_ECC, /* 7 */
546 PCI_SPEED_UNKNOWN, /* 8 */
547 PCI_SPEED_66MHz_PCIX_266, /* 9 */
548 PCI_SPEED_100MHz_PCIX_266, /* A */
549 PCI_SPEED_133MHz_PCIX_266, /* B */
550 PCI_SPEED_UNKNOWN, /* C */
551 PCI_SPEED_66MHz_PCIX_533, /* D */
552 PCI_SPEED_100MHz_PCIX_533, /* E */
553 PCI_SPEED_133MHz_PCIX_533 /* F */
556 const unsigned char pcie_link_speed[] = {
557 PCI_SPEED_UNKNOWN, /* 0 */
558 PCIE_SPEED_2_5GT, /* 1 */
559 PCIE_SPEED_5_0GT, /* 2 */
560 PCIE_SPEED_8_0GT, /* 3 */
561 PCI_SPEED_UNKNOWN, /* 4 */
562 PCI_SPEED_UNKNOWN, /* 5 */
563 PCI_SPEED_UNKNOWN, /* 6 */
564 PCI_SPEED_UNKNOWN, /* 7 */
565 PCI_SPEED_UNKNOWN, /* 8 */
566 PCI_SPEED_UNKNOWN, /* 9 */
567 PCI_SPEED_UNKNOWN, /* A */
568 PCI_SPEED_UNKNOWN, /* B */
569 PCI_SPEED_UNKNOWN, /* C */
570 PCI_SPEED_UNKNOWN, /* D */
571 PCI_SPEED_UNKNOWN, /* E */
572 PCI_SPEED_UNKNOWN /* F */
575 void pcie_update_link_speed(struct pci_bus *bus, u16 linksta)
577 bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS];
579 EXPORT_SYMBOL_GPL(pcie_update_link_speed);
581 static unsigned char agp_speeds[] = {
589 static enum pci_bus_speed agp_speed(int agp3, int agpstat)
595 else if (agpstat & 2)
597 else if (agpstat & 1)
609 return agp_speeds[index];
612 static void pci_set_bus_speed(struct pci_bus *bus)
614 struct pci_dev *bridge = bus->self;
617 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP);
619 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3);
623 pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat);
624 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7);
626 pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd);
627 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7);
630 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
633 enum pci_bus_speed max;
635 pci_read_config_word(bridge, pos + PCI_X_BRIDGE_SSTATUS,
638 if (status & PCI_X_SSTATUS_533MHZ) {
639 max = PCI_SPEED_133MHz_PCIX_533;
640 } else if (status & PCI_X_SSTATUS_266MHZ) {
641 max = PCI_SPEED_133MHz_PCIX_266;
642 } else if (status & PCI_X_SSTATUS_133MHZ) {
643 if ((status & PCI_X_SSTATUS_VERS) == PCI_X_SSTATUS_V2)
644 max = PCI_SPEED_133MHz_PCIX_ECC;
646 max = PCI_SPEED_133MHz_PCIX;
648 max = PCI_SPEED_66MHz_PCIX;
651 bus->max_bus_speed = max;
652 bus->cur_bus_speed = pcix_bus_speed[
653 (status & PCI_X_SSTATUS_FREQ) >> 6];
658 if (pci_is_pcie(bridge)) {
662 pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap);
663 bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS];
665 pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta);
666 pcie_update_link_speed(bus, linksta);
670 static struct irq_domain *pci_host_bridge_msi_domain(struct pci_bus *bus)
672 struct irq_domain *d;
675 * Any firmware interface that can resolve the msi_domain
676 * should be called from here.
678 d = pci_host_bridge_of_msi_domain(bus);
680 d = pci_host_bridge_acpi_msi_domain(bus);
682 #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
684 * If no IRQ domain was found via the OF tree, try looking it up
685 * directly through the fwnode_handle.
688 struct fwnode_handle *fwnode = pci_root_bus_fwnode(bus);
691 d = irq_find_matching_fwnode(fwnode,
699 static void pci_set_bus_msi_domain(struct pci_bus *bus)
701 struct irq_domain *d;
705 * The bus can be a root bus, a subordinate bus, or a virtual bus
706 * created by an SR-IOV device. Walk up to the first bridge device
707 * found or derive the domain from the host bridge.
709 for (b = bus, d = NULL; !d && !pci_is_root_bus(b); b = b->parent) {
711 d = dev_get_msi_domain(&b->self->dev);
715 d = pci_host_bridge_msi_domain(b);
717 dev_set_msi_domain(&bus->dev, d);
720 static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
721 struct pci_dev *bridge, int busnr)
723 struct pci_bus *child;
728 * Allocate a new bus, and inherit stuff from the parent..
730 child = pci_alloc_bus(parent);
734 child->parent = parent;
735 child->ops = parent->ops;
736 child->msi = parent->msi;
737 child->sysdata = parent->sysdata;
738 child->bus_flags = parent->bus_flags;
740 /* initialize some portions of the bus device, but don't register it
741 * now as the parent is not properly set up yet.
743 child->dev.class = &pcibus_class;
744 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
747 * Set up the primary, secondary and subordinate
750 child->number = child->busn_res.start = busnr;
751 child->primary = parent->busn_res.start;
752 child->busn_res.end = 0xff;
755 child->dev.parent = parent->bridge;
759 child->self = bridge;
760 child->bridge = get_device(&bridge->dev);
761 child->dev.parent = child->bridge;
762 pci_set_bus_of_node(child);
763 pci_set_bus_speed(child);
765 /* Set up default resource pointers and names.. */
766 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
767 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
768 child->resource[i]->name = child->name;
770 bridge->subordinate = child;
773 pci_set_bus_msi_domain(child);
774 ret = device_register(&child->dev);
777 pcibios_add_bus(child);
779 if (child->ops->add_bus) {
780 ret = child->ops->add_bus(child);
781 if (WARN_ON(ret < 0))
782 dev_err(&child->dev, "failed to add bus: %d\n", ret);
785 /* Create legacy_io and legacy_mem files for this bus */
786 pci_create_legacy_files(child);
791 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
794 struct pci_bus *child;
796 child = pci_alloc_child_bus(parent, dev, busnr);
798 down_write(&pci_bus_sem);
799 list_add_tail(&child->node, &parent->children);
800 up_write(&pci_bus_sem);
804 EXPORT_SYMBOL(pci_add_new_bus);
806 static void pci_enable_crs(struct pci_dev *pdev)
810 /* Enable CRS Software Visibility if supported */
811 pcie_capability_read_word(pdev, PCI_EXP_RTCAP, &root_cap);
812 if (root_cap & PCI_EXP_RTCAP_CRSVIS)
813 pcie_capability_set_word(pdev, PCI_EXP_RTCTL,
814 PCI_EXP_RTCTL_CRSSVE);
818 * If it's a bridge, configure it and scan the bus behind it.
819 * For CardBus bridges, we don't scan behind as the devices will
820 * be handled by the bridge driver itself.
822 * We need to process bridges in two passes -- first we scan those
823 * already configured by the BIOS and after we are done with all of
824 * them, we proceed to assigning numbers to the remaining buses in
825 * order to avoid overlaps between old and new bus numbers.
827 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
829 struct pci_bus *child;
830 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
833 u8 primary, secondary, subordinate;
837 * Make sure the bridge is powered on to be able to access config
838 * space of devices below it.
840 pm_runtime_get_sync(&dev->dev);
842 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
843 primary = buses & 0xFF;
844 secondary = (buses >> 8) & 0xFF;
845 subordinate = (buses >> 16) & 0xFF;
847 dev_dbg(&dev->dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
848 secondary, subordinate, pass);
850 if (!primary && (primary != bus->number) && secondary && subordinate) {
851 dev_warn(&dev->dev, "Primary bus is hard wired to 0\n");
852 primary = bus->number;
855 /* Check if setup is sensible at all */
857 (primary != bus->number || secondary <= bus->number ||
858 secondary > subordinate)) {
859 dev_info(&dev->dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n",
860 secondary, subordinate);
864 /* Disable MasterAbortMode during probing to avoid reporting
865 of bus errors (in some architectures) */
866 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
867 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
868 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
872 if ((secondary || subordinate) && !pcibios_assign_all_busses() &&
873 !is_cardbus && !broken) {
876 * Bus already configured by firmware, process it in the first
877 * pass and just note the configuration.
883 * The bus might already exist for two reasons: Either we are
884 * rescanning the bus or the bus is reachable through more than
885 * one bridge. The second case can happen with the i450NX
888 child = pci_find_bus(pci_domain_nr(bus), secondary);
890 child = pci_add_new_bus(bus, dev, secondary);
893 child->primary = primary;
894 pci_bus_insert_busn_res(child, secondary, subordinate);
895 child->bridge_ctl = bctl;
898 cmax = pci_scan_child_bus(child);
899 if (cmax > subordinate)
900 dev_warn(&dev->dev, "bridge has subordinate %02x but max busn %02x\n",
902 /* subordinate should equal child->busn_res.end */
903 if (subordinate > max)
907 * We need to assign a number to this bus which we always
908 * do in the second pass.
911 if (pcibios_assign_all_busses() || broken || is_cardbus)
912 /* Temporarily disable forwarding of the
913 configuration cycles on all bridges in
914 this bus segment to avoid possible
915 conflicts in the second pass between two
916 bridges programmed with overlapping
918 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
924 pci_write_config_word(dev, PCI_STATUS, 0xffff);
926 /* Prevent assigning a bus number that already exists.
927 * This can happen when a bridge is hot-plugged, so in
928 * this case we only re-scan this bus. */
929 child = pci_find_bus(pci_domain_nr(bus), max+1);
931 child = pci_add_new_bus(bus, dev, max+1);
934 pci_bus_insert_busn_res(child, max+1, 0xff);
937 buses = (buses & 0xff000000)
938 | ((unsigned int)(child->primary) << 0)
939 | ((unsigned int)(child->busn_res.start) << 8)
940 | ((unsigned int)(child->busn_res.end) << 16);
943 * yenta.c forces a secondary latency timer of 176.
944 * Copy that behaviour here.
947 buses &= ~0xff000000;
948 buses |= CARDBUS_LATENCY_TIMER << 24;
952 * We need to blast all three values with a single write.
954 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
957 child->bridge_ctl = bctl;
958 max = pci_scan_child_bus(child);
961 * For CardBus bridges, we leave 4 bus numbers
962 * as cards with a PCI-to-PCI bridge can be
965 for (i = 0; i < CARDBUS_RESERVE_BUSNR; i++) {
966 struct pci_bus *parent = bus;
967 if (pci_find_bus(pci_domain_nr(bus),
970 while (parent->parent) {
971 if ((!pcibios_assign_all_busses()) &&
972 (parent->busn_res.end > max) &&
973 (parent->busn_res.end <= max+i)) {
976 parent = parent->parent;
980 * Often, there are two cardbus bridges
981 * -- try to leave one valid bus number
991 * Set the subordinate bus number to its real value.
993 pci_bus_update_busn_res_end(child, max);
994 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
998 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
999 pci_domain_nr(bus), child->number);
1001 /* Has only triggered on CardBus, fixup is in yenta_socket */
1002 while (bus->parent) {
1003 if ((child->busn_res.end > bus->busn_res.end) ||
1004 (child->number > bus->busn_res.end) ||
1005 (child->number < bus->number) ||
1006 (child->busn_res.end < bus->number)) {
1007 dev_info(&child->dev, "%pR %s hidden behind%s bridge %s %pR\n",
1009 (bus->number > child->busn_res.end &&
1010 bus->busn_res.end < child->number) ?
1011 "wholly" : "partially",
1012 bus->self->transparent ? " transparent" : "",
1013 dev_name(&bus->dev),
1020 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
1022 pm_runtime_put(&dev->dev);
1026 EXPORT_SYMBOL(pci_scan_bridge);
1029 * Read interrupt line and base address registers.
1030 * The architecture-dependent code can tweak these, of course.
1032 static void pci_read_irq(struct pci_dev *dev)
1036 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
1039 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
1043 void set_pcie_port_type(struct pci_dev *pdev)
1048 struct pci_dev *parent;
1050 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
1053 pdev->pcie_cap = pos;
1054 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
1055 pdev->pcie_flags_reg = reg16;
1056 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16);
1057 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
1060 * A Root Port is always the upstream end of a Link. No PCIe
1061 * component has two Links. Two Links are connected by a Switch
1062 * that has a Port on each Link and internal logic to connect the
1065 type = pci_pcie_type(pdev);
1066 if (type == PCI_EXP_TYPE_ROOT_PORT)
1067 pdev->has_secondary_link = 1;
1068 else if (type == PCI_EXP_TYPE_UPSTREAM ||
1069 type == PCI_EXP_TYPE_DOWNSTREAM) {
1070 parent = pci_upstream_bridge(pdev);
1073 * Usually there's an upstream device (Root Port or Switch
1074 * Downstream Port), but we can't assume one exists.
1076 if (parent && !parent->has_secondary_link)
1077 pdev->has_secondary_link = 1;
1081 void set_pcie_hotplug_bridge(struct pci_dev *pdev)
1085 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, ®32);
1086 if (reg32 & PCI_EXP_SLTCAP_HPC)
1087 pdev->is_hotplug_bridge = 1;
1091 * pci_ext_cfg_is_aliased - is ext config space just an alias of std config?
1094 * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that
1095 * when forwarding a type1 configuration request the bridge must check that
1096 * the extended register address field is zero. The bridge is not permitted
1097 * to forward the transactions and must handle it as an Unsupported Request.
1098 * Some bridges do not follow this rule and simply drop the extended register
1099 * bits, resulting in the standard config space being aliased, every 256
1100 * bytes across the entire configuration space. Test for this condition by
1101 * comparing the first dword of each potential alias to the vendor/device ID.
1103 * ASM1083/1085 PCIe-to-PCI Reversible Bridge (1b21:1080, rev 01 & 03)
1104 * AMD/ATI SBx00 PCI to PCI Bridge (1002:4384, rev 40)
1106 static bool pci_ext_cfg_is_aliased(struct pci_dev *dev)
1108 #ifdef CONFIG_PCI_QUIRKS
1112 pci_read_config_dword(dev, PCI_VENDOR_ID, &header);
1114 for (pos = PCI_CFG_SPACE_SIZE;
1115 pos < PCI_CFG_SPACE_EXP_SIZE; pos += PCI_CFG_SPACE_SIZE) {
1116 if (pci_read_config_dword(dev, pos, &tmp) != PCIBIOS_SUCCESSFUL
1128 * pci_cfg_space_size - get the configuration space size of the PCI device.
1131 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
1132 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
1133 * access it. Maybe we don't have a way to generate extended config space
1134 * accesses, or the device is behind a reverse Express bridge. So we try
1135 * reading the dword at 0x100 which must either be 0 or a valid extended
1136 * capability header.
1138 static int pci_cfg_space_size_ext(struct pci_dev *dev)
1141 int pos = PCI_CFG_SPACE_SIZE;
1143 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
1144 return PCI_CFG_SPACE_SIZE;
1145 if (status == 0xffffffff || pci_ext_cfg_is_aliased(dev))
1146 return PCI_CFG_SPACE_SIZE;
1148 return PCI_CFG_SPACE_EXP_SIZE;
1151 int pci_cfg_space_size(struct pci_dev *dev)
1157 class = dev->class >> 8;
1158 if (class == PCI_CLASS_BRIDGE_HOST)
1159 return pci_cfg_space_size_ext(dev);
1161 if (pci_is_pcie(dev))
1162 return pci_cfg_space_size_ext(dev);
1164 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1166 return PCI_CFG_SPACE_SIZE;
1168 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
1169 if (status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ))
1170 return pci_cfg_space_size_ext(dev);
1172 return PCI_CFG_SPACE_SIZE;
1175 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
1177 static void pci_msi_setup_pci_dev(struct pci_dev *dev)
1180 * Disable the MSI hardware to avoid screaming interrupts
1181 * during boot. This is the power on reset default so
1182 * usually this should be a noop.
1184 dev->msi_cap = pci_find_capability(dev, PCI_CAP_ID_MSI);
1186 pci_msi_set_enable(dev, 0);
1188 dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX);
1190 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
1194 * pci_setup_device - fill in class and map information of a device
1195 * @dev: the device structure to fill
1197 * Initialize the device structure with information about the device's
1198 * vendor,class,memory and IO-space addresses,IRQ lines etc.
1199 * Called at initialisation of the PCI subsystem and by CardBus services.
1200 * Returns 0 on success and negative if unknown type of device (not normal,
1201 * bridge or CardBus).
1203 int pci_setup_device(struct pci_dev *dev)
1209 struct pci_bus_region region;
1210 struct resource *res;
1212 if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type))
1215 dev->sysdata = dev->bus->sysdata;
1216 dev->dev.parent = dev->bus->bridge;
1217 dev->dev.bus = &pci_bus_type;
1218 dev->hdr_type = hdr_type & 0x7f;
1219 dev->multifunction = !!(hdr_type & 0x80);
1220 dev->error_state = pci_channel_io_normal;
1221 set_pcie_port_type(dev);
1223 pci_dev_assign_slot(dev);
1224 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
1225 set this higher, assuming the system even supports it. */
1226 dev->dma_mask = 0xffffffff;
1228 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
1229 dev->bus->number, PCI_SLOT(dev->devfn),
1230 PCI_FUNC(dev->devfn));
1232 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
1233 dev->revision = class & 0xff;
1234 dev->class = class >> 8; /* upper 3 bytes */
1236 dev_printk(KERN_DEBUG, &dev->dev, "[%04x:%04x] type %02x class %#08x\n",
1237 dev->vendor, dev->device, dev->hdr_type, dev->class);
1239 /* need to have dev->class ready */
1240 dev->cfg_size = pci_cfg_space_size(dev);
1242 /* "Unknown power state" */
1243 dev->current_state = PCI_UNKNOWN;
1245 /* Early fixups, before probing the BARs */
1246 pci_fixup_device(pci_fixup_early, dev);
1247 /* device class may be changed after fixup */
1248 class = dev->class >> 8;
1250 if (dev->non_compliant_bars) {
1251 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1252 if (cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
1253 dev_info(&dev->dev, "device has non-compliant BARs; disabling IO/MEM decoding\n");
1254 cmd &= ~PCI_COMMAND_IO;
1255 cmd &= ~PCI_COMMAND_MEMORY;
1256 pci_write_config_word(dev, PCI_COMMAND, cmd);
1260 switch (dev->hdr_type) { /* header type */
1261 case PCI_HEADER_TYPE_NORMAL: /* standard header */
1262 if (class == PCI_CLASS_BRIDGE_PCI)
1265 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
1266 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1267 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
1270 * Do the ugly legacy mode stuff here rather than broken chip
1271 * quirk code. Legacy mode ATA controllers have fixed
1272 * addresses. These are not always echoed in BAR0-3, and
1273 * BAR0-3 in a few cases contain junk!
1275 if (class == PCI_CLASS_STORAGE_IDE) {
1277 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
1278 if ((progif & 1) == 0) {
1279 region.start = 0x1F0;
1281 res = &dev->resource[0];
1282 res->flags = LEGACY_IO_RESOURCE;
1283 pcibios_bus_to_resource(dev->bus, res, ®ion);
1284 dev_info(&dev->dev, "legacy IDE quirk: reg 0x10: %pR\n",
1286 region.start = 0x3F6;
1288 res = &dev->resource[1];
1289 res->flags = LEGACY_IO_RESOURCE;
1290 pcibios_bus_to_resource(dev->bus, res, ®ion);
1291 dev_info(&dev->dev, "legacy IDE quirk: reg 0x14: %pR\n",
1294 if ((progif & 4) == 0) {
1295 region.start = 0x170;
1297 res = &dev->resource[2];
1298 res->flags = LEGACY_IO_RESOURCE;
1299 pcibios_bus_to_resource(dev->bus, res, ®ion);
1300 dev_info(&dev->dev, "legacy IDE quirk: reg 0x18: %pR\n",
1302 region.start = 0x376;
1304 res = &dev->resource[3];
1305 res->flags = LEGACY_IO_RESOURCE;
1306 pcibios_bus_to_resource(dev->bus, res, ®ion);
1307 dev_info(&dev->dev, "legacy IDE quirk: reg 0x1c: %pR\n",
1313 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
1314 if (class != PCI_CLASS_BRIDGE_PCI)
1316 /* The PCI-to-PCI bridge spec requires that subtractive
1317 decoding (i.e. transparent) bridge must have programming
1318 interface code of 0x01. */
1320 dev->transparent = ((dev->class & 0xff) == 1);
1321 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
1322 set_pcie_hotplug_bridge(dev);
1323 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID);
1325 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor);
1326 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device);
1330 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
1331 if (class != PCI_CLASS_BRIDGE_CARDBUS)
1334 pci_read_bases(dev, 1, 0);
1335 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1336 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
1339 default: /* unknown header */
1340 dev_err(&dev->dev, "unknown header type %02x, ignoring device\n",
1345 dev_err(&dev->dev, "ignoring class %#08x (doesn't match header type %02x)\n",
1346 dev->class, dev->hdr_type);
1347 dev->class = PCI_CLASS_NOT_DEFINED << 8;
1350 /* We found a fine healthy device, go go go... */
1354 static void pci_configure_mps(struct pci_dev *dev)
1356 struct pci_dev *bridge = pci_upstream_bridge(dev);
1359 if (!pci_is_pcie(dev) || !bridge || !pci_is_pcie(bridge))
1362 mps = pcie_get_mps(dev);
1363 p_mps = pcie_get_mps(bridge);
1368 if (pcie_bus_config == PCIE_BUS_TUNE_OFF) {
1369 dev_warn(&dev->dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1370 mps, pci_name(bridge), p_mps);
1375 * Fancier MPS configuration is done later by
1376 * pcie_bus_configure_settings()
1378 if (pcie_bus_config != PCIE_BUS_DEFAULT)
1381 rc = pcie_set_mps(dev, p_mps);
1383 dev_warn(&dev->dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1388 dev_info(&dev->dev, "Max Payload Size set to %d (was %d, max %d)\n",
1389 p_mps, mps, 128 << dev->pcie_mpss);
1392 static struct hpp_type0 pci_default_type0 = {
1394 .cache_line_size = 8,
1395 .latency_timer = 0x40,
1400 static void program_hpp_type0(struct pci_dev *dev, struct hpp_type0 *hpp)
1402 u16 pci_cmd, pci_bctl;
1405 hpp = &pci_default_type0;
1407 if (hpp->revision > 1) {
1409 "PCI settings rev %d not supported; using defaults\n",
1411 hpp = &pci_default_type0;
1414 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, hpp->cache_line_size);
1415 pci_write_config_byte(dev, PCI_LATENCY_TIMER, hpp->latency_timer);
1416 pci_read_config_word(dev, PCI_COMMAND, &pci_cmd);
1417 if (hpp->enable_serr)
1418 pci_cmd |= PCI_COMMAND_SERR;
1419 if (hpp->enable_perr)
1420 pci_cmd |= PCI_COMMAND_PARITY;
1421 pci_write_config_word(dev, PCI_COMMAND, pci_cmd);
1423 /* Program bridge control value */
1424 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
1425 pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER,
1426 hpp->latency_timer);
1427 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &pci_bctl);
1428 if (hpp->enable_serr)
1429 pci_bctl |= PCI_BRIDGE_CTL_SERR;
1430 if (hpp->enable_perr)
1431 pci_bctl |= PCI_BRIDGE_CTL_PARITY;
1432 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, pci_bctl);
1436 static void program_hpp_type1(struct pci_dev *dev, struct hpp_type1 *hpp)
1439 dev_warn(&dev->dev, "PCI-X settings not supported\n");
1442 static bool pcie_root_rcb_set(struct pci_dev *dev)
1444 struct pci_dev *rp = pcie_find_root_port(dev);
1450 pcie_capability_read_word(rp, PCI_EXP_LNKCTL, &lnkctl);
1451 if (lnkctl & PCI_EXP_LNKCTL_RCB)
1457 static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp)
1465 if (hpp->revision > 1) {
1466 dev_warn(&dev->dev, "PCIe settings rev %d not supported\n",
1472 * Don't allow _HPX to change MPS or MRRS settings. We manage
1473 * those to make sure they're consistent with the rest of the
1476 hpp->pci_exp_devctl_and |= PCI_EXP_DEVCTL_PAYLOAD |
1477 PCI_EXP_DEVCTL_READRQ;
1478 hpp->pci_exp_devctl_or &= ~(PCI_EXP_DEVCTL_PAYLOAD |
1479 PCI_EXP_DEVCTL_READRQ);
1481 /* Initialize Device Control Register */
1482 pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
1483 ~hpp->pci_exp_devctl_and, hpp->pci_exp_devctl_or);
1485 /* Initialize Link Control Register */
1486 if (pcie_cap_has_lnkctl(dev)) {
1489 * If the Root Port supports Read Completion Boundary of
1490 * 128, set RCB to 128. Otherwise, clear it.
1492 hpp->pci_exp_lnkctl_and |= PCI_EXP_LNKCTL_RCB;
1493 hpp->pci_exp_lnkctl_or &= ~PCI_EXP_LNKCTL_RCB;
1494 if (pcie_root_rcb_set(dev))
1495 hpp->pci_exp_lnkctl_or |= PCI_EXP_LNKCTL_RCB;
1497 pcie_capability_clear_and_set_word(dev, PCI_EXP_LNKCTL,
1498 ~hpp->pci_exp_lnkctl_and, hpp->pci_exp_lnkctl_or);
1501 /* Find Advanced Error Reporting Enhanced Capability */
1502 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
1506 /* Initialize Uncorrectable Error Mask Register */
1507 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, ®32);
1508 reg32 = (reg32 & hpp->unc_err_mask_and) | hpp->unc_err_mask_or;
1509 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, reg32);
1511 /* Initialize Uncorrectable Error Severity Register */
1512 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, ®32);
1513 reg32 = (reg32 & hpp->unc_err_sever_and) | hpp->unc_err_sever_or;
1514 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, reg32);
1516 /* Initialize Correctable Error Mask Register */
1517 pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, ®32);
1518 reg32 = (reg32 & hpp->cor_err_mask_and) | hpp->cor_err_mask_or;
1519 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg32);
1521 /* Initialize Advanced Error Capabilities and Control Register */
1522 pci_read_config_dword(dev, pos + PCI_ERR_CAP, ®32);
1523 reg32 = (reg32 & hpp->adv_err_cap_and) | hpp->adv_err_cap_or;
1524 pci_write_config_dword(dev, pos + PCI_ERR_CAP, reg32);
1527 * FIXME: The following two registers are not supported yet.
1529 * o Secondary Uncorrectable Error Severity Register
1530 * o Secondary Uncorrectable Error Mask Register
1534 static void pci_configure_device(struct pci_dev *dev)
1536 struct hotplug_params hpp;
1539 pci_configure_mps(dev);
1541 memset(&hpp, 0, sizeof(hpp));
1542 ret = pci_get_hp_params(dev, &hpp);
1546 program_hpp_type2(dev, hpp.t2);
1547 program_hpp_type1(dev, hpp.t1);
1548 program_hpp_type0(dev, hpp.t0);
1551 static void pci_release_capabilities(struct pci_dev *dev)
1553 pci_vpd_release(dev);
1554 pci_iov_release(dev);
1555 pci_free_cap_save_buffers(dev);
1559 * pci_release_dev - free a pci device structure when all users of it are finished.
1560 * @dev: device that's been disconnected
1562 * Will be called only by the device core when all users of this pci device are
1565 static void pci_release_dev(struct device *dev)
1567 struct pci_dev *pci_dev;
1569 pci_dev = to_pci_dev(dev);
1570 pci_release_capabilities(pci_dev);
1571 pci_release_of_node(pci_dev);
1572 pcibios_release_device(pci_dev);
1573 pci_bus_put(pci_dev->bus);
1574 kfree(pci_dev->driver_override);
1575 kfree(pci_dev->dma_alias_mask);
1579 struct pci_dev *pci_alloc_dev(struct pci_bus *bus)
1581 struct pci_dev *dev;
1583 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
1587 INIT_LIST_HEAD(&dev->bus_list);
1588 dev->dev.type = &pci_dev_type;
1589 dev->bus = pci_bus_get(bus);
1593 EXPORT_SYMBOL(pci_alloc_dev);
1595 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
1600 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
1603 /* some broken boards return 0 or ~0 if a slot is empty: */
1604 if (*l == 0xffffffff || *l == 0x00000000 ||
1605 *l == 0x0000ffff || *l == 0xffff0000)
1609 * Configuration Request Retry Status. Some root ports return the
1610 * actual device ID instead of the synthetic ID (0xFFFF) required
1611 * by the PCIe spec. Ignore the device ID and only check for
1614 while ((*l & 0xffff) == 0x0001) {
1620 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
1622 /* Card hasn't responded in 60 seconds? Must be stuck. */
1623 if (delay > crs_timeout) {
1624 printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not responding\n",
1625 pci_domain_nr(bus), bus->number, PCI_SLOT(devfn),
1633 EXPORT_SYMBOL(pci_bus_read_dev_vendor_id);
1636 * Read the config data for a PCI device, sanity-check it
1637 * and fill in the dev structure...
1639 static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
1641 struct pci_dev *dev;
1644 if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000))
1647 dev = pci_alloc_dev(bus);
1652 dev->vendor = l & 0xffff;
1653 dev->device = (l >> 16) & 0xffff;
1655 pci_set_of_node(dev);
1657 if (pci_setup_device(dev)) {
1658 pci_bus_put(dev->bus);
1666 static void pci_init_capabilities(struct pci_dev *dev)
1668 /* Enhanced Allocation */
1671 /* Setup MSI caps & disable MSI/MSI-X interrupts */
1672 pci_msi_setup_pci_dev(dev);
1674 /* Buffers for saving PCIe and PCI-X capabilities */
1675 pci_allocate_cap_save_buffers(dev);
1677 /* Power Management */
1680 /* Vital Product Data */
1683 /* Alternative Routing-ID Forwarding */
1684 pci_configure_ari(dev);
1686 /* Single Root I/O Virtualization */
1689 /* Address Translation Services */
1692 /* Enable ACS P2P upstream forwarding */
1693 pci_enable_acs(dev);
1695 /* Precision Time Measurement */
1698 /* Advanced Error Reporting */
1703 * This is the equivalent of pci_host_bridge_msi_domain that acts on
1704 * devices. Firmware interfaces that can select the MSI domain on a
1705 * per-device basis should be called from here.
1707 static struct irq_domain *pci_dev_msi_domain(struct pci_dev *dev)
1709 struct irq_domain *d;
1712 * If a domain has been set through the pcibios_add_device
1713 * callback, then this is the one (platform code knows best).
1715 d = dev_get_msi_domain(&dev->dev);
1720 * Let's see if we have a firmware interface able to provide
1723 d = pci_msi_get_device_domain(dev);
1730 static void pci_set_msi_domain(struct pci_dev *dev)
1732 struct irq_domain *d;
1735 * If the platform or firmware interfaces cannot supply a
1736 * device-specific MSI domain, then inherit the default domain
1737 * from the host bridge itself.
1739 d = pci_dev_msi_domain(dev);
1741 d = dev_get_msi_domain(&dev->bus->dev);
1743 dev_set_msi_domain(&dev->dev, d);
1747 * pci_dma_configure - Setup DMA configuration
1748 * @dev: ptr to pci_dev struct of the PCI device
1750 * Function to update PCI devices's DMA configuration using the same
1751 * info from the OF node or ACPI node of host bridge's parent (if any).
1753 static void pci_dma_configure(struct pci_dev *dev)
1755 struct device *bridge = pci_get_host_bridge_device(dev);
1757 if (IS_ENABLED(CONFIG_OF) &&
1758 bridge->parent && bridge->parent->of_node) {
1759 of_dma_configure(&dev->dev, bridge->parent->of_node);
1760 } else if (has_acpi_companion(bridge)) {
1761 struct acpi_device *adev = to_acpi_device_node(bridge->fwnode);
1762 enum dev_dma_attr attr = acpi_get_dma_attr(adev);
1764 if (attr == DEV_DMA_NOT_SUPPORTED)
1765 dev_warn(&dev->dev, "DMA not supported.\n");
1767 arch_setup_dma_ops(&dev->dev, 0, 0, NULL,
1768 attr == DEV_DMA_COHERENT);
1771 pci_put_host_bridge_device(bridge);
1774 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
1778 pci_configure_device(dev);
1780 device_initialize(&dev->dev);
1781 dev->dev.release = pci_release_dev;
1783 set_dev_node(&dev->dev, pcibus_to_node(bus));
1784 dev->dev.dma_mask = &dev->dma_mask;
1785 dev->dev.dma_parms = &dev->dma_parms;
1786 dev->dev.coherent_dma_mask = 0xffffffffull;
1787 pci_dma_configure(dev);
1789 pci_set_dma_max_seg_size(dev, 65536);
1790 pci_set_dma_seg_boundary(dev, 0xffffffff);
1792 /* Fix up broken headers */
1793 pci_fixup_device(pci_fixup_header, dev);
1795 /* moved out from quirk header fixup code */
1796 pci_reassigndev_resource_alignment(dev);
1798 /* Clear the state_saved flag. */
1799 dev->state_saved = false;
1801 /* Initialize various capabilities */
1802 pci_init_capabilities(dev);
1805 * Add the device to our list of discovered devices
1806 * and the bus list for fixup functions, etc.
1808 down_write(&pci_bus_sem);
1809 list_add_tail(&dev->bus_list, &bus->devices);
1810 up_write(&pci_bus_sem);
1812 ret = pcibios_add_device(dev);
1815 /* Setup MSI irq domain */
1816 pci_set_msi_domain(dev);
1818 /* Notifier could use PCI capabilities */
1819 dev->match_driver = false;
1820 ret = device_add(&dev->dev);
1824 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn)
1826 struct pci_dev *dev;
1828 dev = pci_get_slot(bus, devfn);
1834 dev = pci_scan_device(bus, devfn);
1838 pci_device_add(dev, bus);
1842 EXPORT_SYMBOL(pci_scan_single_device);
1844 static unsigned next_fn(struct pci_bus *bus, struct pci_dev *dev, unsigned fn)
1850 if (pci_ari_enabled(bus)) {
1853 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
1857 pci_read_config_word(dev, pos + PCI_ARI_CAP, &cap);
1858 next_fn = PCI_ARI_CAP_NFN(cap);
1860 return 0; /* protect against malformed list */
1865 /* dev may be NULL for non-contiguous multifunction devices */
1866 if (!dev || dev->multifunction)
1867 return (fn + 1) % 8;
1872 static int only_one_child(struct pci_bus *bus)
1874 struct pci_dev *parent = bus->self;
1876 if (!parent || !pci_is_pcie(parent))
1878 if (pci_pcie_type(parent) == PCI_EXP_TYPE_ROOT_PORT)
1882 * PCIe downstream ports are bridges that normally lead to only a
1883 * device 0, but if PCI_SCAN_ALL_PCIE_DEVS is set, scan all
1884 * possible devices, not just device 0. See PCIe spec r3.0,
1887 if (parent->has_secondary_link &&
1888 !pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS))
1894 * pci_scan_slot - scan a PCI slot on a bus for devices.
1895 * @bus: PCI bus to scan
1896 * @devfn: slot number to scan (must have zero function.)
1898 * Scan a PCI slot on the specified PCI bus for devices, adding
1899 * discovered devices to the @bus->devices list. New devices
1900 * will not have is_added set.
1902 * Returns the number of new devices found.
1904 int pci_scan_slot(struct pci_bus *bus, int devfn)
1906 unsigned fn, nr = 0;
1907 struct pci_dev *dev;
1909 if (only_one_child(bus) && (devfn > 0))
1910 return 0; /* Already scanned the entire slot */
1912 dev = pci_scan_single_device(bus, devfn);
1918 for (fn = next_fn(bus, dev, 0); fn > 0; fn = next_fn(bus, dev, fn)) {
1919 dev = pci_scan_single_device(bus, devfn + fn);
1923 dev->multifunction = 1;
1927 /* only one slot has pcie device */
1928 if (bus->self && nr)
1929 pcie_aspm_init_link_state(bus->self);
1933 EXPORT_SYMBOL(pci_scan_slot);
1935 static int pcie_find_smpss(struct pci_dev *dev, void *data)
1939 if (!pci_is_pcie(dev))
1943 * We don't have a way to change MPS settings on devices that have
1944 * drivers attached. A hot-added device might support only the minimum
1945 * MPS setting (MPS=128). Therefore, if the fabric contains a bridge
1946 * where devices may be hot-added, we limit the fabric MPS to 128 so
1947 * hot-added devices will work correctly.
1949 * However, if we hot-add a device to a slot directly below a Root
1950 * Port, it's impossible for there to be other existing devices below
1951 * the port. We don't limit the MPS in this case because we can
1952 * reconfigure MPS on both the Root Port and the hot-added device,
1953 * and there are no other devices involved.
1955 * Note that this PCIE_BUS_SAFE path assumes no peer-to-peer DMA.
1957 if (dev->is_hotplug_bridge &&
1958 pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
1961 if (*smpss > dev->pcie_mpss)
1962 *smpss = dev->pcie_mpss;
1967 static void pcie_write_mps(struct pci_dev *dev, int mps)
1971 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
1972 mps = 128 << dev->pcie_mpss;
1974 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT &&
1976 /* For "Performance", the assumption is made that
1977 * downstream communication will never be larger than
1978 * the MRRS. So, the MPS only needs to be configured
1979 * for the upstream communication. This being the case,
1980 * walk from the top down and set the MPS of the child
1981 * to that of the parent bus.
1983 * Configure the device MPS with the smaller of the
1984 * device MPSS or the bridge MPS (which is assumed to be
1985 * properly configured at this point to the largest
1986 * allowable MPS based on its parent bus).
1988 mps = min(mps, pcie_get_mps(dev->bus->self));
1991 rc = pcie_set_mps(dev, mps);
1993 dev_err(&dev->dev, "Failed attempting to set the MPS\n");
1996 static void pcie_write_mrrs(struct pci_dev *dev)
2000 /* In the "safe" case, do not configure the MRRS. There appear to be
2001 * issues with setting MRRS to 0 on a number of devices.
2003 if (pcie_bus_config != PCIE_BUS_PERFORMANCE)
2006 /* For Max performance, the MRRS must be set to the largest supported
2007 * value. However, it cannot be configured larger than the MPS the
2008 * device or the bus can support. This should already be properly
2009 * configured by a prior call to pcie_write_mps.
2011 mrrs = pcie_get_mps(dev);
2013 /* MRRS is a R/W register. Invalid values can be written, but a
2014 * subsequent read will verify if the value is acceptable or not.
2015 * If the MRRS value provided is not acceptable (e.g., too large),
2016 * shrink the value until it is acceptable to the HW.
2018 while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) {
2019 rc = pcie_set_readrq(dev, mrrs);
2023 dev_warn(&dev->dev, "Failed attempting to set the MRRS\n");
2028 dev_err(&dev->dev, "MRRS was unable to be configured with a safe value. If problems are experienced, try running with pci=pcie_bus_safe\n");
2031 static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
2035 if (!pci_is_pcie(dev))
2038 if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||
2039 pcie_bus_config == PCIE_BUS_DEFAULT)
2042 mps = 128 << *(u8 *)data;
2043 orig_mps = pcie_get_mps(dev);
2045 pcie_write_mps(dev, mps);
2046 pcie_write_mrrs(dev);
2048 dev_info(&dev->dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n",
2049 pcie_get_mps(dev), 128 << dev->pcie_mpss,
2050 orig_mps, pcie_get_readrq(dev));
2055 /* pcie_bus_configure_settings requires that pci_walk_bus work in a top-down,
2056 * parents then children fashion. If this changes, then this code will not
2059 void pcie_bus_configure_settings(struct pci_bus *bus)
2066 if (!pci_is_pcie(bus->self))
2069 /* FIXME - Peer to peer DMA is possible, though the endpoint would need
2070 * to be aware of the MPS of the destination. To work around this,
2071 * simply force the MPS of the entire system to the smallest possible.
2073 if (pcie_bus_config == PCIE_BUS_PEER2PEER)
2076 if (pcie_bus_config == PCIE_BUS_SAFE) {
2077 smpss = bus->self->pcie_mpss;
2079 pcie_find_smpss(bus->self, &smpss);
2080 pci_walk_bus(bus, pcie_find_smpss, &smpss);
2083 pcie_bus_configure_set(bus->self, &smpss);
2084 pci_walk_bus(bus, pcie_bus_configure_set, &smpss);
2086 EXPORT_SYMBOL_GPL(pcie_bus_configure_settings);
2088 unsigned int pci_scan_child_bus(struct pci_bus *bus)
2090 unsigned int devfn, pass, max = bus->busn_res.start;
2091 struct pci_dev *dev;
2093 dev_dbg(&bus->dev, "scanning bus\n");
2095 /* Go find them, Rover! */
2096 for (devfn = 0; devfn < 0x100; devfn += 8)
2097 pci_scan_slot(bus, devfn);
2099 /* Reserve buses for SR-IOV capability. */
2100 max += pci_iov_bus_range(bus);
2103 * After performing arch-dependent fixup of the bus, look behind
2104 * all PCI-to-PCI bridges on this bus.
2106 if (!bus->is_added) {
2107 dev_dbg(&bus->dev, "fixups for bus\n");
2108 pcibios_fixup_bus(bus);
2112 for (pass = 0; pass < 2; pass++)
2113 list_for_each_entry(dev, &bus->devices, bus_list) {
2114 if (pci_is_bridge(dev))
2115 max = pci_scan_bridge(bus, dev, max, pass);
2119 * Make sure a hotplug bridge has at least the minimum requested
2122 if (bus->self && bus->self->is_hotplug_bridge && pci_hotplug_bus_size) {
2123 if (max - bus->busn_res.start < pci_hotplug_bus_size - 1)
2124 max = bus->busn_res.start + pci_hotplug_bus_size - 1;
2128 * We've scanned the bus and so we know all about what's on
2129 * the other side of any bridges that may be on this bus plus
2132 * Return how far we've got finding sub-buses.
2134 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max);
2137 EXPORT_SYMBOL_GPL(pci_scan_child_bus);
2140 * pcibios_root_bridge_prepare - Platform-specific host bridge setup.
2141 * @bridge: Host bridge to set up.
2143 * Default empty implementation. Replace with an architecture-specific setup
2144 * routine, if necessary.
2146 int __weak pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
2151 void __weak pcibios_add_bus(struct pci_bus *bus)
2155 void __weak pcibios_remove_bus(struct pci_bus *bus)
2159 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
2160 struct pci_ops *ops, void *sysdata, struct list_head *resources)
2163 struct pci_host_bridge *bridge;
2164 struct pci_bus *b, *b2;
2165 struct resource_entry *window, *n;
2166 struct resource *res;
2167 resource_size_t offset;
2171 b = pci_alloc_bus(NULL);
2175 b->sysdata = sysdata;
2177 b->number = b->busn_res.start = bus;
2178 #ifdef CONFIG_PCI_DOMAINS_GENERIC
2179 b->domain_nr = pci_bus_find_domain_nr(b, parent);
2181 b2 = pci_find_bus(pci_domain_nr(b), bus);
2183 /* If we already got to this bus through a different bridge, ignore it */
2184 dev_dbg(&b2->dev, "bus already known\n");
2188 bridge = pci_alloc_host_bridge(b);
2192 bridge->dev.parent = parent;
2193 bridge->dev.release = pci_release_host_bridge_dev;
2194 dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(b), bus);
2195 error = pcibios_root_bridge_prepare(bridge);
2201 error = device_register(&bridge->dev);
2203 put_device(&bridge->dev);
2206 b->bridge = get_device(&bridge->dev);
2207 device_enable_async_suspend(b->bridge);
2208 pci_set_bus_of_node(b);
2209 pci_set_bus_msi_domain(b);
2212 set_dev_node(b->bridge, pcibus_to_node(b));
2214 b->dev.class = &pcibus_class;
2215 b->dev.parent = b->bridge;
2216 dev_set_name(&b->dev, "%04x:%02x", pci_domain_nr(b), bus);
2217 error = device_register(&b->dev);
2219 goto class_dev_reg_err;
2223 /* Create legacy_io and legacy_mem files for this bus */
2224 pci_create_legacy_files(b);
2227 dev_info(parent, "PCI host bridge to bus %s\n", dev_name(&b->dev));
2229 printk(KERN_INFO "PCI host bridge to bus %s\n", dev_name(&b->dev));
2231 /* Add initial resources to the bus */
2232 resource_list_for_each_entry_safe(window, n, resources) {
2233 list_move_tail(&window->node, &bridge->windows);
2235 offset = window->offset;
2236 if (res->flags & IORESOURCE_BUS)
2237 pci_bus_insert_busn_res(b, bus, res->end);
2239 pci_bus_add_resource(b, res, 0);
2241 if (resource_type(res) == IORESOURCE_IO)
2242 fmt = " (bus address [%#06llx-%#06llx])";
2244 fmt = " (bus address [%#010llx-%#010llx])";
2245 snprintf(bus_addr, sizeof(bus_addr), fmt,
2246 (unsigned long long) (res->start - offset),
2247 (unsigned long long) (res->end - offset));
2250 dev_info(&b->dev, "root bus resource %pR%s\n", res, bus_addr);
2253 down_write(&pci_bus_sem);
2254 list_add_tail(&b->node, &pci_root_buses);
2255 up_write(&pci_bus_sem);
2260 put_device(&bridge->dev);
2261 device_unregister(&bridge->dev);
2266 EXPORT_SYMBOL_GPL(pci_create_root_bus);
2268 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max)
2270 struct resource *res = &b->busn_res;
2271 struct resource *parent_res, *conflict;
2275 res->flags = IORESOURCE_BUS;
2277 if (!pci_is_root_bus(b))
2278 parent_res = &b->parent->busn_res;
2280 parent_res = get_pci_domain_busn_res(pci_domain_nr(b));
2281 res->flags |= IORESOURCE_PCI_FIXED;
2284 conflict = request_resource_conflict(parent_res, res);
2287 dev_printk(KERN_DEBUG, &b->dev,
2288 "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n",
2289 res, pci_is_root_bus(b) ? "domain " : "",
2290 parent_res, conflict->name, conflict);
2292 return conflict == NULL;
2295 int pci_bus_update_busn_res_end(struct pci_bus *b, int bus_max)
2297 struct resource *res = &b->busn_res;
2298 struct resource old_res = *res;
2299 resource_size_t size;
2302 if (res->start > bus_max)
2305 size = bus_max - res->start + 1;
2306 ret = adjust_resource(res, res->start, size);
2307 dev_printk(KERN_DEBUG, &b->dev,
2308 "busn_res: %pR end %s updated to %02x\n",
2309 &old_res, ret ? "can not be" : "is", bus_max);
2311 if (!ret && !res->parent)
2312 pci_bus_insert_busn_res(b, res->start, res->end);
2317 void pci_bus_release_busn_res(struct pci_bus *b)
2319 struct resource *res = &b->busn_res;
2322 if (!res->flags || !res->parent)
2325 ret = release_resource(res);
2326 dev_printk(KERN_DEBUG, &b->dev,
2327 "busn_res: %pR %s released\n",
2328 res, ret ? "can not be" : "is");
2331 struct pci_bus *pci_scan_root_bus_msi(struct device *parent, int bus,
2332 struct pci_ops *ops, void *sysdata,
2333 struct list_head *resources, struct msi_controller *msi)
2335 struct resource_entry *window;
2340 resource_list_for_each_entry(window, resources)
2341 if (window->res->flags & IORESOURCE_BUS) {
2346 b = pci_create_root_bus(parent, bus, ops, sysdata, resources);
2354 "No busn resource found for root bus, will use [bus %02x-ff]\n",
2356 pci_bus_insert_busn_res(b, bus, 255);
2359 max = pci_scan_child_bus(b);
2362 pci_bus_update_busn_res_end(b, max);
2367 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
2368 struct pci_ops *ops, void *sysdata, struct list_head *resources)
2370 return pci_scan_root_bus_msi(parent, bus, ops, sysdata, resources,
2373 EXPORT_SYMBOL(pci_scan_root_bus);
2375 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops,
2378 LIST_HEAD(resources);
2381 pci_add_resource(&resources, &ioport_resource);
2382 pci_add_resource(&resources, &iomem_resource);
2383 pci_add_resource(&resources, &busn_resource);
2384 b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources);
2386 pci_scan_child_bus(b);
2388 pci_free_resource_list(&resources);
2392 EXPORT_SYMBOL(pci_scan_bus);
2395 * pci_rescan_bus_bridge_resize - scan a PCI bus for devices.
2396 * @bridge: PCI bridge for the bus to scan
2398 * Scan a PCI bus and child buses for new devices, add them,
2399 * and enable them, resizing bridge mmio/io resource if necessary
2400 * and possible. The caller must ensure the child devices are already
2401 * removed for resizing to occur.
2403 * Returns the max number of subordinate bus discovered.
2405 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge)
2408 struct pci_bus *bus = bridge->subordinate;
2410 max = pci_scan_child_bus(bus);
2412 pci_assign_unassigned_bridge_resources(bridge);
2414 pci_bus_add_devices(bus);
2420 * pci_rescan_bus - scan a PCI bus for devices.
2421 * @bus: PCI bus to scan
2423 * Scan a PCI bus and child buses for new devices, adds them,
2426 * Returns the max number of subordinate bus discovered.
2428 unsigned int pci_rescan_bus(struct pci_bus *bus)
2432 max = pci_scan_child_bus(bus);
2433 pci_assign_unassigned_bus_resources(bus);
2434 pci_bus_add_devices(bus);
2438 EXPORT_SYMBOL_GPL(pci_rescan_bus);
2441 * pci_rescan_bus(), pci_rescan_bus_bridge_resize() and PCI device removal
2442 * routines should always be executed under this mutex.
2444 static DEFINE_MUTEX(pci_rescan_remove_lock);
2446 void pci_lock_rescan_remove(void)
2448 mutex_lock(&pci_rescan_remove_lock);
2450 EXPORT_SYMBOL_GPL(pci_lock_rescan_remove);
2452 void pci_unlock_rescan_remove(void)
2454 mutex_unlock(&pci_rescan_remove_lock);
2456 EXPORT_SYMBOL_GPL(pci_unlock_rescan_remove);
2458 static int __init pci_sort_bf_cmp(const struct device *d_a,
2459 const struct device *d_b)
2461 const struct pci_dev *a = to_pci_dev(d_a);
2462 const struct pci_dev *b = to_pci_dev(d_b);
2464 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
2465 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
2467 if (a->bus->number < b->bus->number) return -1;
2468 else if (a->bus->number > b->bus->number) return 1;
2470 if (a->devfn < b->devfn) return -1;
2471 else if (a->devfn > b->devfn) return 1;
2476 void __init pci_sort_breadthfirst(void)
2478 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp);