2 * probe.c - PCI detection and setup code
5 #include <linux/kernel.h>
6 #include <linux/delay.h>
7 #include <linux/init.h>
9 #include <linux/slab.h>
10 #include <linux/module.h>
11 #include <linux/cpumask.h>
12 #include <linux/pci-aspm.h>
15 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
16 #define CARDBUS_RESERVE_BUSNR 3
17 #define PCI_CFG_SPACE_SIZE 256
18 #define PCI_CFG_SPACE_EXP_SIZE 4096
20 /* Ugh. Need to stop exporting this to modules. */
21 LIST_HEAD(pci_root_buses);
22 EXPORT_SYMBOL(pci_root_buses);
25 static int find_anything(struct device *dev, void *data)
31 * Some device drivers need know if pci is initiated.
32 * Basically, we think pci is not initiated when there
33 * is no device to be found on the pci_bus_type.
35 int no_pci_devices(void)
40 dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything);
41 no_devices = (dev == NULL);
45 EXPORT_SYMBOL(no_pci_devices);
47 #ifdef HAVE_PCI_LEGACY
49 * pci_create_legacy_files - create legacy I/O port and memory files
50 * @b: bus to create files under
52 * Some platforms allow access to legacy I/O port and ISA memory space on
53 * a per-bus basis. This routine creates the files and ties them into
54 * their associated read, write and mmap files from pci-sysfs.c
56 static void pci_create_legacy_files(struct pci_bus *b)
58 b->legacy_io = kzalloc(sizeof(struct bin_attribute) * 2,
61 b->legacy_io->attr.name = "legacy_io";
62 b->legacy_io->size = 0xffff;
63 b->legacy_io->attr.mode = S_IRUSR | S_IWUSR;
64 b->legacy_io->read = pci_read_legacy_io;
65 b->legacy_io->write = pci_write_legacy_io;
66 device_create_bin_file(&b->dev, b->legacy_io);
68 /* Allocated above after the legacy_io struct */
69 b->legacy_mem = b->legacy_io + 1;
70 b->legacy_mem->attr.name = "legacy_mem";
71 b->legacy_mem->size = 1024*1024;
72 b->legacy_mem->attr.mode = S_IRUSR | S_IWUSR;
73 b->legacy_mem->mmap = pci_mmap_legacy_mem;
74 device_create_bin_file(&b->dev, b->legacy_mem);
78 void pci_remove_legacy_files(struct pci_bus *b)
81 device_remove_bin_file(&b->dev, b->legacy_io);
82 device_remove_bin_file(&b->dev, b->legacy_mem);
83 kfree(b->legacy_io); /* both are allocated here */
86 #else /* !HAVE_PCI_LEGACY */
87 static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
88 void pci_remove_legacy_files(struct pci_bus *bus) { return; }
89 #endif /* HAVE_PCI_LEGACY */
92 * PCI Bus Class Devices
94 static ssize_t pci_bus_show_cpuaffinity(struct device *dev,
95 struct device_attribute *attr,
101 cpumask = pcibus_to_cpumask(to_pci_bus(dev));
102 ret = cpumask_scnprintf(buf, PAGE_SIZE, cpumask);
107 DEVICE_ATTR(cpuaffinity, S_IRUGO, pci_bus_show_cpuaffinity, NULL);
112 static void release_pcibus_dev(struct device *dev)
114 struct pci_bus *pci_bus = to_pci_bus(dev);
117 put_device(pci_bus->bridge);
121 static struct class pcibus_class = {
123 .dev_release = &release_pcibus_dev,
126 static int __init pcibus_class_init(void)
128 return class_register(&pcibus_class);
130 postcore_initcall(pcibus_class_init);
133 * Translate the low bits of the PCI base
134 * to the resource type
136 static inline unsigned int pci_calc_resource_flags(unsigned int flags)
138 if (flags & PCI_BASE_ADDRESS_SPACE_IO)
139 return IORESOURCE_IO;
141 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
142 return IORESOURCE_MEM | IORESOURCE_PREFETCH;
144 return IORESOURCE_MEM;
148 * Find the extent of a PCI decode..
150 static u32 pci_size(u32 base, u32 maxbase, u32 mask)
152 u32 size = mask & maxbase; /* Find the significant bits */
156 /* Get the lowest of them to find the decode size, and
157 from that the extent. */
158 size = (size & ~(size-1)) - 1;
160 /* base == maxbase can be valid only if the BAR has
161 already been programmed with all 1s. */
162 if (base == maxbase && ((base | size) & mask) != mask)
168 static u64 pci_size64(u64 base, u64 maxbase, u64 mask)
170 u64 size = mask & maxbase; /* Find the significant bits */
174 /* Get the lowest of them to find the decode size, and
175 from that the extent. */
176 size = (size & ~(size-1)) - 1;
178 /* base == maxbase can be valid only if the BAR has
179 already been programmed with all 1s. */
180 if (base == maxbase && ((base | size) & mask) != mask)
186 static inline int is_64bit_memory(u32 mask)
188 if ((mask & (PCI_BASE_ADDRESS_SPACE|PCI_BASE_ADDRESS_MEM_TYPE_MASK)) ==
189 (PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64))
194 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
196 unsigned int pos, reg, next;
198 struct resource *res;
200 for(pos=0; pos<howmany; pos = next) {
206 res = &dev->resource[pos];
207 res->name = pci_name(dev);
208 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
209 pci_read_config_dword(dev, reg, &l);
210 pci_write_config_dword(dev, reg, ~0);
211 pci_read_config_dword(dev, reg, &sz);
212 pci_write_config_dword(dev, reg, l);
213 if (!sz || sz == 0xffffffff)
218 if ((l & PCI_BASE_ADDRESS_SPACE) ==
219 PCI_BASE_ADDRESS_SPACE_MEMORY) {
220 sz = pci_size(l, sz, (u32)PCI_BASE_ADDRESS_MEM_MASK);
222 * For 64bit prefetchable memory sz could be 0, if the
223 * real size is bigger than 4G, so we need to check
226 if (!is_64bit_memory(l) && !sz)
228 res->start = l & PCI_BASE_ADDRESS_MEM_MASK;
229 res->flags |= l & ~PCI_BASE_ADDRESS_MEM_MASK;
231 sz = pci_size(l, sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff);
234 res->start = l & PCI_BASE_ADDRESS_IO_MASK;
235 res->flags |= l & ~PCI_BASE_ADDRESS_IO_MASK;
237 res->end = res->start + (unsigned long) sz;
238 res->flags |= pci_calc_resource_flags(l) | IORESOURCE_SIZEALIGN;
239 if (is_64bit_memory(l)) {
242 pci_read_config_dword(dev, reg+4, &lhi);
243 pci_write_config_dword(dev, reg+4, ~0);
244 pci_read_config_dword(dev, reg+4, &szhi);
245 pci_write_config_dword(dev, reg+4, lhi);
246 sz64 = ((u64)szhi << 32) | raw_sz;
247 l64 = ((u64)lhi << 32) | l;
248 sz64 = pci_size64(l64, sz64, PCI_BASE_ADDRESS_MEM_MASK);
250 #if BITS_PER_LONG == 64
257 res->start = l64 & PCI_BASE_ADDRESS_MEM_MASK;
258 res->end = res->start + sz64;
260 if (sz64 > 0x100000000ULL) {
261 printk(KERN_ERR "PCI: Unable to handle 64-bit "
262 "BAR for device %s\n", pci_name(dev));
266 /* 64-bit wide address, treat as disabled */
267 pci_write_config_dword(dev, reg,
268 l & ~(u32)PCI_BASE_ADDRESS_MEM_MASK);
269 pci_write_config_dword(dev, reg+4, 0);
277 dev->rom_base_reg = rom;
278 res = &dev->resource[PCI_ROM_RESOURCE];
279 res->name = pci_name(dev);
280 pci_read_config_dword(dev, rom, &l);
281 pci_write_config_dword(dev, rom, ~PCI_ROM_ADDRESS_ENABLE);
282 pci_read_config_dword(dev, rom, &sz);
283 pci_write_config_dword(dev, rom, l);
286 if (sz && sz != 0xffffffff) {
287 sz = pci_size(l, sz, (u32)PCI_ROM_ADDRESS_MASK);
289 res->flags = (l & IORESOURCE_ROM_ENABLE) |
290 IORESOURCE_MEM | IORESOURCE_PREFETCH |
291 IORESOURCE_READONLY | IORESOURCE_CACHEABLE |
292 IORESOURCE_SIZEALIGN;
293 res->start = l & PCI_ROM_ADDRESS_MASK;
294 res->end = res->start + (unsigned long) sz;
300 void __devinit pci_read_bridge_bases(struct pci_bus *child)
302 struct pci_dev *dev = child->self;
303 u8 io_base_lo, io_limit_lo;
304 u16 mem_base_lo, mem_limit_lo;
305 unsigned long base, limit;
306 struct resource *res;
309 if (!dev) /* It's a host bus, nothing to read */
312 if (dev->transparent) {
313 printk(KERN_INFO "PCI: Transparent bridge - %s\n", pci_name(dev));
314 for(i = 3; i < PCI_BUS_NUM_RESOURCES; i++)
315 child->resource[i] = child->parent->resource[i - 3];
319 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
321 res = child->resource[0];
322 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
323 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
324 base = (io_base_lo & PCI_IO_RANGE_MASK) << 8;
325 limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8;
327 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
328 u16 io_base_hi, io_limit_hi;
329 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
330 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
331 base |= (io_base_hi << 16);
332 limit |= (io_limit_hi << 16);
336 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
340 res->end = limit + 0xfff;
343 res = child->resource[1];
344 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
345 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
346 base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
347 limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
349 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
351 res->end = limit + 0xfffff;
354 res = child->resource[2];
355 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
356 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
357 base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
358 limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
360 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
361 u32 mem_base_hi, mem_limit_hi;
362 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
363 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
366 * Some bridges set the base > limit by default, and some
367 * (broken) BIOSes do not initialize them. If we find
368 * this, just assume they are not being used.
370 if (mem_base_hi <= mem_limit_hi) {
371 #if BITS_PER_LONG == 64
372 base |= ((long) mem_base_hi) << 32;
373 limit |= ((long) mem_limit_hi) << 32;
375 if (mem_base_hi || mem_limit_hi) {
376 printk(KERN_ERR "PCI: Unable to handle 64-bit address space for bridge %s\n", pci_name(dev));
383 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM | IORESOURCE_PREFETCH;
385 res->end = limit + 0xfffff;
389 static struct pci_bus * pci_alloc_bus(void)
393 b = kzalloc(sizeof(*b), GFP_KERNEL);
395 INIT_LIST_HEAD(&b->node);
396 INIT_LIST_HEAD(&b->children);
397 INIT_LIST_HEAD(&b->devices);
402 static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
403 struct pci_dev *bridge, int busnr)
405 struct pci_bus *child;
409 * Allocate a new bus, and inherit stuff from the parent..
411 child = pci_alloc_bus();
415 child->self = bridge;
416 child->parent = parent;
417 child->ops = parent->ops;
418 child->sysdata = parent->sysdata;
419 child->bus_flags = parent->bus_flags;
420 child->bridge = get_device(&bridge->dev);
422 /* initialize some portions of the bus device, but don't register it
423 * now as the parent is not properly set up yet. This device will get
424 * registered later in pci_bus_add_devices()
426 child->dev.class = &pcibus_class;
427 sprintf(child->dev.bus_id, "%04x:%02x", pci_domain_nr(child), busnr);
430 * Set up the primary, secondary and subordinate
433 child->number = child->secondary = busnr;
434 child->primary = parent->secondary;
435 child->subordinate = 0xff;
437 /* Set up default resource pointers and names.. */
438 for (i = 0; i < 4; i++) {
439 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
440 child->resource[i]->name = child->name;
442 bridge->subordinate = child;
447 struct pci_bus *__ref pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr)
449 struct pci_bus *child;
451 child = pci_alloc_child_bus(parent, dev, busnr);
453 down_write(&pci_bus_sem);
454 list_add_tail(&child->node, &parent->children);
455 up_write(&pci_bus_sem);
460 static void pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max)
462 struct pci_bus *parent = child->parent;
464 /* Attempts to fix that up are really dangerous unless
465 we're going to re-assign all bus numbers. */
466 if (!pcibios_assign_all_busses())
469 while (parent->parent && parent->subordinate < max) {
470 parent->subordinate = max;
471 pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max);
472 parent = parent->parent;
477 * If it's a bridge, configure it and scan the bus behind it.
478 * For CardBus bridges, we don't scan behind as the devices will
479 * be handled by the bridge driver itself.
481 * We need to process bridges in two passes -- first we scan those
482 * already configured by the BIOS and after we are done with all of
483 * them, we proceed to assigning numbers to the remaining buses in
484 * order to avoid overlaps between old and new bus numbers.
486 int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
488 struct pci_bus *child;
489 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
493 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
495 pr_debug("PCI: Scanning behind PCI bridge %s, config %06x, pass %d\n",
496 pci_name(dev), buses & 0xffffff, pass);
498 /* Disable MasterAbortMode during probing to avoid reporting
499 of bus errors (in some architectures) */
500 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
501 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
502 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
504 if ((buses & 0xffff00) && !pcibios_assign_all_busses() && !is_cardbus) {
505 unsigned int cmax, busnr;
507 * Bus already configured by firmware, process it in the first
508 * pass and just note the configuration.
512 busnr = (buses >> 8) & 0xFF;
515 * If we already got to this bus through a different bridge,
516 * ignore it. This can happen with the i450NX chipset.
518 if (pci_find_bus(pci_domain_nr(bus), busnr)) {
519 printk(KERN_INFO "PCI: Bus %04x:%02x already known\n",
520 pci_domain_nr(bus), busnr);
524 child = pci_add_new_bus(bus, dev, busnr);
527 child->primary = buses & 0xFF;
528 child->subordinate = (buses >> 16) & 0xFF;
529 child->bridge_ctl = bctl;
531 cmax = pci_scan_child_bus(child);
534 if (child->subordinate > max)
535 max = child->subordinate;
538 * We need to assign a number to this bus which we always
539 * do in the second pass.
542 if (pcibios_assign_all_busses())
543 /* Temporarily disable forwarding of the
544 configuration cycles on all bridges in
545 this bus segment to avoid possible
546 conflicts in the second pass between two
547 bridges programmed with overlapping
549 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
555 pci_write_config_word(dev, PCI_STATUS, 0xffff);
557 /* Prevent assigning a bus number that already exists.
558 * This can happen when a bridge is hot-plugged */
559 if (pci_find_bus(pci_domain_nr(bus), max+1))
561 child = pci_add_new_bus(bus, dev, ++max);
562 buses = (buses & 0xff000000)
563 | ((unsigned int)(child->primary) << 0)
564 | ((unsigned int)(child->secondary) << 8)
565 | ((unsigned int)(child->subordinate) << 16);
568 * yenta.c forces a secondary latency timer of 176.
569 * Copy that behaviour here.
572 buses &= ~0xff000000;
573 buses |= CARDBUS_LATENCY_TIMER << 24;
577 * We need to blast all three values with a single write.
579 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
582 child->bridge_ctl = bctl;
584 * Adjust subordinate busnr in parent buses.
585 * We do this before scanning for children because
586 * some devices may not be detected if the bios
589 pci_fixup_parent_subordinate_busnr(child, max);
590 /* Now we can scan all subordinate buses... */
591 max = pci_scan_child_bus(child);
593 * now fix it up again since we have found
594 * the real value of max.
596 pci_fixup_parent_subordinate_busnr(child, max);
599 * For CardBus bridges, we leave 4 bus numbers
600 * as cards with a PCI-to-PCI bridge can be
603 for (i=0; i<CARDBUS_RESERVE_BUSNR; i++) {
604 struct pci_bus *parent = bus;
605 if (pci_find_bus(pci_domain_nr(bus),
608 while (parent->parent) {
609 if ((!pcibios_assign_all_busses()) &&
610 (parent->subordinate > max) &&
611 (parent->subordinate <= max+i)) {
614 parent = parent->parent;
618 * Often, there are two cardbus bridges
619 * -- try to leave one valid bus number
627 pci_fixup_parent_subordinate_busnr(child, max);
630 * Set the subordinate bus number to its real value.
632 child->subordinate = max;
633 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
637 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
638 pci_domain_nr(bus), child->number);
640 /* Has only triggered on CardBus, fixup is in yenta_socket */
641 while (bus->parent) {
642 if ((child->subordinate > bus->subordinate) ||
643 (child->number > bus->subordinate) ||
644 (child->number < bus->number) ||
645 (child->subordinate < bus->number)) {
646 pr_debug("PCI: Bus #%02x (-#%02x) is %s "
647 "hidden behind%s bridge #%02x (-#%02x)\n",
648 child->number, child->subordinate,
649 (bus->number > child->subordinate &&
650 bus->subordinate < child->number) ?
651 "wholly" : "partially",
652 bus->self->transparent ? " transparent" : "",
653 bus->number, bus->subordinate);
659 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
665 * Read interrupt line and base address registers.
666 * The architecture-dependent code can tweak these, of course.
668 static void pci_read_irq(struct pci_dev *dev)
672 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
675 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
679 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
682 * pci_setup_device - fill in class and map information of a device
683 * @dev: the device structure to fill
685 * Initialize the device structure with information about the device's
686 * vendor,class,memory and IO-space addresses,IRQ lines etc.
687 * Called at initialisation of the PCI subsystem and by CardBus services.
688 * Returns 0 on success and -1 if unknown type of device (not normal, bridge
691 static int pci_setup_device(struct pci_dev * dev)
695 sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
696 dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
698 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
699 dev->revision = class & 0xff;
700 class >>= 8; /* upper 3 bytes */
704 pr_debug("PCI: Found %s [%04x/%04x] %06x %02x\n", pci_name(dev),
705 dev->vendor, dev->device, class, dev->hdr_type);
707 /* "Unknown power state" */
708 dev->current_state = PCI_UNKNOWN;
710 /* Early fixups, before probing the BARs */
711 pci_fixup_device(pci_fixup_early, dev);
712 class = dev->class >> 8;
714 switch (dev->hdr_type) { /* header type */
715 case PCI_HEADER_TYPE_NORMAL: /* standard header */
716 if (class == PCI_CLASS_BRIDGE_PCI)
719 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
720 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
721 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
724 * Do the ugly legacy mode stuff here rather than broken chip
725 * quirk code. Legacy mode ATA controllers have fixed
726 * addresses. These are not always echoed in BAR0-3, and
727 * BAR0-3 in a few cases contain junk!
729 if (class == PCI_CLASS_STORAGE_IDE) {
731 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
732 if ((progif & 1) == 0) {
733 dev->resource[0].start = 0x1F0;
734 dev->resource[0].end = 0x1F7;
735 dev->resource[0].flags = LEGACY_IO_RESOURCE;
736 dev->resource[1].start = 0x3F6;
737 dev->resource[1].end = 0x3F6;
738 dev->resource[1].flags = LEGACY_IO_RESOURCE;
740 if ((progif & 4) == 0) {
741 dev->resource[2].start = 0x170;
742 dev->resource[2].end = 0x177;
743 dev->resource[2].flags = LEGACY_IO_RESOURCE;
744 dev->resource[3].start = 0x376;
745 dev->resource[3].end = 0x376;
746 dev->resource[3].flags = LEGACY_IO_RESOURCE;
751 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
752 if (class != PCI_CLASS_BRIDGE_PCI)
754 /* The PCI-to-PCI bridge spec requires that subtractive
755 decoding (i.e. transparent) bridge must have programming
756 interface code of 0x01. */
758 dev->transparent = ((dev->class & 0xff) == 1);
759 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
762 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
763 if (class != PCI_CLASS_BRIDGE_CARDBUS)
766 pci_read_bases(dev, 1, 0);
767 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
768 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
771 default: /* unknown header */
772 printk(KERN_ERR "PCI: device %s has unknown header type %02x, ignoring.\n",
773 pci_name(dev), dev->hdr_type);
777 printk(KERN_ERR "PCI: %s: class %x doesn't match header type %02x. Ignoring class.\n",
778 pci_name(dev), class, dev->hdr_type);
779 dev->class = PCI_CLASS_NOT_DEFINED;
782 /* We found a fine healthy device, go go go... */
787 * pci_release_dev - free a pci device structure when all users of it are finished.
788 * @dev: device that's been disconnected
790 * Will be called only by the device core when all users of this pci device are
793 static void pci_release_dev(struct device *dev)
795 struct pci_dev *pci_dev;
797 pci_dev = to_pci_dev(dev);
798 pci_vpd_release(pci_dev);
802 static void set_pcie_port_type(struct pci_dev *pdev)
807 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
811 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
812 pdev->pcie_type = (reg16 & PCI_EXP_FLAGS_TYPE) >> 4;
816 * pci_cfg_space_size - get the configuration space size of the PCI device.
819 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
820 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
821 * access it. Maybe we don't have a way to generate extended config space
822 * accesses, or the device is behind a reverse Express bridge. So we try
823 * reading the dword at 0x100 which must either be 0 or a valid extended
826 int pci_cfg_space_size(struct pci_dev *dev)
831 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
833 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
837 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
838 if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
842 if (pci_read_config_dword(dev, 256, &status) != PCIBIOS_SUCCESSFUL)
844 if (status == 0xffffffff)
847 return PCI_CFG_SPACE_EXP_SIZE;
850 return PCI_CFG_SPACE_SIZE;
853 static void pci_release_bus_bridge_dev(struct device *dev)
858 struct pci_dev *alloc_pci_dev(void)
862 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
866 INIT_LIST_HEAD(&dev->bus_list);
868 pci_msi_init_pci_dev(dev);
872 EXPORT_SYMBOL(alloc_pci_dev);
875 * Read the config data for a PCI device, sanity-check it
876 * and fill in the dev structure...
878 static struct pci_dev * __devinit
879 pci_scan_device(struct pci_bus *bus, int devfn)
886 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
889 /* some broken boards return 0 or ~0 if a slot is empty: */
890 if (l == 0xffffffff || l == 0x00000000 ||
891 l == 0x0000ffff || l == 0xffff0000)
894 /* Configuration request Retry Status */
895 while (l == 0xffff0001) {
898 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
900 /* Card hasn't responded in 60 seconds? Must be stuck. */
901 if (delay > 60 * 1000) {
902 printk(KERN_WARNING "Device %04x:%02x:%02x.%d not "
903 "responding\n", pci_domain_nr(bus),
904 bus->number, PCI_SLOT(devfn),
910 if (pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type))
913 dev = alloc_pci_dev();
918 dev->sysdata = bus->sysdata;
919 dev->dev.parent = bus->bridge;
920 dev->dev.bus = &pci_bus_type;
922 dev->hdr_type = hdr_type & 0x7f;
923 dev->multifunction = !!(hdr_type & 0x80);
924 dev->vendor = l & 0xffff;
925 dev->device = (l >> 16) & 0xffff;
926 dev->cfg_size = pci_cfg_space_size(dev);
927 dev->error_state = pci_channel_io_normal;
928 set_pcie_port_type(dev);
930 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
931 set this higher, assuming the system even supports it. */
932 dev->dma_mask = 0xffffffff;
933 if (pci_setup_device(dev) < 0) {
938 pci_vpd_pci22_init(dev);
943 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
945 device_initialize(&dev->dev);
946 dev->dev.release = pci_release_dev;
949 set_dev_node(&dev->dev, pcibus_to_node(bus));
950 dev->dev.dma_mask = &dev->dma_mask;
951 dev->dev.dma_parms = &dev->dma_parms;
952 dev->dev.coherent_dma_mask = 0xffffffffull;
954 pci_set_dma_max_seg_size(dev, 65536);
955 pci_set_dma_seg_boundary(dev, 0xffffffff);
957 /* Fix up broken headers */
958 pci_fixup_device(pci_fixup_header, dev);
961 * Add the device to our list of discovered devices
962 * and the bus list for fixup functions, etc.
964 down_write(&pci_bus_sem);
965 list_add_tail(&dev->bus_list, &bus->devices);
966 up_write(&pci_bus_sem);
969 struct pci_dev *__ref pci_scan_single_device(struct pci_bus *bus, int devfn)
973 dev = pci_scan_device(bus, devfn);
977 pci_device_add(dev, bus);
981 EXPORT_SYMBOL(pci_scan_single_device);
984 * pci_scan_slot - scan a PCI slot on a bus for devices.
985 * @bus: PCI bus to scan
986 * @devfn: slot number to scan (must have zero function.)
988 * Scan a PCI slot on the specified PCI bus for devices, adding
989 * discovered devices to the @bus->devices list. New devices
990 * will not have is_added set.
992 int pci_scan_slot(struct pci_bus *bus, int devfn)
997 scan_all_fns = pcibios_scan_all_fns(bus, devfn);
999 for (func = 0; func < 8; func++, devfn++) {
1000 struct pci_dev *dev;
1002 dev = pci_scan_single_device(bus, devfn);
1007 * If this is a single function device,
1008 * don't scan past the first function.
1010 if (!dev->multifunction) {
1012 dev->multifunction = 1;
1018 if (func == 0 && !scan_all_fns)
1024 pcie_aspm_init_link_state(bus->self);
1029 unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus)
1031 unsigned int devfn, pass, max = bus->secondary;
1032 struct pci_dev *dev;
1034 pr_debug("PCI: Scanning bus %04x:%02x\n", pci_domain_nr(bus), bus->number);
1036 /* Go find them, Rover! */
1037 for (devfn = 0; devfn < 0x100; devfn += 8)
1038 pci_scan_slot(bus, devfn);
1041 * After performing arch-dependent fixup of the bus, look behind
1042 * all PCI-to-PCI bridges on this bus.
1044 pr_debug("PCI: Fixups for bus %04x:%02x\n", pci_domain_nr(bus), bus->number);
1045 pcibios_fixup_bus(bus);
1046 for (pass=0; pass < 2; pass++)
1047 list_for_each_entry(dev, &bus->devices, bus_list) {
1048 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
1049 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
1050 max = pci_scan_bridge(bus, dev, max, pass);
1054 * We've scanned the bus and so we know all about what's on
1055 * the other side of any bridges that may be on this bus plus
1058 * Return how far we've got finding sub-buses.
1060 pr_debug("PCI: Bus scan for %04x:%02x returning with max=%02x\n",
1061 pci_domain_nr(bus), bus->number, max);
1065 struct pci_bus * pci_create_bus(struct device *parent,
1066 int bus, struct pci_ops *ops, void *sysdata)
1072 b = pci_alloc_bus();
1076 dev = kmalloc(sizeof(*dev), GFP_KERNEL);
1082 b->sysdata = sysdata;
1085 if (pci_find_bus(pci_domain_nr(b), bus)) {
1086 /* If we already got to this bus through a different bridge, ignore it */
1087 pr_debug("PCI: Bus %04x:%02x already known\n", pci_domain_nr(b), bus);
1091 down_write(&pci_bus_sem);
1092 list_add_tail(&b->node, &pci_root_buses);
1093 up_write(&pci_bus_sem);
1095 memset(dev, 0, sizeof(*dev));
1096 dev->parent = parent;
1097 dev->release = pci_release_bus_bridge_dev;
1098 sprintf(dev->bus_id, "pci%04x:%02x", pci_domain_nr(b), bus);
1099 error = device_register(dev);
1102 b->bridge = get_device(dev);
1104 b->dev.class = &pcibus_class;
1105 b->dev.parent = b->bridge;
1106 sprintf(b->dev.bus_id, "%04x:%02x", pci_domain_nr(b), bus);
1107 error = device_register(&b->dev);
1109 goto class_dev_reg_err;
1110 error = device_create_file(&b->dev, &dev_attr_cpuaffinity);
1112 goto dev_create_file_err;
1114 /* Create legacy_io and legacy_mem files for this bus */
1115 pci_create_legacy_files(b);
1117 b->number = b->secondary = bus;
1118 b->resource[0] = &ioport_resource;
1119 b->resource[1] = &iomem_resource;
1123 dev_create_file_err:
1124 device_unregister(&b->dev);
1126 device_unregister(dev);
1128 down_write(&pci_bus_sem);
1130 up_write(&pci_bus_sem);
1137 struct pci_bus * __devinit pci_scan_bus_parented(struct device *parent,
1138 int bus, struct pci_ops *ops, void *sysdata)
1142 b = pci_create_bus(parent, bus, ops, sysdata);
1144 b->subordinate = pci_scan_child_bus(b);
1147 EXPORT_SYMBOL(pci_scan_bus_parented);
1149 #ifdef CONFIG_HOTPLUG
1150 EXPORT_SYMBOL(pci_add_new_bus);
1151 EXPORT_SYMBOL(pci_scan_slot);
1152 EXPORT_SYMBOL(pci_scan_bridge);
1153 EXPORT_SYMBOL_GPL(pci_scan_child_bus);
1156 static int __init pci_sort_bf_cmp(const struct pci_dev *a, const struct pci_dev *b)
1158 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
1159 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
1161 if (a->bus->number < b->bus->number) return -1;
1162 else if (a->bus->number > b->bus->number) return 1;
1164 if (a->devfn < b->devfn) return -1;
1165 else if (a->devfn > b->devfn) return 1;
1171 * Yes, this forcably breaks the klist abstraction temporarily. It
1172 * just wants to sort the klist, not change reference counts and
1173 * take/drop locks rapidly in the process. It does all this while
1174 * holding the lock for the list, so objects can't otherwise be
1175 * added/removed while we're swizzling.
1177 static void __init pci_insertion_sort_klist(struct pci_dev *a, struct list_head *list)
1179 struct list_head *pos;
1180 struct klist_node *n;
1184 list_for_each(pos, list) {
1185 n = container_of(pos, struct klist_node, n_node);
1186 dev = container_of(n, struct device, knode_bus);
1187 b = to_pci_dev(dev);
1188 if (pci_sort_bf_cmp(a, b) <= 0) {
1189 list_move_tail(&a->dev.knode_bus.n_node, &b->dev.knode_bus.n_node);
1193 list_move_tail(&a->dev.knode_bus.n_node, list);
1196 void __init pci_sort_breadthfirst(void)
1198 LIST_HEAD(sorted_devices);
1199 struct list_head *pos, *tmp;
1200 struct klist_node *n;
1202 struct pci_dev *pdev;
1203 struct klist *device_klist;
1205 device_klist = bus_get_device_klist(&pci_bus_type);
1207 spin_lock(&device_klist->k_lock);
1208 list_for_each_safe(pos, tmp, &device_klist->k_list) {
1209 n = container_of(pos, struct klist_node, n_node);
1210 dev = container_of(n, struct device, knode_bus);
1211 pdev = to_pci_dev(dev);
1212 pci_insertion_sort_klist(pdev, &sorted_devices);
1214 list_splice(&sorted_devices, &device_klist->k_list);
1215 spin_unlock(&device_klist->k_lock);