2 * probe.c - PCI detection and setup code
5 #include <linux/kernel.h>
6 #include <linux/delay.h>
7 #include <linux/init.h>
9 #include <linux/of_device.h>
10 #include <linux/of_pci.h>
11 #include <linux/pci_hotplug.h>
12 #include <linux/slab.h>
13 #include <linux/module.h>
14 #include <linux/cpumask.h>
15 #include <linux/pci-aspm.h>
16 #include <linux/aer.h>
17 #include <linux/acpi.h>
20 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
21 #define CARDBUS_RESERVE_BUSNR 3
23 static struct resource busn_resource = {
27 .flags = IORESOURCE_BUS,
30 /* Ugh. Need to stop exporting this to modules. */
31 LIST_HEAD(pci_root_buses);
32 EXPORT_SYMBOL(pci_root_buses);
34 static LIST_HEAD(pci_domain_busn_res_list);
36 struct pci_domain_busn_res {
37 struct list_head list;
42 static struct resource *get_pci_domain_busn_res(int domain_nr)
44 struct pci_domain_busn_res *r;
46 list_for_each_entry(r, &pci_domain_busn_res_list, list)
47 if (r->domain_nr == domain_nr)
50 r = kzalloc(sizeof(*r), GFP_KERNEL);
54 r->domain_nr = domain_nr;
57 r->res.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED;
59 list_add_tail(&r->list, &pci_domain_busn_res_list);
64 static int find_anything(struct device *dev, void *data)
70 * Some device drivers need know if pci is initiated.
71 * Basically, we think pci is not initiated when there
72 * is no device to be found on the pci_bus_type.
74 int no_pci_devices(void)
79 dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything);
80 no_devices = (dev == NULL);
84 EXPORT_SYMBOL(no_pci_devices);
89 static void release_pcibus_dev(struct device *dev)
91 struct pci_bus *pci_bus = to_pci_bus(dev);
93 put_device(pci_bus->bridge);
94 pci_bus_remove_resources(pci_bus);
95 pci_release_bus_of_node(pci_bus);
99 static struct class pcibus_class = {
101 .dev_release = &release_pcibus_dev,
102 .dev_groups = pcibus_groups,
105 static int __init pcibus_class_init(void)
107 return class_register(&pcibus_class);
109 postcore_initcall(pcibus_class_init);
111 static u64 pci_size(u64 base, u64 maxbase, u64 mask)
113 u64 size = mask & maxbase; /* Find the significant bits */
117 /* Get the lowest of them to find the decode size, and
118 from that the extent. */
119 size = (size & ~(size-1)) - 1;
121 /* base == maxbase can be valid only if the BAR has
122 already been programmed with all 1s. */
123 if (base == maxbase && ((base | size) & mask) != mask)
129 static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar)
134 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
135 flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
136 flags |= IORESOURCE_IO;
140 flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
141 flags |= IORESOURCE_MEM;
142 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
143 flags |= IORESOURCE_PREFETCH;
145 mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
147 case PCI_BASE_ADDRESS_MEM_TYPE_32:
149 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
150 /* 1M mem BAR treated as 32-bit BAR */
152 case PCI_BASE_ADDRESS_MEM_TYPE_64:
153 flags |= IORESOURCE_MEM_64;
156 /* mem unknown type treated as 32-bit BAR */
162 #define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)
165 * pci_read_base - read a PCI BAR
166 * @dev: the PCI device
167 * @type: type of the BAR
168 * @res: resource buffer to be filled in
169 * @pos: BAR position in the config space
171 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
173 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
174 struct resource *res, unsigned int pos)
177 u64 l64, sz64, mask64;
179 struct pci_bus_region region, inverted_region;
181 mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
183 /* No printks while decoding is disabled! */
184 if (!dev->mmio_always_on) {
185 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);
186 if (orig_cmd & PCI_COMMAND_DECODE_ENABLE) {
187 pci_write_config_word(dev, PCI_COMMAND,
188 orig_cmd & ~PCI_COMMAND_DECODE_ENABLE);
192 res->name = pci_name(dev);
194 pci_read_config_dword(dev, pos, &l);
195 pci_write_config_dword(dev, pos, l | mask);
196 pci_read_config_dword(dev, pos, &sz);
197 pci_write_config_dword(dev, pos, l);
200 * All bits set in sz means the device isn't working properly.
201 * If the BAR isn't implemented, all bits must be 0. If it's a
202 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
205 if (sz == 0xffffffff)
209 * I don't know how l can have all bits set. Copied from old code.
210 * Maybe it fixes a bug on some ancient platform.
215 if (type == pci_bar_unknown) {
216 res->flags = decode_bar(dev, l);
217 res->flags |= IORESOURCE_SIZEALIGN;
218 if (res->flags & IORESOURCE_IO) {
219 l64 = l & PCI_BASE_ADDRESS_IO_MASK;
220 sz64 = sz & PCI_BASE_ADDRESS_IO_MASK;
221 mask64 = PCI_BASE_ADDRESS_IO_MASK & (u32)IO_SPACE_LIMIT;
223 l64 = l & PCI_BASE_ADDRESS_MEM_MASK;
224 sz64 = sz & PCI_BASE_ADDRESS_MEM_MASK;
225 mask64 = (u32)PCI_BASE_ADDRESS_MEM_MASK;
228 res->flags |= (l & IORESOURCE_ROM_ENABLE);
229 l64 = l & PCI_ROM_ADDRESS_MASK;
230 sz64 = sz & PCI_ROM_ADDRESS_MASK;
231 mask64 = (u32)PCI_ROM_ADDRESS_MASK;
234 if (res->flags & IORESOURCE_MEM_64) {
235 pci_read_config_dword(dev, pos + 4, &l);
236 pci_write_config_dword(dev, pos + 4, ~0);
237 pci_read_config_dword(dev, pos + 4, &sz);
238 pci_write_config_dword(dev, pos + 4, l);
240 l64 |= ((u64)l << 32);
241 sz64 |= ((u64)sz << 32);
242 mask64 |= ((u64)~0 << 32);
245 if (!dev->mmio_always_on && (orig_cmd & PCI_COMMAND_DECODE_ENABLE))
246 pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
251 sz64 = pci_size(l64, sz64, mask64);
253 dev_info(&dev->dev, FW_BUG "reg 0x%x: invalid BAR (can't size)\n",
258 if (res->flags & IORESOURCE_MEM_64) {
259 if ((sizeof(pci_bus_addr_t) < 8 || sizeof(resource_size_t) < 8)
260 && sz64 > 0x100000000ULL) {
261 res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED;
264 dev_err(&dev->dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n",
265 pos, (unsigned long long)sz64);
269 if ((sizeof(pci_bus_addr_t) < 8) && l) {
270 /* Above 32-bit boundary; try to reallocate */
271 res->flags |= IORESOURCE_UNSET;
274 dev_info(&dev->dev, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n",
275 pos, (unsigned long long)l64);
281 region.end = l64 + sz64;
283 pcibios_bus_to_resource(dev->bus, res, ®ion);
284 pcibios_resource_to_bus(dev->bus, &inverted_region, res);
287 * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is
288 * the corresponding resource address (the physical address used by
289 * the CPU. Converting that resource address back to a bus address
290 * should yield the original BAR value:
292 * resource_to_bus(bus_to_resource(A)) == A
294 * If it doesn't, CPU accesses to "bus_to_resource(A)" will not
295 * be claimed by the device.
297 if (inverted_region.start != region.start) {
298 res->flags |= IORESOURCE_UNSET;
300 res->end = region.end - region.start;
301 dev_info(&dev->dev, "reg 0x%x: initial BAR value %#010llx invalid\n",
302 pos, (unsigned long long)region.start);
312 dev_printk(KERN_DEBUG, &dev->dev, "reg 0x%x: %pR\n", pos, res);
314 return (res->flags & IORESOURCE_MEM_64) ? 1 : 0;
317 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
319 unsigned int pos, reg;
321 for (pos = 0; pos < howmany; pos++) {
322 struct resource *res = &dev->resource[pos];
323 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
324 pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
328 struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
329 dev->rom_base_reg = rom;
330 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
331 IORESOURCE_READONLY | IORESOURCE_SIZEALIGN;
332 __pci_read_base(dev, pci_bar_mem32, res, rom);
336 static void pci_read_bridge_io(struct pci_bus *child)
338 struct pci_dev *dev = child->self;
339 u8 io_base_lo, io_limit_lo;
340 unsigned long io_mask, io_granularity, base, limit;
341 struct pci_bus_region region;
342 struct resource *res;
344 io_mask = PCI_IO_RANGE_MASK;
345 io_granularity = 0x1000;
346 if (dev->io_window_1k) {
347 /* Support 1K I/O space granularity */
348 io_mask = PCI_IO_1K_RANGE_MASK;
349 io_granularity = 0x400;
352 res = child->resource[0];
353 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
354 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
355 base = (io_base_lo & io_mask) << 8;
356 limit = (io_limit_lo & io_mask) << 8;
358 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
359 u16 io_base_hi, io_limit_hi;
361 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
362 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
363 base |= ((unsigned long) io_base_hi << 16);
364 limit |= ((unsigned long) io_limit_hi << 16);
368 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
370 region.end = limit + io_granularity - 1;
371 pcibios_bus_to_resource(dev->bus, res, ®ion);
372 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
376 static void pci_read_bridge_mmio(struct pci_bus *child)
378 struct pci_dev *dev = child->self;
379 u16 mem_base_lo, mem_limit_lo;
380 unsigned long base, limit;
381 struct pci_bus_region region;
382 struct resource *res;
384 res = child->resource[1];
385 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
386 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
387 base = ((unsigned long) mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
388 limit = ((unsigned long) mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
390 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
392 region.end = limit + 0xfffff;
393 pcibios_bus_to_resource(dev->bus, res, ®ion);
394 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
398 static void pci_read_bridge_mmio_pref(struct pci_bus *child)
400 struct pci_dev *dev = child->self;
401 u16 mem_base_lo, mem_limit_lo;
403 pci_bus_addr_t base, limit;
404 struct pci_bus_region region;
405 struct resource *res;
407 res = child->resource[2];
408 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
409 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
410 base64 = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
411 limit64 = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
413 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
414 u32 mem_base_hi, mem_limit_hi;
416 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
417 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
420 * Some bridges set the base > limit by default, and some
421 * (broken) BIOSes do not initialize them. If we find
422 * this, just assume they are not being used.
424 if (mem_base_hi <= mem_limit_hi) {
425 base64 |= (u64) mem_base_hi << 32;
426 limit64 |= (u64) mem_limit_hi << 32;
430 base = (pci_bus_addr_t) base64;
431 limit = (pci_bus_addr_t) limit64;
433 if (base != base64) {
434 dev_err(&dev->dev, "can't handle bridge window above 4GB (bus address %#010llx)\n",
435 (unsigned long long) base64);
440 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) |
441 IORESOURCE_MEM | IORESOURCE_PREFETCH;
442 if (res->flags & PCI_PREF_RANGE_TYPE_64)
443 res->flags |= IORESOURCE_MEM_64;
445 region.end = limit + 0xfffff;
446 pcibios_bus_to_resource(dev->bus, res, ®ion);
447 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
451 void pci_read_bridge_bases(struct pci_bus *child)
453 struct pci_dev *dev = child->self;
454 struct resource *res;
457 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */
460 dev_info(&dev->dev, "PCI bridge to %pR%s\n",
462 dev->transparent ? " (subtractive decode)" : "");
464 pci_bus_remove_resources(child);
465 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
466 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
468 pci_read_bridge_io(child);
469 pci_read_bridge_mmio(child);
470 pci_read_bridge_mmio_pref(child);
472 if (dev->transparent) {
473 pci_bus_for_each_resource(child->parent, res, i) {
474 if (res && res->flags) {
475 pci_bus_add_resource(child, res,
476 PCI_SUBTRACTIVE_DECODE);
477 dev_printk(KERN_DEBUG, &dev->dev,
478 " bridge window %pR (subtractive decode)\n",
485 static struct pci_bus *pci_alloc_bus(struct pci_bus *parent)
489 b = kzalloc(sizeof(*b), GFP_KERNEL);
493 INIT_LIST_HEAD(&b->node);
494 INIT_LIST_HEAD(&b->children);
495 INIT_LIST_HEAD(&b->devices);
496 INIT_LIST_HEAD(&b->slots);
497 INIT_LIST_HEAD(&b->resources);
498 b->max_bus_speed = PCI_SPEED_UNKNOWN;
499 b->cur_bus_speed = PCI_SPEED_UNKNOWN;
500 #ifdef CONFIG_PCI_DOMAINS_GENERIC
502 b->domain_nr = parent->domain_nr;
507 static void pci_release_host_bridge_dev(struct device *dev)
509 struct pci_host_bridge *bridge = to_pci_host_bridge(dev);
511 if (bridge->release_fn)
512 bridge->release_fn(bridge);
514 pci_free_resource_list(&bridge->windows);
519 static struct pci_host_bridge *pci_alloc_host_bridge(struct pci_bus *b)
521 struct pci_host_bridge *bridge;
523 bridge = kzalloc(sizeof(*bridge), GFP_KERNEL);
527 INIT_LIST_HEAD(&bridge->windows);
532 static const unsigned char pcix_bus_speed[] = {
533 PCI_SPEED_UNKNOWN, /* 0 */
534 PCI_SPEED_66MHz_PCIX, /* 1 */
535 PCI_SPEED_100MHz_PCIX, /* 2 */
536 PCI_SPEED_133MHz_PCIX, /* 3 */
537 PCI_SPEED_UNKNOWN, /* 4 */
538 PCI_SPEED_66MHz_PCIX_ECC, /* 5 */
539 PCI_SPEED_100MHz_PCIX_ECC, /* 6 */
540 PCI_SPEED_133MHz_PCIX_ECC, /* 7 */
541 PCI_SPEED_UNKNOWN, /* 8 */
542 PCI_SPEED_66MHz_PCIX_266, /* 9 */
543 PCI_SPEED_100MHz_PCIX_266, /* A */
544 PCI_SPEED_133MHz_PCIX_266, /* B */
545 PCI_SPEED_UNKNOWN, /* C */
546 PCI_SPEED_66MHz_PCIX_533, /* D */
547 PCI_SPEED_100MHz_PCIX_533, /* E */
548 PCI_SPEED_133MHz_PCIX_533 /* F */
551 const unsigned char pcie_link_speed[] = {
552 PCI_SPEED_UNKNOWN, /* 0 */
553 PCIE_SPEED_2_5GT, /* 1 */
554 PCIE_SPEED_5_0GT, /* 2 */
555 PCIE_SPEED_8_0GT, /* 3 */
556 PCI_SPEED_UNKNOWN, /* 4 */
557 PCI_SPEED_UNKNOWN, /* 5 */
558 PCI_SPEED_UNKNOWN, /* 6 */
559 PCI_SPEED_UNKNOWN, /* 7 */
560 PCI_SPEED_UNKNOWN, /* 8 */
561 PCI_SPEED_UNKNOWN, /* 9 */
562 PCI_SPEED_UNKNOWN, /* A */
563 PCI_SPEED_UNKNOWN, /* B */
564 PCI_SPEED_UNKNOWN, /* C */
565 PCI_SPEED_UNKNOWN, /* D */
566 PCI_SPEED_UNKNOWN, /* E */
567 PCI_SPEED_UNKNOWN /* F */
570 void pcie_update_link_speed(struct pci_bus *bus, u16 linksta)
572 bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS];
574 EXPORT_SYMBOL_GPL(pcie_update_link_speed);
576 static unsigned char agp_speeds[] = {
584 static enum pci_bus_speed agp_speed(int agp3, int agpstat)
590 else if (agpstat & 2)
592 else if (agpstat & 1)
604 return agp_speeds[index];
607 static void pci_set_bus_speed(struct pci_bus *bus)
609 struct pci_dev *bridge = bus->self;
612 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP);
614 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3);
618 pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat);
619 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7);
621 pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd);
622 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7);
625 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
628 enum pci_bus_speed max;
630 pci_read_config_word(bridge, pos + PCI_X_BRIDGE_SSTATUS,
633 if (status & PCI_X_SSTATUS_533MHZ) {
634 max = PCI_SPEED_133MHz_PCIX_533;
635 } else if (status & PCI_X_SSTATUS_266MHZ) {
636 max = PCI_SPEED_133MHz_PCIX_266;
637 } else if (status & PCI_X_SSTATUS_133MHZ) {
638 if ((status & PCI_X_SSTATUS_VERS) == PCI_X_SSTATUS_V2)
639 max = PCI_SPEED_133MHz_PCIX_ECC;
641 max = PCI_SPEED_133MHz_PCIX;
643 max = PCI_SPEED_66MHz_PCIX;
646 bus->max_bus_speed = max;
647 bus->cur_bus_speed = pcix_bus_speed[
648 (status & PCI_X_SSTATUS_FREQ) >> 6];
653 if (pci_is_pcie(bridge)) {
657 pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap);
658 bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS];
660 pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta);
661 pcie_update_link_speed(bus, linksta);
665 static struct irq_domain *pci_host_bridge_msi_domain(struct pci_bus *bus)
667 struct irq_domain *d;
670 * Any firmware interface that can resolve the msi_domain
671 * should be called from here.
673 d = pci_host_bridge_of_msi_domain(bus);
675 d = pci_host_bridge_acpi_msi_domain(bus);
680 static void pci_set_bus_msi_domain(struct pci_bus *bus)
682 struct irq_domain *d;
686 * The bus can be a root bus, a subordinate bus, or a virtual bus
687 * created by an SR-IOV device. Walk up to the first bridge device
688 * found or derive the domain from the host bridge.
690 for (b = bus, d = NULL; !d && !pci_is_root_bus(b); b = b->parent) {
692 d = dev_get_msi_domain(&b->self->dev);
696 d = pci_host_bridge_msi_domain(b);
698 dev_set_msi_domain(&bus->dev, d);
701 static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
702 struct pci_dev *bridge, int busnr)
704 struct pci_bus *child;
709 * Allocate a new bus, and inherit stuff from the parent..
711 child = pci_alloc_bus(parent);
715 child->parent = parent;
716 child->ops = parent->ops;
717 child->msi = parent->msi;
718 child->sysdata = parent->sysdata;
719 child->bus_flags = parent->bus_flags;
721 /* initialize some portions of the bus device, but don't register it
722 * now as the parent is not properly set up yet.
724 child->dev.class = &pcibus_class;
725 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
728 * Set up the primary, secondary and subordinate
731 child->number = child->busn_res.start = busnr;
732 child->primary = parent->busn_res.start;
733 child->busn_res.end = 0xff;
736 child->dev.parent = parent->bridge;
740 child->self = bridge;
741 child->bridge = get_device(&bridge->dev);
742 child->dev.parent = child->bridge;
743 pci_set_bus_of_node(child);
744 pci_set_bus_speed(child);
746 /* Set up default resource pointers and names.. */
747 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
748 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
749 child->resource[i]->name = child->name;
751 bridge->subordinate = child;
754 pci_set_bus_msi_domain(child);
755 ret = device_register(&child->dev);
758 pcibios_add_bus(child);
760 /* Create legacy_io and legacy_mem files for this bus */
761 pci_create_legacy_files(child);
766 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
769 struct pci_bus *child;
771 child = pci_alloc_child_bus(parent, dev, busnr);
773 down_write(&pci_bus_sem);
774 list_add_tail(&child->node, &parent->children);
775 up_write(&pci_bus_sem);
779 EXPORT_SYMBOL(pci_add_new_bus);
781 static void pci_enable_crs(struct pci_dev *pdev)
785 /* Enable CRS Software Visibility if supported */
786 pcie_capability_read_word(pdev, PCI_EXP_RTCAP, &root_cap);
787 if (root_cap & PCI_EXP_RTCAP_CRSVIS)
788 pcie_capability_set_word(pdev, PCI_EXP_RTCTL,
789 PCI_EXP_RTCTL_CRSSVE);
793 * If it's a bridge, configure it and scan the bus behind it.
794 * For CardBus bridges, we don't scan behind as the devices will
795 * be handled by the bridge driver itself.
797 * We need to process bridges in two passes -- first we scan those
798 * already configured by the BIOS and after we are done with all of
799 * them, we proceed to assigning numbers to the remaining buses in
800 * order to avoid overlaps between old and new bus numbers.
802 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
804 struct pci_bus *child;
805 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
808 u8 primary, secondary, subordinate;
811 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
812 primary = buses & 0xFF;
813 secondary = (buses >> 8) & 0xFF;
814 subordinate = (buses >> 16) & 0xFF;
816 dev_dbg(&dev->dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
817 secondary, subordinate, pass);
819 if (!primary && (primary != bus->number) && secondary && subordinate) {
820 dev_warn(&dev->dev, "Primary bus is hard wired to 0\n");
821 primary = bus->number;
824 /* Check if setup is sensible at all */
826 (primary != bus->number || secondary <= bus->number ||
827 secondary > subordinate)) {
828 dev_info(&dev->dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n",
829 secondary, subordinate);
833 /* Disable MasterAbortMode during probing to avoid reporting
834 of bus errors (in some architectures) */
835 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
836 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
837 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
841 if ((secondary || subordinate) && !pcibios_assign_all_busses() &&
842 !is_cardbus && !broken) {
845 * Bus already configured by firmware, process it in the first
846 * pass and just note the configuration.
852 * The bus might already exist for two reasons: Either we are
853 * rescanning the bus or the bus is reachable through more than
854 * one bridge. The second case can happen with the i450NX
857 child = pci_find_bus(pci_domain_nr(bus), secondary);
859 child = pci_add_new_bus(bus, dev, secondary);
862 child->primary = primary;
863 pci_bus_insert_busn_res(child, secondary, subordinate);
864 child->bridge_ctl = bctl;
867 cmax = pci_scan_child_bus(child);
868 if (cmax > subordinate)
869 dev_warn(&dev->dev, "bridge has subordinate %02x but max busn %02x\n",
871 /* subordinate should equal child->busn_res.end */
872 if (subordinate > max)
876 * We need to assign a number to this bus which we always
877 * do in the second pass.
880 if (pcibios_assign_all_busses() || broken || is_cardbus)
881 /* Temporarily disable forwarding of the
882 configuration cycles on all bridges in
883 this bus segment to avoid possible
884 conflicts in the second pass between two
885 bridges programmed with overlapping
887 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
893 pci_write_config_word(dev, PCI_STATUS, 0xffff);
895 /* Prevent assigning a bus number that already exists.
896 * This can happen when a bridge is hot-plugged, so in
897 * this case we only re-scan this bus. */
898 child = pci_find_bus(pci_domain_nr(bus), max+1);
900 child = pci_add_new_bus(bus, dev, max+1);
903 pci_bus_insert_busn_res(child, max+1, 0xff);
906 buses = (buses & 0xff000000)
907 | ((unsigned int)(child->primary) << 0)
908 | ((unsigned int)(child->busn_res.start) << 8)
909 | ((unsigned int)(child->busn_res.end) << 16);
912 * yenta.c forces a secondary latency timer of 176.
913 * Copy that behaviour here.
916 buses &= ~0xff000000;
917 buses |= CARDBUS_LATENCY_TIMER << 24;
921 * We need to blast all three values with a single write.
923 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
926 child->bridge_ctl = bctl;
927 max = pci_scan_child_bus(child);
930 * For CardBus bridges, we leave 4 bus numbers
931 * as cards with a PCI-to-PCI bridge can be
934 for (i = 0; i < CARDBUS_RESERVE_BUSNR; i++) {
935 struct pci_bus *parent = bus;
936 if (pci_find_bus(pci_domain_nr(bus),
939 while (parent->parent) {
940 if ((!pcibios_assign_all_busses()) &&
941 (parent->busn_res.end > max) &&
942 (parent->busn_res.end <= max+i)) {
945 parent = parent->parent;
949 * Often, there are two cardbus bridges
950 * -- try to leave one valid bus number
960 * Set the subordinate bus number to its real value.
962 pci_bus_update_busn_res_end(child, max);
963 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
967 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
968 pci_domain_nr(bus), child->number);
970 /* Has only triggered on CardBus, fixup is in yenta_socket */
971 while (bus->parent) {
972 if ((child->busn_res.end > bus->busn_res.end) ||
973 (child->number > bus->busn_res.end) ||
974 (child->number < bus->number) ||
975 (child->busn_res.end < bus->number)) {
976 dev_info(&child->dev, "%pR %s hidden behind%s bridge %s %pR\n",
978 (bus->number > child->busn_res.end &&
979 bus->busn_res.end < child->number) ?
980 "wholly" : "partially",
981 bus->self->transparent ? " transparent" : "",
989 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
993 EXPORT_SYMBOL(pci_scan_bridge);
996 * Read interrupt line and base address registers.
997 * The architecture-dependent code can tweak these, of course.
999 static void pci_read_irq(struct pci_dev *dev)
1003 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
1006 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
1010 void set_pcie_port_type(struct pci_dev *pdev)
1015 struct pci_dev *parent;
1017 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
1020 pdev->pcie_cap = pos;
1021 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
1022 pdev->pcie_flags_reg = reg16;
1023 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16);
1024 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
1027 * A Root Port is always the upstream end of a Link. No PCIe
1028 * component has two Links. Two Links are connected by a Switch
1029 * that has a Port on each Link and internal logic to connect the
1032 type = pci_pcie_type(pdev);
1033 if (type == PCI_EXP_TYPE_ROOT_PORT)
1034 pdev->has_secondary_link = 1;
1035 else if (type == PCI_EXP_TYPE_UPSTREAM ||
1036 type == PCI_EXP_TYPE_DOWNSTREAM) {
1037 parent = pci_upstream_bridge(pdev);
1040 * Usually there's an upstream device (Root Port or Switch
1041 * Downstream Port), but we can't assume one exists.
1043 if (parent && !parent->has_secondary_link)
1044 pdev->has_secondary_link = 1;
1048 void set_pcie_hotplug_bridge(struct pci_dev *pdev)
1052 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, ®32);
1053 if (reg32 & PCI_EXP_SLTCAP_HPC)
1054 pdev->is_hotplug_bridge = 1;
1058 * pci_ext_cfg_is_aliased - is ext config space just an alias of std config?
1061 * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that
1062 * when forwarding a type1 configuration request the bridge must check that
1063 * the extended register address field is zero. The bridge is not permitted
1064 * to forward the transactions and must handle it as an Unsupported Request.
1065 * Some bridges do not follow this rule and simply drop the extended register
1066 * bits, resulting in the standard config space being aliased, every 256
1067 * bytes across the entire configuration space. Test for this condition by
1068 * comparing the first dword of each potential alias to the vendor/device ID.
1070 * ASM1083/1085 PCIe-to-PCI Reversible Bridge (1b21:1080, rev 01 & 03)
1071 * AMD/ATI SBx00 PCI to PCI Bridge (1002:4384, rev 40)
1073 static bool pci_ext_cfg_is_aliased(struct pci_dev *dev)
1075 #ifdef CONFIG_PCI_QUIRKS
1079 pci_read_config_dword(dev, PCI_VENDOR_ID, &header);
1081 for (pos = PCI_CFG_SPACE_SIZE;
1082 pos < PCI_CFG_SPACE_EXP_SIZE; pos += PCI_CFG_SPACE_SIZE) {
1083 if (pci_read_config_dword(dev, pos, &tmp) != PCIBIOS_SUCCESSFUL
1095 * pci_cfg_space_size - get the configuration space size of the PCI device.
1098 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
1099 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
1100 * access it. Maybe we don't have a way to generate extended config space
1101 * accesses, or the device is behind a reverse Express bridge. So we try
1102 * reading the dword at 0x100 which must either be 0 or a valid extended
1103 * capability header.
1105 static int pci_cfg_space_size_ext(struct pci_dev *dev)
1108 int pos = PCI_CFG_SPACE_SIZE;
1110 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
1111 return PCI_CFG_SPACE_SIZE;
1112 if (status == 0xffffffff || pci_ext_cfg_is_aliased(dev))
1113 return PCI_CFG_SPACE_SIZE;
1115 return PCI_CFG_SPACE_EXP_SIZE;
1118 int pci_cfg_space_size(struct pci_dev *dev)
1124 class = dev->class >> 8;
1125 if (class == PCI_CLASS_BRIDGE_HOST)
1126 return pci_cfg_space_size_ext(dev);
1128 if (pci_is_pcie(dev))
1129 return pci_cfg_space_size_ext(dev);
1131 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1133 return PCI_CFG_SPACE_SIZE;
1135 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
1136 if (status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ))
1137 return pci_cfg_space_size_ext(dev);
1139 return PCI_CFG_SPACE_SIZE;
1142 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
1144 static void pci_msi_setup_pci_dev(struct pci_dev *dev)
1147 * Disable the MSI hardware to avoid screaming interrupts
1148 * during boot. This is the power on reset default so
1149 * usually this should be a noop.
1151 dev->msi_cap = pci_find_capability(dev, PCI_CAP_ID_MSI);
1153 pci_msi_set_enable(dev, 0);
1155 dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX);
1157 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
1161 * pci_setup_device - fill in class and map information of a device
1162 * @dev: the device structure to fill
1164 * Initialize the device structure with information about the device's
1165 * vendor,class,memory and IO-space addresses,IRQ lines etc.
1166 * Called at initialisation of the PCI subsystem and by CardBus services.
1167 * Returns 0 on success and negative if unknown type of device (not normal,
1168 * bridge or CardBus).
1170 int pci_setup_device(struct pci_dev *dev)
1175 struct pci_bus_region region;
1176 struct resource *res;
1178 if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type))
1181 dev->sysdata = dev->bus->sysdata;
1182 dev->dev.parent = dev->bus->bridge;
1183 dev->dev.bus = &pci_bus_type;
1184 dev->hdr_type = hdr_type & 0x7f;
1185 dev->multifunction = !!(hdr_type & 0x80);
1186 dev->error_state = pci_channel_io_normal;
1187 set_pcie_port_type(dev);
1189 pci_dev_assign_slot(dev);
1190 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
1191 set this higher, assuming the system even supports it. */
1192 dev->dma_mask = 0xffffffff;
1194 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
1195 dev->bus->number, PCI_SLOT(dev->devfn),
1196 PCI_FUNC(dev->devfn));
1198 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
1199 dev->revision = class & 0xff;
1200 dev->class = class >> 8; /* upper 3 bytes */
1202 dev_printk(KERN_DEBUG, &dev->dev, "[%04x:%04x] type %02x class %#08x\n",
1203 dev->vendor, dev->device, dev->hdr_type, dev->class);
1205 /* need to have dev->class ready */
1206 dev->cfg_size = pci_cfg_space_size(dev);
1208 /* "Unknown power state" */
1209 dev->current_state = PCI_UNKNOWN;
1211 /* Early fixups, before probing the BARs */
1212 pci_fixup_device(pci_fixup_early, dev);
1213 /* device class may be changed after fixup */
1214 class = dev->class >> 8;
1216 switch (dev->hdr_type) { /* header type */
1217 case PCI_HEADER_TYPE_NORMAL: /* standard header */
1218 if (class == PCI_CLASS_BRIDGE_PCI)
1221 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
1222 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1223 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
1226 * Do the ugly legacy mode stuff here rather than broken chip
1227 * quirk code. Legacy mode ATA controllers have fixed
1228 * addresses. These are not always echoed in BAR0-3, and
1229 * BAR0-3 in a few cases contain junk!
1231 if (class == PCI_CLASS_STORAGE_IDE) {
1233 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
1234 if ((progif & 1) == 0) {
1235 region.start = 0x1F0;
1237 res = &dev->resource[0];
1238 res->flags = LEGACY_IO_RESOURCE;
1239 pcibios_bus_to_resource(dev->bus, res, ®ion);
1240 dev_info(&dev->dev, "legacy IDE quirk: reg 0x10: %pR\n",
1242 region.start = 0x3F6;
1244 res = &dev->resource[1];
1245 res->flags = LEGACY_IO_RESOURCE;
1246 pcibios_bus_to_resource(dev->bus, res, ®ion);
1247 dev_info(&dev->dev, "legacy IDE quirk: reg 0x14: %pR\n",
1250 if ((progif & 4) == 0) {
1251 region.start = 0x170;
1253 res = &dev->resource[2];
1254 res->flags = LEGACY_IO_RESOURCE;
1255 pcibios_bus_to_resource(dev->bus, res, ®ion);
1256 dev_info(&dev->dev, "legacy IDE quirk: reg 0x18: %pR\n",
1258 region.start = 0x376;
1260 res = &dev->resource[3];
1261 res->flags = LEGACY_IO_RESOURCE;
1262 pcibios_bus_to_resource(dev->bus, res, ®ion);
1263 dev_info(&dev->dev, "legacy IDE quirk: reg 0x1c: %pR\n",
1269 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
1270 if (class != PCI_CLASS_BRIDGE_PCI)
1272 /* The PCI-to-PCI bridge spec requires that subtractive
1273 decoding (i.e. transparent) bridge must have programming
1274 interface code of 0x01. */
1276 dev->transparent = ((dev->class & 0xff) == 1);
1277 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
1278 set_pcie_hotplug_bridge(dev);
1279 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID);
1281 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor);
1282 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device);
1286 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
1287 if (class != PCI_CLASS_BRIDGE_CARDBUS)
1290 pci_read_bases(dev, 1, 0);
1291 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1292 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
1295 default: /* unknown header */
1296 dev_err(&dev->dev, "unknown header type %02x, ignoring device\n",
1301 dev_err(&dev->dev, "ignoring class %#08x (doesn't match header type %02x)\n",
1302 dev->class, dev->hdr_type);
1303 dev->class = PCI_CLASS_NOT_DEFINED << 8;
1306 /* We found a fine healthy device, go go go... */
1310 static void pci_configure_mps(struct pci_dev *dev)
1312 struct pci_dev *bridge = pci_upstream_bridge(dev);
1315 if (!pci_is_pcie(dev) || !bridge || !pci_is_pcie(bridge))
1318 mps = pcie_get_mps(dev);
1319 p_mps = pcie_get_mps(bridge);
1324 if (pcie_bus_config == PCIE_BUS_TUNE_OFF) {
1325 dev_warn(&dev->dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1326 mps, pci_name(bridge), p_mps);
1331 * Fancier MPS configuration is done later by
1332 * pcie_bus_configure_settings()
1334 if (pcie_bus_config != PCIE_BUS_DEFAULT)
1337 rc = pcie_set_mps(dev, p_mps);
1339 dev_warn(&dev->dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1344 dev_info(&dev->dev, "Max Payload Size set to %d (was %d, max %d)\n",
1345 p_mps, mps, 128 << dev->pcie_mpss);
1348 static struct hpp_type0 pci_default_type0 = {
1350 .cache_line_size = 8,
1351 .latency_timer = 0x40,
1356 static void program_hpp_type0(struct pci_dev *dev, struct hpp_type0 *hpp)
1358 u16 pci_cmd, pci_bctl;
1361 hpp = &pci_default_type0;
1363 if (hpp->revision > 1) {
1365 "PCI settings rev %d not supported; using defaults\n",
1367 hpp = &pci_default_type0;
1370 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, hpp->cache_line_size);
1371 pci_write_config_byte(dev, PCI_LATENCY_TIMER, hpp->latency_timer);
1372 pci_read_config_word(dev, PCI_COMMAND, &pci_cmd);
1373 if (hpp->enable_serr)
1374 pci_cmd |= PCI_COMMAND_SERR;
1375 if (hpp->enable_perr)
1376 pci_cmd |= PCI_COMMAND_PARITY;
1377 pci_write_config_word(dev, PCI_COMMAND, pci_cmd);
1379 /* Program bridge control value */
1380 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
1381 pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER,
1382 hpp->latency_timer);
1383 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &pci_bctl);
1384 if (hpp->enable_serr)
1385 pci_bctl |= PCI_BRIDGE_CTL_SERR;
1386 if (hpp->enable_perr)
1387 pci_bctl |= PCI_BRIDGE_CTL_PARITY;
1388 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, pci_bctl);
1392 static void program_hpp_type1(struct pci_dev *dev, struct hpp_type1 *hpp)
1395 dev_warn(&dev->dev, "PCI-X settings not supported\n");
1398 static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp)
1406 if (hpp->revision > 1) {
1407 dev_warn(&dev->dev, "PCIe settings rev %d not supported\n",
1413 * Don't allow _HPX to change MPS or MRRS settings. We manage
1414 * those to make sure they're consistent with the rest of the
1417 hpp->pci_exp_devctl_and |= PCI_EXP_DEVCTL_PAYLOAD |
1418 PCI_EXP_DEVCTL_READRQ;
1419 hpp->pci_exp_devctl_or &= ~(PCI_EXP_DEVCTL_PAYLOAD |
1420 PCI_EXP_DEVCTL_READRQ);
1422 /* Initialize Device Control Register */
1423 pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
1424 ~hpp->pci_exp_devctl_and, hpp->pci_exp_devctl_or);
1426 /* Initialize Link Control Register */
1427 if (pcie_cap_has_lnkctl(dev))
1428 pcie_capability_clear_and_set_word(dev, PCI_EXP_LNKCTL,
1429 ~hpp->pci_exp_lnkctl_and, hpp->pci_exp_lnkctl_or);
1431 /* Find Advanced Error Reporting Enhanced Capability */
1432 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
1436 /* Initialize Uncorrectable Error Mask Register */
1437 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, ®32);
1438 reg32 = (reg32 & hpp->unc_err_mask_and) | hpp->unc_err_mask_or;
1439 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, reg32);
1441 /* Initialize Uncorrectable Error Severity Register */
1442 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, ®32);
1443 reg32 = (reg32 & hpp->unc_err_sever_and) | hpp->unc_err_sever_or;
1444 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, reg32);
1446 /* Initialize Correctable Error Mask Register */
1447 pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, ®32);
1448 reg32 = (reg32 & hpp->cor_err_mask_and) | hpp->cor_err_mask_or;
1449 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg32);
1451 /* Initialize Advanced Error Capabilities and Control Register */
1452 pci_read_config_dword(dev, pos + PCI_ERR_CAP, ®32);
1453 reg32 = (reg32 & hpp->adv_err_cap_and) | hpp->adv_err_cap_or;
1454 pci_write_config_dword(dev, pos + PCI_ERR_CAP, reg32);
1457 * FIXME: The following two registers are not supported yet.
1459 * o Secondary Uncorrectable Error Severity Register
1460 * o Secondary Uncorrectable Error Mask Register
1464 static void pci_configure_device(struct pci_dev *dev)
1466 struct hotplug_params hpp;
1469 pci_configure_mps(dev);
1471 memset(&hpp, 0, sizeof(hpp));
1472 ret = pci_get_hp_params(dev, &hpp);
1476 program_hpp_type2(dev, hpp.t2);
1477 program_hpp_type1(dev, hpp.t1);
1478 program_hpp_type0(dev, hpp.t0);
1481 static void pci_release_capabilities(struct pci_dev *dev)
1483 pci_vpd_release(dev);
1484 pci_iov_release(dev);
1485 pci_free_cap_save_buffers(dev);
1489 * pci_release_dev - free a pci device structure when all users of it are finished.
1490 * @dev: device that's been disconnected
1492 * Will be called only by the device core when all users of this pci device are
1495 static void pci_release_dev(struct device *dev)
1497 struct pci_dev *pci_dev;
1499 pci_dev = to_pci_dev(dev);
1500 pci_release_capabilities(pci_dev);
1501 pci_release_of_node(pci_dev);
1502 pcibios_release_device(pci_dev);
1503 pci_bus_put(pci_dev->bus);
1504 kfree(pci_dev->driver_override);
1508 struct pci_dev *pci_alloc_dev(struct pci_bus *bus)
1510 struct pci_dev *dev;
1512 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
1516 INIT_LIST_HEAD(&dev->bus_list);
1517 dev->dev.type = &pci_dev_type;
1518 dev->bus = pci_bus_get(bus);
1522 EXPORT_SYMBOL(pci_alloc_dev);
1524 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
1529 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
1532 /* some broken boards return 0 or ~0 if a slot is empty: */
1533 if (*l == 0xffffffff || *l == 0x00000000 ||
1534 *l == 0x0000ffff || *l == 0xffff0000)
1538 * Configuration Request Retry Status. Some root ports return the
1539 * actual device ID instead of the synthetic ID (0xFFFF) required
1540 * by the PCIe spec. Ignore the device ID and only check for
1543 while ((*l & 0xffff) == 0x0001) {
1549 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
1551 /* Card hasn't responded in 60 seconds? Must be stuck. */
1552 if (delay > crs_timeout) {
1553 printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not responding\n",
1554 pci_domain_nr(bus), bus->number, PCI_SLOT(devfn),
1562 EXPORT_SYMBOL(pci_bus_read_dev_vendor_id);
1565 * Read the config data for a PCI device, sanity-check it
1566 * and fill in the dev structure...
1568 static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
1570 struct pci_dev *dev;
1573 if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000))
1576 dev = pci_alloc_dev(bus);
1581 dev->vendor = l & 0xffff;
1582 dev->device = (l >> 16) & 0xffff;
1584 pci_set_of_node(dev);
1586 if (pci_setup_device(dev)) {
1587 pci_bus_put(dev->bus);
1595 static void pci_init_capabilities(struct pci_dev *dev)
1597 /* Enhanced Allocation */
1600 /* Setup MSI caps & disable MSI/MSI-X interrupts */
1601 pci_msi_setup_pci_dev(dev);
1603 /* Buffers for saving PCIe and PCI-X capabilities */
1604 pci_allocate_cap_save_buffers(dev);
1606 /* Power Management */
1609 /* Vital Product Data */
1610 pci_vpd_pci22_init(dev);
1612 /* Alternative Routing-ID Forwarding */
1613 pci_configure_ari(dev);
1615 /* Single Root I/O Virtualization */
1618 /* Address Translation Services */
1621 /* Enable ACS P2P upstream forwarding */
1622 pci_enable_acs(dev);
1624 pci_cleanup_aer_error_status_regs(dev);
1628 * This is the equivalent of pci_host_bridge_msi_domain that acts on
1629 * devices. Firmware interfaces that can select the MSI domain on a
1630 * per-device basis should be called from here.
1632 static struct irq_domain *pci_dev_msi_domain(struct pci_dev *dev)
1634 struct irq_domain *d;
1637 * If a domain has been set through the pcibios_add_device
1638 * callback, then this is the one (platform code knows best).
1640 d = dev_get_msi_domain(&dev->dev);
1645 * Let's see if we have a firmware interface able to provide
1648 d = pci_msi_get_device_domain(dev);
1655 static void pci_set_msi_domain(struct pci_dev *dev)
1657 struct irq_domain *d;
1660 * If the platform or firmware interfaces cannot supply a
1661 * device-specific MSI domain, then inherit the default domain
1662 * from the host bridge itself.
1664 d = pci_dev_msi_domain(dev);
1666 d = dev_get_msi_domain(&dev->bus->dev);
1668 dev_set_msi_domain(&dev->dev, d);
1672 * pci_dma_configure - Setup DMA configuration
1673 * @dev: ptr to pci_dev struct of the PCI device
1675 * Function to update PCI devices's DMA configuration using the same
1676 * info from the OF node or ACPI node of host bridge's parent (if any).
1678 static void pci_dma_configure(struct pci_dev *dev)
1680 struct device *bridge = pci_get_host_bridge_device(dev);
1682 if (IS_ENABLED(CONFIG_OF) &&
1683 bridge->parent && bridge->parent->of_node) {
1684 of_dma_configure(&dev->dev, bridge->parent->of_node);
1685 } else if (has_acpi_companion(bridge)) {
1686 struct acpi_device *adev = to_acpi_device_node(bridge->fwnode);
1687 enum dev_dma_attr attr = acpi_get_dma_attr(adev);
1689 if (attr == DEV_DMA_NOT_SUPPORTED)
1690 dev_warn(&dev->dev, "DMA not supported.\n");
1692 arch_setup_dma_ops(&dev->dev, 0, 0, NULL,
1693 attr == DEV_DMA_COHERENT);
1696 pci_put_host_bridge_device(bridge);
1699 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
1703 pci_configure_device(dev);
1705 device_initialize(&dev->dev);
1706 dev->dev.release = pci_release_dev;
1708 set_dev_node(&dev->dev, pcibus_to_node(bus));
1709 dev->dev.dma_mask = &dev->dma_mask;
1710 dev->dev.dma_parms = &dev->dma_parms;
1711 dev->dev.coherent_dma_mask = 0xffffffffull;
1712 pci_dma_configure(dev);
1714 pci_set_dma_max_seg_size(dev, 65536);
1715 pci_set_dma_seg_boundary(dev, 0xffffffff);
1717 /* Fix up broken headers */
1718 pci_fixup_device(pci_fixup_header, dev);
1720 /* moved out from quirk header fixup code */
1721 pci_reassigndev_resource_alignment(dev);
1723 /* Clear the state_saved flag. */
1724 dev->state_saved = false;
1726 /* Initialize various capabilities */
1727 pci_init_capabilities(dev);
1730 * Add the device to our list of discovered devices
1731 * and the bus list for fixup functions, etc.
1733 down_write(&pci_bus_sem);
1734 list_add_tail(&dev->bus_list, &bus->devices);
1735 up_write(&pci_bus_sem);
1737 ret = pcibios_add_device(dev);
1740 /* Setup MSI irq domain */
1741 pci_set_msi_domain(dev);
1743 /* Notifier could use PCI capabilities */
1744 dev->match_driver = false;
1745 ret = device_add(&dev->dev);
1749 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn)
1751 struct pci_dev *dev;
1753 dev = pci_get_slot(bus, devfn);
1759 dev = pci_scan_device(bus, devfn);
1763 pci_device_add(dev, bus);
1767 EXPORT_SYMBOL(pci_scan_single_device);
1769 static unsigned next_fn(struct pci_bus *bus, struct pci_dev *dev, unsigned fn)
1775 if (pci_ari_enabled(bus)) {
1778 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
1782 pci_read_config_word(dev, pos + PCI_ARI_CAP, &cap);
1783 next_fn = PCI_ARI_CAP_NFN(cap);
1785 return 0; /* protect against malformed list */
1790 /* dev may be NULL for non-contiguous multifunction devices */
1791 if (!dev || dev->multifunction)
1792 return (fn + 1) % 8;
1797 static int only_one_child(struct pci_bus *bus)
1799 struct pci_dev *parent = bus->self;
1801 if (!parent || !pci_is_pcie(parent))
1803 if (pci_pcie_type(parent) == PCI_EXP_TYPE_ROOT_PORT)
1807 * PCIe downstream ports are bridges that normally lead to only a
1808 * device 0, but if PCI_SCAN_ALL_PCIE_DEVS is set, scan all
1809 * possible devices, not just device 0. See PCIe spec r3.0,
1812 if (parent->has_secondary_link &&
1813 !pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS))
1819 * pci_scan_slot - scan a PCI slot on a bus for devices.
1820 * @bus: PCI bus to scan
1821 * @devfn: slot number to scan (must have zero function.)
1823 * Scan a PCI slot on the specified PCI bus for devices, adding
1824 * discovered devices to the @bus->devices list. New devices
1825 * will not have is_added set.
1827 * Returns the number of new devices found.
1829 int pci_scan_slot(struct pci_bus *bus, int devfn)
1831 unsigned fn, nr = 0;
1832 struct pci_dev *dev;
1834 if (only_one_child(bus) && (devfn > 0))
1835 return 0; /* Already scanned the entire slot */
1837 dev = pci_scan_single_device(bus, devfn);
1843 for (fn = next_fn(bus, dev, 0); fn > 0; fn = next_fn(bus, dev, fn)) {
1844 dev = pci_scan_single_device(bus, devfn + fn);
1848 dev->multifunction = 1;
1852 /* only one slot has pcie device */
1853 if (bus->self && nr)
1854 pcie_aspm_init_link_state(bus->self);
1858 EXPORT_SYMBOL(pci_scan_slot);
1860 static int pcie_find_smpss(struct pci_dev *dev, void *data)
1864 if (!pci_is_pcie(dev))
1868 * We don't have a way to change MPS settings on devices that have
1869 * drivers attached. A hot-added device might support only the minimum
1870 * MPS setting (MPS=128). Therefore, if the fabric contains a bridge
1871 * where devices may be hot-added, we limit the fabric MPS to 128 so
1872 * hot-added devices will work correctly.
1874 * However, if we hot-add a device to a slot directly below a Root
1875 * Port, it's impossible for there to be other existing devices below
1876 * the port. We don't limit the MPS in this case because we can
1877 * reconfigure MPS on both the Root Port and the hot-added device,
1878 * and there are no other devices involved.
1880 * Note that this PCIE_BUS_SAFE path assumes no peer-to-peer DMA.
1882 if (dev->is_hotplug_bridge &&
1883 pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
1886 if (*smpss > dev->pcie_mpss)
1887 *smpss = dev->pcie_mpss;
1892 static void pcie_write_mps(struct pci_dev *dev, int mps)
1896 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
1897 mps = 128 << dev->pcie_mpss;
1899 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT &&
1901 /* For "Performance", the assumption is made that
1902 * downstream communication will never be larger than
1903 * the MRRS. So, the MPS only needs to be configured
1904 * for the upstream communication. This being the case,
1905 * walk from the top down and set the MPS of the child
1906 * to that of the parent bus.
1908 * Configure the device MPS with the smaller of the
1909 * device MPSS or the bridge MPS (which is assumed to be
1910 * properly configured at this point to the largest
1911 * allowable MPS based on its parent bus).
1913 mps = min(mps, pcie_get_mps(dev->bus->self));
1916 rc = pcie_set_mps(dev, mps);
1918 dev_err(&dev->dev, "Failed attempting to set the MPS\n");
1921 static void pcie_write_mrrs(struct pci_dev *dev)
1925 /* In the "safe" case, do not configure the MRRS. There appear to be
1926 * issues with setting MRRS to 0 on a number of devices.
1928 if (pcie_bus_config != PCIE_BUS_PERFORMANCE)
1931 /* For Max performance, the MRRS must be set to the largest supported
1932 * value. However, it cannot be configured larger than the MPS the
1933 * device or the bus can support. This should already be properly
1934 * configured by a prior call to pcie_write_mps.
1936 mrrs = pcie_get_mps(dev);
1938 /* MRRS is a R/W register. Invalid values can be written, but a
1939 * subsequent read will verify if the value is acceptable or not.
1940 * If the MRRS value provided is not acceptable (e.g., too large),
1941 * shrink the value until it is acceptable to the HW.
1943 while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) {
1944 rc = pcie_set_readrq(dev, mrrs);
1948 dev_warn(&dev->dev, "Failed attempting to set the MRRS\n");
1953 dev_err(&dev->dev, "MRRS was unable to be configured with a safe value. If problems are experienced, try running with pci=pcie_bus_safe\n");
1956 static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
1960 if (!pci_is_pcie(dev))
1963 if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||
1964 pcie_bus_config == PCIE_BUS_DEFAULT)
1967 mps = 128 << *(u8 *)data;
1968 orig_mps = pcie_get_mps(dev);
1970 pcie_write_mps(dev, mps);
1971 pcie_write_mrrs(dev);
1973 dev_info(&dev->dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n",
1974 pcie_get_mps(dev), 128 << dev->pcie_mpss,
1975 orig_mps, pcie_get_readrq(dev));
1980 /* pcie_bus_configure_settings requires that pci_walk_bus work in a top-down,
1981 * parents then children fashion. If this changes, then this code will not
1984 void pcie_bus_configure_settings(struct pci_bus *bus)
1991 if (!pci_is_pcie(bus->self))
1994 /* FIXME - Peer to peer DMA is possible, though the endpoint would need
1995 * to be aware of the MPS of the destination. To work around this,
1996 * simply force the MPS of the entire system to the smallest possible.
1998 if (pcie_bus_config == PCIE_BUS_PEER2PEER)
2001 if (pcie_bus_config == PCIE_BUS_SAFE) {
2002 smpss = bus->self->pcie_mpss;
2004 pcie_find_smpss(bus->self, &smpss);
2005 pci_walk_bus(bus, pcie_find_smpss, &smpss);
2008 pcie_bus_configure_set(bus->self, &smpss);
2009 pci_walk_bus(bus, pcie_bus_configure_set, &smpss);
2011 EXPORT_SYMBOL_GPL(pcie_bus_configure_settings);
2013 unsigned int pci_scan_child_bus(struct pci_bus *bus)
2015 unsigned int devfn, pass, max = bus->busn_res.start;
2016 struct pci_dev *dev;
2018 dev_dbg(&bus->dev, "scanning bus\n");
2020 /* Go find them, Rover! */
2021 for (devfn = 0; devfn < 0x100; devfn += 8)
2022 pci_scan_slot(bus, devfn);
2024 /* Reserve buses for SR-IOV capability. */
2025 max += pci_iov_bus_range(bus);
2028 * After performing arch-dependent fixup of the bus, look behind
2029 * all PCI-to-PCI bridges on this bus.
2031 if (!bus->is_added) {
2032 dev_dbg(&bus->dev, "fixups for bus\n");
2033 pcibios_fixup_bus(bus);
2037 for (pass = 0; pass < 2; pass++)
2038 list_for_each_entry(dev, &bus->devices, bus_list) {
2039 if (pci_is_bridge(dev))
2040 max = pci_scan_bridge(bus, dev, max, pass);
2044 * We've scanned the bus and so we know all about what's on
2045 * the other side of any bridges that may be on this bus plus
2048 * Return how far we've got finding sub-buses.
2050 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max);
2053 EXPORT_SYMBOL_GPL(pci_scan_child_bus);
2056 * pcibios_root_bridge_prepare - Platform-specific host bridge setup.
2057 * @bridge: Host bridge to set up.
2059 * Default empty implementation. Replace with an architecture-specific setup
2060 * routine, if necessary.
2062 int __weak pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
2067 void __weak pcibios_add_bus(struct pci_bus *bus)
2071 void __weak pcibios_remove_bus(struct pci_bus *bus)
2075 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
2076 struct pci_ops *ops, void *sysdata, struct list_head *resources)
2079 struct pci_host_bridge *bridge;
2080 struct pci_bus *b, *b2;
2081 struct resource_entry *window, *n;
2082 struct resource *res;
2083 resource_size_t offset;
2087 b = pci_alloc_bus(NULL);
2091 b->sysdata = sysdata;
2093 b->number = b->busn_res.start = bus;
2094 pci_bus_assign_domain_nr(b, parent);
2095 b2 = pci_find_bus(pci_domain_nr(b), bus);
2097 /* If we already got to this bus through a different bridge, ignore it */
2098 dev_dbg(&b2->dev, "bus already known\n");
2102 bridge = pci_alloc_host_bridge(b);
2106 bridge->dev.parent = parent;
2107 bridge->dev.release = pci_release_host_bridge_dev;
2108 dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(b), bus);
2109 error = pcibios_root_bridge_prepare(bridge);
2115 error = device_register(&bridge->dev);
2117 put_device(&bridge->dev);
2120 b->bridge = get_device(&bridge->dev);
2121 device_enable_async_suspend(b->bridge);
2122 pci_set_bus_of_node(b);
2123 pci_set_bus_msi_domain(b);
2126 set_dev_node(b->bridge, pcibus_to_node(b));
2128 b->dev.class = &pcibus_class;
2129 b->dev.parent = b->bridge;
2130 dev_set_name(&b->dev, "%04x:%02x", pci_domain_nr(b), bus);
2131 error = device_register(&b->dev);
2133 goto class_dev_reg_err;
2137 /* Create legacy_io and legacy_mem files for this bus */
2138 pci_create_legacy_files(b);
2141 dev_info(parent, "PCI host bridge to bus %s\n", dev_name(&b->dev));
2143 printk(KERN_INFO "PCI host bridge to bus %s\n", dev_name(&b->dev));
2145 /* Add initial resources to the bus */
2146 resource_list_for_each_entry_safe(window, n, resources) {
2147 list_move_tail(&window->node, &bridge->windows);
2149 offset = window->offset;
2150 if (res->flags & IORESOURCE_BUS)
2151 pci_bus_insert_busn_res(b, bus, res->end);
2153 pci_bus_add_resource(b, res, 0);
2155 if (resource_type(res) == IORESOURCE_IO)
2156 fmt = " (bus address [%#06llx-%#06llx])";
2158 fmt = " (bus address [%#010llx-%#010llx])";
2159 snprintf(bus_addr, sizeof(bus_addr), fmt,
2160 (unsigned long long) (res->start - offset),
2161 (unsigned long long) (res->end - offset));
2164 dev_info(&b->dev, "root bus resource %pR%s\n", res, bus_addr);
2167 down_write(&pci_bus_sem);
2168 list_add_tail(&b->node, &pci_root_buses);
2169 up_write(&pci_bus_sem);
2174 put_device(&bridge->dev);
2175 device_unregister(&bridge->dev);
2180 EXPORT_SYMBOL_GPL(pci_create_root_bus);
2182 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max)
2184 struct resource *res = &b->busn_res;
2185 struct resource *parent_res, *conflict;
2189 res->flags = IORESOURCE_BUS;
2191 if (!pci_is_root_bus(b))
2192 parent_res = &b->parent->busn_res;
2194 parent_res = get_pci_domain_busn_res(pci_domain_nr(b));
2195 res->flags |= IORESOURCE_PCI_FIXED;
2198 conflict = request_resource_conflict(parent_res, res);
2201 dev_printk(KERN_DEBUG, &b->dev,
2202 "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n",
2203 res, pci_is_root_bus(b) ? "domain " : "",
2204 parent_res, conflict->name, conflict);
2206 return conflict == NULL;
2209 int pci_bus_update_busn_res_end(struct pci_bus *b, int bus_max)
2211 struct resource *res = &b->busn_res;
2212 struct resource old_res = *res;
2213 resource_size_t size;
2216 if (res->start > bus_max)
2219 size = bus_max - res->start + 1;
2220 ret = adjust_resource(res, res->start, size);
2221 dev_printk(KERN_DEBUG, &b->dev,
2222 "busn_res: %pR end %s updated to %02x\n",
2223 &old_res, ret ? "can not be" : "is", bus_max);
2225 if (!ret && !res->parent)
2226 pci_bus_insert_busn_res(b, res->start, res->end);
2231 void pci_bus_release_busn_res(struct pci_bus *b)
2233 struct resource *res = &b->busn_res;
2236 if (!res->flags || !res->parent)
2239 ret = release_resource(res);
2240 dev_printk(KERN_DEBUG, &b->dev,
2241 "busn_res: %pR %s released\n",
2242 res, ret ? "can not be" : "is");
2245 struct pci_bus *pci_scan_root_bus_msi(struct device *parent, int bus,
2246 struct pci_ops *ops, void *sysdata,
2247 struct list_head *resources, struct msi_controller *msi)
2249 struct resource_entry *window;
2254 resource_list_for_each_entry(window, resources)
2255 if (window->res->flags & IORESOURCE_BUS) {
2260 b = pci_create_root_bus(parent, bus, ops, sysdata, resources);
2268 "No busn resource found for root bus, will use [bus %02x-ff]\n",
2270 pci_bus_insert_busn_res(b, bus, 255);
2273 max = pci_scan_child_bus(b);
2276 pci_bus_update_busn_res_end(b, max);
2281 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
2282 struct pci_ops *ops, void *sysdata, struct list_head *resources)
2284 return pci_scan_root_bus_msi(parent, bus, ops, sysdata, resources,
2287 EXPORT_SYMBOL(pci_scan_root_bus);
2289 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops,
2292 LIST_HEAD(resources);
2295 pci_add_resource(&resources, &ioport_resource);
2296 pci_add_resource(&resources, &iomem_resource);
2297 pci_add_resource(&resources, &busn_resource);
2298 b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources);
2300 pci_scan_child_bus(b);
2302 pci_free_resource_list(&resources);
2306 EXPORT_SYMBOL(pci_scan_bus);
2309 * pci_rescan_bus_bridge_resize - scan a PCI bus for devices.
2310 * @bridge: PCI bridge for the bus to scan
2312 * Scan a PCI bus and child buses for new devices, add them,
2313 * and enable them, resizing bridge mmio/io resource if necessary
2314 * and possible. The caller must ensure the child devices are already
2315 * removed for resizing to occur.
2317 * Returns the max number of subordinate bus discovered.
2319 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge)
2322 struct pci_bus *bus = bridge->subordinate;
2324 max = pci_scan_child_bus(bus);
2326 pci_assign_unassigned_bridge_resources(bridge);
2328 pci_bus_add_devices(bus);
2334 * pci_rescan_bus - scan a PCI bus for devices.
2335 * @bus: PCI bus to scan
2337 * Scan a PCI bus and child buses for new devices, adds them,
2340 * Returns the max number of subordinate bus discovered.
2342 unsigned int pci_rescan_bus(struct pci_bus *bus)
2346 max = pci_scan_child_bus(bus);
2347 pci_assign_unassigned_bus_resources(bus);
2348 pci_bus_add_devices(bus);
2352 EXPORT_SYMBOL_GPL(pci_rescan_bus);
2355 * pci_rescan_bus(), pci_rescan_bus_bridge_resize() and PCI device removal
2356 * routines should always be executed under this mutex.
2358 static DEFINE_MUTEX(pci_rescan_remove_lock);
2360 void pci_lock_rescan_remove(void)
2362 mutex_lock(&pci_rescan_remove_lock);
2364 EXPORT_SYMBOL_GPL(pci_lock_rescan_remove);
2366 void pci_unlock_rescan_remove(void)
2368 mutex_unlock(&pci_rescan_remove_lock);
2370 EXPORT_SYMBOL_GPL(pci_unlock_rescan_remove);
2372 static int __init pci_sort_bf_cmp(const struct device *d_a,
2373 const struct device *d_b)
2375 const struct pci_dev *a = to_pci_dev(d_a);
2376 const struct pci_dev *b = to_pci_dev(d_b);
2378 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
2379 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
2381 if (a->bus->number < b->bus->number) return -1;
2382 else if (a->bus->number > b->bus->number) return 1;
2384 if (a->devfn < b->devfn) return -1;
2385 else if (a->devfn > b->devfn) return 1;
2390 void __init pci_sort_breadthfirst(void)
2392 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp);