2 * probe.c - PCI detection and setup code
5 #include <linux/kernel.h>
6 #include <linux/delay.h>
7 #include <linux/init.h>
9 #include <linux/of_device.h>
10 #include <linux/of_pci.h>
11 #include <linux/pci_hotplug.h>
12 #include <linux/slab.h>
13 #include <linux/module.h>
14 #include <linux/cpumask.h>
15 #include <linux/pci-aspm.h>
16 #include <linux/aer.h>
17 #include <linux/acpi.h>
18 #include <linux/irqdomain.h>
19 #include <linux/pm_runtime.h>
22 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
23 #define CARDBUS_RESERVE_BUSNR 3
25 static struct resource busn_resource = {
29 .flags = IORESOURCE_BUS,
32 /* Ugh. Need to stop exporting this to modules. */
33 LIST_HEAD(pci_root_buses);
34 EXPORT_SYMBOL(pci_root_buses);
36 static LIST_HEAD(pci_domain_busn_res_list);
38 struct pci_domain_busn_res {
39 struct list_head list;
44 static struct resource *get_pci_domain_busn_res(int domain_nr)
46 struct pci_domain_busn_res *r;
48 list_for_each_entry(r, &pci_domain_busn_res_list, list)
49 if (r->domain_nr == domain_nr)
52 r = kzalloc(sizeof(*r), GFP_KERNEL);
56 r->domain_nr = domain_nr;
59 r->res.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED;
61 list_add_tail(&r->list, &pci_domain_busn_res_list);
66 static int find_anything(struct device *dev, void *data)
72 * Some device drivers need know if pci is initiated.
73 * Basically, we think pci is not initiated when there
74 * is no device to be found on the pci_bus_type.
76 int no_pci_devices(void)
81 dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything);
82 no_devices = (dev == NULL);
86 EXPORT_SYMBOL(no_pci_devices);
91 static void release_pcibus_dev(struct device *dev)
93 struct pci_bus *pci_bus = to_pci_bus(dev);
95 put_device(pci_bus->bridge);
96 pci_bus_remove_resources(pci_bus);
97 pci_release_bus_of_node(pci_bus);
101 static struct class pcibus_class = {
103 .dev_release = &release_pcibus_dev,
104 .dev_groups = pcibus_groups,
107 static int __init pcibus_class_init(void)
109 return class_register(&pcibus_class);
111 postcore_initcall(pcibus_class_init);
113 static u64 pci_size(u64 base, u64 maxbase, u64 mask)
115 u64 size = mask & maxbase; /* Find the significant bits */
119 /* Get the lowest of them to find the decode size, and
120 from that the extent. */
121 size = (size & ~(size-1)) - 1;
123 /* base == maxbase can be valid only if the BAR has
124 already been programmed with all 1s. */
125 if (base == maxbase && ((base | size) & mask) != mask)
131 static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar)
136 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
137 flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
138 flags |= IORESOURCE_IO;
142 flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
143 flags |= IORESOURCE_MEM;
144 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
145 flags |= IORESOURCE_PREFETCH;
147 mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
149 case PCI_BASE_ADDRESS_MEM_TYPE_32:
151 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
152 /* 1M mem BAR treated as 32-bit BAR */
154 case PCI_BASE_ADDRESS_MEM_TYPE_64:
155 flags |= IORESOURCE_MEM_64;
158 /* mem unknown type treated as 32-bit BAR */
164 #define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)
167 * pci_read_base - read a PCI BAR
168 * @dev: the PCI device
169 * @type: type of the BAR
170 * @res: resource buffer to be filled in
171 * @pos: BAR position in the config space
173 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
175 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
176 struct resource *res, unsigned int pos)
179 u64 l64, sz64, mask64;
181 struct pci_bus_region region, inverted_region;
183 mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
185 /* No printks while decoding is disabled! */
186 if (!dev->mmio_always_on) {
187 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);
188 if (orig_cmd & PCI_COMMAND_DECODE_ENABLE) {
189 pci_write_config_word(dev, PCI_COMMAND,
190 orig_cmd & ~PCI_COMMAND_DECODE_ENABLE);
194 res->name = pci_name(dev);
196 pci_read_config_dword(dev, pos, &l);
197 pci_write_config_dword(dev, pos, l | mask);
198 pci_read_config_dword(dev, pos, &sz);
199 pci_write_config_dword(dev, pos, l);
202 * All bits set in sz means the device isn't working properly.
203 * If the BAR isn't implemented, all bits must be 0. If it's a
204 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
207 if (sz == 0xffffffff)
211 * I don't know how l can have all bits set. Copied from old code.
212 * Maybe it fixes a bug on some ancient platform.
217 if (type == pci_bar_unknown) {
218 res->flags = decode_bar(dev, l);
219 res->flags |= IORESOURCE_SIZEALIGN;
220 if (res->flags & IORESOURCE_IO) {
221 l64 = l & PCI_BASE_ADDRESS_IO_MASK;
222 sz64 = sz & PCI_BASE_ADDRESS_IO_MASK;
223 mask64 = PCI_BASE_ADDRESS_IO_MASK & (u32)IO_SPACE_LIMIT;
225 l64 = l & PCI_BASE_ADDRESS_MEM_MASK;
226 sz64 = sz & PCI_BASE_ADDRESS_MEM_MASK;
227 mask64 = (u32)PCI_BASE_ADDRESS_MEM_MASK;
230 res->flags |= (l & IORESOURCE_ROM_ENABLE);
231 l64 = l & PCI_ROM_ADDRESS_MASK;
232 sz64 = sz & PCI_ROM_ADDRESS_MASK;
233 mask64 = (u32)PCI_ROM_ADDRESS_MASK;
236 if (res->flags & IORESOURCE_MEM_64) {
237 pci_read_config_dword(dev, pos + 4, &l);
238 pci_write_config_dword(dev, pos + 4, ~0);
239 pci_read_config_dword(dev, pos + 4, &sz);
240 pci_write_config_dword(dev, pos + 4, l);
242 l64 |= ((u64)l << 32);
243 sz64 |= ((u64)sz << 32);
244 mask64 |= ((u64)~0 << 32);
247 if (!dev->mmio_always_on && (orig_cmd & PCI_COMMAND_DECODE_ENABLE))
248 pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
253 sz64 = pci_size(l64, sz64, mask64);
255 dev_info(&dev->dev, FW_BUG "reg 0x%x: invalid BAR (can't size)\n",
260 if (res->flags & IORESOURCE_MEM_64) {
261 if ((sizeof(pci_bus_addr_t) < 8 || sizeof(resource_size_t) < 8)
262 && sz64 > 0x100000000ULL) {
263 res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED;
266 dev_err(&dev->dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n",
267 pos, (unsigned long long)sz64);
271 if ((sizeof(pci_bus_addr_t) < 8) && l) {
272 /* Above 32-bit boundary; try to reallocate */
273 res->flags |= IORESOURCE_UNSET;
276 dev_info(&dev->dev, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n",
277 pos, (unsigned long long)l64);
283 region.end = l64 + sz64;
285 pcibios_bus_to_resource(dev->bus, res, ®ion);
286 pcibios_resource_to_bus(dev->bus, &inverted_region, res);
289 * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is
290 * the corresponding resource address (the physical address used by
291 * the CPU. Converting that resource address back to a bus address
292 * should yield the original BAR value:
294 * resource_to_bus(bus_to_resource(A)) == A
296 * If it doesn't, CPU accesses to "bus_to_resource(A)" will not
297 * be claimed by the device.
299 if (inverted_region.start != region.start) {
300 res->flags |= IORESOURCE_UNSET;
302 res->end = region.end - region.start;
303 dev_info(&dev->dev, "reg 0x%x: initial BAR value %#010llx invalid\n",
304 pos, (unsigned long long)region.start);
314 dev_printk(KERN_DEBUG, &dev->dev, "reg 0x%x: %pR\n", pos, res);
316 return (res->flags & IORESOURCE_MEM_64) ? 1 : 0;
319 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
321 unsigned int pos, reg;
323 if (dev->non_compliant_bars)
326 for (pos = 0; pos < howmany; pos++) {
327 struct resource *res = &dev->resource[pos];
328 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
329 pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
333 struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
334 dev->rom_base_reg = rom;
335 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
336 IORESOURCE_READONLY | IORESOURCE_SIZEALIGN;
337 __pci_read_base(dev, pci_bar_mem32, res, rom);
341 static void pci_read_bridge_io(struct pci_bus *child)
343 struct pci_dev *dev = child->self;
344 u8 io_base_lo, io_limit_lo;
345 unsigned long io_mask, io_granularity, base, limit;
346 struct pci_bus_region region;
347 struct resource *res;
349 io_mask = PCI_IO_RANGE_MASK;
350 io_granularity = 0x1000;
351 if (dev->io_window_1k) {
352 /* Support 1K I/O space granularity */
353 io_mask = PCI_IO_1K_RANGE_MASK;
354 io_granularity = 0x400;
357 res = child->resource[0];
358 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
359 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
360 base = (io_base_lo & io_mask) << 8;
361 limit = (io_limit_lo & io_mask) << 8;
363 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
364 u16 io_base_hi, io_limit_hi;
366 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
367 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
368 base |= ((unsigned long) io_base_hi << 16);
369 limit |= ((unsigned long) io_limit_hi << 16);
373 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
375 region.end = limit + io_granularity - 1;
376 pcibios_bus_to_resource(dev->bus, res, ®ion);
377 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
381 static void pci_read_bridge_mmio(struct pci_bus *child)
383 struct pci_dev *dev = child->self;
384 u16 mem_base_lo, mem_limit_lo;
385 unsigned long base, limit;
386 struct pci_bus_region region;
387 struct resource *res;
389 res = child->resource[1];
390 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
391 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
392 base = ((unsigned long) mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
393 limit = ((unsigned long) mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
395 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
397 region.end = limit + 0xfffff;
398 pcibios_bus_to_resource(dev->bus, res, ®ion);
399 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
403 static void pci_read_bridge_mmio_pref(struct pci_bus *child)
405 struct pci_dev *dev = child->self;
406 u16 mem_base_lo, mem_limit_lo;
408 pci_bus_addr_t base, limit;
409 struct pci_bus_region region;
410 struct resource *res;
412 res = child->resource[2];
413 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
414 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
415 base64 = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
416 limit64 = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
418 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
419 u32 mem_base_hi, mem_limit_hi;
421 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
422 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
425 * Some bridges set the base > limit by default, and some
426 * (broken) BIOSes do not initialize them. If we find
427 * this, just assume they are not being used.
429 if (mem_base_hi <= mem_limit_hi) {
430 base64 |= (u64) mem_base_hi << 32;
431 limit64 |= (u64) mem_limit_hi << 32;
435 base = (pci_bus_addr_t) base64;
436 limit = (pci_bus_addr_t) limit64;
438 if (base != base64) {
439 dev_err(&dev->dev, "can't handle bridge window above 4GB (bus address %#010llx)\n",
440 (unsigned long long) base64);
445 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) |
446 IORESOURCE_MEM | IORESOURCE_PREFETCH;
447 if (res->flags & PCI_PREF_RANGE_TYPE_64)
448 res->flags |= IORESOURCE_MEM_64;
450 region.end = limit + 0xfffff;
451 pcibios_bus_to_resource(dev->bus, res, ®ion);
452 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
456 void pci_read_bridge_bases(struct pci_bus *child)
458 struct pci_dev *dev = child->self;
459 struct resource *res;
462 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */
465 dev_info(&dev->dev, "PCI bridge to %pR%s\n",
467 dev->transparent ? " (subtractive decode)" : "");
469 pci_bus_remove_resources(child);
470 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
471 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
473 pci_read_bridge_io(child);
474 pci_read_bridge_mmio(child);
475 pci_read_bridge_mmio_pref(child);
477 if (dev->transparent) {
478 pci_bus_for_each_resource(child->parent, res, i) {
479 if (res && res->flags) {
480 pci_bus_add_resource(child, res,
481 PCI_SUBTRACTIVE_DECODE);
482 dev_printk(KERN_DEBUG, &dev->dev,
483 " bridge window %pR (subtractive decode)\n",
490 static struct pci_bus *pci_alloc_bus(struct pci_bus *parent)
494 b = kzalloc(sizeof(*b), GFP_KERNEL);
498 INIT_LIST_HEAD(&b->node);
499 INIT_LIST_HEAD(&b->children);
500 INIT_LIST_HEAD(&b->devices);
501 INIT_LIST_HEAD(&b->slots);
502 INIT_LIST_HEAD(&b->resources);
503 b->max_bus_speed = PCI_SPEED_UNKNOWN;
504 b->cur_bus_speed = PCI_SPEED_UNKNOWN;
505 #ifdef CONFIG_PCI_DOMAINS_GENERIC
507 b->domain_nr = parent->domain_nr;
512 static void pci_release_host_bridge_dev(struct device *dev)
514 struct pci_host_bridge *bridge = to_pci_host_bridge(dev);
516 if (bridge->release_fn)
517 bridge->release_fn(bridge);
519 pci_free_resource_list(&bridge->windows);
524 static struct pci_host_bridge *pci_alloc_host_bridge(size_t priv)
526 struct pci_host_bridge *bridge;
528 bridge = kzalloc(sizeof(*bridge) + priv, GFP_KERNEL);
532 INIT_LIST_HEAD(&bridge->windows);
537 static const unsigned char pcix_bus_speed[] = {
538 PCI_SPEED_UNKNOWN, /* 0 */
539 PCI_SPEED_66MHz_PCIX, /* 1 */
540 PCI_SPEED_100MHz_PCIX, /* 2 */
541 PCI_SPEED_133MHz_PCIX, /* 3 */
542 PCI_SPEED_UNKNOWN, /* 4 */
543 PCI_SPEED_66MHz_PCIX_ECC, /* 5 */
544 PCI_SPEED_100MHz_PCIX_ECC, /* 6 */
545 PCI_SPEED_133MHz_PCIX_ECC, /* 7 */
546 PCI_SPEED_UNKNOWN, /* 8 */
547 PCI_SPEED_66MHz_PCIX_266, /* 9 */
548 PCI_SPEED_100MHz_PCIX_266, /* A */
549 PCI_SPEED_133MHz_PCIX_266, /* B */
550 PCI_SPEED_UNKNOWN, /* C */
551 PCI_SPEED_66MHz_PCIX_533, /* D */
552 PCI_SPEED_100MHz_PCIX_533, /* E */
553 PCI_SPEED_133MHz_PCIX_533 /* F */
556 const unsigned char pcie_link_speed[] = {
557 PCI_SPEED_UNKNOWN, /* 0 */
558 PCIE_SPEED_2_5GT, /* 1 */
559 PCIE_SPEED_5_0GT, /* 2 */
560 PCIE_SPEED_8_0GT, /* 3 */
561 PCI_SPEED_UNKNOWN, /* 4 */
562 PCI_SPEED_UNKNOWN, /* 5 */
563 PCI_SPEED_UNKNOWN, /* 6 */
564 PCI_SPEED_UNKNOWN, /* 7 */
565 PCI_SPEED_UNKNOWN, /* 8 */
566 PCI_SPEED_UNKNOWN, /* 9 */
567 PCI_SPEED_UNKNOWN, /* A */
568 PCI_SPEED_UNKNOWN, /* B */
569 PCI_SPEED_UNKNOWN, /* C */
570 PCI_SPEED_UNKNOWN, /* D */
571 PCI_SPEED_UNKNOWN, /* E */
572 PCI_SPEED_UNKNOWN /* F */
575 void pcie_update_link_speed(struct pci_bus *bus, u16 linksta)
577 bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS];
579 EXPORT_SYMBOL_GPL(pcie_update_link_speed);
581 static unsigned char agp_speeds[] = {
589 static enum pci_bus_speed agp_speed(int agp3, int agpstat)
595 else if (agpstat & 2)
597 else if (agpstat & 1)
609 return agp_speeds[index];
612 static void pci_set_bus_speed(struct pci_bus *bus)
614 struct pci_dev *bridge = bus->self;
617 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP);
619 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3);
623 pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat);
624 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7);
626 pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd);
627 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7);
630 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
633 enum pci_bus_speed max;
635 pci_read_config_word(bridge, pos + PCI_X_BRIDGE_SSTATUS,
638 if (status & PCI_X_SSTATUS_533MHZ) {
639 max = PCI_SPEED_133MHz_PCIX_533;
640 } else if (status & PCI_X_SSTATUS_266MHZ) {
641 max = PCI_SPEED_133MHz_PCIX_266;
642 } else if (status & PCI_X_SSTATUS_133MHZ) {
643 if ((status & PCI_X_SSTATUS_VERS) == PCI_X_SSTATUS_V2)
644 max = PCI_SPEED_133MHz_PCIX_ECC;
646 max = PCI_SPEED_133MHz_PCIX;
648 max = PCI_SPEED_66MHz_PCIX;
651 bus->max_bus_speed = max;
652 bus->cur_bus_speed = pcix_bus_speed[
653 (status & PCI_X_SSTATUS_FREQ) >> 6];
658 if (pci_is_pcie(bridge)) {
662 pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap);
663 bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS];
665 pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta);
666 pcie_update_link_speed(bus, linksta);
670 static struct irq_domain *pci_host_bridge_msi_domain(struct pci_bus *bus)
672 struct irq_domain *d;
675 * Any firmware interface that can resolve the msi_domain
676 * should be called from here.
678 d = pci_host_bridge_of_msi_domain(bus);
680 d = pci_host_bridge_acpi_msi_domain(bus);
682 #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
684 * If no IRQ domain was found via the OF tree, try looking it up
685 * directly through the fwnode_handle.
688 struct fwnode_handle *fwnode = pci_root_bus_fwnode(bus);
691 d = irq_find_matching_fwnode(fwnode,
699 static void pci_set_bus_msi_domain(struct pci_bus *bus)
701 struct irq_domain *d;
705 * The bus can be a root bus, a subordinate bus, or a virtual bus
706 * created by an SR-IOV device. Walk up to the first bridge device
707 * found or derive the domain from the host bridge.
709 for (b = bus, d = NULL; !d && !pci_is_root_bus(b); b = b->parent) {
711 d = dev_get_msi_domain(&b->self->dev);
715 d = pci_host_bridge_msi_domain(b);
717 dev_set_msi_domain(&bus->dev, d);
720 static int pci_register_host_bridge(struct pci_host_bridge *bridge)
722 struct device *parent = bridge->dev.parent;
723 struct resource_entry *window, *n;
724 struct pci_bus *bus, *b;
725 resource_size_t offset;
726 LIST_HEAD(resources);
727 struct resource *res;
732 bus = pci_alloc_bus(NULL);
738 /* temporarily move resources off the list */
739 list_splice_init(&bridge->windows, &resources);
740 bus->sysdata = bridge->sysdata;
741 bus->msi = bridge->msi;
742 bus->ops = bridge->ops;
743 bus->number = bus->busn_res.start = bridge->busnr;
744 #ifdef CONFIG_PCI_DOMAINS_GENERIC
745 bus->domain_nr = pci_bus_find_domain_nr(bus, parent);
748 b = pci_find_bus(pci_domain_nr(bus), bridge->busnr);
750 /* If we already got to this bus through a different bridge, ignore it */
751 dev_dbg(&b->dev, "bus already known\n");
756 dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(bus),
759 err = pcibios_root_bridge_prepare(bridge);
763 err = device_register(&bridge->dev);
765 put_device(&bridge->dev);
767 bus->bridge = get_device(&bridge->dev);
768 device_enable_async_suspend(bus->bridge);
769 pci_set_bus_of_node(bus);
770 pci_set_bus_msi_domain(bus);
773 set_dev_node(bus->bridge, pcibus_to_node(bus));
775 bus->dev.class = &pcibus_class;
776 bus->dev.parent = bus->bridge;
778 dev_set_name(&bus->dev, "%04x:%02x", pci_domain_nr(bus), bus->number);
779 name = dev_name(&bus->dev);
781 err = device_register(&bus->dev);
785 pcibios_add_bus(bus);
787 /* Create legacy_io and legacy_mem files for this bus */
788 pci_create_legacy_files(bus);
791 dev_info(parent, "PCI host bridge to bus %s\n", name);
793 pr_info("PCI host bridge to bus %s\n", name);
795 /* Add initial resources to the bus */
796 resource_list_for_each_entry_safe(window, n, &resources) {
797 list_move_tail(&window->node, &bridge->windows);
798 offset = window->offset;
801 if (res->flags & IORESOURCE_BUS)
802 pci_bus_insert_busn_res(bus, bus->number, res->end);
804 pci_bus_add_resource(bus, res, 0);
807 if (resource_type(res) == IORESOURCE_IO)
808 fmt = " (bus address [%#06llx-%#06llx])";
810 fmt = " (bus address [%#010llx-%#010llx])";
812 snprintf(addr, sizeof(addr), fmt,
813 (unsigned long long)(res->start - offset),
814 (unsigned long long)(res->end - offset));
818 dev_info(&bus->dev, "root bus resource %pR%s\n", res, addr);
821 down_write(&pci_bus_sem);
822 list_add_tail(&bus->node, &pci_root_buses);
823 up_write(&pci_bus_sem);
828 put_device(&bridge->dev);
829 device_unregister(&bridge->dev);
836 static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
837 struct pci_dev *bridge, int busnr)
839 struct pci_bus *child;
844 * Allocate a new bus, and inherit stuff from the parent..
846 child = pci_alloc_bus(parent);
850 child->parent = parent;
851 child->ops = parent->ops;
852 child->msi = parent->msi;
853 child->sysdata = parent->sysdata;
854 child->bus_flags = parent->bus_flags;
856 /* initialize some portions of the bus device, but don't register it
857 * now as the parent is not properly set up yet.
859 child->dev.class = &pcibus_class;
860 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
863 * Set up the primary, secondary and subordinate
866 child->number = child->busn_res.start = busnr;
867 child->primary = parent->busn_res.start;
868 child->busn_res.end = 0xff;
871 child->dev.parent = parent->bridge;
875 child->self = bridge;
876 child->bridge = get_device(&bridge->dev);
877 child->dev.parent = child->bridge;
878 pci_set_bus_of_node(child);
879 pci_set_bus_speed(child);
881 /* Set up default resource pointers and names.. */
882 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
883 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
884 child->resource[i]->name = child->name;
886 bridge->subordinate = child;
889 pci_set_bus_msi_domain(child);
890 ret = device_register(&child->dev);
893 pcibios_add_bus(child);
895 if (child->ops->add_bus) {
896 ret = child->ops->add_bus(child);
897 if (WARN_ON(ret < 0))
898 dev_err(&child->dev, "failed to add bus: %d\n", ret);
901 /* Create legacy_io and legacy_mem files for this bus */
902 pci_create_legacy_files(child);
907 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
910 struct pci_bus *child;
912 child = pci_alloc_child_bus(parent, dev, busnr);
914 down_write(&pci_bus_sem);
915 list_add_tail(&child->node, &parent->children);
916 up_write(&pci_bus_sem);
920 EXPORT_SYMBOL(pci_add_new_bus);
922 static void pci_enable_crs(struct pci_dev *pdev)
926 /* Enable CRS Software Visibility if supported */
927 pcie_capability_read_word(pdev, PCI_EXP_RTCAP, &root_cap);
928 if (root_cap & PCI_EXP_RTCAP_CRSVIS)
929 pcie_capability_set_word(pdev, PCI_EXP_RTCTL,
930 PCI_EXP_RTCTL_CRSSVE);
934 * If it's a bridge, configure it and scan the bus behind it.
935 * For CardBus bridges, we don't scan behind as the devices will
936 * be handled by the bridge driver itself.
938 * We need to process bridges in two passes -- first we scan those
939 * already configured by the BIOS and after we are done with all of
940 * them, we proceed to assigning numbers to the remaining buses in
941 * order to avoid overlaps between old and new bus numbers.
943 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
945 struct pci_bus *child;
946 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
949 u8 primary, secondary, subordinate;
953 * Make sure the bridge is powered on to be able to access config
954 * space of devices below it.
956 pm_runtime_get_sync(&dev->dev);
958 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
959 primary = buses & 0xFF;
960 secondary = (buses >> 8) & 0xFF;
961 subordinate = (buses >> 16) & 0xFF;
963 dev_dbg(&dev->dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
964 secondary, subordinate, pass);
966 if (!primary && (primary != bus->number) && secondary && subordinate) {
967 dev_warn(&dev->dev, "Primary bus is hard wired to 0\n");
968 primary = bus->number;
971 /* Check if setup is sensible at all */
973 (primary != bus->number || secondary <= bus->number ||
974 secondary > subordinate)) {
975 dev_info(&dev->dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n",
976 secondary, subordinate);
980 /* Disable MasterAbortMode during probing to avoid reporting
981 of bus errors (in some architectures) */
982 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
983 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
984 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
988 if ((secondary || subordinate) && !pcibios_assign_all_busses() &&
989 !is_cardbus && !broken) {
992 * Bus already configured by firmware, process it in the first
993 * pass and just note the configuration.
999 * The bus might already exist for two reasons: Either we are
1000 * rescanning the bus or the bus is reachable through more than
1001 * one bridge. The second case can happen with the i450NX
1004 child = pci_find_bus(pci_domain_nr(bus), secondary);
1006 child = pci_add_new_bus(bus, dev, secondary);
1009 child->primary = primary;
1010 pci_bus_insert_busn_res(child, secondary, subordinate);
1011 child->bridge_ctl = bctl;
1014 cmax = pci_scan_child_bus(child);
1015 if (cmax > subordinate)
1016 dev_warn(&dev->dev, "bridge has subordinate %02x but max busn %02x\n",
1018 /* subordinate should equal child->busn_res.end */
1019 if (subordinate > max)
1023 * We need to assign a number to this bus which we always
1024 * do in the second pass.
1027 if (pcibios_assign_all_busses() || broken || is_cardbus)
1028 /* Temporarily disable forwarding of the
1029 configuration cycles on all bridges in
1030 this bus segment to avoid possible
1031 conflicts in the second pass between two
1032 bridges programmed with overlapping
1034 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
1040 pci_write_config_word(dev, PCI_STATUS, 0xffff);
1042 /* Prevent assigning a bus number that already exists.
1043 * This can happen when a bridge is hot-plugged, so in
1044 * this case we only re-scan this bus. */
1045 child = pci_find_bus(pci_domain_nr(bus), max+1);
1047 child = pci_add_new_bus(bus, dev, max+1);
1050 pci_bus_insert_busn_res(child, max+1, 0xff);
1053 buses = (buses & 0xff000000)
1054 | ((unsigned int)(child->primary) << 0)
1055 | ((unsigned int)(child->busn_res.start) << 8)
1056 | ((unsigned int)(child->busn_res.end) << 16);
1059 * yenta.c forces a secondary latency timer of 176.
1060 * Copy that behaviour here.
1063 buses &= ~0xff000000;
1064 buses |= CARDBUS_LATENCY_TIMER << 24;
1068 * We need to blast all three values with a single write.
1070 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
1073 child->bridge_ctl = bctl;
1074 max = pci_scan_child_bus(child);
1077 * For CardBus bridges, we leave 4 bus numbers
1078 * as cards with a PCI-to-PCI bridge can be
1081 for (i = 0; i < CARDBUS_RESERVE_BUSNR; i++) {
1082 struct pci_bus *parent = bus;
1083 if (pci_find_bus(pci_domain_nr(bus),
1086 while (parent->parent) {
1087 if ((!pcibios_assign_all_busses()) &&
1088 (parent->busn_res.end > max) &&
1089 (parent->busn_res.end <= max+i)) {
1092 parent = parent->parent;
1096 * Often, there are two cardbus bridges
1097 * -- try to leave one valid bus number
1107 * Set the subordinate bus number to its real value.
1109 pci_bus_update_busn_res_end(child, max);
1110 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
1113 sprintf(child->name,
1114 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
1115 pci_domain_nr(bus), child->number);
1117 /* Has only triggered on CardBus, fixup is in yenta_socket */
1118 while (bus->parent) {
1119 if ((child->busn_res.end > bus->busn_res.end) ||
1120 (child->number > bus->busn_res.end) ||
1121 (child->number < bus->number) ||
1122 (child->busn_res.end < bus->number)) {
1123 dev_info(&child->dev, "%pR %s hidden behind%s bridge %s %pR\n",
1125 (bus->number > child->busn_res.end &&
1126 bus->busn_res.end < child->number) ?
1127 "wholly" : "partially",
1128 bus->self->transparent ? " transparent" : "",
1129 dev_name(&bus->dev),
1136 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
1138 pm_runtime_put(&dev->dev);
1142 EXPORT_SYMBOL(pci_scan_bridge);
1145 * Read interrupt line and base address registers.
1146 * The architecture-dependent code can tweak these, of course.
1148 static void pci_read_irq(struct pci_dev *dev)
1152 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
1155 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
1159 void set_pcie_port_type(struct pci_dev *pdev)
1164 struct pci_dev *parent;
1166 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
1169 pdev->pcie_cap = pos;
1170 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
1171 pdev->pcie_flags_reg = reg16;
1172 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16);
1173 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
1176 * A Root Port is always the upstream end of a Link. No PCIe
1177 * component has two Links. Two Links are connected by a Switch
1178 * that has a Port on each Link and internal logic to connect the
1181 type = pci_pcie_type(pdev);
1182 if (type == PCI_EXP_TYPE_ROOT_PORT)
1183 pdev->has_secondary_link = 1;
1184 else if (type == PCI_EXP_TYPE_UPSTREAM ||
1185 type == PCI_EXP_TYPE_DOWNSTREAM) {
1186 parent = pci_upstream_bridge(pdev);
1189 * Usually there's an upstream device (Root Port or Switch
1190 * Downstream Port), but we can't assume one exists.
1192 if (parent && !parent->has_secondary_link)
1193 pdev->has_secondary_link = 1;
1197 void set_pcie_hotplug_bridge(struct pci_dev *pdev)
1201 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, ®32);
1202 if (reg32 & PCI_EXP_SLTCAP_HPC)
1203 pdev->is_hotplug_bridge = 1;
1207 * pci_ext_cfg_is_aliased - is ext config space just an alias of std config?
1210 * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that
1211 * when forwarding a type1 configuration request the bridge must check that
1212 * the extended register address field is zero. The bridge is not permitted
1213 * to forward the transactions and must handle it as an Unsupported Request.
1214 * Some bridges do not follow this rule and simply drop the extended register
1215 * bits, resulting in the standard config space being aliased, every 256
1216 * bytes across the entire configuration space. Test for this condition by
1217 * comparing the first dword of each potential alias to the vendor/device ID.
1219 * ASM1083/1085 PCIe-to-PCI Reversible Bridge (1b21:1080, rev 01 & 03)
1220 * AMD/ATI SBx00 PCI to PCI Bridge (1002:4384, rev 40)
1222 static bool pci_ext_cfg_is_aliased(struct pci_dev *dev)
1224 #ifdef CONFIG_PCI_QUIRKS
1228 pci_read_config_dword(dev, PCI_VENDOR_ID, &header);
1230 for (pos = PCI_CFG_SPACE_SIZE;
1231 pos < PCI_CFG_SPACE_EXP_SIZE; pos += PCI_CFG_SPACE_SIZE) {
1232 if (pci_read_config_dword(dev, pos, &tmp) != PCIBIOS_SUCCESSFUL
1244 * pci_cfg_space_size - get the configuration space size of the PCI device.
1247 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
1248 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
1249 * access it. Maybe we don't have a way to generate extended config space
1250 * accesses, or the device is behind a reverse Express bridge. So we try
1251 * reading the dword at 0x100 which must either be 0 or a valid extended
1252 * capability header.
1254 static int pci_cfg_space_size_ext(struct pci_dev *dev)
1257 int pos = PCI_CFG_SPACE_SIZE;
1259 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
1260 return PCI_CFG_SPACE_SIZE;
1261 if (status == 0xffffffff || pci_ext_cfg_is_aliased(dev))
1262 return PCI_CFG_SPACE_SIZE;
1264 return PCI_CFG_SPACE_EXP_SIZE;
1267 int pci_cfg_space_size(struct pci_dev *dev)
1273 class = dev->class >> 8;
1274 if (class == PCI_CLASS_BRIDGE_HOST)
1275 return pci_cfg_space_size_ext(dev);
1277 if (pci_is_pcie(dev))
1278 return pci_cfg_space_size_ext(dev);
1280 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1282 return PCI_CFG_SPACE_SIZE;
1284 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
1285 if (status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ))
1286 return pci_cfg_space_size_ext(dev);
1288 return PCI_CFG_SPACE_SIZE;
1291 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
1293 static void pci_msi_setup_pci_dev(struct pci_dev *dev)
1296 * Disable the MSI hardware to avoid screaming interrupts
1297 * during boot. This is the power on reset default so
1298 * usually this should be a noop.
1300 dev->msi_cap = pci_find_capability(dev, PCI_CAP_ID_MSI);
1302 pci_msi_set_enable(dev, 0);
1304 dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX);
1306 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
1310 * pci_setup_device - fill in class and map information of a device
1311 * @dev: the device structure to fill
1313 * Initialize the device structure with information about the device's
1314 * vendor,class,memory and IO-space addresses,IRQ lines etc.
1315 * Called at initialisation of the PCI subsystem and by CardBus services.
1316 * Returns 0 on success and negative if unknown type of device (not normal,
1317 * bridge or CardBus).
1319 int pci_setup_device(struct pci_dev *dev)
1325 struct pci_bus_region region;
1326 struct resource *res;
1328 if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type))
1331 dev->sysdata = dev->bus->sysdata;
1332 dev->dev.parent = dev->bus->bridge;
1333 dev->dev.bus = &pci_bus_type;
1334 dev->hdr_type = hdr_type & 0x7f;
1335 dev->multifunction = !!(hdr_type & 0x80);
1336 dev->error_state = pci_channel_io_normal;
1337 set_pcie_port_type(dev);
1339 pci_dev_assign_slot(dev);
1340 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
1341 set this higher, assuming the system even supports it. */
1342 dev->dma_mask = 0xffffffff;
1344 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
1345 dev->bus->number, PCI_SLOT(dev->devfn),
1346 PCI_FUNC(dev->devfn));
1348 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
1349 dev->revision = class & 0xff;
1350 dev->class = class >> 8; /* upper 3 bytes */
1352 dev_printk(KERN_DEBUG, &dev->dev, "[%04x:%04x] type %02x class %#08x\n",
1353 dev->vendor, dev->device, dev->hdr_type, dev->class);
1355 /* need to have dev->class ready */
1356 dev->cfg_size = pci_cfg_space_size(dev);
1358 /* "Unknown power state" */
1359 dev->current_state = PCI_UNKNOWN;
1361 /* Early fixups, before probing the BARs */
1362 pci_fixup_device(pci_fixup_early, dev);
1363 /* device class may be changed after fixup */
1364 class = dev->class >> 8;
1366 if (dev->non_compliant_bars) {
1367 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1368 if (cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
1369 dev_info(&dev->dev, "device has non-compliant BARs; disabling IO/MEM decoding\n");
1370 cmd &= ~PCI_COMMAND_IO;
1371 cmd &= ~PCI_COMMAND_MEMORY;
1372 pci_write_config_word(dev, PCI_COMMAND, cmd);
1376 switch (dev->hdr_type) { /* header type */
1377 case PCI_HEADER_TYPE_NORMAL: /* standard header */
1378 if (class == PCI_CLASS_BRIDGE_PCI)
1381 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
1382 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1383 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
1386 * Do the ugly legacy mode stuff here rather than broken chip
1387 * quirk code. Legacy mode ATA controllers have fixed
1388 * addresses. These are not always echoed in BAR0-3, and
1389 * BAR0-3 in a few cases contain junk!
1391 if (class == PCI_CLASS_STORAGE_IDE) {
1393 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
1394 if ((progif & 1) == 0) {
1395 region.start = 0x1F0;
1397 res = &dev->resource[0];
1398 res->flags = LEGACY_IO_RESOURCE;
1399 pcibios_bus_to_resource(dev->bus, res, ®ion);
1400 dev_info(&dev->dev, "legacy IDE quirk: reg 0x10: %pR\n",
1402 region.start = 0x3F6;
1404 res = &dev->resource[1];
1405 res->flags = LEGACY_IO_RESOURCE;
1406 pcibios_bus_to_resource(dev->bus, res, ®ion);
1407 dev_info(&dev->dev, "legacy IDE quirk: reg 0x14: %pR\n",
1410 if ((progif & 4) == 0) {
1411 region.start = 0x170;
1413 res = &dev->resource[2];
1414 res->flags = LEGACY_IO_RESOURCE;
1415 pcibios_bus_to_resource(dev->bus, res, ®ion);
1416 dev_info(&dev->dev, "legacy IDE quirk: reg 0x18: %pR\n",
1418 region.start = 0x376;
1420 res = &dev->resource[3];
1421 res->flags = LEGACY_IO_RESOURCE;
1422 pcibios_bus_to_resource(dev->bus, res, ®ion);
1423 dev_info(&dev->dev, "legacy IDE quirk: reg 0x1c: %pR\n",
1429 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
1430 if (class != PCI_CLASS_BRIDGE_PCI)
1432 /* The PCI-to-PCI bridge spec requires that subtractive
1433 decoding (i.e. transparent) bridge must have programming
1434 interface code of 0x01. */
1436 dev->transparent = ((dev->class & 0xff) == 1);
1437 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
1438 set_pcie_hotplug_bridge(dev);
1439 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID);
1441 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor);
1442 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device);
1446 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
1447 if (class != PCI_CLASS_BRIDGE_CARDBUS)
1450 pci_read_bases(dev, 1, 0);
1451 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1452 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
1455 default: /* unknown header */
1456 dev_err(&dev->dev, "unknown header type %02x, ignoring device\n",
1461 dev_err(&dev->dev, "ignoring class %#08x (doesn't match header type %02x)\n",
1462 dev->class, dev->hdr_type);
1463 dev->class = PCI_CLASS_NOT_DEFINED << 8;
1466 /* We found a fine healthy device, go go go... */
1470 static void pci_configure_mps(struct pci_dev *dev)
1472 struct pci_dev *bridge = pci_upstream_bridge(dev);
1475 if (!pci_is_pcie(dev) || !bridge || !pci_is_pcie(bridge))
1478 mps = pcie_get_mps(dev);
1479 p_mps = pcie_get_mps(bridge);
1484 if (pcie_bus_config == PCIE_BUS_TUNE_OFF) {
1485 dev_warn(&dev->dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1486 mps, pci_name(bridge), p_mps);
1491 * Fancier MPS configuration is done later by
1492 * pcie_bus_configure_settings()
1494 if (pcie_bus_config != PCIE_BUS_DEFAULT)
1497 rc = pcie_set_mps(dev, p_mps);
1499 dev_warn(&dev->dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1504 dev_info(&dev->dev, "Max Payload Size set to %d (was %d, max %d)\n",
1505 p_mps, mps, 128 << dev->pcie_mpss);
1508 static struct hpp_type0 pci_default_type0 = {
1510 .cache_line_size = 8,
1511 .latency_timer = 0x40,
1516 static void program_hpp_type0(struct pci_dev *dev, struct hpp_type0 *hpp)
1518 u16 pci_cmd, pci_bctl;
1521 hpp = &pci_default_type0;
1523 if (hpp->revision > 1) {
1525 "PCI settings rev %d not supported; using defaults\n",
1527 hpp = &pci_default_type0;
1530 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, hpp->cache_line_size);
1531 pci_write_config_byte(dev, PCI_LATENCY_TIMER, hpp->latency_timer);
1532 pci_read_config_word(dev, PCI_COMMAND, &pci_cmd);
1533 if (hpp->enable_serr)
1534 pci_cmd |= PCI_COMMAND_SERR;
1535 if (hpp->enable_perr)
1536 pci_cmd |= PCI_COMMAND_PARITY;
1537 pci_write_config_word(dev, PCI_COMMAND, pci_cmd);
1539 /* Program bridge control value */
1540 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
1541 pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER,
1542 hpp->latency_timer);
1543 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &pci_bctl);
1544 if (hpp->enable_serr)
1545 pci_bctl |= PCI_BRIDGE_CTL_SERR;
1546 if (hpp->enable_perr)
1547 pci_bctl |= PCI_BRIDGE_CTL_PARITY;
1548 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, pci_bctl);
1552 static void program_hpp_type1(struct pci_dev *dev, struct hpp_type1 *hpp)
1555 dev_warn(&dev->dev, "PCI-X settings not supported\n");
1558 static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp)
1566 if (hpp->revision > 1) {
1567 dev_warn(&dev->dev, "PCIe settings rev %d not supported\n",
1573 * Don't allow _HPX to change MPS or MRRS settings. We manage
1574 * those to make sure they're consistent with the rest of the
1577 hpp->pci_exp_devctl_and |= PCI_EXP_DEVCTL_PAYLOAD |
1578 PCI_EXP_DEVCTL_READRQ;
1579 hpp->pci_exp_devctl_or &= ~(PCI_EXP_DEVCTL_PAYLOAD |
1580 PCI_EXP_DEVCTL_READRQ);
1582 /* Initialize Device Control Register */
1583 pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
1584 ~hpp->pci_exp_devctl_and, hpp->pci_exp_devctl_or);
1586 /* Initialize Link Control Register */
1587 if (pcie_cap_has_lnkctl(dev))
1588 pcie_capability_clear_and_set_word(dev, PCI_EXP_LNKCTL,
1589 ~hpp->pci_exp_lnkctl_and, hpp->pci_exp_lnkctl_or);
1591 /* Find Advanced Error Reporting Enhanced Capability */
1592 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
1596 /* Initialize Uncorrectable Error Mask Register */
1597 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, ®32);
1598 reg32 = (reg32 & hpp->unc_err_mask_and) | hpp->unc_err_mask_or;
1599 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, reg32);
1601 /* Initialize Uncorrectable Error Severity Register */
1602 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, ®32);
1603 reg32 = (reg32 & hpp->unc_err_sever_and) | hpp->unc_err_sever_or;
1604 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, reg32);
1606 /* Initialize Correctable Error Mask Register */
1607 pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, ®32);
1608 reg32 = (reg32 & hpp->cor_err_mask_and) | hpp->cor_err_mask_or;
1609 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg32);
1611 /* Initialize Advanced Error Capabilities and Control Register */
1612 pci_read_config_dword(dev, pos + PCI_ERR_CAP, ®32);
1613 reg32 = (reg32 & hpp->adv_err_cap_and) | hpp->adv_err_cap_or;
1614 pci_write_config_dword(dev, pos + PCI_ERR_CAP, reg32);
1617 * FIXME: The following two registers are not supported yet.
1619 * o Secondary Uncorrectable Error Severity Register
1620 * o Secondary Uncorrectable Error Mask Register
1624 static void pci_configure_device(struct pci_dev *dev)
1626 struct hotplug_params hpp;
1629 pci_configure_mps(dev);
1631 memset(&hpp, 0, sizeof(hpp));
1632 ret = pci_get_hp_params(dev, &hpp);
1636 program_hpp_type2(dev, hpp.t2);
1637 program_hpp_type1(dev, hpp.t1);
1638 program_hpp_type0(dev, hpp.t0);
1641 static void pci_release_capabilities(struct pci_dev *dev)
1643 pci_vpd_release(dev);
1644 pci_iov_release(dev);
1645 pci_free_cap_save_buffers(dev);
1649 * pci_release_dev - free a pci device structure when all users of it are finished.
1650 * @dev: device that's been disconnected
1652 * Will be called only by the device core when all users of this pci device are
1655 static void pci_release_dev(struct device *dev)
1657 struct pci_dev *pci_dev;
1659 pci_dev = to_pci_dev(dev);
1660 pci_release_capabilities(pci_dev);
1661 pci_release_of_node(pci_dev);
1662 pcibios_release_device(pci_dev);
1663 pci_bus_put(pci_dev->bus);
1664 kfree(pci_dev->driver_override);
1665 kfree(pci_dev->dma_alias_mask);
1669 struct pci_dev *pci_alloc_dev(struct pci_bus *bus)
1671 struct pci_dev *dev;
1673 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
1677 INIT_LIST_HEAD(&dev->bus_list);
1678 dev->dev.type = &pci_dev_type;
1679 dev->bus = pci_bus_get(bus);
1683 EXPORT_SYMBOL(pci_alloc_dev);
1685 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
1690 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
1693 /* some broken boards return 0 or ~0 if a slot is empty: */
1694 if (*l == 0xffffffff || *l == 0x00000000 ||
1695 *l == 0x0000ffff || *l == 0xffff0000)
1699 * Configuration Request Retry Status. Some root ports return the
1700 * actual device ID instead of the synthetic ID (0xFFFF) required
1701 * by the PCIe spec. Ignore the device ID and only check for
1704 while ((*l & 0xffff) == 0x0001) {
1710 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
1712 /* Card hasn't responded in 60 seconds? Must be stuck. */
1713 if (delay > crs_timeout) {
1714 printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not responding\n",
1715 pci_domain_nr(bus), bus->number, PCI_SLOT(devfn),
1723 EXPORT_SYMBOL(pci_bus_read_dev_vendor_id);
1726 * Read the config data for a PCI device, sanity-check it
1727 * and fill in the dev structure...
1729 static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
1731 struct pci_dev *dev;
1734 if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000))
1737 dev = pci_alloc_dev(bus);
1742 dev->vendor = l & 0xffff;
1743 dev->device = (l >> 16) & 0xffff;
1745 pci_set_of_node(dev);
1747 if (pci_setup_device(dev)) {
1748 pci_bus_put(dev->bus);
1756 static void pci_init_capabilities(struct pci_dev *dev)
1758 /* Enhanced Allocation */
1761 /* Setup MSI caps & disable MSI/MSI-X interrupts */
1762 pci_msi_setup_pci_dev(dev);
1764 /* Buffers for saving PCIe and PCI-X capabilities */
1765 pci_allocate_cap_save_buffers(dev);
1767 /* Power Management */
1770 /* Vital Product Data */
1773 /* Alternative Routing-ID Forwarding */
1774 pci_configure_ari(dev);
1776 /* Single Root I/O Virtualization */
1779 /* Address Translation Services */
1782 /* Enable ACS P2P upstream forwarding */
1783 pci_enable_acs(dev);
1785 /* Precision Time Measurement */
1788 /* Advanced Error Reporting */
1793 * This is the equivalent of pci_host_bridge_msi_domain that acts on
1794 * devices. Firmware interfaces that can select the MSI domain on a
1795 * per-device basis should be called from here.
1797 static struct irq_domain *pci_dev_msi_domain(struct pci_dev *dev)
1799 struct irq_domain *d;
1802 * If a domain has been set through the pcibios_add_device
1803 * callback, then this is the one (platform code knows best).
1805 d = dev_get_msi_domain(&dev->dev);
1810 * Let's see if we have a firmware interface able to provide
1813 d = pci_msi_get_device_domain(dev);
1820 static void pci_set_msi_domain(struct pci_dev *dev)
1822 struct irq_domain *d;
1825 * If the platform or firmware interfaces cannot supply a
1826 * device-specific MSI domain, then inherit the default domain
1827 * from the host bridge itself.
1829 d = pci_dev_msi_domain(dev);
1831 d = dev_get_msi_domain(&dev->bus->dev);
1833 dev_set_msi_domain(&dev->dev, d);
1837 * pci_dma_configure - Setup DMA configuration
1838 * @dev: ptr to pci_dev struct of the PCI device
1840 * Function to update PCI devices's DMA configuration using the same
1841 * info from the OF node or ACPI node of host bridge's parent (if any).
1843 static void pci_dma_configure(struct pci_dev *dev)
1845 struct device *bridge = pci_get_host_bridge_device(dev);
1847 if (IS_ENABLED(CONFIG_OF) &&
1848 bridge->parent && bridge->parent->of_node) {
1849 of_dma_configure(&dev->dev, bridge->parent->of_node);
1850 } else if (has_acpi_companion(bridge)) {
1851 struct acpi_device *adev = to_acpi_device_node(bridge->fwnode);
1852 enum dev_dma_attr attr = acpi_get_dma_attr(adev);
1854 if (attr == DEV_DMA_NOT_SUPPORTED)
1855 dev_warn(&dev->dev, "DMA not supported.\n");
1857 arch_setup_dma_ops(&dev->dev, 0, 0, NULL,
1858 attr == DEV_DMA_COHERENT);
1861 pci_put_host_bridge_device(bridge);
1864 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
1868 pci_configure_device(dev);
1870 device_initialize(&dev->dev);
1871 dev->dev.release = pci_release_dev;
1873 set_dev_node(&dev->dev, pcibus_to_node(bus));
1874 dev->dev.dma_mask = &dev->dma_mask;
1875 dev->dev.dma_parms = &dev->dma_parms;
1876 dev->dev.coherent_dma_mask = 0xffffffffull;
1877 pci_dma_configure(dev);
1879 pci_set_dma_max_seg_size(dev, 65536);
1880 pci_set_dma_seg_boundary(dev, 0xffffffff);
1882 /* Fix up broken headers */
1883 pci_fixup_device(pci_fixup_header, dev);
1885 /* moved out from quirk header fixup code */
1886 pci_reassigndev_resource_alignment(dev);
1888 /* Clear the state_saved flag. */
1889 dev->state_saved = false;
1891 /* Initialize various capabilities */
1892 pci_init_capabilities(dev);
1895 * Add the device to our list of discovered devices
1896 * and the bus list for fixup functions, etc.
1898 down_write(&pci_bus_sem);
1899 list_add_tail(&dev->bus_list, &bus->devices);
1900 up_write(&pci_bus_sem);
1902 ret = pcibios_add_device(dev);
1905 /* Setup MSI irq domain */
1906 pci_set_msi_domain(dev);
1908 /* Notifier could use PCI capabilities */
1909 dev->match_driver = false;
1910 ret = device_add(&dev->dev);
1914 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn)
1916 struct pci_dev *dev;
1918 dev = pci_get_slot(bus, devfn);
1924 dev = pci_scan_device(bus, devfn);
1928 pci_device_add(dev, bus);
1932 EXPORT_SYMBOL(pci_scan_single_device);
1934 static unsigned next_fn(struct pci_bus *bus, struct pci_dev *dev, unsigned fn)
1940 if (pci_ari_enabled(bus)) {
1943 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
1947 pci_read_config_word(dev, pos + PCI_ARI_CAP, &cap);
1948 next_fn = PCI_ARI_CAP_NFN(cap);
1950 return 0; /* protect against malformed list */
1955 /* dev may be NULL for non-contiguous multifunction devices */
1956 if (!dev || dev->multifunction)
1957 return (fn + 1) % 8;
1962 static int only_one_child(struct pci_bus *bus)
1964 struct pci_dev *parent = bus->self;
1966 if (!parent || !pci_is_pcie(parent))
1968 if (pci_pcie_type(parent) == PCI_EXP_TYPE_ROOT_PORT)
1972 * PCIe downstream ports are bridges that normally lead to only a
1973 * device 0, but if PCI_SCAN_ALL_PCIE_DEVS is set, scan all
1974 * possible devices, not just device 0. See PCIe spec r3.0,
1977 if (parent->has_secondary_link &&
1978 !pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS))
1984 * pci_scan_slot - scan a PCI slot on a bus for devices.
1985 * @bus: PCI bus to scan
1986 * @devfn: slot number to scan (must have zero function.)
1988 * Scan a PCI slot on the specified PCI bus for devices, adding
1989 * discovered devices to the @bus->devices list. New devices
1990 * will not have is_added set.
1992 * Returns the number of new devices found.
1994 int pci_scan_slot(struct pci_bus *bus, int devfn)
1996 unsigned fn, nr = 0;
1997 struct pci_dev *dev;
1999 if (only_one_child(bus) && (devfn > 0))
2000 return 0; /* Already scanned the entire slot */
2002 dev = pci_scan_single_device(bus, devfn);
2008 for (fn = next_fn(bus, dev, 0); fn > 0; fn = next_fn(bus, dev, fn)) {
2009 dev = pci_scan_single_device(bus, devfn + fn);
2013 dev->multifunction = 1;
2017 /* only one slot has pcie device */
2018 if (bus->self && nr)
2019 pcie_aspm_init_link_state(bus->self);
2023 EXPORT_SYMBOL(pci_scan_slot);
2025 static int pcie_find_smpss(struct pci_dev *dev, void *data)
2029 if (!pci_is_pcie(dev))
2033 * We don't have a way to change MPS settings on devices that have
2034 * drivers attached. A hot-added device might support only the minimum
2035 * MPS setting (MPS=128). Therefore, if the fabric contains a bridge
2036 * where devices may be hot-added, we limit the fabric MPS to 128 so
2037 * hot-added devices will work correctly.
2039 * However, if we hot-add a device to a slot directly below a Root
2040 * Port, it's impossible for there to be other existing devices below
2041 * the port. We don't limit the MPS in this case because we can
2042 * reconfigure MPS on both the Root Port and the hot-added device,
2043 * and there are no other devices involved.
2045 * Note that this PCIE_BUS_SAFE path assumes no peer-to-peer DMA.
2047 if (dev->is_hotplug_bridge &&
2048 pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
2051 if (*smpss > dev->pcie_mpss)
2052 *smpss = dev->pcie_mpss;
2057 static void pcie_write_mps(struct pci_dev *dev, int mps)
2061 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
2062 mps = 128 << dev->pcie_mpss;
2064 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT &&
2066 /* For "Performance", the assumption is made that
2067 * downstream communication will never be larger than
2068 * the MRRS. So, the MPS only needs to be configured
2069 * for the upstream communication. This being the case,
2070 * walk from the top down and set the MPS of the child
2071 * to that of the parent bus.
2073 * Configure the device MPS with the smaller of the
2074 * device MPSS or the bridge MPS (which is assumed to be
2075 * properly configured at this point to the largest
2076 * allowable MPS based on its parent bus).
2078 mps = min(mps, pcie_get_mps(dev->bus->self));
2081 rc = pcie_set_mps(dev, mps);
2083 dev_err(&dev->dev, "Failed attempting to set the MPS\n");
2086 static void pcie_write_mrrs(struct pci_dev *dev)
2090 /* In the "safe" case, do not configure the MRRS. There appear to be
2091 * issues with setting MRRS to 0 on a number of devices.
2093 if (pcie_bus_config != PCIE_BUS_PERFORMANCE)
2096 /* For Max performance, the MRRS must be set to the largest supported
2097 * value. However, it cannot be configured larger than the MPS the
2098 * device or the bus can support. This should already be properly
2099 * configured by a prior call to pcie_write_mps.
2101 mrrs = pcie_get_mps(dev);
2103 /* MRRS is a R/W register. Invalid values can be written, but a
2104 * subsequent read will verify if the value is acceptable or not.
2105 * If the MRRS value provided is not acceptable (e.g., too large),
2106 * shrink the value until it is acceptable to the HW.
2108 while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) {
2109 rc = pcie_set_readrq(dev, mrrs);
2113 dev_warn(&dev->dev, "Failed attempting to set the MRRS\n");
2118 dev_err(&dev->dev, "MRRS was unable to be configured with a safe value. If problems are experienced, try running with pci=pcie_bus_safe\n");
2121 static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
2125 if (!pci_is_pcie(dev))
2128 if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||
2129 pcie_bus_config == PCIE_BUS_DEFAULT)
2132 mps = 128 << *(u8 *)data;
2133 orig_mps = pcie_get_mps(dev);
2135 pcie_write_mps(dev, mps);
2136 pcie_write_mrrs(dev);
2138 dev_info(&dev->dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n",
2139 pcie_get_mps(dev), 128 << dev->pcie_mpss,
2140 orig_mps, pcie_get_readrq(dev));
2145 /* pcie_bus_configure_settings requires that pci_walk_bus work in a top-down,
2146 * parents then children fashion. If this changes, then this code will not
2149 void pcie_bus_configure_settings(struct pci_bus *bus)
2156 if (!pci_is_pcie(bus->self))
2159 /* FIXME - Peer to peer DMA is possible, though the endpoint would need
2160 * to be aware of the MPS of the destination. To work around this,
2161 * simply force the MPS of the entire system to the smallest possible.
2163 if (pcie_bus_config == PCIE_BUS_PEER2PEER)
2166 if (pcie_bus_config == PCIE_BUS_SAFE) {
2167 smpss = bus->self->pcie_mpss;
2169 pcie_find_smpss(bus->self, &smpss);
2170 pci_walk_bus(bus, pcie_find_smpss, &smpss);
2173 pcie_bus_configure_set(bus->self, &smpss);
2174 pci_walk_bus(bus, pcie_bus_configure_set, &smpss);
2176 EXPORT_SYMBOL_GPL(pcie_bus_configure_settings);
2178 unsigned int pci_scan_child_bus(struct pci_bus *bus)
2180 unsigned int devfn, pass, max = bus->busn_res.start;
2181 struct pci_dev *dev;
2183 dev_dbg(&bus->dev, "scanning bus\n");
2185 /* Go find them, Rover! */
2186 for (devfn = 0; devfn < 0x100; devfn += 8)
2187 pci_scan_slot(bus, devfn);
2189 /* Reserve buses for SR-IOV capability. */
2190 max += pci_iov_bus_range(bus);
2193 * After performing arch-dependent fixup of the bus, look behind
2194 * all PCI-to-PCI bridges on this bus.
2196 if (!bus->is_added) {
2197 dev_dbg(&bus->dev, "fixups for bus\n");
2198 pcibios_fixup_bus(bus);
2202 for (pass = 0; pass < 2; pass++)
2203 list_for_each_entry(dev, &bus->devices, bus_list) {
2204 if (pci_is_bridge(dev))
2205 max = pci_scan_bridge(bus, dev, max, pass);
2209 * Make sure a hotplug bridge has at least the minimum requested
2212 if (bus->self && bus->self->is_hotplug_bridge && pci_hotplug_bus_size) {
2213 if (max - bus->busn_res.start < pci_hotplug_bus_size - 1)
2214 max = bus->busn_res.start + pci_hotplug_bus_size - 1;
2218 * We've scanned the bus and so we know all about what's on
2219 * the other side of any bridges that may be on this bus plus
2222 * Return how far we've got finding sub-buses.
2224 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max);
2227 EXPORT_SYMBOL_GPL(pci_scan_child_bus);
2230 * pcibios_root_bridge_prepare - Platform-specific host bridge setup.
2231 * @bridge: Host bridge to set up.
2233 * Default empty implementation. Replace with an architecture-specific setup
2234 * routine, if necessary.
2236 int __weak pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
2241 void __weak pcibios_add_bus(struct pci_bus *bus)
2245 void __weak pcibios_remove_bus(struct pci_bus *bus)
2249 static struct pci_bus *pci_create_root_bus_msi(struct device *parent,
2250 int bus, struct pci_ops *ops, void *sysdata,
2251 struct list_head *resources, struct msi_controller *msi)
2254 struct pci_host_bridge *bridge;
2256 bridge = pci_alloc_host_bridge(0);
2260 bridge->dev.parent = parent;
2261 bridge->dev.release = pci_release_host_bridge_dev;
2263 list_splice_init(resources, &bridge->windows);
2264 bridge->sysdata = sysdata;
2265 bridge->busnr = bus;
2269 error = pci_register_host_bridge(bridge);
2280 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
2281 struct pci_ops *ops, void *sysdata, struct list_head *resources)
2283 return pci_create_root_bus_msi(parent, bus, ops, sysdata, resources,
2286 EXPORT_SYMBOL_GPL(pci_create_root_bus);
2288 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max)
2290 struct resource *res = &b->busn_res;
2291 struct resource *parent_res, *conflict;
2295 res->flags = IORESOURCE_BUS;
2297 if (!pci_is_root_bus(b))
2298 parent_res = &b->parent->busn_res;
2300 parent_res = get_pci_domain_busn_res(pci_domain_nr(b));
2301 res->flags |= IORESOURCE_PCI_FIXED;
2304 conflict = request_resource_conflict(parent_res, res);
2307 dev_printk(KERN_DEBUG, &b->dev,
2308 "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n",
2309 res, pci_is_root_bus(b) ? "domain " : "",
2310 parent_res, conflict->name, conflict);
2312 return conflict == NULL;
2315 int pci_bus_update_busn_res_end(struct pci_bus *b, int bus_max)
2317 struct resource *res = &b->busn_res;
2318 struct resource old_res = *res;
2319 resource_size_t size;
2322 if (res->start > bus_max)
2325 size = bus_max - res->start + 1;
2326 ret = adjust_resource(res, res->start, size);
2327 dev_printk(KERN_DEBUG, &b->dev,
2328 "busn_res: %pR end %s updated to %02x\n",
2329 &old_res, ret ? "can not be" : "is", bus_max);
2331 if (!ret && !res->parent)
2332 pci_bus_insert_busn_res(b, res->start, res->end);
2337 void pci_bus_release_busn_res(struct pci_bus *b)
2339 struct resource *res = &b->busn_res;
2342 if (!res->flags || !res->parent)
2345 ret = release_resource(res);
2346 dev_printk(KERN_DEBUG, &b->dev,
2347 "busn_res: %pR %s released\n",
2348 res, ret ? "can not be" : "is");
2351 struct pci_bus *pci_scan_root_bus_msi(struct device *parent, int bus,
2352 struct pci_ops *ops, void *sysdata,
2353 struct list_head *resources, struct msi_controller *msi)
2355 struct resource_entry *window;
2360 resource_list_for_each_entry(window, resources)
2361 if (window->res->flags & IORESOURCE_BUS) {
2366 b = pci_create_root_bus_msi(parent, bus, ops, sysdata, resources, msi);
2372 "No busn resource found for root bus, will use [bus %02x-ff]\n",
2374 pci_bus_insert_busn_res(b, bus, 255);
2377 max = pci_scan_child_bus(b);
2380 pci_bus_update_busn_res_end(b, max);
2385 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
2386 struct pci_ops *ops, void *sysdata, struct list_head *resources)
2388 return pci_scan_root_bus_msi(parent, bus, ops, sysdata, resources,
2391 EXPORT_SYMBOL(pci_scan_root_bus);
2393 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops,
2396 LIST_HEAD(resources);
2399 pci_add_resource(&resources, &ioport_resource);
2400 pci_add_resource(&resources, &iomem_resource);
2401 pci_add_resource(&resources, &busn_resource);
2402 b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources);
2404 pci_scan_child_bus(b);
2406 pci_free_resource_list(&resources);
2410 EXPORT_SYMBOL(pci_scan_bus);
2413 * pci_rescan_bus_bridge_resize - scan a PCI bus for devices.
2414 * @bridge: PCI bridge for the bus to scan
2416 * Scan a PCI bus and child buses for new devices, add them,
2417 * and enable them, resizing bridge mmio/io resource if necessary
2418 * and possible. The caller must ensure the child devices are already
2419 * removed for resizing to occur.
2421 * Returns the max number of subordinate bus discovered.
2423 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge)
2426 struct pci_bus *bus = bridge->subordinate;
2428 max = pci_scan_child_bus(bus);
2430 pci_assign_unassigned_bridge_resources(bridge);
2432 pci_bus_add_devices(bus);
2438 * pci_rescan_bus - scan a PCI bus for devices.
2439 * @bus: PCI bus to scan
2441 * Scan a PCI bus and child buses for new devices, adds them,
2444 * Returns the max number of subordinate bus discovered.
2446 unsigned int pci_rescan_bus(struct pci_bus *bus)
2450 max = pci_scan_child_bus(bus);
2451 pci_assign_unassigned_bus_resources(bus);
2452 pci_bus_add_devices(bus);
2456 EXPORT_SYMBOL_GPL(pci_rescan_bus);
2459 * pci_rescan_bus(), pci_rescan_bus_bridge_resize() and PCI device removal
2460 * routines should always be executed under this mutex.
2462 static DEFINE_MUTEX(pci_rescan_remove_lock);
2464 void pci_lock_rescan_remove(void)
2466 mutex_lock(&pci_rescan_remove_lock);
2468 EXPORT_SYMBOL_GPL(pci_lock_rescan_remove);
2470 void pci_unlock_rescan_remove(void)
2472 mutex_unlock(&pci_rescan_remove_lock);
2474 EXPORT_SYMBOL_GPL(pci_unlock_rescan_remove);
2476 static int __init pci_sort_bf_cmp(const struct device *d_a,
2477 const struct device *d_b)
2479 const struct pci_dev *a = to_pci_dev(d_a);
2480 const struct pci_dev *b = to_pci_dev(d_b);
2482 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
2483 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
2485 if (a->bus->number < b->bus->number) return -1;
2486 else if (a->bus->number > b->bus->number) return 1;
2488 if (a->devfn < b->devfn) return -1;
2489 else if (a->devfn > b->devfn) return 1;
2494 void __init pci_sort_breadthfirst(void)
2496 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp);