2 * probe.c - PCI detection and setup code
5 #include <linux/kernel.h>
6 #include <linux/delay.h>
7 #include <linux/init.h>
9 #include <linux/of_device.h>
10 #include <linux/of_pci.h>
11 #include <linux/pci_hotplug.h>
12 #include <linux/slab.h>
13 #include <linux/module.h>
14 #include <linux/cpumask.h>
15 #include <linux/pci-aspm.h>
16 #include <linux/aer.h>
17 #include <linux/acpi.h>
18 #include <asm-generic/pci-bridge.h>
21 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
22 #define CARDBUS_RESERVE_BUSNR 3
24 static struct resource busn_resource = {
28 .flags = IORESOURCE_BUS,
31 /* Ugh. Need to stop exporting this to modules. */
32 LIST_HEAD(pci_root_buses);
33 EXPORT_SYMBOL(pci_root_buses);
35 static LIST_HEAD(pci_domain_busn_res_list);
37 struct pci_domain_busn_res {
38 struct list_head list;
43 static struct resource *get_pci_domain_busn_res(int domain_nr)
45 struct pci_domain_busn_res *r;
47 list_for_each_entry(r, &pci_domain_busn_res_list, list)
48 if (r->domain_nr == domain_nr)
51 r = kzalloc(sizeof(*r), GFP_KERNEL);
55 r->domain_nr = domain_nr;
58 r->res.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED;
60 list_add_tail(&r->list, &pci_domain_busn_res_list);
65 static int find_anything(struct device *dev, void *data)
71 * Some device drivers need know if pci is initiated.
72 * Basically, we think pci is not initiated when there
73 * is no device to be found on the pci_bus_type.
75 int no_pci_devices(void)
80 dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything);
81 no_devices = (dev == NULL);
85 EXPORT_SYMBOL(no_pci_devices);
90 static void release_pcibus_dev(struct device *dev)
92 struct pci_bus *pci_bus = to_pci_bus(dev);
94 put_device(pci_bus->bridge);
95 pci_bus_remove_resources(pci_bus);
96 pci_release_bus_of_node(pci_bus);
100 static struct class pcibus_class = {
102 .dev_release = &release_pcibus_dev,
103 .dev_groups = pcibus_groups,
106 static int __init pcibus_class_init(void)
108 return class_register(&pcibus_class);
110 postcore_initcall(pcibus_class_init);
112 static u64 pci_size(u64 base, u64 maxbase, u64 mask)
114 u64 size = mask & maxbase; /* Find the significant bits */
118 /* Get the lowest of them to find the decode size, and
119 from that the extent. */
120 size = (size & ~(size-1)) - 1;
122 /* base == maxbase can be valid only if the BAR has
123 already been programmed with all 1s. */
124 if (base == maxbase && ((base | size) & mask) != mask)
130 static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar)
135 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
136 flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
137 flags |= IORESOURCE_IO;
141 flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
142 flags |= IORESOURCE_MEM;
143 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
144 flags |= IORESOURCE_PREFETCH;
146 mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
148 case PCI_BASE_ADDRESS_MEM_TYPE_32:
150 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
151 /* 1M mem BAR treated as 32-bit BAR */
153 case PCI_BASE_ADDRESS_MEM_TYPE_64:
154 flags |= IORESOURCE_MEM_64;
157 /* mem unknown type treated as 32-bit BAR */
163 #define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)
166 * pci_read_base - read a PCI BAR
167 * @dev: the PCI device
168 * @type: type of the BAR
169 * @res: resource buffer to be filled in
170 * @pos: BAR position in the config space
172 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
174 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
175 struct resource *res, unsigned int pos)
178 u64 l64, sz64, mask64;
180 struct pci_bus_region region, inverted_region;
182 mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
184 /* No printks while decoding is disabled! */
185 if (!dev->mmio_always_on) {
186 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);
187 if (orig_cmd & PCI_COMMAND_DECODE_ENABLE) {
188 pci_write_config_word(dev, PCI_COMMAND,
189 orig_cmd & ~PCI_COMMAND_DECODE_ENABLE);
193 res->name = pci_name(dev);
195 pci_read_config_dword(dev, pos, &l);
196 pci_write_config_dword(dev, pos, l | mask);
197 pci_read_config_dword(dev, pos, &sz);
198 pci_write_config_dword(dev, pos, l);
201 * All bits set in sz means the device isn't working properly.
202 * If the BAR isn't implemented, all bits must be 0. If it's a
203 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
206 if (sz == 0xffffffff)
210 * I don't know how l can have all bits set. Copied from old code.
211 * Maybe it fixes a bug on some ancient platform.
216 if (type == pci_bar_unknown) {
217 res->flags = decode_bar(dev, l);
218 res->flags |= IORESOURCE_SIZEALIGN;
219 if (res->flags & IORESOURCE_IO) {
220 l64 = l & PCI_BASE_ADDRESS_IO_MASK;
221 sz64 = sz & PCI_BASE_ADDRESS_IO_MASK;
222 mask64 = PCI_BASE_ADDRESS_IO_MASK & (u32)IO_SPACE_LIMIT;
224 l64 = l & PCI_BASE_ADDRESS_MEM_MASK;
225 sz64 = sz & PCI_BASE_ADDRESS_MEM_MASK;
226 mask64 = (u32)PCI_BASE_ADDRESS_MEM_MASK;
229 res->flags |= (l & IORESOURCE_ROM_ENABLE);
230 l64 = l & PCI_ROM_ADDRESS_MASK;
231 sz64 = sz & PCI_ROM_ADDRESS_MASK;
232 mask64 = (u32)PCI_ROM_ADDRESS_MASK;
235 if (res->flags & IORESOURCE_MEM_64) {
236 pci_read_config_dword(dev, pos + 4, &l);
237 pci_write_config_dword(dev, pos + 4, ~0);
238 pci_read_config_dword(dev, pos + 4, &sz);
239 pci_write_config_dword(dev, pos + 4, l);
241 l64 |= ((u64)l << 32);
242 sz64 |= ((u64)sz << 32);
243 mask64 |= ((u64)~0 << 32);
246 if (!dev->mmio_always_on && (orig_cmd & PCI_COMMAND_DECODE_ENABLE))
247 pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
252 sz64 = pci_size(l64, sz64, mask64);
254 dev_info(&dev->dev, FW_BUG "reg 0x%x: invalid BAR (can't size)\n",
259 if (res->flags & IORESOURCE_MEM_64) {
260 if ((sizeof(pci_bus_addr_t) < 8 || sizeof(resource_size_t) < 8)
261 && sz64 > 0x100000000ULL) {
262 res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED;
265 dev_err(&dev->dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n",
266 pos, (unsigned long long)sz64);
270 if ((sizeof(pci_bus_addr_t) < 8) && l) {
271 /* Above 32-bit boundary; try to reallocate */
272 res->flags |= IORESOURCE_UNSET;
275 dev_info(&dev->dev, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n",
276 pos, (unsigned long long)l64);
282 region.end = l64 + sz64;
284 pcibios_bus_to_resource(dev->bus, res, ®ion);
285 pcibios_resource_to_bus(dev->bus, &inverted_region, res);
288 * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is
289 * the corresponding resource address (the physical address used by
290 * the CPU. Converting that resource address back to a bus address
291 * should yield the original BAR value:
293 * resource_to_bus(bus_to_resource(A)) == A
295 * If it doesn't, CPU accesses to "bus_to_resource(A)" will not
296 * be claimed by the device.
298 if (inverted_region.start != region.start) {
299 res->flags |= IORESOURCE_UNSET;
301 res->end = region.end - region.start;
302 dev_info(&dev->dev, "reg 0x%x: initial BAR value %#010llx invalid\n",
303 pos, (unsigned long long)region.start);
313 dev_printk(KERN_DEBUG, &dev->dev, "reg 0x%x: %pR\n", pos, res);
315 return (res->flags & IORESOURCE_MEM_64) ? 1 : 0;
318 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
320 unsigned int pos, reg;
322 for (pos = 0; pos < howmany; pos++) {
323 struct resource *res = &dev->resource[pos];
324 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
325 pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
329 struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
330 dev->rom_base_reg = rom;
331 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
332 IORESOURCE_READONLY | IORESOURCE_SIZEALIGN;
333 __pci_read_base(dev, pci_bar_mem32, res, rom);
337 static void pci_read_bridge_io(struct pci_bus *child)
339 struct pci_dev *dev = child->self;
340 u8 io_base_lo, io_limit_lo;
341 unsigned long io_mask, io_granularity, base, limit;
342 struct pci_bus_region region;
343 struct resource *res;
345 io_mask = PCI_IO_RANGE_MASK;
346 io_granularity = 0x1000;
347 if (dev->io_window_1k) {
348 /* Support 1K I/O space granularity */
349 io_mask = PCI_IO_1K_RANGE_MASK;
350 io_granularity = 0x400;
353 res = child->resource[0];
354 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
355 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
356 base = (io_base_lo & io_mask) << 8;
357 limit = (io_limit_lo & io_mask) << 8;
359 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
360 u16 io_base_hi, io_limit_hi;
362 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
363 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
364 base |= ((unsigned long) io_base_hi << 16);
365 limit |= ((unsigned long) io_limit_hi << 16);
369 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
371 region.end = limit + io_granularity - 1;
372 pcibios_bus_to_resource(dev->bus, res, ®ion);
373 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
377 static void pci_read_bridge_mmio(struct pci_bus *child)
379 struct pci_dev *dev = child->self;
380 u16 mem_base_lo, mem_limit_lo;
381 unsigned long base, limit;
382 struct pci_bus_region region;
383 struct resource *res;
385 res = child->resource[1];
386 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
387 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
388 base = ((unsigned long) mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
389 limit = ((unsigned long) mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
391 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
393 region.end = limit + 0xfffff;
394 pcibios_bus_to_resource(dev->bus, res, ®ion);
395 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
399 static void pci_read_bridge_mmio_pref(struct pci_bus *child)
401 struct pci_dev *dev = child->self;
402 u16 mem_base_lo, mem_limit_lo;
404 pci_bus_addr_t base, limit;
405 struct pci_bus_region region;
406 struct resource *res;
408 res = child->resource[2];
409 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
410 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
411 base64 = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
412 limit64 = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
414 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
415 u32 mem_base_hi, mem_limit_hi;
417 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
418 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
421 * Some bridges set the base > limit by default, and some
422 * (broken) BIOSes do not initialize them. If we find
423 * this, just assume they are not being used.
425 if (mem_base_hi <= mem_limit_hi) {
426 base64 |= (u64) mem_base_hi << 32;
427 limit64 |= (u64) mem_limit_hi << 32;
431 base = (pci_bus_addr_t) base64;
432 limit = (pci_bus_addr_t) limit64;
434 if (base != base64) {
435 dev_err(&dev->dev, "can't handle bridge window above 4GB (bus address %#010llx)\n",
436 (unsigned long long) base64);
441 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) |
442 IORESOURCE_MEM | IORESOURCE_PREFETCH;
443 if (res->flags & PCI_PREF_RANGE_TYPE_64)
444 res->flags |= IORESOURCE_MEM_64;
446 region.end = limit + 0xfffff;
447 pcibios_bus_to_resource(dev->bus, res, ®ion);
448 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
452 void pci_read_bridge_bases(struct pci_bus *child)
454 struct pci_dev *dev = child->self;
455 struct resource *res;
458 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */
461 dev_info(&dev->dev, "PCI bridge to %pR%s\n",
463 dev->transparent ? " (subtractive decode)" : "");
465 pci_bus_remove_resources(child);
466 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
467 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
469 pci_read_bridge_io(child);
470 pci_read_bridge_mmio(child);
471 pci_read_bridge_mmio_pref(child);
473 if (dev->transparent) {
474 pci_bus_for_each_resource(child->parent, res, i) {
475 if (res && res->flags) {
476 pci_bus_add_resource(child, res,
477 PCI_SUBTRACTIVE_DECODE);
478 dev_printk(KERN_DEBUG, &dev->dev,
479 " bridge window %pR (subtractive decode)\n",
486 static struct pci_bus *pci_alloc_bus(struct pci_bus *parent)
490 b = kzalloc(sizeof(*b), GFP_KERNEL);
494 INIT_LIST_HEAD(&b->node);
495 INIT_LIST_HEAD(&b->children);
496 INIT_LIST_HEAD(&b->devices);
497 INIT_LIST_HEAD(&b->slots);
498 INIT_LIST_HEAD(&b->resources);
499 b->max_bus_speed = PCI_SPEED_UNKNOWN;
500 b->cur_bus_speed = PCI_SPEED_UNKNOWN;
501 #ifdef CONFIG_PCI_DOMAINS_GENERIC
503 b->domain_nr = parent->domain_nr;
508 static void pci_release_host_bridge_dev(struct device *dev)
510 struct pci_host_bridge *bridge = to_pci_host_bridge(dev);
512 if (bridge->release_fn)
513 bridge->release_fn(bridge);
515 pci_free_resource_list(&bridge->windows);
520 static struct pci_host_bridge *pci_alloc_host_bridge(struct pci_bus *b)
522 struct pci_host_bridge *bridge;
524 bridge = kzalloc(sizeof(*bridge), GFP_KERNEL);
528 INIT_LIST_HEAD(&bridge->windows);
533 static const unsigned char pcix_bus_speed[] = {
534 PCI_SPEED_UNKNOWN, /* 0 */
535 PCI_SPEED_66MHz_PCIX, /* 1 */
536 PCI_SPEED_100MHz_PCIX, /* 2 */
537 PCI_SPEED_133MHz_PCIX, /* 3 */
538 PCI_SPEED_UNKNOWN, /* 4 */
539 PCI_SPEED_66MHz_PCIX_ECC, /* 5 */
540 PCI_SPEED_100MHz_PCIX_ECC, /* 6 */
541 PCI_SPEED_133MHz_PCIX_ECC, /* 7 */
542 PCI_SPEED_UNKNOWN, /* 8 */
543 PCI_SPEED_66MHz_PCIX_266, /* 9 */
544 PCI_SPEED_100MHz_PCIX_266, /* A */
545 PCI_SPEED_133MHz_PCIX_266, /* B */
546 PCI_SPEED_UNKNOWN, /* C */
547 PCI_SPEED_66MHz_PCIX_533, /* D */
548 PCI_SPEED_100MHz_PCIX_533, /* E */
549 PCI_SPEED_133MHz_PCIX_533 /* F */
552 const unsigned char pcie_link_speed[] = {
553 PCI_SPEED_UNKNOWN, /* 0 */
554 PCIE_SPEED_2_5GT, /* 1 */
555 PCIE_SPEED_5_0GT, /* 2 */
556 PCIE_SPEED_8_0GT, /* 3 */
557 PCI_SPEED_UNKNOWN, /* 4 */
558 PCI_SPEED_UNKNOWN, /* 5 */
559 PCI_SPEED_UNKNOWN, /* 6 */
560 PCI_SPEED_UNKNOWN, /* 7 */
561 PCI_SPEED_UNKNOWN, /* 8 */
562 PCI_SPEED_UNKNOWN, /* 9 */
563 PCI_SPEED_UNKNOWN, /* A */
564 PCI_SPEED_UNKNOWN, /* B */
565 PCI_SPEED_UNKNOWN, /* C */
566 PCI_SPEED_UNKNOWN, /* D */
567 PCI_SPEED_UNKNOWN, /* E */
568 PCI_SPEED_UNKNOWN /* F */
571 void pcie_update_link_speed(struct pci_bus *bus, u16 linksta)
573 bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS];
575 EXPORT_SYMBOL_GPL(pcie_update_link_speed);
577 static unsigned char agp_speeds[] = {
585 static enum pci_bus_speed agp_speed(int agp3, int agpstat)
591 else if (agpstat & 2)
593 else if (agpstat & 1)
605 return agp_speeds[index];
608 static void pci_set_bus_speed(struct pci_bus *bus)
610 struct pci_dev *bridge = bus->self;
613 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP);
615 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3);
619 pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat);
620 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7);
622 pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd);
623 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7);
626 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
629 enum pci_bus_speed max;
631 pci_read_config_word(bridge, pos + PCI_X_BRIDGE_SSTATUS,
634 if (status & PCI_X_SSTATUS_533MHZ) {
635 max = PCI_SPEED_133MHz_PCIX_533;
636 } else if (status & PCI_X_SSTATUS_266MHZ) {
637 max = PCI_SPEED_133MHz_PCIX_266;
638 } else if (status & PCI_X_SSTATUS_133MHZ) {
639 if ((status & PCI_X_SSTATUS_VERS) == PCI_X_SSTATUS_V2)
640 max = PCI_SPEED_133MHz_PCIX_ECC;
642 max = PCI_SPEED_133MHz_PCIX;
644 max = PCI_SPEED_66MHz_PCIX;
647 bus->max_bus_speed = max;
648 bus->cur_bus_speed = pcix_bus_speed[
649 (status & PCI_X_SSTATUS_FREQ) >> 6];
654 if (pci_is_pcie(bridge)) {
658 pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap);
659 bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS];
661 pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta);
662 pcie_update_link_speed(bus, linksta);
666 static struct irq_domain *pci_host_bridge_msi_domain(struct pci_bus *bus)
668 struct irq_domain *d;
671 * Any firmware interface that can resolve the msi_domain
672 * should be called from here.
674 d = pci_host_bridge_of_msi_domain(bus);
679 static void pci_set_bus_msi_domain(struct pci_bus *bus)
681 struct irq_domain *d;
685 * The bus can be a root bus, a subordinate bus, or a virtual bus
686 * created by an SR-IOV device. Walk up to the first bridge device
687 * found or derive the domain from the host bridge.
689 for (b = bus, d = NULL; !d && !pci_is_root_bus(b); b = b->parent) {
691 d = dev_get_msi_domain(&b->self->dev);
695 d = pci_host_bridge_msi_domain(b);
697 dev_set_msi_domain(&bus->dev, d);
700 static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
701 struct pci_dev *bridge, int busnr)
703 struct pci_bus *child;
708 * Allocate a new bus, and inherit stuff from the parent..
710 child = pci_alloc_bus(parent);
714 child->parent = parent;
715 child->ops = parent->ops;
716 child->msi = parent->msi;
717 child->sysdata = parent->sysdata;
718 child->bus_flags = parent->bus_flags;
720 /* initialize some portions of the bus device, but don't register it
721 * now as the parent is not properly set up yet.
723 child->dev.class = &pcibus_class;
724 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
727 * Set up the primary, secondary and subordinate
730 child->number = child->busn_res.start = busnr;
731 child->primary = parent->busn_res.start;
732 child->busn_res.end = 0xff;
735 child->dev.parent = parent->bridge;
739 child->self = bridge;
740 child->bridge = get_device(&bridge->dev);
741 child->dev.parent = child->bridge;
742 pci_set_bus_of_node(child);
743 pci_set_bus_speed(child);
745 /* Set up default resource pointers and names.. */
746 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
747 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
748 child->resource[i]->name = child->name;
750 bridge->subordinate = child;
753 pci_set_bus_msi_domain(child);
754 ret = device_register(&child->dev);
757 pcibios_add_bus(child);
759 /* Create legacy_io and legacy_mem files for this bus */
760 pci_create_legacy_files(child);
765 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
768 struct pci_bus *child;
770 child = pci_alloc_child_bus(parent, dev, busnr);
772 down_write(&pci_bus_sem);
773 list_add_tail(&child->node, &parent->children);
774 up_write(&pci_bus_sem);
778 EXPORT_SYMBOL(pci_add_new_bus);
780 static void pci_enable_crs(struct pci_dev *pdev)
784 /* Enable CRS Software Visibility if supported */
785 pcie_capability_read_word(pdev, PCI_EXP_RTCAP, &root_cap);
786 if (root_cap & PCI_EXP_RTCAP_CRSVIS)
787 pcie_capability_set_word(pdev, PCI_EXP_RTCTL,
788 PCI_EXP_RTCTL_CRSSVE);
792 * If it's a bridge, configure it and scan the bus behind it.
793 * For CardBus bridges, we don't scan behind as the devices will
794 * be handled by the bridge driver itself.
796 * We need to process bridges in two passes -- first we scan those
797 * already configured by the BIOS and after we are done with all of
798 * them, we proceed to assigning numbers to the remaining buses in
799 * order to avoid overlaps between old and new bus numbers.
801 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
803 struct pci_bus *child;
804 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
807 u8 primary, secondary, subordinate;
810 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
811 primary = buses & 0xFF;
812 secondary = (buses >> 8) & 0xFF;
813 subordinate = (buses >> 16) & 0xFF;
815 dev_dbg(&dev->dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
816 secondary, subordinate, pass);
818 if (!primary && (primary != bus->number) && secondary && subordinate) {
819 dev_warn(&dev->dev, "Primary bus is hard wired to 0\n");
820 primary = bus->number;
823 /* Check if setup is sensible at all */
825 (primary != bus->number || secondary <= bus->number ||
826 secondary > subordinate)) {
827 dev_info(&dev->dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n",
828 secondary, subordinate);
832 /* Disable MasterAbortMode during probing to avoid reporting
833 of bus errors (in some architectures) */
834 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
835 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
836 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
840 if ((secondary || subordinate) && !pcibios_assign_all_busses() &&
841 !is_cardbus && !broken) {
844 * Bus already configured by firmware, process it in the first
845 * pass and just note the configuration.
851 * The bus might already exist for two reasons: Either we are
852 * rescanning the bus or the bus is reachable through more than
853 * one bridge. The second case can happen with the i450NX
856 child = pci_find_bus(pci_domain_nr(bus), secondary);
858 child = pci_add_new_bus(bus, dev, secondary);
861 child->primary = primary;
862 pci_bus_insert_busn_res(child, secondary, subordinate);
863 child->bridge_ctl = bctl;
866 cmax = pci_scan_child_bus(child);
867 if (cmax > subordinate)
868 dev_warn(&dev->dev, "bridge has subordinate %02x but max busn %02x\n",
870 /* subordinate should equal child->busn_res.end */
871 if (subordinate > max)
875 * We need to assign a number to this bus which we always
876 * do in the second pass.
879 if (pcibios_assign_all_busses() || broken || is_cardbus)
880 /* Temporarily disable forwarding of the
881 configuration cycles on all bridges in
882 this bus segment to avoid possible
883 conflicts in the second pass between two
884 bridges programmed with overlapping
886 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
892 pci_write_config_word(dev, PCI_STATUS, 0xffff);
894 /* Prevent assigning a bus number that already exists.
895 * This can happen when a bridge is hot-plugged, so in
896 * this case we only re-scan this bus. */
897 child = pci_find_bus(pci_domain_nr(bus), max+1);
899 child = pci_add_new_bus(bus, dev, max+1);
902 pci_bus_insert_busn_res(child, max+1, 0xff);
905 buses = (buses & 0xff000000)
906 | ((unsigned int)(child->primary) << 0)
907 | ((unsigned int)(child->busn_res.start) << 8)
908 | ((unsigned int)(child->busn_res.end) << 16);
911 * yenta.c forces a secondary latency timer of 176.
912 * Copy that behaviour here.
915 buses &= ~0xff000000;
916 buses |= CARDBUS_LATENCY_TIMER << 24;
920 * We need to blast all three values with a single write.
922 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
925 child->bridge_ctl = bctl;
926 max = pci_scan_child_bus(child);
929 * For CardBus bridges, we leave 4 bus numbers
930 * as cards with a PCI-to-PCI bridge can be
933 for (i = 0; i < CARDBUS_RESERVE_BUSNR; i++) {
934 struct pci_bus *parent = bus;
935 if (pci_find_bus(pci_domain_nr(bus),
938 while (parent->parent) {
939 if ((!pcibios_assign_all_busses()) &&
940 (parent->busn_res.end > max) &&
941 (parent->busn_res.end <= max+i)) {
944 parent = parent->parent;
948 * Often, there are two cardbus bridges
949 * -- try to leave one valid bus number
959 * Set the subordinate bus number to its real value.
961 pci_bus_update_busn_res_end(child, max);
962 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
966 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
967 pci_domain_nr(bus), child->number);
969 /* Has only triggered on CardBus, fixup is in yenta_socket */
970 while (bus->parent) {
971 if ((child->busn_res.end > bus->busn_res.end) ||
972 (child->number > bus->busn_res.end) ||
973 (child->number < bus->number) ||
974 (child->busn_res.end < bus->number)) {
975 dev_info(&child->dev, "%pR %s hidden behind%s bridge %s %pR\n",
977 (bus->number > child->busn_res.end &&
978 bus->busn_res.end < child->number) ?
979 "wholly" : "partially",
980 bus->self->transparent ? " transparent" : "",
988 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
992 EXPORT_SYMBOL(pci_scan_bridge);
995 * Read interrupt line and base address registers.
996 * The architecture-dependent code can tweak these, of course.
998 static void pci_read_irq(struct pci_dev *dev)
1002 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
1005 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
1009 void set_pcie_port_type(struct pci_dev *pdev)
1014 struct pci_dev *parent;
1016 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
1019 pdev->pcie_cap = pos;
1020 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
1021 pdev->pcie_flags_reg = reg16;
1022 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16);
1023 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
1026 * A Root Port is always the upstream end of a Link. No PCIe
1027 * component has two Links. Two Links are connected by a Switch
1028 * that has a Port on each Link and internal logic to connect the
1031 type = pci_pcie_type(pdev);
1032 if (type == PCI_EXP_TYPE_ROOT_PORT)
1033 pdev->has_secondary_link = 1;
1034 else if (type == PCI_EXP_TYPE_UPSTREAM ||
1035 type == PCI_EXP_TYPE_DOWNSTREAM) {
1036 parent = pci_upstream_bridge(pdev);
1039 * Usually there's an upstream device (Root Port or Switch
1040 * Downstream Port), but we can't assume one exists.
1042 if (parent && !parent->has_secondary_link)
1043 pdev->has_secondary_link = 1;
1047 void set_pcie_hotplug_bridge(struct pci_dev *pdev)
1051 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, ®32);
1052 if (reg32 & PCI_EXP_SLTCAP_HPC)
1053 pdev->is_hotplug_bridge = 1;
1057 * pci_ext_cfg_is_aliased - is ext config space just an alias of std config?
1060 * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that
1061 * when forwarding a type1 configuration request the bridge must check that
1062 * the extended register address field is zero. The bridge is not permitted
1063 * to forward the transactions and must handle it as an Unsupported Request.
1064 * Some bridges do not follow this rule and simply drop the extended register
1065 * bits, resulting in the standard config space being aliased, every 256
1066 * bytes across the entire configuration space. Test for this condition by
1067 * comparing the first dword of each potential alias to the vendor/device ID.
1069 * ASM1083/1085 PCIe-to-PCI Reversible Bridge (1b21:1080, rev 01 & 03)
1070 * AMD/ATI SBx00 PCI to PCI Bridge (1002:4384, rev 40)
1072 static bool pci_ext_cfg_is_aliased(struct pci_dev *dev)
1074 #ifdef CONFIG_PCI_QUIRKS
1078 pci_read_config_dword(dev, PCI_VENDOR_ID, &header);
1080 for (pos = PCI_CFG_SPACE_SIZE;
1081 pos < PCI_CFG_SPACE_EXP_SIZE; pos += PCI_CFG_SPACE_SIZE) {
1082 if (pci_read_config_dword(dev, pos, &tmp) != PCIBIOS_SUCCESSFUL
1094 * pci_cfg_space_size - get the configuration space size of the PCI device.
1097 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
1098 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
1099 * access it. Maybe we don't have a way to generate extended config space
1100 * accesses, or the device is behind a reverse Express bridge. So we try
1101 * reading the dword at 0x100 which must either be 0 or a valid extended
1102 * capability header.
1104 static int pci_cfg_space_size_ext(struct pci_dev *dev)
1107 int pos = PCI_CFG_SPACE_SIZE;
1109 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
1110 return PCI_CFG_SPACE_SIZE;
1111 if (status == 0xffffffff || pci_ext_cfg_is_aliased(dev))
1112 return PCI_CFG_SPACE_SIZE;
1114 return PCI_CFG_SPACE_EXP_SIZE;
1117 int pci_cfg_space_size(struct pci_dev *dev)
1123 class = dev->class >> 8;
1124 if (class == PCI_CLASS_BRIDGE_HOST)
1125 return pci_cfg_space_size_ext(dev);
1127 if (pci_is_pcie(dev))
1128 return pci_cfg_space_size_ext(dev);
1130 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1132 return PCI_CFG_SPACE_SIZE;
1134 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
1135 if (status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ))
1136 return pci_cfg_space_size_ext(dev);
1138 return PCI_CFG_SPACE_SIZE;
1141 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
1143 static void pci_msi_setup_pci_dev(struct pci_dev *dev)
1146 * Disable the MSI hardware to avoid screaming interrupts
1147 * during boot. This is the power on reset default so
1148 * usually this should be a noop.
1150 dev->msi_cap = pci_find_capability(dev, PCI_CAP_ID_MSI);
1152 pci_msi_set_enable(dev, 0);
1154 dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX);
1156 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
1160 * pci_setup_device - fill in class and map information of a device
1161 * @dev: the device structure to fill
1163 * Initialize the device structure with information about the device's
1164 * vendor,class,memory and IO-space addresses,IRQ lines etc.
1165 * Called at initialisation of the PCI subsystem and by CardBus services.
1166 * Returns 0 on success and negative if unknown type of device (not normal,
1167 * bridge or CardBus).
1169 int pci_setup_device(struct pci_dev *dev)
1174 struct pci_bus_region region;
1175 struct resource *res;
1177 if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type))
1180 dev->sysdata = dev->bus->sysdata;
1181 dev->dev.parent = dev->bus->bridge;
1182 dev->dev.bus = &pci_bus_type;
1183 dev->hdr_type = hdr_type & 0x7f;
1184 dev->multifunction = !!(hdr_type & 0x80);
1185 dev->error_state = pci_channel_io_normal;
1186 set_pcie_port_type(dev);
1188 pci_dev_assign_slot(dev);
1189 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
1190 set this higher, assuming the system even supports it. */
1191 dev->dma_mask = 0xffffffff;
1193 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
1194 dev->bus->number, PCI_SLOT(dev->devfn),
1195 PCI_FUNC(dev->devfn));
1197 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
1198 dev->revision = class & 0xff;
1199 dev->class = class >> 8; /* upper 3 bytes */
1201 dev_printk(KERN_DEBUG, &dev->dev, "[%04x:%04x] type %02x class %#08x\n",
1202 dev->vendor, dev->device, dev->hdr_type, dev->class);
1204 /* need to have dev->class ready */
1205 dev->cfg_size = pci_cfg_space_size(dev);
1207 /* "Unknown power state" */
1208 dev->current_state = PCI_UNKNOWN;
1210 /* Early fixups, before probing the BARs */
1211 pci_fixup_device(pci_fixup_early, dev);
1212 /* device class may be changed after fixup */
1213 class = dev->class >> 8;
1215 switch (dev->hdr_type) { /* header type */
1216 case PCI_HEADER_TYPE_NORMAL: /* standard header */
1217 if (class == PCI_CLASS_BRIDGE_PCI)
1220 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
1221 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1222 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
1225 * Do the ugly legacy mode stuff here rather than broken chip
1226 * quirk code. Legacy mode ATA controllers have fixed
1227 * addresses. These are not always echoed in BAR0-3, and
1228 * BAR0-3 in a few cases contain junk!
1230 if (class == PCI_CLASS_STORAGE_IDE) {
1232 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
1233 if ((progif & 1) == 0) {
1234 region.start = 0x1F0;
1236 res = &dev->resource[0];
1237 res->flags = LEGACY_IO_RESOURCE;
1238 pcibios_bus_to_resource(dev->bus, res, ®ion);
1239 dev_info(&dev->dev, "legacy IDE quirk: reg 0x10: %pR\n",
1241 region.start = 0x3F6;
1243 res = &dev->resource[1];
1244 res->flags = LEGACY_IO_RESOURCE;
1245 pcibios_bus_to_resource(dev->bus, res, ®ion);
1246 dev_info(&dev->dev, "legacy IDE quirk: reg 0x14: %pR\n",
1249 if ((progif & 4) == 0) {
1250 region.start = 0x170;
1252 res = &dev->resource[2];
1253 res->flags = LEGACY_IO_RESOURCE;
1254 pcibios_bus_to_resource(dev->bus, res, ®ion);
1255 dev_info(&dev->dev, "legacy IDE quirk: reg 0x18: %pR\n",
1257 region.start = 0x376;
1259 res = &dev->resource[3];
1260 res->flags = LEGACY_IO_RESOURCE;
1261 pcibios_bus_to_resource(dev->bus, res, ®ion);
1262 dev_info(&dev->dev, "legacy IDE quirk: reg 0x1c: %pR\n",
1268 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
1269 if (class != PCI_CLASS_BRIDGE_PCI)
1271 /* The PCI-to-PCI bridge spec requires that subtractive
1272 decoding (i.e. transparent) bridge must have programming
1273 interface code of 0x01. */
1275 dev->transparent = ((dev->class & 0xff) == 1);
1276 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
1277 set_pcie_hotplug_bridge(dev);
1278 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID);
1280 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor);
1281 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device);
1285 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
1286 if (class != PCI_CLASS_BRIDGE_CARDBUS)
1289 pci_read_bases(dev, 1, 0);
1290 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1291 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
1294 default: /* unknown header */
1295 dev_err(&dev->dev, "unknown header type %02x, ignoring device\n",
1300 dev_err(&dev->dev, "ignoring class %#08x (doesn't match header type %02x)\n",
1301 dev->class, dev->hdr_type);
1302 dev->class = PCI_CLASS_NOT_DEFINED << 8;
1305 /* We found a fine healthy device, go go go... */
1309 static void pci_configure_mps(struct pci_dev *dev)
1311 struct pci_dev *bridge = pci_upstream_bridge(dev);
1314 if (!pci_is_pcie(dev) || !bridge || !pci_is_pcie(bridge))
1317 mps = pcie_get_mps(dev);
1318 p_mps = pcie_get_mps(bridge);
1323 if (pcie_bus_config == PCIE_BUS_TUNE_OFF) {
1324 dev_warn(&dev->dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1325 mps, pci_name(bridge), p_mps);
1330 * Fancier MPS configuration is done later by
1331 * pcie_bus_configure_settings()
1333 if (pcie_bus_config != PCIE_BUS_DEFAULT)
1336 rc = pcie_set_mps(dev, p_mps);
1338 dev_warn(&dev->dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1343 dev_info(&dev->dev, "Max Payload Size set to %d (was %d, max %d)\n",
1344 p_mps, mps, 128 << dev->pcie_mpss);
1347 static struct hpp_type0 pci_default_type0 = {
1349 .cache_line_size = 8,
1350 .latency_timer = 0x40,
1355 static void program_hpp_type0(struct pci_dev *dev, struct hpp_type0 *hpp)
1357 u16 pci_cmd, pci_bctl;
1360 hpp = &pci_default_type0;
1362 if (hpp->revision > 1) {
1364 "PCI settings rev %d not supported; using defaults\n",
1366 hpp = &pci_default_type0;
1369 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, hpp->cache_line_size);
1370 pci_write_config_byte(dev, PCI_LATENCY_TIMER, hpp->latency_timer);
1371 pci_read_config_word(dev, PCI_COMMAND, &pci_cmd);
1372 if (hpp->enable_serr)
1373 pci_cmd |= PCI_COMMAND_SERR;
1374 if (hpp->enable_perr)
1375 pci_cmd |= PCI_COMMAND_PARITY;
1376 pci_write_config_word(dev, PCI_COMMAND, pci_cmd);
1378 /* Program bridge control value */
1379 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
1380 pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER,
1381 hpp->latency_timer);
1382 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &pci_bctl);
1383 if (hpp->enable_serr)
1384 pci_bctl |= PCI_BRIDGE_CTL_SERR;
1385 if (hpp->enable_perr)
1386 pci_bctl |= PCI_BRIDGE_CTL_PARITY;
1387 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, pci_bctl);
1391 static void program_hpp_type1(struct pci_dev *dev, struct hpp_type1 *hpp)
1394 dev_warn(&dev->dev, "PCI-X settings not supported\n");
1397 static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp)
1405 if (hpp->revision > 1) {
1406 dev_warn(&dev->dev, "PCIe settings rev %d not supported\n",
1412 * Don't allow _HPX to change MPS or MRRS settings. We manage
1413 * those to make sure they're consistent with the rest of the
1416 hpp->pci_exp_devctl_and |= PCI_EXP_DEVCTL_PAYLOAD |
1417 PCI_EXP_DEVCTL_READRQ;
1418 hpp->pci_exp_devctl_or &= ~(PCI_EXP_DEVCTL_PAYLOAD |
1419 PCI_EXP_DEVCTL_READRQ);
1421 /* Initialize Device Control Register */
1422 pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
1423 ~hpp->pci_exp_devctl_and, hpp->pci_exp_devctl_or);
1425 /* Initialize Link Control Register */
1426 if (pcie_cap_has_lnkctl(dev))
1427 pcie_capability_clear_and_set_word(dev, PCI_EXP_LNKCTL,
1428 ~hpp->pci_exp_lnkctl_and, hpp->pci_exp_lnkctl_or);
1430 /* Find Advanced Error Reporting Enhanced Capability */
1431 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
1435 /* Initialize Uncorrectable Error Mask Register */
1436 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, ®32);
1437 reg32 = (reg32 & hpp->unc_err_mask_and) | hpp->unc_err_mask_or;
1438 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, reg32);
1440 /* Initialize Uncorrectable Error Severity Register */
1441 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, ®32);
1442 reg32 = (reg32 & hpp->unc_err_sever_and) | hpp->unc_err_sever_or;
1443 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, reg32);
1445 /* Initialize Correctable Error Mask Register */
1446 pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, ®32);
1447 reg32 = (reg32 & hpp->cor_err_mask_and) | hpp->cor_err_mask_or;
1448 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg32);
1450 /* Initialize Advanced Error Capabilities and Control Register */
1451 pci_read_config_dword(dev, pos + PCI_ERR_CAP, ®32);
1452 reg32 = (reg32 & hpp->adv_err_cap_and) | hpp->adv_err_cap_or;
1453 pci_write_config_dword(dev, pos + PCI_ERR_CAP, reg32);
1456 * FIXME: The following two registers are not supported yet.
1458 * o Secondary Uncorrectable Error Severity Register
1459 * o Secondary Uncorrectable Error Mask Register
1463 static void pci_configure_device(struct pci_dev *dev)
1465 struct hotplug_params hpp;
1468 pci_configure_mps(dev);
1470 memset(&hpp, 0, sizeof(hpp));
1471 ret = pci_get_hp_params(dev, &hpp);
1475 program_hpp_type2(dev, hpp.t2);
1476 program_hpp_type1(dev, hpp.t1);
1477 program_hpp_type0(dev, hpp.t0);
1480 static void pci_release_capabilities(struct pci_dev *dev)
1482 pci_vpd_release(dev);
1483 pci_iov_release(dev);
1484 pci_free_cap_save_buffers(dev);
1488 * pci_release_dev - free a pci device structure when all users of it are finished.
1489 * @dev: device that's been disconnected
1491 * Will be called only by the device core when all users of this pci device are
1494 static void pci_release_dev(struct device *dev)
1496 struct pci_dev *pci_dev;
1498 pci_dev = to_pci_dev(dev);
1499 pci_release_capabilities(pci_dev);
1500 pci_release_of_node(pci_dev);
1501 pcibios_release_device(pci_dev);
1502 pci_bus_put(pci_dev->bus);
1503 kfree(pci_dev->driver_override);
1507 struct pci_dev *pci_alloc_dev(struct pci_bus *bus)
1509 struct pci_dev *dev;
1511 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
1515 INIT_LIST_HEAD(&dev->bus_list);
1516 dev->dev.type = &pci_dev_type;
1517 dev->bus = pci_bus_get(bus);
1521 EXPORT_SYMBOL(pci_alloc_dev);
1523 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
1528 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
1531 /* some broken boards return 0 or ~0 if a slot is empty: */
1532 if (*l == 0xffffffff || *l == 0x00000000 ||
1533 *l == 0x0000ffff || *l == 0xffff0000)
1537 * Configuration Request Retry Status. Some root ports return the
1538 * actual device ID instead of the synthetic ID (0xFFFF) required
1539 * by the PCIe spec. Ignore the device ID and only check for
1542 while ((*l & 0xffff) == 0x0001) {
1548 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
1550 /* Card hasn't responded in 60 seconds? Must be stuck. */
1551 if (delay > crs_timeout) {
1552 printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not responding\n",
1553 pci_domain_nr(bus), bus->number, PCI_SLOT(devfn),
1561 EXPORT_SYMBOL(pci_bus_read_dev_vendor_id);
1564 * Read the config data for a PCI device, sanity-check it
1565 * and fill in the dev structure...
1567 static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
1569 struct pci_dev *dev;
1572 if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000))
1575 dev = pci_alloc_dev(bus);
1580 dev->vendor = l & 0xffff;
1581 dev->device = (l >> 16) & 0xffff;
1583 pci_set_of_node(dev);
1585 if (pci_setup_device(dev)) {
1586 pci_bus_put(dev->bus);
1594 static void pci_init_capabilities(struct pci_dev *dev)
1596 /* Enhanced Allocation */
1599 /* Setup MSI caps & disable MSI/MSI-X interrupts */
1600 pci_msi_setup_pci_dev(dev);
1602 /* Buffers for saving PCIe and PCI-X capabilities */
1603 pci_allocate_cap_save_buffers(dev);
1605 /* Power Management */
1608 /* Vital Product Data */
1609 pci_vpd_pci22_init(dev);
1611 /* Alternative Routing-ID Forwarding */
1612 pci_configure_ari(dev);
1614 /* Single Root I/O Virtualization */
1617 /* Address Translation Services */
1620 /* Enable ACS P2P upstream forwarding */
1621 pci_enable_acs(dev);
1623 pci_cleanup_aer_error_status_regs(dev);
1627 * This is the equivalent of pci_host_bridge_msi_domain that acts on
1628 * devices. Firmware interfaces that can select the MSI domain on a
1629 * per-device basis should be called from here.
1631 static struct irq_domain *pci_dev_msi_domain(struct pci_dev *dev)
1633 struct irq_domain *d;
1636 * If a domain has been set through the pcibios_add_device
1637 * callback, then this is the one (platform code knows best).
1639 d = dev_get_msi_domain(&dev->dev);
1644 * Let's see if we have a firmware interface able to provide
1647 d = pci_msi_get_device_domain(dev);
1654 static void pci_set_msi_domain(struct pci_dev *dev)
1656 struct irq_domain *d;
1659 * If the platform or firmware interfaces cannot supply a
1660 * device-specific MSI domain, then inherit the default domain
1661 * from the host bridge itself.
1663 d = pci_dev_msi_domain(dev);
1665 d = dev_get_msi_domain(&dev->bus->dev);
1667 dev_set_msi_domain(&dev->dev, d);
1671 * pci_dma_configure - Setup DMA configuration
1672 * @dev: ptr to pci_dev struct of the PCI device
1674 * Function to update PCI devices's DMA configuration using the same
1675 * info from the OF node or ACPI node of host bridge's parent (if any).
1677 static void pci_dma_configure(struct pci_dev *dev)
1679 struct device *bridge = pci_get_host_bridge_device(dev);
1681 if (IS_ENABLED(CONFIG_OF) &&
1682 bridge->parent && bridge->parent->of_node) {
1683 of_dma_configure(&dev->dev, bridge->parent->of_node);
1684 } else if (has_acpi_companion(bridge)) {
1685 struct acpi_device *adev = to_acpi_device_node(bridge->fwnode);
1686 enum dev_dma_attr attr = acpi_get_dma_attr(adev);
1688 if (attr == DEV_DMA_NOT_SUPPORTED)
1689 dev_warn(&dev->dev, "DMA not supported.\n");
1691 arch_setup_dma_ops(&dev->dev, 0, 0, NULL,
1692 attr == DEV_DMA_COHERENT);
1695 pci_put_host_bridge_device(bridge);
1698 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
1702 pci_configure_device(dev);
1704 device_initialize(&dev->dev);
1705 dev->dev.release = pci_release_dev;
1707 set_dev_node(&dev->dev, pcibus_to_node(bus));
1708 dev->dev.dma_mask = &dev->dma_mask;
1709 dev->dev.dma_parms = &dev->dma_parms;
1710 dev->dev.coherent_dma_mask = 0xffffffffull;
1711 pci_dma_configure(dev);
1713 pci_set_dma_max_seg_size(dev, 65536);
1714 pci_set_dma_seg_boundary(dev, 0xffffffff);
1716 /* Fix up broken headers */
1717 pci_fixup_device(pci_fixup_header, dev);
1719 /* moved out from quirk header fixup code */
1720 pci_reassigndev_resource_alignment(dev);
1722 /* Clear the state_saved flag. */
1723 dev->state_saved = false;
1725 /* Initialize various capabilities */
1726 pci_init_capabilities(dev);
1729 * Add the device to our list of discovered devices
1730 * and the bus list for fixup functions, etc.
1732 down_write(&pci_bus_sem);
1733 list_add_tail(&dev->bus_list, &bus->devices);
1734 up_write(&pci_bus_sem);
1736 ret = pcibios_add_device(dev);
1739 /* Setup MSI irq domain */
1740 pci_set_msi_domain(dev);
1742 /* Notifier could use PCI capabilities */
1743 dev->match_driver = false;
1744 ret = device_add(&dev->dev);
1748 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn)
1750 struct pci_dev *dev;
1752 dev = pci_get_slot(bus, devfn);
1758 dev = pci_scan_device(bus, devfn);
1762 pci_device_add(dev, bus);
1766 EXPORT_SYMBOL(pci_scan_single_device);
1768 static unsigned next_fn(struct pci_bus *bus, struct pci_dev *dev, unsigned fn)
1774 if (pci_ari_enabled(bus)) {
1777 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
1781 pci_read_config_word(dev, pos + PCI_ARI_CAP, &cap);
1782 next_fn = PCI_ARI_CAP_NFN(cap);
1784 return 0; /* protect against malformed list */
1789 /* dev may be NULL for non-contiguous multifunction devices */
1790 if (!dev || dev->multifunction)
1791 return (fn + 1) % 8;
1796 static int only_one_child(struct pci_bus *bus)
1798 struct pci_dev *parent = bus->self;
1800 if (!parent || !pci_is_pcie(parent))
1802 if (pci_pcie_type(parent) == PCI_EXP_TYPE_ROOT_PORT)
1804 if (parent->has_secondary_link &&
1805 !pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS))
1811 * pci_scan_slot - scan a PCI slot on a bus for devices.
1812 * @bus: PCI bus to scan
1813 * @devfn: slot number to scan (must have zero function.)
1815 * Scan a PCI slot on the specified PCI bus for devices, adding
1816 * discovered devices to the @bus->devices list. New devices
1817 * will not have is_added set.
1819 * Returns the number of new devices found.
1821 int pci_scan_slot(struct pci_bus *bus, int devfn)
1823 unsigned fn, nr = 0;
1824 struct pci_dev *dev;
1826 if (only_one_child(bus) && (devfn > 0))
1827 return 0; /* Already scanned the entire slot */
1829 dev = pci_scan_single_device(bus, devfn);
1835 for (fn = next_fn(bus, dev, 0); fn > 0; fn = next_fn(bus, dev, fn)) {
1836 dev = pci_scan_single_device(bus, devfn + fn);
1840 dev->multifunction = 1;
1844 /* only one slot has pcie device */
1845 if (bus->self && nr)
1846 pcie_aspm_init_link_state(bus->self);
1850 EXPORT_SYMBOL(pci_scan_slot);
1852 static int pcie_find_smpss(struct pci_dev *dev, void *data)
1856 if (!pci_is_pcie(dev))
1860 * We don't have a way to change MPS settings on devices that have
1861 * drivers attached. A hot-added device might support only the minimum
1862 * MPS setting (MPS=128). Therefore, if the fabric contains a bridge
1863 * where devices may be hot-added, we limit the fabric MPS to 128 so
1864 * hot-added devices will work correctly.
1866 * However, if we hot-add a device to a slot directly below a Root
1867 * Port, it's impossible for there to be other existing devices below
1868 * the port. We don't limit the MPS in this case because we can
1869 * reconfigure MPS on both the Root Port and the hot-added device,
1870 * and there are no other devices involved.
1872 * Note that this PCIE_BUS_SAFE path assumes no peer-to-peer DMA.
1874 if (dev->is_hotplug_bridge &&
1875 pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
1878 if (*smpss > dev->pcie_mpss)
1879 *smpss = dev->pcie_mpss;
1884 static void pcie_write_mps(struct pci_dev *dev, int mps)
1888 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
1889 mps = 128 << dev->pcie_mpss;
1891 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT &&
1893 /* For "Performance", the assumption is made that
1894 * downstream communication will never be larger than
1895 * the MRRS. So, the MPS only needs to be configured
1896 * for the upstream communication. This being the case,
1897 * walk from the top down and set the MPS of the child
1898 * to that of the parent bus.
1900 * Configure the device MPS with the smaller of the
1901 * device MPSS or the bridge MPS (which is assumed to be
1902 * properly configured at this point to the largest
1903 * allowable MPS based on its parent bus).
1905 mps = min(mps, pcie_get_mps(dev->bus->self));
1908 rc = pcie_set_mps(dev, mps);
1910 dev_err(&dev->dev, "Failed attempting to set the MPS\n");
1913 static void pcie_write_mrrs(struct pci_dev *dev)
1917 /* In the "safe" case, do not configure the MRRS. There appear to be
1918 * issues with setting MRRS to 0 on a number of devices.
1920 if (pcie_bus_config != PCIE_BUS_PERFORMANCE)
1923 /* For Max performance, the MRRS must be set to the largest supported
1924 * value. However, it cannot be configured larger than the MPS the
1925 * device or the bus can support. This should already be properly
1926 * configured by a prior call to pcie_write_mps.
1928 mrrs = pcie_get_mps(dev);
1930 /* MRRS is a R/W register. Invalid values can be written, but a
1931 * subsequent read will verify if the value is acceptable or not.
1932 * If the MRRS value provided is not acceptable (e.g., too large),
1933 * shrink the value until it is acceptable to the HW.
1935 while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) {
1936 rc = pcie_set_readrq(dev, mrrs);
1940 dev_warn(&dev->dev, "Failed attempting to set the MRRS\n");
1945 dev_err(&dev->dev, "MRRS was unable to be configured with a safe value. If problems are experienced, try running with pci=pcie_bus_safe\n");
1948 static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
1952 if (!pci_is_pcie(dev))
1955 if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||
1956 pcie_bus_config == PCIE_BUS_DEFAULT)
1959 mps = 128 << *(u8 *)data;
1960 orig_mps = pcie_get_mps(dev);
1962 pcie_write_mps(dev, mps);
1963 pcie_write_mrrs(dev);
1965 dev_info(&dev->dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n",
1966 pcie_get_mps(dev), 128 << dev->pcie_mpss,
1967 orig_mps, pcie_get_readrq(dev));
1972 /* pcie_bus_configure_settings requires that pci_walk_bus work in a top-down,
1973 * parents then children fashion. If this changes, then this code will not
1976 void pcie_bus_configure_settings(struct pci_bus *bus)
1983 if (!pci_is_pcie(bus->self))
1986 /* FIXME - Peer to peer DMA is possible, though the endpoint would need
1987 * to be aware of the MPS of the destination. To work around this,
1988 * simply force the MPS of the entire system to the smallest possible.
1990 if (pcie_bus_config == PCIE_BUS_PEER2PEER)
1993 if (pcie_bus_config == PCIE_BUS_SAFE) {
1994 smpss = bus->self->pcie_mpss;
1996 pcie_find_smpss(bus->self, &smpss);
1997 pci_walk_bus(bus, pcie_find_smpss, &smpss);
2000 pcie_bus_configure_set(bus->self, &smpss);
2001 pci_walk_bus(bus, pcie_bus_configure_set, &smpss);
2003 EXPORT_SYMBOL_GPL(pcie_bus_configure_settings);
2005 unsigned int pci_scan_child_bus(struct pci_bus *bus)
2007 unsigned int devfn, pass, max = bus->busn_res.start;
2008 struct pci_dev *dev;
2010 dev_dbg(&bus->dev, "scanning bus\n");
2012 /* Go find them, Rover! */
2013 for (devfn = 0; devfn < 0x100; devfn += 8)
2014 pci_scan_slot(bus, devfn);
2016 /* Reserve buses for SR-IOV capability. */
2017 max += pci_iov_bus_range(bus);
2020 * After performing arch-dependent fixup of the bus, look behind
2021 * all PCI-to-PCI bridges on this bus.
2023 if (!bus->is_added) {
2024 dev_dbg(&bus->dev, "fixups for bus\n");
2025 pcibios_fixup_bus(bus);
2029 for (pass = 0; pass < 2; pass++)
2030 list_for_each_entry(dev, &bus->devices, bus_list) {
2031 if (pci_is_bridge(dev))
2032 max = pci_scan_bridge(bus, dev, max, pass);
2036 * We've scanned the bus and so we know all about what's on
2037 * the other side of any bridges that may be on this bus plus
2040 * Return how far we've got finding sub-buses.
2042 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max);
2045 EXPORT_SYMBOL_GPL(pci_scan_child_bus);
2048 * pcibios_root_bridge_prepare - Platform-specific host bridge setup.
2049 * @bridge: Host bridge to set up.
2051 * Default empty implementation. Replace with an architecture-specific setup
2052 * routine, if necessary.
2054 int __weak pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
2059 void __weak pcibios_add_bus(struct pci_bus *bus)
2063 void __weak pcibios_remove_bus(struct pci_bus *bus)
2067 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
2068 struct pci_ops *ops, void *sysdata, struct list_head *resources)
2071 struct pci_host_bridge *bridge;
2072 struct pci_bus *b, *b2;
2073 struct resource_entry *window, *n;
2074 struct resource *res;
2075 resource_size_t offset;
2079 b = pci_alloc_bus(NULL);
2083 b->sysdata = sysdata;
2085 b->number = b->busn_res.start = bus;
2086 pci_bus_assign_domain_nr(b, parent);
2087 b2 = pci_find_bus(pci_domain_nr(b), bus);
2089 /* If we already got to this bus through a different bridge, ignore it */
2090 dev_dbg(&b2->dev, "bus already known\n");
2094 bridge = pci_alloc_host_bridge(b);
2098 bridge->dev.parent = parent;
2099 bridge->dev.release = pci_release_host_bridge_dev;
2100 dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(b), bus);
2101 error = pcibios_root_bridge_prepare(bridge);
2107 error = device_register(&bridge->dev);
2109 put_device(&bridge->dev);
2112 b->bridge = get_device(&bridge->dev);
2113 device_enable_async_suspend(b->bridge);
2114 pci_set_bus_of_node(b);
2115 pci_set_bus_msi_domain(b);
2118 set_dev_node(b->bridge, pcibus_to_node(b));
2120 b->dev.class = &pcibus_class;
2121 b->dev.parent = b->bridge;
2122 dev_set_name(&b->dev, "%04x:%02x", pci_domain_nr(b), bus);
2123 error = device_register(&b->dev);
2125 goto class_dev_reg_err;
2129 /* Create legacy_io and legacy_mem files for this bus */
2130 pci_create_legacy_files(b);
2133 dev_info(parent, "PCI host bridge to bus %s\n", dev_name(&b->dev));
2135 printk(KERN_INFO "PCI host bridge to bus %s\n", dev_name(&b->dev));
2137 /* Add initial resources to the bus */
2138 resource_list_for_each_entry_safe(window, n, resources) {
2139 list_move_tail(&window->node, &bridge->windows);
2141 offset = window->offset;
2142 if (res->flags & IORESOURCE_BUS)
2143 pci_bus_insert_busn_res(b, bus, res->end);
2145 pci_bus_add_resource(b, res, 0);
2147 if (resource_type(res) == IORESOURCE_IO)
2148 fmt = " (bus address [%#06llx-%#06llx])";
2150 fmt = " (bus address [%#010llx-%#010llx])";
2151 snprintf(bus_addr, sizeof(bus_addr), fmt,
2152 (unsigned long long) (res->start - offset),
2153 (unsigned long long) (res->end - offset));
2156 dev_info(&b->dev, "root bus resource %pR%s\n", res, bus_addr);
2159 down_write(&pci_bus_sem);
2160 list_add_tail(&b->node, &pci_root_buses);
2161 up_write(&pci_bus_sem);
2166 put_device(&bridge->dev);
2167 device_unregister(&bridge->dev);
2172 EXPORT_SYMBOL_GPL(pci_create_root_bus);
2174 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max)
2176 struct resource *res = &b->busn_res;
2177 struct resource *parent_res, *conflict;
2181 res->flags = IORESOURCE_BUS;
2183 if (!pci_is_root_bus(b))
2184 parent_res = &b->parent->busn_res;
2186 parent_res = get_pci_domain_busn_res(pci_domain_nr(b));
2187 res->flags |= IORESOURCE_PCI_FIXED;
2190 conflict = request_resource_conflict(parent_res, res);
2193 dev_printk(KERN_DEBUG, &b->dev,
2194 "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n",
2195 res, pci_is_root_bus(b) ? "domain " : "",
2196 parent_res, conflict->name, conflict);
2198 return conflict == NULL;
2201 int pci_bus_update_busn_res_end(struct pci_bus *b, int bus_max)
2203 struct resource *res = &b->busn_res;
2204 struct resource old_res = *res;
2205 resource_size_t size;
2208 if (res->start > bus_max)
2211 size = bus_max - res->start + 1;
2212 ret = adjust_resource(res, res->start, size);
2213 dev_printk(KERN_DEBUG, &b->dev,
2214 "busn_res: %pR end %s updated to %02x\n",
2215 &old_res, ret ? "can not be" : "is", bus_max);
2217 if (!ret && !res->parent)
2218 pci_bus_insert_busn_res(b, res->start, res->end);
2223 void pci_bus_release_busn_res(struct pci_bus *b)
2225 struct resource *res = &b->busn_res;
2228 if (!res->flags || !res->parent)
2231 ret = release_resource(res);
2232 dev_printk(KERN_DEBUG, &b->dev,
2233 "busn_res: %pR %s released\n",
2234 res, ret ? "can not be" : "is");
2237 struct pci_bus *pci_scan_root_bus_msi(struct device *parent, int bus,
2238 struct pci_ops *ops, void *sysdata,
2239 struct list_head *resources, struct msi_controller *msi)
2241 struct resource_entry *window;
2246 resource_list_for_each_entry(window, resources)
2247 if (window->res->flags & IORESOURCE_BUS) {
2252 b = pci_create_root_bus(parent, bus, ops, sysdata, resources);
2260 "No busn resource found for root bus, will use [bus %02x-ff]\n",
2262 pci_bus_insert_busn_res(b, bus, 255);
2265 max = pci_scan_child_bus(b);
2268 pci_bus_update_busn_res_end(b, max);
2273 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
2274 struct pci_ops *ops, void *sysdata, struct list_head *resources)
2276 return pci_scan_root_bus_msi(parent, bus, ops, sysdata, resources,
2279 EXPORT_SYMBOL(pci_scan_root_bus);
2281 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops,
2284 LIST_HEAD(resources);
2287 pci_add_resource(&resources, &ioport_resource);
2288 pci_add_resource(&resources, &iomem_resource);
2289 pci_add_resource(&resources, &busn_resource);
2290 b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources);
2292 pci_scan_child_bus(b);
2294 pci_free_resource_list(&resources);
2298 EXPORT_SYMBOL(pci_scan_bus);
2301 * pci_rescan_bus_bridge_resize - scan a PCI bus for devices.
2302 * @bridge: PCI bridge for the bus to scan
2304 * Scan a PCI bus and child buses for new devices, add them,
2305 * and enable them, resizing bridge mmio/io resource if necessary
2306 * and possible. The caller must ensure the child devices are already
2307 * removed for resizing to occur.
2309 * Returns the max number of subordinate bus discovered.
2311 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge)
2314 struct pci_bus *bus = bridge->subordinate;
2316 max = pci_scan_child_bus(bus);
2318 pci_assign_unassigned_bridge_resources(bridge);
2320 pci_bus_add_devices(bus);
2326 * pci_rescan_bus - scan a PCI bus for devices.
2327 * @bus: PCI bus to scan
2329 * Scan a PCI bus and child buses for new devices, adds them,
2332 * Returns the max number of subordinate bus discovered.
2334 unsigned int pci_rescan_bus(struct pci_bus *bus)
2338 max = pci_scan_child_bus(bus);
2339 pci_assign_unassigned_bus_resources(bus);
2340 pci_bus_add_devices(bus);
2344 EXPORT_SYMBOL_GPL(pci_rescan_bus);
2347 * pci_rescan_bus(), pci_rescan_bus_bridge_resize() and PCI device removal
2348 * routines should always be executed under this mutex.
2350 static DEFINE_MUTEX(pci_rescan_remove_lock);
2352 void pci_lock_rescan_remove(void)
2354 mutex_lock(&pci_rescan_remove_lock);
2356 EXPORT_SYMBOL_GPL(pci_lock_rescan_remove);
2358 void pci_unlock_rescan_remove(void)
2360 mutex_unlock(&pci_rescan_remove_lock);
2362 EXPORT_SYMBOL_GPL(pci_unlock_rescan_remove);
2364 static int __init pci_sort_bf_cmp(const struct device *d_a,
2365 const struct device *d_b)
2367 const struct pci_dev *a = to_pci_dev(d_a);
2368 const struct pci_dev *b = to_pci_dev(d_b);
2370 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
2371 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
2373 if (a->bus->number < b->bus->number) return -1;
2374 else if (a->bus->number > b->bus->number) return 1;
2376 if (a->devfn < b->devfn) return -1;
2377 else if (a->devfn > b->devfn) return 1;
2382 void __init pci_sort_breadthfirst(void)
2384 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp);