2 * drivers/pci/setup-bus.c
4 * Extruded from code written by
5 * Dave Rusling (david.rusling@reo.mts.dec.com)
6 * David Mosberger (davidm@cs.arizona.edu)
7 * David Miller (davem@redhat.com)
9 * Support routines for initializing a PCI subsystem.
13 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
14 * PCI-PCI bridges cleanup, sorted resource allocation.
15 * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
16 * Converted to allocation in 3 passes, which gives
17 * tighter packing. Prefetchable range support.
20 #include <linux/init.h>
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/pci.h>
24 #include <linux/errno.h>
25 #include <linux/ioport.h>
26 #include <linux/cache.h>
27 #include <linux/slab.h>
28 #include <asm-generic/pci-bridge.h>
31 unsigned int pci_flags;
33 struct pci_dev_resource {
34 struct list_head list;
37 resource_size_t start;
39 resource_size_t add_size;
40 resource_size_t min_align;
44 static void free_list(struct list_head *head)
46 struct pci_dev_resource *dev_res, *tmp;
48 list_for_each_entry_safe(dev_res, tmp, head, list) {
49 list_del(&dev_res->list);
55 * add_to_list() - add a new resource tracker to the list
56 * @head: Head of the list
57 * @dev: device corresponding to which the resource
59 * @res: The resource to be tracked
60 * @add_size: additional size to be optionally added
63 static int add_to_list(struct list_head *head,
64 struct pci_dev *dev, struct resource *res,
65 resource_size_t add_size, resource_size_t min_align)
67 struct pci_dev_resource *tmp;
69 tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
71 pr_warn("add_to_list: kmalloc() failed!\n");
77 tmp->start = res->start;
79 tmp->flags = res->flags;
80 tmp->add_size = add_size;
81 tmp->min_align = min_align;
83 list_add(&tmp->list, head);
88 static void remove_from_list(struct list_head *head,
91 struct pci_dev_resource *dev_res, *tmp;
93 list_for_each_entry_safe(dev_res, tmp, head, list) {
94 if (dev_res->res == res) {
95 list_del(&dev_res->list);
102 static struct pci_dev_resource *res_to_dev_res(struct list_head *head,
103 struct resource *res)
105 struct pci_dev_resource *dev_res;
107 list_for_each_entry(dev_res, head, list) {
108 if (dev_res->res == res) {
109 int idx = res - &dev_res->dev->resource[0];
111 dev_printk(KERN_DEBUG, &dev_res->dev->dev,
112 "res[%d]=%pR res_to_dev_res add_size %llx min_align %llx\n",
114 (unsigned long long)dev_res->add_size,
115 (unsigned long long)dev_res->min_align);
124 static resource_size_t get_res_add_size(struct list_head *head,
125 struct resource *res)
127 struct pci_dev_resource *dev_res;
129 dev_res = res_to_dev_res(head, res);
130 return dev_res ? dev_res->add_size : 0;
133 static resource_size_t get_res_add_align(struct list_head *head,
134 struct resource *res)
136 struct pci_dev_resource *dev_res;
138 dev_res = res_to_dev_res(head, res);
139 return dev_res ? dev_res->min_align : 0;
143 /* Sort resources by alignment */
144 static void pdev_sort_resources(struct pci_dev *dev, struct list_head *head)
148 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
150 struct pci_dev_resource *dev_res, *tmp;
151 resource_size_t r_align;
154 r = &dev->resource[i];
156 if (r->flags & IORESOURCE_PCI_FIXED)
159 if (!(r->flags) || r->parent)
162 r_align = pci_resource_alignment(dev, r);
164 dev_warn(&dev->dev, "BAR %d: %pR has bogus alignment\n",
169 tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
171 panic("pdev_sort_resources(): kmalloc() failed!\n");
175 /* fallback is smallest one or list is empty*/
177 list_for_each_entry(dev_res, head, list) {
178 resource_size_t align;
180 align = pci_resource_alignment(dev_res->dev,
183 if (r_align > align) {
188 /* Insert it just before n*/
189 list_add_tail(&tmp->list, n);
193 static void __dev_sort_resources(struct pci_dev *dev,
194 struct list_head *head)
196 u16 class = dev->class >> 8;
198 /* Don't touch classless devices or host bridges or ioapics. */
199 if (class == PCI_CLASS_NOT_DEFINED || class == PCI_CLASS_BRIDGE_HOST)
202 /* Don't touch ioapic devices already enabled by firmware */
203 if (class == PCI_CLASS_SYSTEM_PIC) {
205 pci_read_config_word(dev, PCI_COMMAND, &command);
206 if (command & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY))
210 pdev_sort_resources(dev, head);
213 static inline void reset_resource(struct resource *res)
221 * reassign_resources_sorted() - satisfy any additional resource requests
223 * @realloc_head : head of the list tracking requests requiring additional
225 * @head : head of the list tracking requests with allocated
228 * Walk through each element of the realloc_head and try to procure
229 * additional resources for the element, provided the element
230 * is in the head list.
232 static void reassign_resources_sorted(struct list_head *realloc_head,
233 struct list_head *head)
235 struct resource *res;
236 struct pci_dev_resource *add_res, *tmp;
237 struct pci_dev_resource *dev_res;
238 resource_size_t add_size, align;
241 list_for_each_entry_safe(add_res, tmp, realloc_head, list) {
242 bool found_match = false;
245 /* skip resource that has been reset */
249 /* skip this resource if not found in head list */
250 list_for_each_entry(dev_res, head, list) {
251 if (dev_res->res == res) {
256 if (!found_match)/* just skip */
259 idx = res - &add_res->dev->resource[0];
260 add_size = add_res->add_size;
261 align = add_res->min_align;
262 if (!resource_size(res)) {
264 res->end = res->start + add_size - 1;
265 if (pci_assign_resource(add_res->dev, idx))
268 res->flags |= add_res->flags &
269 (IORESOURCE_STARTALIGN|IORESOURCE_SIZEALIGN);
270 if (pci_reassign_resource(add_res->dev, idx,
272 dev_printk(KERN_DEBUG, &add_res->dev->dev,
273 "failed to add %llx res[%d]=%pR\n",
274 (unsigned long long)add_size,
278 list_del(&add_res->list);
284 * assign_requested_resources_sorted() - satisfy resource requests
286 * @head : head of the list tracking requests for resources
287 * @fail_head : head of the list tracking requests that could
290 * Satisfy resource requests of each element in the list. Add
291 * requests that could not satisfied to the failed_list.
293 static void assign_requested_resources_sorted(struct list_head *head,
294 struct list_head *fail_head)
296 struct resource *res;
297 struct pci_dev_resource *dev_res;
300 list_for_each_entry(dev_res, head, list) {
302 idx = res - &dev_res->dev->resource[0];
303 if (resource_size(res) &&
304 pci_assign_resource(dev_res->dev, idx)) {
307 * if the failed res is for ROM BAR, and it will
308 * be enabled later, don't add it to the list
310 if (!((idx == PCI_ROM_RESOURCE) &&
311 (!(res->flags & IORESOURCE_ROM_ENABLE))))
312 add_to_list(fail_head,
322 static unsigned long pci_fail_res_type_mask(struct list_head *fail_head)
324 struct pci_dev_resource *fail_res;
325 unsigned long mask = 0;
327 /* check failed type */
328 list_for_each_entry(fail_res, fail_head, list)
329 mask |= fail_res->flags;
332 * one pref failed resource will set IORESOURCE_MEM,
333 * as we can allocate pref in non-pref range.
334 * Will release all assigned non-pref sibling resources
335 * according to that bit.
337 return mask & (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH);
340 static bool pci_need_to_release(unsigned long mask, struct resource *res)
342 if (res->flags & IORESOURCE_IO)
343 return !!(mask & IORESOURCE_IO);
345 /* check pref at first */
346 if (res->flags & IORESOURCE_PREFETCH) {
347 if (mask & IORESOURCE_PREFETCH)
349 /* count pref if its parent is non-pref */
350 else if ((mask & IORESOURCE_MEM) &&
351 !(res->parent->flags & IORESOURCE_PREFETCH))
357 if (res->flags & IORESOURCE_MEM)
358 return !!(mask & IORESOURCE_MEM);
360 return false; /* should not get here */
363 static void __assign_resources_sorted(struct list_head *head,
364 struct list_head *realloc_head,
365 struct list_head *fail_head)
368 * Should not assign requested resources at first.
369 * they could be adjacent, so later reassign can not reallocate
370 * them one by one in parent resource window.
371 * Try to assign requested + add_size at beginning
372 * if could do that, could get out early.
373 * if could not do that, we still try to assign requested at first,
374 * then try to reassign add_size for some resources.
376 * Separate three resource type checking if we need to release
377 * assigned resource after requested + add_size try.
378 * 1. if there is io port assign fail, will release assigned
380 * 2. if there is pref mmio assign fail, release assigned
382 * if assigned pref mmio's parent is non-pref mmio and there
383 * is non-pref mmio assign fail, will release that assigned
385 * 3. if there is non-pref mmio assign fail or pref mmio
386 * assigned fail, will release assigned non-pref mmio.
388 LIST_HEAD(save_head);
389 LIST_HEAD(local_fail_head);
390 struct pci_dev_resource *save_res;
391 struct pci_dev_resource *dev_res, *tmp_res, *dev_res2;
392 unsigned long fail_type;
393 resource_size_t add_align, align;
395 /* Check if optional add_size is there */
396 if (!realloc_head || list_empty(realloc_head))
397 goto requested_and_reassign;
399 /* Save original start, end, flags etc at first */
400 list_for_each_entry(dev_res, head, list) {
401 if (add_to_list(&save_head, dev_res->dev, dev_res->res, 0, 0)) {
402 free_list(&save_head);
403 goto requested_and_reassign;
407 /* Update res in head list with add_size in realloc_head list */
408 list_for_each_entry_safe(dev_res, tmp_res, head, list) {
409 dev_res->res->end += get_res_add_size(realloc_head,
413 * There are two kinds of additional resources in the list:
414 * 1. bridge resource -- IORESOURCE_STARTALIGN
415 * 2. SR-IOV resource -- IORESOURCE_SIZEALIGN
416 * Here just fix the additional alignment for bridge
418 if (!(dev_res->res->flags & IORESOURCE_STARTALIGN))
421 add_align = get_res_add_align(realloc_head, dev_res->res);
424 * The "head" list is sorted by the alignment to make sure
425 * resources with bigger alignment will be assigned first.
426 * After we change the alignment of a dev_res in "head" list,
427 * we need to reorder the list by alignment to make it
430 if (add_align > dev_res->res->start) {
431 dev_res->res->start = add_align;
432 dev_res->res->end = add_align +
433 resource_size(dev_res->res);
435 list_for_each_entry(dev_res2, head, list) {
436 align = pci_resource_alignment(dev_res2->dev,
438 if (add_align > align)
439 list_move_tail(&dev_res->list,
446 /* Try updated head list with add_size added */
447 assign_requested_resources_sorted(head, &local_fail_head);
449 /* all assigned with add_size ? */
450 if (list_empty(&local_fail_head)) {
451 /* Remove head list from realloc_head list */
452 list_for_each_entry(dev_res, head, list)
453 remove_from_list(realloc_head, dev_res->res);
454 free_list(&save_head);
459 /* check failed type */
460 fail_type = pci_fail_res_type_mask(&local_fail_head);
461 /* remove not need to be released assigned res from head list etc */
462 list_for_each_entry_safe(dev_res, tmp_res, head, list)
463 if (dev_res->res->parent &&
464 !pci_need_to_release(fail_type, dev_res->res)) {
465 /* remove it from realloc_head list */
466 remove_from_list(realloc_head, dev_res->res);
467 remove_from_list(&save_head, dev_res->res);
468 list_del(&dev_res->list);
472 free_list(&local_fail_head);
473 /* Release assigned resource */
474 list_for_each_entry(dev_res, head, list)
475 if (dev_res->res->parent)
476 release_resource(dev_res->res);
477 /* Restore start/end/flags from saved list */
478 list_for_each_entry(save_res, &save_head, list) {
479 struct resource *res = save_res->res;
481 res->start = save_res->start;
482 res->end = save_res->end;
483 res->flags = save_res->flags;
485 free_list(&save_head);
487 requested_and_reassign:
488 /* Satisfy the must-have resource requests */
489 assign_requested_resources_sorted(head, fail_head);
491 /* Try to satisfy any additional optional resource
494 reassign_resources_sorted(realloc_head, head);
498 static void pdev_assign_resources_sorted(struct pci_dev *dev,
499 struct list_head *add_head,
500 struct list_head *fail_head)
504 __dev_sort_resources(dev, &head);
505 __assign_resources_sorted(&head, add_head, fail_head);
509 static void pbus_assign_resources_sorted(const struct pci_bus *bus,
510 struct list_head *realloc_head,
511 struct list_head *fail_head)
516 list_for_each_entry(dev, &bus->devices, bus_list)
517 __dev_sort_resources(dev, &head);
519 __assign_resources_sorted(&head, realloc_head, fail_head);
522 void pci_setup_cardbus(struct pci_bus *bus)
524 struct pci_dev *bridge = bus->self;
525 struct resource *res;
526 struct pci_bus_region region;
528 dev_info(&bridge->dev, "CardBus bridge to %pR\n",
531 res = bus->resource[0];
532 pcibios_resource_to_bus(bridge->bus, ®ion, res);
533 if (res->flags & IORESOURCE_IO) {
535 * The IO resource is allocated a range twice as large as it
536 * would normally need. This allows us to set both IO regs.
538 dev_info(&bridge->dev, " bridge window %pR\n", res);
539 pci_write_config_dword(bridge, PCI_CB_IO_BASE_0,
541 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0,
545 res = bus->resource[1];
546 pcibios_resource_to_bus(bridge->bus, ®ion, res);
547 if (res->flags & IORESOURCE_IO) {
548 dev_info(&bridge->dev, " bridge window %pR\n", res);
549 pci_write_config_dword(bridge, PCI_CB_IO_BASE_1,
551 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1,
555 res = bus->resource[2];
556 pcibios_resource_to_bus(bridge->bus, ®ion, res);
557 if (res->flags & IORESOURCE_MEM) {
558 dev_info(&bridge->dev, " bridge window %pR\n", res);
559 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0,
561 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0,
565 res = bus->resource[3];
566 pcibios_resource_to_bus(bridge->bus, ®ion, res);
567 if (res->flags & IORESOURCE_MEM) {
568 dev_info(&bridge->dev, " bridge window %pR\n", res);
569 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1,
571 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1,
575 EXPORT_SYMBOL(pci_setup_cardbus);
577 /* Initialize bridges with base/limit values we have collected.
578 PCI-to-PCI Bridge Architecture Specification rev. 1.1 (1998)
579 requires that if there is no I/O ports or memory behind the
580 bridge, corresponding range must be turned off by writing base
581 value greater than limit to the bridge's base/limit registers.
583 Note: care must be taken when updating I/O base/limit registers
584 of bridges which support 32-bit I/O. This update requires two
585 config space writes, so it's quite possible that an I/O window of
586 the bridge will have some undesirable address (e.g. 0) after the
587 first write. Ditto 64-bit prefetchable MMIO. */
588 static void pci_setup_bridge_io(struct pci_dev *bridge)
590 struct resource *res;
591 struct pci_bus_region region;
592 unsigned long io_mask;
593 u8 io_base_lo, io_limit_lo;
597 io_mask = PCI_IO_RANGE_MASK;
598 if (bridge->io_window_1k)
599 io_mask = PCI_IO_1K_RANGE_MASK;
601 /* Set up the top and bottom of the PCI I/O segment for this bus. */
602 res = &bridge->resource[PCI_BRIDGE_RESOURCES + 0];
603 pcibios_resource_to_bus(bridge->bus, ®ion, res);
604 if (res->flags & IORESOURCE_IO) {
605 pci_read_config_word(bridge, PCI_IO_BASE, &l);
606 io_base_lo = (region.start >> 8) & io_mask;
607 io_limit_lo = (region.end >> 8) & io_mask;
608 l = ((u16) io_limit_lo << 8) | io_base_lo;
609 /* Set up upper 16 bits of I/O base/limit. */
610 io_upper16 = (region.end & 0xffff0000) | (region.start >> 16);
611 dev_info(&bridge->dev, " bridge window %pR\n", res);
613 /* Clear upper 16 bits of I/O base/limit. */
617 /* Temporarily disable the I/O range before updating PCI_IO_BASE. */
618 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff);
619 /* Update lower 16 bits of I/O base/limit. */
620 pci_write_config_word(bridge, PCI_IO_BASE, l);
621 /* Update upper 16 bits of I/O base/limit. */
622 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16);
625 static void pci_setup_bridge_mmio(struct pci_dev *bridge)
627 struct resource *res;
628 struct pci_bus_region region;
631 /* Set up the top and bottom of the PCI Memory segment for this bus. */
632 res = &bridge->resource[PCI_BRIDGE_RESOURCES + 1];
633 pcibios_resource_to_bus(bridge->bus, ®ion, res);
634 if (res->flags & IORESOURCE_MEM) {
635 l = (region.start >> 16) & 0xfff0;
636 l |= region.end & 0xfff00000;
637 dev_info(&bridge->dev, " bridge window %pR\n", res);
641 pci_write_config_dword(bridge, PCI_MEMORY_BASE, l);
644 static void pci_setup_bridge_mmio_pref(struct pci_dev *bridge)
646 struct resource *res;
647 struct pci_bus_region region;
650 /* Clear out the upper 32 bits of PREF limit.
651 If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily
652 disables PREF range, which is ok. */
653 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0);
655 /* Set up PREF base/limit. */
657 res = &bridge->resource[PCI_BRIDGE_RESOURCES + 2];
658 pcibios_resource_to_bus(bridge->bus, ®ion, res);
659 if (res->flags & IORESOURCE_PREFETCH) {
660 l = (region.start >> 16) & 0xfff0;
661 l |= region.end & 0xfff00000;
662 if (res->flags & IORESOURCE_MEM_64) {
663 bu = upper_32_bits(region.start);
664 lu = upper_32_bits(region.end);
666 dev_info(&bridge->dev, " bridge window %pR\n", res);
670 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l);
672 /* Set the upper 32 bits of PREF base & limit. */
673 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu);
674 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu);
677 static void __pci_setup_bridge(struct pci_bus *bus, unsigned long type)
679 struct pci_dev *bridge = bus->self;
681 dev_info(&bridge->dev, "PCI bridge to %pR\n",
684 if (type & IORESOURCE_IO)
685 pci_setup_bridge_io(bridge);
687 if (type & IORESOURCE_MEM)
688 pci_setup_bridge_mmio(bridge);
690 if (type & IORESOURCE_PREFETCH)
691 pci_setup_bridge_mmio_pref(bridge);
693 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl);
696 void pci_setup_bridge(struct pci_bus *bus)
698 unsigned long type = IORESOURCE_IO | IORESOURCE_MEM |
701 __pci_setup_bridge(bus, type);
705 int pci_claim_bridge_resource(struct pci_dev *bridge, int i)
707 if (i < PCI_BRIDGE_RESOURCES || i > PCI_BRIDGE_RESOURCE_END)
710 if (pci_claim_resource(bridge, i) == 0)
711 return 0; /* claimed the window */
713 if ((bridge->class >> 8) != PCI_CLASS_BRIDGE_PCI)
716 if (!pci_bus_clip_resource(bridge, i))
717 return -EINVAL; /* clipping didn't change anything */
719 switch (i - PCI_BRIDGE_RESOURCES) {
721 pci_setup_bridge_io(bridge);
724 pci_setup_bridge_mmio(bridge);
727 pci_setup_bridge_mmio_pref(bridge);
733 if (pci_claim_resource(bridge, i) == 0)
734 return 0; /* claimed a smaller window */
739 /* Check whether the bridge supports optional I/O and
740 prefetchable memory ranges. If not, the respective
741 base/limit registers must be read-only and read as 0. */
742 static void pci_bridge_check_ranges(struct pci_bus *bus)
746 struct pci_dev *bridge = bus->self;
747 struct resource *b_res;
749 b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
750 b_res[1].flags |= IORESOURCE_MEM;
752 pci_read_config_word(bridge, PCI_IO_BASE, &io);
754 pci_write_config_word(bridge, PCI_IO_BASE, 0xe0f0);
755 pci_read_config_word(bridge, PCI_IO_BASE, &io);
756 pci_write_config_word(bridge, PCI_IO_BASE, 0x0);
759 b_res[0].flags |= IORESOURCE_IO;
761 /* DECchip 21050 pass 2 errata: the bridge may miss an address
762 disconnect boundary by one PCI data phase.
763 Workaround: do not use prefetching on this device. */
764 if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001)
767 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
769 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE,
771 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
772 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0);
775 b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
776 if ((pmem & PCI_PREF_RANGE_TYPE_MASK) ==
777 PCI_PREF_RANGE_TYPE_64) {
778 b_res[2].flags |= IORESOURCE_MEM_64;
779 b_res[2].flags |= PCI_PREF_RANGE_TYPE_64;
783 /* double check if bridge does support 64 bit pref */
784 if (b_res[2].flags & IORESOURCE_MEM_64) {
785 u32 mem_base_hi, tmp;
786 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32,
788 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
790 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp);
792 b_res[2].flags &= ~IORESOURCE_MEM_64;
793 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
798 /* Helper function for sizing routines: find first available
799 bus resource of a given type. Note: we intentionally skip
800 the bus resources which have already been assigned (that is,
801 have non-NULL parent resource). */
802 static struct resource *find_free_bus_resource(struct pci_bus *bus,
803 unsigned long type_mask, unsigned long type)
808 pci_bus_for_each_resource(bus, r, i) {
809 if (r == &ioport_resource || r == &iomem_resource)
811 if (r && (r->flags & type_mask) == type && !r->parent)
817 static resource_size_t calculate_iosize(resource_size_t size,
818 resource_size_t min_size,
819 resource_size_t size1,
820 resource_size_t old_size,
821 resource_size_t align)
827 /* To be fixed in 2.5: we should have sort of HAVE_ISA
828 flag in the struct pci_bus. */
829 #if defined(CONFIG_ISA) || defined(CONFIG_EISA)
830 size = (size & 0xff) + ((size & ~0xffUL) << 2);
832 size = ALIGN(size + size1, align);
838 static resource_size_t calculate_memsize(resource_size_t size,
839 resource_size_t min_size,
840 resource_size_t size1,
841 resource_size_t old_size,
842 resource_size_t align)
850 size = ALIGN(size + size1, align);
854 resource_size_t __weak pcibios_window_alignment(struct pci_bus *bus,
860 #define PCI_P2P_DEFAULT_MEM_ALIGN 0x100000 /* 1MiB */
861 #define PCI_P2P_DEFAULT_IO_ALIGN 0x1000 /* 4KiB */
862 #define PCI_P2P_DEFAULT_IO_ALIGN_1K 0x400 /* 1KiB */
864 static resource_size_t window_alignment(struct pci_bus *bus,
867 resource_size_t align = 1, arch_align;
869 if (type & IORESOURCE_MEM)
870 align = PCI_P2P_DEFAULT_MEM_ALIGN;
871 else if (type & IORESOURCE_IO) {
873 * Per spec, I/O windows are 4K-aligned, but some
874 * bridges have an extension to support 1K alignment.
876 if (bus->self->io_window_1k)
877 align = PCI_P2P_DEFAULT_IO_ALIGN_1K;
879 align = PCI_P2P_DEFAULT_IO_ALIGN;
882 arch_align = pcibios_window_alignment(bus, type);
883 return max(align, arch_align);
887 * pbus_size_io() - size the io window of a given bus
890 * @min_size : the minimum io window that must to be allocated
891 * @add_size : additional optional io window
892 * @realloc_head : track the additional io window on this list
894 * Sizing the IO windows of the PCI-PCI bridge is trivial,
895 * since these windows have 1K or 4K granularity and the IO ranges
896 * of non-bridge PCI devices are limited to 256 bytes.
897 * We must be careful with the ISA aliasing though.
899 static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size,
900 resource_size_t add_size, struct list_head *realloc_head)
903 struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO,
905 resource_size_t size = 0, size0 = 0, size1 = 0;
906 resource_size_t children_add_size = 0;
907 resource_size_t min_align, align;
912 min_align = window_alignment(bus, IORESOURCE_IO);
913 list_for_each_entry(dev, &bus->devices, bus_list) {
916 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
917 struct resource *r = &dev->resource[i];
918 unsigned long r_size;
920 if (r->parent || !(r->flags & IORESOURCE_IO))
922 r_size = resource_size(r);
925 /* Might be re-aligned for ISA */
930 align = pci_resource_alignment(dev, r);
931 if (align > min_align)
935 children_add_size += get_res_add_size(realloc_head, r);
939 size0 = calculate_iosize(size, min_size, size1,
940 resource_size(b_res), min_align);
941 if (children_add_size > add_size)
942 add_size = children_add_size;
943 size1 = (!realloc_head || (realloc_head && !add_size)) ? size0 :
944 calculate_iosize(size, min_size, add_size + size1,
945 resource_size(b_res), min_align);
946 if (!size0 && !size1) {
947 if (b_res->start || b_res->end)
948 dev_info(&bus->self->dev, "disabling bridge window %pR to %pR (unused)\n",
949 b_res, &bus->busn_res);
954 b_res->start = min_align;
955 b_res->end = b_res->start + size0 - 1;
956 b_res->flags |= IORESOURCE_STARTALIGN;
957 if (size1 > size0 && realloc_head) {
958 add_to_list(realloc_head, bus->self, b_res, size1-size0,
960 dev_printk(KERN_DEBUG, &bus->self->dev, "bridge window %pR to %pR add_size %llx\n",
961 b_res, &bus->busn_res,
962 (unsigned long long)size1-size0);
966 static inline resource_size_t calculate_mem_align(resource_size_t *aligns,
969 resource_size_t align = 0;
970 resource_size_t min_align = 0;
973 for (order = 0; order <= max_order; order++) {
974 resource_size_t align1 = 1;
976 align1 <<= (order + 20);
980 else if (ALIGN(align + min_align, min_align) < align1)
981 min_align = align1 >> 1;
982 align += aligns[order];
989 * pbus_size_mem() - size the memory window of a given bus
992 * @mask: mask the resource flag, then compare it with type
993 * @type: the type of free resource from bridge
994 * @type2: second match type
995 * @type3: third match type
996 * @min_size : the minimum memory window that must to be allocated
997 * @add_size : additional optional memory window
998 * @realloc_head : track the additional memory window on this list
1000 * Calculate the size of the bus and minimal alignment which
1001 * guarantees that all child resources fit in this size.
1003 * Returns -ENOSPC if there's no available bus resource of the desired type.
1004 * Otherwise, sets the bus resource start/end to indicate the required
1005 * size, adds things to realloc_head (if supplied), and returns 0.
1007 static int pbus_size_mem(struct pci_bus *bus, unsigned long mask,
1008 unsigned long type, unsigned long type2,
1009 unsigned long type3,
1010 resource_size_t min_size, resource_size_t add_size,
1011 struct list_head *realloc_head)
1013 struct pci_dev *dev;
1014 resource_size_t min_align, align, size, size0, size1;
1015 resource_size_t aligns[18]; /* Alignments from 1Mb to 128Gb */
1016 int order, max_order;
1017 struct resource *b_res = find_free_bus_resource(bus,
1018 mask | IORESOURCE_PREFETCH, type);
1019 resource_size_t children_add_size = 0;
1020 resource_size_t children_add_align = 0;
1021 resource_size_t add_align = 0;
1026 memset(aligns, 0, sizeof(aligns));
1030 list_for_each_entry(dev, &bus->devices, bus_list) {
1033 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1034 struct resource *r = &dev->resource[i];
1035 resource_size_t r_size;
1037 if (r->parent || ((r->flags & mask) != type &&
1038 (r->flags & mask) != type2 &&
1039 (r->flags & mask) != type3))
1041 r_size = resource_size(r);
1042 #ifdef CONFIG_PCI_IOV
1043 /* put SRIOV requested res to the optional list */
1044 if (realloc_head && i >= PCI_IOV_RESOURCES &&
1045 i <= PCI_IOV_RESOURCE_END) {
1046 add_align = max(pci_resource_alignment(dev, r), add_align);
1047 r->end = r->start - 1;
1048 add_to_list(realloc_head, dev, r, r_size, 0/* don't care */);
1049 children_add_size += r_size;
1054 * aligns[0] is for 1MB (since bridge memory
1055 * windows are always at least 1MB aligned), so
1056 * keep "order" from being negative for smaller
1059 align = pci_resource_alignment(dev, r);
1060 order = __ffs(align) - 20;
1063 if (order >= ARRAY_SIZE(aligns)) {
1064 dev_warn(&dev->dev, "disabling BAR %d: %pR (bad alignment %#llx)\n",
1065 i, r, (unsigned long long) align);
1070 /* Exclude ranges with size > align from
1071 calculation of the alignment. */
1072 if (r_size == align)
1073 aligns[order] += align;
1074 if (order > max_order)
1078 children_add_size += get_res_add_size(realloc_head, r);
1079 children_add_align = get_res_add_align(realloc_head, r);
1080 add_align = max(add_align, children_add_align);
1085 min_align = calculate_mem_align(aligns, max_order);
1086 min_align = max(min_align, window_alignment(bus, b_res->flags));
1087 size0 = calculate_memsize(size, min_size, 0, resource_size(b_res), min_align);
1088 add_align = max(min_align, add_align);
1089 if (children_add_size > add_size)
1090 add_size = children_add_size;
1091 size1 = (!realloc_head || (realloc_head && !add_size)) ? size0 :
1092 calculate_memsize(size, min_size, add_size,
1093 resource_size(b_res), add_align);
1094 if (!size0 && !size1) {
1095 if (b_res->start || b_res->end)
1096 dev_info(&bus->self->dev, "disabling bridge window %pR to %pR (unused)\n",
1097 b_res, &bus->busn_res);
1101 b_res->start = min_align;
1102 b_res->end = size0 + min_align - 1;
1103 b_res->flags |= IORESOURCE_STARTALIGN;
1104 if (size1 > size0 && realloc_head) {
1105 add_to_list(realloc_head, bus->self, b_res, size1-size0, add_align);
1106 dev_printk(KERN_DEBUG, &bus->self->dev, "bridge window %pR to %pR add_size %llx add_align %llx\n",
1107 b_res, &bus->busn_res,
1108 (unsigned long long) (size1 - size0),
1109 (unsigned long long) add_align);
1114 unsigned long pci_cardbus_resource_alignment(struct resource *res)
1116 if (res->flags & IORESOURCE_IO)
1117 return pci_cardbus_io_size;
1118 if (res->flags & IORESOURCE_MEM)
1119 return pci_cardbus_mem_size;
1123 static void pci_bus_size_cardbus(struct pci_bus *bus,
1124 struct list_head *realloc_head)
1126 struct pci_dev *bridge = bus->self;
1127 struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
1128 resource_size_t b_res_3_size = pci_cardbus_mem_size * 2;
1131 if (b_res[0].parent)
1132 goto handle_b_res_1;
1134 * Reserve some resources for CardBus. We reserve
1135 * a fixed amount of bus space for CardBus bridges.
1137 b_res[0].start = pci_cardbus_io_size;
1138 b_res[0].end = b_res[0].start + pci_cardbus_io_size - 1;
1139 b_res[0].flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN;
1141 b_res[0].end -= pci_cardbus_io_size;
1142 add_to_list(realloc_head, bridge, b_res, pci_cardbus_io_size,
1143 pci_cardbus_io_size);
1147 if (b_res[1].parent)
1148 goto handle_b_res_2;
1149 b_res[1].start = pci_cardbus_io_size;
1150 b_res[1].end = b_res[1].start + pci_cardbus_io_size - 1;
1151 b_res[1].flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN;
1153 b_res[1].end -= pci_cardbus_io_size;
1154 add_to_list(realloc_head, bridge, b_res+1, pci_cardbus_io_size,
1155 pci_cardbus_io_size);
1159 /* MEM1 must not be pref mmio */
1160 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
1161 if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM1) {
1162 ctrl &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM1;
1163 pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl);
1164 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
1168 * Check whether prefetchable memory is supported
1171 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
1172 if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) {
1173 ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
1174 pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl);
1175 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
1178 if (b_res[2].parent)
1179 goto handle_b_res_3;
1181 * If we have prefetchable memory support, allocate
1182 * two regions. Otherwise, allocate one region of
1185 if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) {
1186 b_res[2].start = pci_cardbus_mem_size;
1187 b_res[2].end = b_res[2].start + pci_cardbus_mem_size - 1;
1188 b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH |
1189 IORESOURCE_STARTALIGN;
1191 b_res[2].end -= pci_cardbus_mem_size;
1192 add_to_list(realloc_head, bridge, b_res+2,
1193 pci_cardbus_mem_size, pci_cardbus_mem_size);
1196 /* reduce that to half */
1197 b_res_3_size = pci_cardbus_mem_size;
1201 if (b_res[3].parent)
1203 b_res[3].start = pci_cardbus_mem_size;
1204 b_res[3].end = b_res[3].start + b_res_3_size - 1;
1205 b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_STARTALIGN;
1207 b_res[3].end -= b_res_3_size;
1208 add_to_list(realloc_head, bridge, b_res+3, b_res_3_size,
1209 pci_cardbus_mem_size);
1216 void __pci_bus_size_bridges(struct pci_bus *bus, struct list_head *realloc_head)
1218 struct pci_dev *dev;
1219 unsigned long mask, prefmask, type2 = 0, type3 = 0;
1220 resource_size_t additional_mem_size = 0, additional_io_size = 0;
1221 struct resource *b_res;
1224 list_for_each_entry(dev, &bus->devices, bus_list) {
1225 struct pci_bus *b = dev->subordinate;
1229 switch (dev->class >> 8) {
1230 case PCI_CLASS_BRIDGE_CARDBUS:
1231 pci_bus_size_cardbus(b, realloc_head);
1234 case PCI_CLASS_BRIDGE_PCI:
1236 __pci_bus_size_bridges(b, realloc_head);
1242 if (pci_is_root_bus(bus))
1245 switch (bus->self->class >> 8) {
1246 case PCI_CLASS_BRIDGE_CARDBUS:
1247 /* don't size cardbuses yet. */
1250 case PCI_CLASS_BRIDGE_PCI:
1251 pci_bridge_check_ranges(bus);
1252 if (bus->self->is_hotplug_bridge) {
1253 additional_io_size = pci_hotplug_io_size;
1254 additional_mem_size = pci_hotplug_mem_size;
1258 pbus_size_io(bus, realloc_head ? 0 : additional_io_size,
1259 additional_io_size, realloc_head);
1262 * If there's a 64-bit prefetchable MMIO window, compute
1263 * the size required to put all 64-bit prefetchable
1266 b_res = &bus->self->resource[PCI_BRIDGE_RESOURCES];
1267 mask = IORESOURCE_MEM;
1268 prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH;
1269 if (b_res[2].flags & IORESOURCE_MEM_64) {
1270 prefmask |= IORESOURCE_MEM_64;
1271 ret = pbus_size_mem(bus, prefmask, prefmask,
1273 realloc_head ? 0 : additional_mem_size,
1274 additional_mem_size, realloc_head);
1277 * If successful, all non-prefetchable resources
1278 * and any 32-bit prefetchable resources will go in
1279 * the non-prefetchable window.
1283 type2 = prefmask & ~IORESOURCE_MEM_64;
1284 type3 = prefmask & ~IORESOURCE_PREFETCH;
1289 * If there is no 64-bit prefetchable window, compute the
1290 * size required to put all prefetchable resources in the
1291 * 32-bit prefetchable window (if there is one).
1294 prefmask &= ~IORESOURCE_MEM_64;
1295 ret = pbus_size_mem(bus, prefmask, prefmask,
1297 realloc_head ? 0 : additional_mem_size,
1298 additional_mem_size, realloc_head);
1301 * If successful, only non-prefetchable resources
1302 * will go in the non-prefetchable window.
1307 additional_mem_size += additional_mem_size;
1309 type2 = type3 = IORESOURCE_MEM;
1313 * Compute the size required to put everything else in the
1314 * non-prefetchable window. This includes:
1316 * - all non-prefetchable resources
1317 * - 32-bit prefetchable resources if there's a 64-bit
1318 * prefetchable window or no prefetchable window at all
1319 * - 64-bit prefetchable resources if there's no
1320 * prefetchable window at all
1322 * Note that the strategy in __pci_assign_resource() must
1323 * match that used here. Specifically, we cannot put a
1324 * 32-bit prefetchable resource in a 64-bit prefetchable
1327 pbus_size_mem(bus, mask, IORESOURCE_MEM, type2, type3,
1328 realloc_head ? 0 : additional_mem_size,
1329 additional_mem_size, realloc_head);
1334 void pci_bus_size_bridges(struct pci_bus *bus)
1336 __pci_bus_size_bridges(bus, NULL);
1338 EXPORT_SYMBOL(pci_bus_size_bridges);
1340 void __pci_bus_assign_resources(const struct pci_bus *bus,
1341 struct list_head *realloc_head,
1342 struct list_head *fail_head)
1345 struct pci_dev *dev;
1347 pbus_assign_resources_sorted(bus, realloc_head, fail_head);
1349 list_for_each_entry(dev, &bus->devices, bus_list) {
1350 b = dev->subordinate;
1354 __pci_bus_assign_resources(b, realloc_head, fail_head);
1356 switch (dev->class >> 8) {
1357 case PCI_CLASS_BRIDGE_PCI:
1358 if (!pci_is_enabled(dev))
1359 pci_setup_bridge(b);
1362 case PCI_CLASS_BRIDGE_CARDBUS:
1363 pci_setup_cardbus(b);
1367 dev_info(&dev->dev, "not setting up bridge for bus %04x:%02x\n",
1368 pci_domain_nr(b), b->number);
1374 void pci_bus_assign_resources(const struct pci_bus *bus)
1376 __pci_bus_assign_resources(bus, NULL, NULL);
1378 EXPORT_SYMBOL(pci_bus_assign_resources);
1380 static void __pci_bridge_assign_resources(const struct pci_dev *bridge,
1381 struct list_head *add_head,
1382 struct list_head *fail_head)
1386 pdev_assign_resources_sorted((struct pci_dev *)bridge,
1387 add_head, fail_head);
1389 b = bridge->subordinate;
1393 __pci_bus_assign_resources(b, add_head, fail_head);
1395 switch (bridge->class >> 8) {
1396 case PCI_CLASS_BRIDGE_PCI:
1397 pci_setup_bridge(b);
1400 case PCI_CLASS_BRIDGE_CARDBUS:
1401 pci_setup_cardbus(b);
1405 dev_info(&bridge->dev, "not setting up bridge for bus %04x:%02x\n",
1406 pci_domain_nr(b), b->number);
1410 static void pci_bridge_release_resources(struct pci_bus *bus,
1413 struct pci_dev *dev = bus->self;
1415 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
1416 IORESOURCE_PREFETCH | IORESOURCE_MEM_64;
1417 unsigned old_flags = 0;
1418 struct resource *b_res;
1421 b_res = &dev->resource[PCI_BRIDGE_RESOURCES];
1424 * 1. if there is io port assign fail, will release bridge
1426 * 2. if there is non pref mmio assign fail, release bridge
1428 * 3. if there is 64bit pref mmio assign fail, and bridge pref
1429 * is 64bit, release bridge pref mmio.
1430 * 4. if there is pref mmio assign fail, and bridge pref is
1431 * 32bit mmio, release bridge pref mmio
1432 * 5. if there is pref mmio assign fail, and bridge pref is not
1433 * assigned, release bridge nonpref mmio.
1435 if (type & IORESOURCE_IO)
1437 else if (!(type & IORESOURCE_PREFETCH))
1439 else if ((type & IORESOURCE_MEM_64) &&
1440 (b_res[2].flags & IORESOURCE_MEM_64))
1442 else if (!(b_res[2].flags & IORESOURCE_MEM_64) &&
1443 (b_res[2].flags & IORESOURCE_PREFETCH))
1454 * if there are children under that, we should release them
1457 release_child_resources(r);
1458 if (!release_resource(r)) {
1459 type = old_flags = r->flags & type_mask;
1460 dev_printk(KERN_DEBUG, &dev->dev, "resource %d %pR released\n",
1461 PCI_BRIDGE_RESOURCES + idx, r);
1462 /* keep the old size */
1463 r->end = resource_size(r) - 1;
1467 /* avoiding touch the one without PREF */
1468 if (type & IORESOURCE_PREFETCH)
1469 type = IORESOURCE_PREFETCH;
1470 __pci_setup_bridge(bus, type);
1471 /* for next child res under same bridge */
1472 r->flags = old_flags;
1481 * try to release pci bridge resources that is from leaf bridge,
1482 * so we can allocate big new one later
1484 static void pci_bus_release_bridge_resources(struct pci_bus *bus,
1486 enum release_type rel_type)
1488 struct pci_dev *dev;
1489 bool is_leaf_bridge = true;
1491 list_for_each_entry(dev, &bus->devices, bus_list) {
1492 struct pci_bus *b = dev->subordinate;
1496 is_leaf_bridge = false;
1498 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
1501 if (rel_type == whole_subtree)
1502 pci_bus_release_bridge_resources(b, type,
1506 if (pci_is_root_bus(bus))
1509 if ((bus->self->class >> 8) != PCI_CLASS_BRIDGE_PCI)
1512 if ((rel_type == whole_subtree) || is_leaf_bridge)
1513 pci_bridge_release_resources(bus, type);
1516 static void pci_bus_dump_res(struct pci_bus *bus)
1518 struct resource *res;
1521 pci_bus_for_each_resource(bus, res, i) {
1522 if (!res || !res->end || !res->flags)
1525 dev_printk(KERN_DEBUG, &bus->dev, "resource %d %pR\n", i, res);
1529 static void pci_bus_dump_resources(struct pci_bus *bus)
1532 struct pci_dev *dev;
1535 pci_bus_dump_res(bus);
1537 list_for_each_entry(dev, &bus->devices, bus_list) {
1538 b = dev->subordinate;
1542 pci_bus_dump_resources(b);
1546 static int pci_bus_get_depth(struct pci_bus *bus)
1549 struct pci_bus *child_bus;
1551 list_for_each_entry(child_bus, &bus->children, node) {
1554 ret = pci_bus_get_depth(child_bus);
1555 if (ret + 1 > depth)
1563 * -1: undefined, will auto detect later
1564 * 0: disabled by user
1565 * 1: disabled by auto detect
1566 * 2: enabled by user
1567 * 3: enabled by auto detect
1577 static enum enable_type pci_realloc_enable = undefined;
1578 void __init pci_realloc_get_opt(char *str)
1580 if (!strncmp(str, "off", 3))
1581 pci_realloc_enable = user_disabled;
1582 else if (!strncmp(str, "on", 2))
1583 pci_realloc_enable = user_enabled;
1585 static bool pci_realloc_enabled(enum enable_type enable)
1587 return enable >= user_enabled;
1590 #if defined(CONFIG_PCI_IOV) && defined(CONFIG_PCI_REALLOC_ENABLE_AUTO)
1591 static int iov_resources_unassigned(struct pci_dev *dev, void *data)
1594 bool *unassigned = data;
1596 for (i = PCI_IOV_RESOURCES; i <= PCI_IOV_RESOURCE_END; i++) {
1597 struct resource *r = &dev->resource[i];
1598 struct pci_bus_region region;
1600 /* Not assigned or rejected by kernel? */
1604 pcibios_resource_to_bus(dev->bus, ®ion, r);
1605 if (!region.start) {
1607 return 1; /* return early from pci_walk_bus() */
1614 static enum enable_type pci_realloc_detect(struct pci_bus *bus,
1615 enum enable_type enable_local)
1617 bool unassigned = false;
1619 if (enable_local != undefined)
1620 return enable_local;
1622 pci_walk_bus(bus, iov_resources_unassigned, &unassigned);
1624 return auto_enabled;
1626 return enable_local;
1629 static enum enable_type pci_realloc_detect(struct pci_bus *bus,
1630 enum enable_type enable_local)
1632 return enable_local;
1637 * first try will not touch pci bridge res
1638 * second and later try will clear small leaf bridge res
1639 * will stop till to the max depth if can not find good one
1641 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus)
1643 LIST_HEAD(realloc_head); /* list of resources that
1644 want additional resources */
1645 struct list_head *add_list = NULL;
1646 int tried_times = 0;
1647 enum release_type rel_type = leaf_only;
1648 LIST_HEAD(fail_head);
1649 struct pci_dev_resource *fail_res;
1650 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
1651 IORESOURCE_PREFETCH | IORESOURCE_MEM_64;
1652 int pci_try_num = 1;
1653 enum enable_type enable_local;
1655 /* don't realloc if asked to do so */
1656 enable_local = pci_realloc_detect(bus, pci_realloc_enable);
1657 if (pci_realloc_enabled(enable_local)) {
1658 int max_depth = pci_bus_get_depth(bus);
1660 pci_try_num = max_depth + 1;
1661 dev_printk(KERN_DEBUG, &bus->dev,
1662 "max bus depth: %d pci_try_num: %d\n",
1663 max_depth, pci_try_num);
1668 * last try will use add_list, otherwise will try good to have as
1669 * must have, so can realloc parent bridge resource
1671 if (tried_times + 1 == pci_try_num)
1672 add_list = &realloc_head;
1673 /* Depth first, calculate sizes and alignments of all
1674 subordinate buses. */
1675 __pci_bus_size_bridges(bus, add_list);
1677 /* Depth last, allocate resources and update the hardware. */
1678 __pci_bus_assign_resources(bus, add_list, &fail_head);
1680 BUG_ON(!list_empty(add_list));
1683 /* any device complain? */
1684 if (list_empty(&fail_head))
1687 if (tried_times >= pci_try_num) {
1688 if (enable_local == undefined)
1689 dev_info(&bus->dev, "Some PCI device resources are unassigned, try booting with pci=realloc\n");
1690 else if (enable_local == auto_enabled)
1691 dev_info(&bus->dev, "Automatically enabled pci realloc, if you have problem, try booting with pci=realloc=off\n");
1693 free_list(&fail_head);
1697 dev_printk(KERN_DEBUG, &bus->dev,
1698 "No. %d try to assign unassigned res\n", tried_times + 1);
1700 /* third times and later will not check if it is leaf */
1701 if ((tried_times + 1) > 2)
1702 rel_type = whole_subtree;
1705 * Try to release leaf bridge's resources that doesn't fit resource of
1706 * child device under that bridge
1708 list_for_each_entry(fail_res, &fail_head, list)
1709 pci_bus_release_bridge_resources(fail_res->dev->bus,
1710 fail_res->flags & type_mask,
1713 /* restore size and flags */
1714 list_for_each_entry(fail_res, &fail_head, list) {
1715 struct resource *res = fail_res->res;
1717 res->start = fail_res->start;
1718 res->end = fail_res->end;
1719 res->flags = fail_res->flags;
1720 if (fail_res->dev->subordinate)
1723 free_list(&fail_head);
1728 /* dump the resource on buses */
1729 pci_bus_dump_resources(bus);
1732 void __init pci_assign_unassigned_resources(void)
1734 struct pci_bus *root_bus;
1736 list_for_each_entry(root_bus, &pci_root_buses, node)
1737 pci_assign_unassigned_root_bus_resources(root_bus);
1740 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge)
1742 struct pci_bus *parent = bridge->subordinate;
1743 LIST_HEAD(add_list); /* list of resources that
1744 want additional resources */
1745 int tried_times = 0;
1746 LIST_HEAD(fail_head);
1747 struct pci_dev_resource *fail_res;
1749 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
1750 IORESOURCE_PREFETCH | IORESOURCE_MEM_64;
1753 __pci_bus_size_bridges(parent, &add_list);
1754 __pci_bridge_assign_resources(bridge, &add_list, &fail_head);
1755 BUG_ON(!list_empty(&add_list));
1758 if (list_empty(&fail_head))
1761 if (tried_times >= 2) {
1762 /* still fail, don't need to try more */
1763 free_list(&fail_head);
1767 printk(KERN_DEBUG "PCI: No. %d try to assign unassigned res\n",
1771 * Try to release leaf bridge's resources that doesn't fit resource of
1772 * child device under that bridge
1774 list_for_each_entry(fail_res, &fail_head, list)
1775 pci_bus_release_bridge_resources(fail_res->dev->bus,
1776 fail_res->flags & type_mask,
1779 /* restore size and flags */
1780 list_for_each_entry(fail_res, &fail_head, list) {
1781 struct resource *res = fail_res->res;
1783 res->start = fail_res->start;
1784 res->end = fail_res->end;
1785 res->flags = fail_res->flags;
1786 if (fail_res->dev->subordinate)
1789 free_list(&fail_head);
1794 retval = pci_reenable_device(bridge);
1796 dev_err(&bridge->dev, "Error reenabling bridge (%d)\n", retval);
1797 pci_set_master(bridge);
1799 EXPORT_SYMBOL_GPL(pci_assign_unassigned_bridge_resources);
1801 void pci_assign_unassigned_bus_resources(struct pci_bus *bus)
1803 struct pci_dev *dev;
1804 LIST_HEAD(add_list); /* list of resources that
1805 want additional resources */
1807 down_read(&pci_bus_sem);
1808 list_for_each_entry(dev, &bus->devices, bus_list)
1809 if (pci_is_bridge(dev) && pci_has_subordinate(dev))
1810 __pci_bus_size_bridges(dev->subordinate,
1812 up_read(&pci_bus_sem);
1813 __pci_bus_assign_resources(bus, &add_list, NULL);
1814 BUG_ON(!list_empty(&add_list));
1816 EXPORT_SYMBOL_GPL(pci_assign_unassigned_bus_resources);