2 * drivers/pci/setup-bus.c
4 * Extruded from code written by
5 * Dave Rusling (david.rusling@reo.mts.dec.com)
6 * David Mosberger (davidm@cs.arizona.edu)
7 * David Miller (davem@redhat.com)
9 * Support routines for initializing a PCI subsystem.
13 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
14 * PCI-PCI bridges cleanup, sorted resource allocation.
15 * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
16 * Converted to allocation in 3 passes, which gives
17 * tighter packing. Prefetchable range support.
20 #include <linux/init.h>
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/pci.h>
24 #include <linux/errno.h>
25 #include <linux/ioport.h>
26 #include <linux/cache.h>
27 #include <linux/slab.h>
30 #define DEBUG_CONFIG 1
32 #define DBG(x...) printk(x)
37 static void pbus_assign_resources_sorted(struct pci_bus *bus)
41 struct resource_list head, *list, *tmp;
45 list_for_each_entry(dev, &bus->devices, bus_list) {
46 u16 class = dev->class >> 8;
48 /* Don't touch classless devices or host bridges or ioapics. */
49 if (class == PCI_CLASS_NOT_DEFINED ||
50 class == PCI_CLASS_BRIDGE_HOST)
53 /* Don't touch ioapic devices already enabled by firmware */
54 if (class == PCI_CLASS_SYSTEM_PIC) {
56 pci_read_config_word(dev, PCI_COMMAND, &command);
57 if (command & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY))
61 pdev_sort_resources(dev, &head);
64 for (list = head.next; list;) {
66 idx = res - &list->dev->resource[0];
67 if (pci_assign_resource(list->dev, idx)) {
68 /* FIXME: get rid of this */
79 void pci_setup_cardbus(struct pci_bus *bus)
81 struct pci_dev *bridge = bus->self;
82 struct pci_bus_region region;
84 printk("PCI: Bus %d, cardbus bridge: %s\n",
85 bus->number, pci_name(bridge));
87 pcibios_resource_to_bus(bridge, ®ion, bus->resource[0]);
88 if (bus->resource[0]->flags & IORESOURCE_IO) {
90 * The IO resource is allocated a range twice as large as it
91 * would normally need. This allows us to set both IO regs.
93 printk(KERN_INFO " IO window: 0x%08lx-0x%08lx\n",
94 (unsigned long)region.start,
95 (unsigned long)region.end);
96 pci_write_config_dword(bridge, PCI_CB_IO_BASE_0,
98 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0,
102 pcibios_resource_to_bus(bridge, ®ion, bus->resource[1]);
103 if (bus->resource[1]->flags & IORESOURCE_IO) {
104 printk(KERN_INFO " IO window: 0x%08lx-0x%08lx\n",
105 (unsigned long)region.start,
106 (unsigned long)region.end);
107 pci_write_config_dword(bridge, PCI_CB_IO_BASE_1,
109 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1,
113 pcibios_resource_to_bus(bridge, ®ion, bus->resource[2]);
114 if (bus->resource[2]->flags & IORESOURCE_MEM) {
115 printk(KERN_INFO " PREFETCH window: 0x%08lx-0x%08lx\n",
116 (unsigned long)region.start,
117 (unsigned long)region.end);
118 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0,
120 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0,
124 pcibios_resource_to_bus(bridge, ®ion, bus->resource[3]);
125 if (bus->resource[3]->flags & IORESOURCE_MEM) {
126 printk(KERN_INFO " MEM window: 0x%08lx-0x%08lx\n",
127 (unsigned long)region.start,
128 (unsigned long)region.end);
129 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1,
131 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1,
135 EXPORT_SYMBOL(pci_setup_cardbus);
137 /* Initialize bridges with base/limit values we have collected.
138 PCI-to-PCI Bridge Architecture Specification rev. 1.1 (1998)
139 requires that if there is no I/O ports or memory behind the
140 bridge, corresponding range must be turned off by writing base
141 value greater than limit to the bridge's base/limit registers.
143 Note: care must be taken when updating I/O base/limit registers
144 of bridges which support 32-bit I/O. This update requires two
145 config space writes, so it's quite possible that an I/O window of
146 the bridge will have some undesirable address (e.g. 0) after the
147 first write. Ditto 64-bit prefetchable MMIO. */
148 static void __devinit
149 pci_setup_bridge(struct pci_bus *bus)
151 struct pci_dev *bridge = bus->self;
152 struct pci_bus_region region;
153 u32 l, bu, lu, io_upper16;
155 DBG(KERN_INFO "PCI: Bridge: %s\n", pci_name(bridge));
157 /* Set up the top and bottom of the PCI I/O segment for this bus. */
158 pcibios_resource_to_bus(bridge, ®ion, bus->resource[0]);
159 if (bus->resource[0]->flags & IORESOURCE_IO) {
160 pci_read_config_dword(bridge, PCI_IO_BASE, &l);
162 l |= (region.start >> 8) & 0x00f0;
163 l |= region.end & 0xf000;
164 /* Set up upper 16 bits of I/O base/limit. */
165 io_upper16 = (region.end & 0xffff0000) | (region.start >> 16);
166 DBG(KERN_INFO " IO window: %04lx-%04lx\n",
167 (unsigned long)region.start,
168 (unsigned long)region.end);
171 /* Clear upper 16 bits of I/O base/limit. */
174 DBG(KERN_INFO " IO window: disabled.\n");
176 /* Temporarily disable the I/O range before updating PCI_IO_BASE. */
177 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff);
178 /* Update lower 16 bits of I/O base/limit. */
179 pci_write_config_dword(bridge, PCI_IO_BASE, l);
180 /* Update upper 16 bits of I/O base/limit. */
181 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16);
183 /* Set up the top and bottom of the PCI Memory segment
185 pcibios_resource_to_bus(bridge, ®ion, bus->resource[1]);
186 if (bus->resource[1]->flags & IORESOURCE_MEM) {
187 l = (region.start >> 16) & 0xfff0;
188 l |= region.end & 0xfff00000;
189 DBG(KERN_INFO " MEM window: 0x%08lx-0x%08lx\n",
190 (unsigned long)region.start,
191 (unsigned long)region.end);
195 DBG(KERN_INFO " MEM window: disabled.\n");
197 pci_write_config_dword(bridge, PCI_MEMORY_BASE, l);
199 /* Clear out the upper 32 bits of PREF limit.
200 If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily
201 disables PREF range, which is ok. */
202 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0);
204 /* Set up PREF base/limit. */
206 pcibios_resource_to_bus(bridge, ®ion, bus->resource[2]);
207 if (bus->resource[2]->flags & IORESOURCE_PREFETCH) {
208 l = (region.start >> 16) & 0xfff0;
209 l |= region.end & 0xfff00000;
210 bu = upper_32_bits(region.start);
211 lu = upper_32_bits(region.end);
212 DBG(KERN_INFO " PREFETCH window: 0x%016llx-0x%016llx\n",
213 (unsigned long long)region.start,
214 (unsigned long long)region.end);
218 DBG(KERN_INFO " PREFETCH window: disabled.\n");
220 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l);
222 /* Set the upper 32 bits of PREF base & limit. */
223 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu);
224 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu);
226 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl);
229 /* Check whether the bridge supports optional I/O and
230 prefetchable memory ranges. If not, the respective
231 base/limit registers must be read-only and read as 0. */
232 static void pci_bridge_check_ranges(struct pci_bus *bus)
236 struct pci_dev *bridge = bus->self;
237 struct resource *b_res;
239 b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
240 b_res[1].flags |= IORESOURCE_MEM;
242 pci_read_config_word(bridge, PCI_IO_BASE, &io);
244 pci_write_config_word(bridge, PCI_IO_BASE, 0xf0f0);
245 pci_read_config_word(bridge, PCI_IO_BASE, &io);
246 pci_write_config_word(bridge, PCI_IO_BASE, 0x0);
249 b_res[0].flags |= IORESOURCE_IO;
250 /* DECchip 21050 pass 2 errata: the bridge may miss an address
251 disconnect boundary by one PCI data phase.
252 Workaround: do not use prefetching on this device. */
253 if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001)
255 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
257 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE,
259 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
260 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0);
263 b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
266 /* Helper function for sizing routines: find first available
267 bus resource of a given type. Note: we intentionally skip
268 the bus resources which have already been assigned (that is,
269 have non-NULL parent resource). */
270 static struct resource *find_free_bus_resource(struct pci_bus *bus, unsigned long type)
274 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
277 for (i = 0; i < PCI_BUS_NUM_RESOURCES; i++) {
278 r = bus->resource[i];
279 if (r == &ioport_resource || r == &iomem_resource)
281 if (r && (r->flags & type_mask) == type && !r->parent)
287 /* Sizing the IO windows of the PCI-PCI bridge is trivial,
288 since these windows have 4K granularity and the IO ranges
289 of non-bridge PCI devices are limited to 256 bytes.
290 We must be careful with the ISA aliasing though. */
291 static void pbus_size_io(struct pci_bus *bus)
294 struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO);
295 unsigned long size = 0, size1 = 0;
300 list_for_each_entry(dev, &bus->devices, bus_list) {
303 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
304 struct resource *r = &dev->resource[i];
305 unsigned long r_size;
307 if (r->parent || !(r->flags & IORESOURCE_IO))
309 r_size = r->end - r->start + 1;
312 /* Might be re-aligned for ISA */
318 /* To be fixed in 2.5: we should have sort of HAVE_ISA
319 flag in the struct pci_bus. */
320 #if defined(CONFIG_ISA) || defined(CONFIG_EISA)
321 size = (size & 0xff) + ((size & ~0xffUL) << 2);
323 size = ALIGN(size + size1, 4096);
328 /* Alignment of the IO window is always 4K */
330 b_res->end = b_res->start + size - 1;
331 b_res->flags |= IORESOURCE_STARTALIGN;
334 /* Calculate the size of the bus and minimal alignment which
335 guarantees that all child resources fit in this size. */
336 static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, unsigned long type)
339 resource_size_t min_align, align, size;
340 resource_size_t aligns[12]; /* Alignments from 1Mb to 2Gb */
341 int order, max_order;
342 struct resource *b_res = find_free_bus_resource(bus, type);
347 memset(aligns, 0, sizeof(aligns));
351 list_for_each_entry(dev, &bus->devices, bus_list) {
354 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
355 struct resource *r = &dev->resource[i];
356 resource_size_t r_size;
358 if (r->parent || (r->flags & mask) != type)
360 r_size = r->end - r->start + 1;
361 /* For bridges size != alignment */
362 align = (i < PCI_BRIDGE_RESOURCES) ? r_size : r->start;
363 order = __ffs(align) - 20;
365 printk(KERN_WARNING "PCI: region %s/%d "
366 "too large: 0x%016llx-0x%016llx\n",
368 (unsigned long long)r->start,
369 (unsigned long long)r->end);
376 /* Exclude ranges with size > align from
377 calculation of the alignment. */
379 aligns[order] += align;
380 if (order > max_order)
387 for (order = 0; order <= max_order; order++) {
388 #ifdef CONFIG_RESOURCES_64BIT
389 resource_size_t align1 = 1ULL << (order + 20);
391 resource_size_t align1 = 1U << (order + 20);
395 else if (ALIGN(align + min_align, min_align) < align1)
396 min_align = align1 >> 1;
397 align += aligns[order];
399 size = ALIGN(size, min_align);
404 b_res->start = min_align;
405 b_res->end = size + min_align - 1;
406 b_res->flags |= IORESOURCE_STARTALIGN;
410 static void pci_bus_size_cardbus(struct pci_bus *bus)
412 struct pci_dev *bridge = bus->self;
413 struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
417 * Reserve some resources for CardBus. We reserve
418 * a fixed amount of bus space for CardBus bridges.
420 b_res[0].start = pci_cardbus_io_size;
421 b_res[0].end = b_res[0].start + pci_cardbus_io_size - 1;
422 b_res[0].flags |= IORESOURCE_IO;
424 b_res[1].start = pci_cardbus_io_size;
425 b_res[1].end = b_res[1].start + pci_cardbus_io_size - 1;
426 b_res[1].flags |= IORESOURCE_IO;
429 * Check whether prefetchable memory is supported
432 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
433 if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) {
434 ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
435 pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl);
436 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
440 * If we have prefetchable memory support, allocate
441 * two regions. Otherwise, allocate one region of
444 if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) {
445 b_res[2].start = pci_cardbus_mem_size;
446 b_res[2].end = b_res[2].start + pci_cardbus_mem_size - 1;
447 b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
449 b_res[3].start = pci_cardbus_mem_size;
450 b_res[3].end = b_res[3].start + pci_cardbus_mem_size - 1;
451 b_res[3].flags |= IORESOURCE_MEM;
453 b_res[3].start = pci_cardbus_mem_size * 2;
454 b_res[3].end = b_res[3].start + pci_cardbus_mem_size * 2 - 1;
455 b_res[3].flags |= IORESOURCE_MEM;
459 void __ref pci_bus_size_bridges(struct pci_bus *bus)
462 unsigned long mask, prefmask;
464 list_for_each_entry(dev, &bus->devices, bus_list) {
465 struct pci_bus *b = dev->subordinate;
469 switch (dev->class >> 8) {
470 case PCI_CLASS_BRIDGE_CARDBUS:
471 pci_bus_size_cardbus(b);
474 case PCI_CLASS_BRIDGE_PCI:
476 pci_bus_size_bridges(b);
485 switch (bus->self->class >> 8) {
486 case PCI_CLASS_BRIDGE_CARDBUS:
487 /* don't size cardbuses yet. */
490 case PCI_CLASS_BRIDGE_PCI:
491 pci_bridge_check_ranges(bus);
494 /* If the bridge supports prefetchable range, size it
495 separately. If it doesn't, or its prefetchable window
496 has already been allocated by arch code, try
497 non-prefetchable range for both types of PCI memory
499 mask = IORESOURCE_MEM;
500 prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH;
501 if (pbus_size_mem(bus, prefmask, prefmask))
502 mask = prefmask; /* Success, size non-prefetch only. */
503 pbus_size_mem(bus, mask, IORESOURCE_MEM);
507 EXPORT_SYMBOL(pci_bus_size_bridges);
509 void __ref pci_bus_assign_resources(struct pci_bus *bus)
514 pbus_assign_resources_sorted(bus);
516 list_for_each_entry(dev, &bus->devices, bus_list) {
517 b = dev->subordinate;
521 pci_bus_assign_resources(b);
523 switch (dev->class >> 8) {
524 case PCI_CLASS_BRIDGE_PCI:
528 case PCI_CLASS_BRIDGE_CARDBUS:
529 pci_setup_cardbus(b);
533 printk(KERN_INFO "PCI: not setting up bridge %s "
534 "for bus %d\n", pci_name(dev), b->number);
539 EXPORT_SYMBOL(pci_bus_assign_resources);
542 pci_assign_unassigned_resources(void)
546 /* Depth first, calculate sizes and alignments of all
547 subordinate buses. */
548 list_for_each_entry(bus, &pci_root_buses, node) {
549 pci_bus_size_bridges(bus);
551 /* Depth last, allocate resources and update the hardware. */
552 list_for_each_entry(bus, &pci_root_buses, node) {
553 pci_bus_assign_resources(bus);
554 pci_enable_bridges(bus);