2 * drivers/pcmcia/m32r_cfc.c
4 * Device driver for the CFC functionality of M32R.
6 * Copyright (c) 2001, 2002, 2003, 2004
7 * Hiroyuki Kondo, Naoto Sugai, Hayato Fujiwara
10 #include <linux/module.h>
11 #include <linux/moduleparam.h>
12 #include <linux/init.h>
13 #include <linux/types.h>
14 #include <linux/fcntl.h>
15 #include <linux/string.h>
16 #include <linux/kernel.h>
17 #include <linux/errno.h>
18 #include <linux/timer.h>
19 #include <linux/ioport.h>
20 #include <linux/delay.h>
21 #include <linux/workqueue.h>
22 #include <linux/interrupt.h>
23 #include <linux/platform_device.h>
24 #include <linux/bitops.h>
27 #include <asm/system.h>
29 #include <pcmcia/ss.h>
30 #include <pcmcia/cs.h>
32 #undef MAX_IO_WIN /* FIXME */
34 #undef MAX_WIN /* FIXME */
39 /* Poll status interval -- 0 means default to interrupt */
40 static int poll_interval = 0;
42 typedef enum pcc_space { as_none = 0, as_comm, as_attr, as_io } pcc_as_t;
44 typedef struct pcc_socket {
46 struct pcmcia_socket socket;
50 u_long base; /* PCC register base */
51 u_char cs_irq1, cs_irq2, intr;
52 pccard_io_map io_map[MAX_IO_WIN];
53 pccard_mem_map mem_map[MAX_WIN];
56 pcc_as_t current_space;
59 struct proc_dir_entry *proc;
63 static int pcc_sockets = 0;
64 static pcc_socket_t socket[M32R_MAX_PCC] = {
68 /*====================================================================*/
70 static unsigned int pcc_get(u_short, unsigned int);
71 static void pcc_set(u_short, unsigned int , unsigned int );
73 static DEFINE_SPINLOCK(pcc_lock);
75 #if !defined(CONFIG_PLAT_USRV)
76 static inline u_long pcc_port2addr(unsigned long port, int size) {
80 if (size == 1) { /* byte access */
83 addr = CFC_IO_MAPBASE_BYTE - CFC_IOPORT_BASE + odd + port;
85 addr = CFC_IO_MAPBASE_WORD - CFC_IOPORT_BASE + port;
89 #else /* CONFIG_PLAT_USRV */
90 static inline u_long pcc_port2addr(unsigned long port, int size) {
92 u_long addr = ((port - CFC_IOPORT_BASE) & 0xf000) << 8;
94 if (size == 1) { /* byte access */
98 addr = (addr | CFC_IO_MAPBASE_BYTE) + odd + (port & 0xfff);
99 } else if (size == 2) /* word access */
100 addr = (addr | CFC_IO_MAPBASE_WORD) + (port & 0xfff);
104 #endif /* CONFIG_PLAT_USRV */
106 void pcc_ioread_byte(int sock, unsigned long port, void *buf, size_t size,
107 size_t nmemb, int flag)
110 unsigned char *bp = (unsigned char *)buf;
113 pr_debug("m32r_cfc: pcc_ioread_byte: sock=%d, port=%#lx, buf=%p, "
114 "size=%u, nmemb=%d, flag=%d\n",
115 sock, port, buf, size, nmemb, flag);
117 addr = pcc_port2addr(port, 1);
119 printk("m32r_cfc:ioread_byte null port :%#lx\n",port);
122 pr_debug("m32r_cfc: pcc_ioread_byte: addr=%#lx\n", addr);
124 spin_lock_irqsave(&pcc_lock, flags);
128 spin_unlock_irqrestore(&pcc_lock, flags);
131 void pcc_ioread_word(int sock, unsigned long port, void *buf, size_t size,
132 size_t nmemb, int flag)
135 unsigned short *bp = (unsigned short *)buf;
138 pr_debug("m32r_cfc: pcc_ioread_word: sock=%d, port=%#lx, "
139 "buf=%p, size=%u, nmemb=%d, flag=%d\n",
140 sock, port, buf, size, nmemb, flag);
143 printk("m32r_cfc: ioread_word :illigal size %u : %#lx\n", size,
146 printk("m32r_cfc: ioread_word :insw \n");
148 addr = pcc_port2addr(port, 2);
150 printk("m32r_cfc:ioread_word null port :%#lx\n",port);
153 pr_debug("m32r_cfc: pcc_ioread_word: addr=%#lx\n", addr);
155 spin_lock_irqsave(&pcc_lock, flags);
159 spin_unlock_irqrestore(&pcc_lock, flags);
162 void pcc_iowrite_byte(int sock, unsigned long port, void *buf, size_t size,
163 size_t nmemb, int flag)
166 unsigned char *bp = (unsigned char *)buf;
169 pr_debug("m32r_cfc: pcc_iowrite_byte: sock=%d, port=%#lx, "
170 "buf=%p, size=%u, nmemb=%d, flag=%d\n",
171 sock, port, buf, size, nmemb, flag);
174 addr = pcc_port2addr(port, 1);
176 printk("m32r_cfc:iowrite_byte null port:%#lx\n",port);
179 pr_debug("m32r_cfc: pcc_iowrite_byte: addr=%#lx\n", addr);
181 spin_lock_irqsave(&pcc_lock, flags);
184 spin_unlock_irqrestore(&pcc_lock, flags);
187 void pcc_iowrite_word(int sock, unsigned long port, void *buf, size_t size,
188 size_t nmemb, int flag)
191 unsigned short *bp = (unsigned short *)buf;
194 pr_debug("m32r_cfc: pcc_iowrite_word: sock=%d, port=%#lx, "
195 "buf=%p, size=%u, nmemb=%d, flag=%d\n",
196 sock, port, buf, size, nmemb, flag);
199 printk("m32r_cfc: iowrite_word :illigal size %u : %#lx\n",
202 printk("m32r_cfc: iowrite_word :outsw \n");
204 addr = pcc_port2addr(port, 2);
206 printk("m32r_cfc:iowrite_word null addr :%#lx\n",port);
211 printk("m32r_cfc:iowrite_word port addr (%#lx):%#lx\n", port,
216 pr_debug("m32r_cfc: pcc_iowrite_word: addr=%#lx\n", addr);
218 spin_lock_irqsave(&pcc_lock, flags);
221 spin_unlock_irqrestore(&pcc_lock, flags);
224 /*====================================================================*/
226 #define IS_REGISTERED 0x2000
227 #define IS_ALIVE 0x8000
229 typedef struct pcc_t {
234 static pcc_t pcc[] = {
235 #if !defined(CONFIG_PLAT_USRV)
236 { "m32r_cfc", 0 }, { "", 0 },
237 #else /* CONFIG_PLAT_USRV */
238 { "m32r_cfc", 0 }, { "m32r_cfc", 0 }, { "m32r_cfc", 0 },
239 { "m32r_cfc", 0 }, { "m32r_cfc", 0 }, { "", 0 },
240 #endif /* CONFIG_PLAT_USRV */
243 static irqreturn_t pcc_interrupt(int, void *);
245 /*====================================================================*/
247 static struct timer_list poll_timer;
249 static unsigned int pcc_get(u_short sock, unsigned int reg)
251 unsigned int val = inw(reg);
252 pr_debug("m32r_cfc: pcc_get: reg(0x%08x)=0x%04x\n", reg, val);
257 static void pcc_set(u_short sock, unsigned int reg, unsigned int data)
260 pr_debug("m32r_cfc: pcc_set: reg(0x%08x)=0x%04x\n", reg, data);
263 /*======================================================================
265 See if a card is present, powered up, in IO mode, and already
266 bound to a (non PC Card) Linux driver. We leave these alone.
268 We make an exception for cards that seem to be serial devices.
270 ======================================================================*/
272 static int __init is_alive(u_short sock)
276 pr_debug("m32r_cfc: is_alive:\n");
279 stat = pcc_get(sock, (unsigned int)PLD_CFSTS);
282 printk("Card is detected at socket %d : stat = 0x%08x\n", sock, stat);
283 pr_debug("m32r_cfc: is_alive: sock stat is 0x%04x\n", stat);
288 static void add_pcc_socket(ulong base, int irq, ulong mapaddr,
291 pcc_socket_t *t = &socket[pcc_sockets];
293 pr_debug("m32r_cfc: add_pcc_socket: base=%#lx, irq=%d, "
294 "mapaddr=%#lx, ioaddr=%08x\n",
295 base, irq, mapaddr, ioaddr);
299 t->mapaddr = mapaddr;
300 #if !defined(CONFIG_PLAT_USRV)
303 t->cs_irq1 = irq; // insert irq
304 t->cs_irq2 = irq + 1; // eject irq
305 #else /* CONFIG_PLAT_USRV */
308 t->cs_irq1 = 0; // insert irq
309 t->cs_irq2 = 0; // eject irq
310 #endif /* CONFIG_PLAT_USRV */
312 if (is_alive(pcc_sockets))
313 t->flags |= IS_ALIVE;
316 #if !defined(CONFIG_PLAT_USRV)
317 request_region((unsigned int)PLD_CFRSTCR, 0x20, "m32r_cfc");
318 #else /* CONFIG_PLAT_USRV */
320 unsigned int reg_base;
322 reg_base = (unsigned int)PLD_CFRSTCR;
323 reg_base |= pcc_sockets << 8;
324 request_region(reg_base, 0x20, "m32r_cfc");
326 #endif /* CONFIG_PLAT_USRV */
327 printk(KERN_INFO " %s ", pcc[pcc_sockets].name);
328 printk("pcc at 0x%08lx\n", t->base);
330 /* Update socket interrupt information, capabilities */
331 t->socket.features |= (SS_CAP_PCCARD | SS_CAP_STATIC_MAP);
332 t->socket.map_size = M32R_PCC_MAPSIZE;
333 t->socket.io_offset = ioaddr; /* use for io access offset */
334 t->socket.irq_mask = 0;
335 #if !defined(CONFIG_PLAT_USRV)
336 t->socket.pci_irq = PLD_IRQ_CFIREQ ; /* card interrupt */
337 #else /* CONFIG_PLAT_USRV */
338 t->socket.pci_irq = PLD_IRQ_CF0 + pcc_sockets;
339 #endif /* CONFIG_PLAT_USRV */
341 #ifndef CONFIG_PLAT_USRV
342 /* insert interrupt */
343 request_irq(irq, pcc_interrupt, 0, "m32r_cfc", pcc_interrupt);
344 #ifndef CONFIG_PLAT_MAPPI3
345 /* eject interrupt */
346 request_irq(irq+1, pcc_interrupt, 0, "m32r_cfc", pcc_interrupt);
348 pr_debug("m32r_cfc: enable CFMSK, RDYSEL\n");
349 pcc_set(pcc_sockets, (unsigned int)PLD_CFIMASK, 0x01);
350 #endif /* CONFIG_PLAT_USRV */
351 #if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_USRV) || defined(CONFIG_PLAT_OPSPUT)
352 pcc_set(pcc_sockets, (unsigned int)PLD_CFCR1, 0x0200);
360 /*====================================================================*/
362 static irqreturn_t pcc_interrupt(int irq, void *dev)
368 pr_debug("m32r_cfc: pcc_interrupt: irq=%d, dev=%p\n", irq, dev);
369 for (i = 0; i < pcc_sockets; i++) {
370 if (socket[i].cs_irq1 != irq && socket[i].cs_irq2 != irq)
374 pr_debug("m32r_cfc: pcc_interrupt: socket %d irq 0x%02x ",
376 events |= SS_DETECT; /* insert or eject */
378 pcmcia_parse_events(&socket[i].socket, events);
380 pr_debug("m32r_cfc: pcc_interrupt: done\n");
382 return IRQ_RETVAL(handled);
383 } /* pcc_interrupt */
385 static void pcc_interrupt_wrapper(u_long data)
387 pr_debug("m32r_cfc: pcc_interrupt_wrapper:\n");
388 pcc_interrupt(0, NULL);
389 init_timer(&poll_timer);
390 poll_timer.expires = jiffies + poll_interval;
391 add_timer(&poll_timer);
394 /*====================================================================*/
396 static int _pcc_get_status(u_short sock, u_int *value)
400 pr_debug("m32r_cfc: _pcc_get_status:\n");
401 status = pcc_get(sock, (unsigned int)PLD_CFSTS);
402 *value = (status) ? SS_DETECT : 0;
403 pr_debug("m32r_cfc: _pcc_get_status: status=0x%08x\n", status);
405 #if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_USRV) || defined(CONFIG_PLAT_OPSPUT)
407 /* enable CF power */
408 status = inw((unsigned int)PLD_CPCR);
409 if (!(status & PLD_CPCR_CF)) {
410 pr_debug("m32r_cfc: _pcc_get_status: "
411 "power on (CPCR=0x%08x)\n", status);
412 status |= PLD_CPCR_CF;
413 outw(status, (unsigned int)PLD_CPCR);
416 *value |= SS_POWERON;
418 pcc_set(sock, (unsigned int)PLD_CFBUFCR,0);/* enable buffer */
421 *value |= SS_READY; /* always ready */
424 /* disable CF power */
425 status = inw((unsigned int)PLD_CPCR);
426 status &= ~PLD_CPCR_CF;
427 outw(status, (unsigned int)PLD_CPCR);
429 pr_debug("m32r_cfc: _pcc_get_status: "
430 "power off (CPCR=0x%08x)\n", status);
432 #elif defined(CONFIG_PLAT_MAPPI2) || defined(CONFIG_PLAT_MAPPI3)
434 status = pcc_get(sock, (unsigned int)PLD_CPCR);
435 if (status == 0) { /* power off */
436 pcc_set(sock, (unsigned int)PLD_CPCR, 1);
437 pcc_set(sock, (unsigned int)PLD_CFBUFCR,0); /* force buffer off for ZA-36 */
440 *value |= SS_POWERON;
442 pcc_set(sock, (unsigned int)PLD_CFBUFCR,0);
444 pcc_set(sock, (unsigned int)PLD_CFRSTCR, 0x0101);
445 udelay(25); /* for IDE reset */
446 pcc_set(sock, (unsigned int)PLD_CFRSTCR, 0x0100);
447 mdelay(2); /* for IDE reset */
452 /* disable CF power */
453 pcc_set(sock, (unsigned int)PLD_CPCR, 0);
455 pr_debug("m32r_cfc: _pcc_get_status: "
456 "power off (CPCR=0x%08x)\n", status);
459 #error no platform configuration
461 pr_debug("m32r_cfc: _pcc_get_status: GetStatus(%d) = %#4.4x\n",
466 /*====================================================================*/
468 static int _pcc_set_socket(u_short sock, socket_state_t *state)
470 pr_debug("m32r_cfc: SetSocket(%d, flags %#3.3x, Vcc %d, Vpp %d, "
471 "io_irq %d, csc_mask %#2.2x)\n", sock, state->flags,
472 state->Vcc, state->Vpp, state->io_irq, state->csc_mask);
474 #if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_USRV) || defined(CONFIG_PLAT_OPSPUT) || defined(CONFIG_PLAT_MAPPI2) || defined(CONFIG_PLAT_MAPPI3)
476 if ((state->Vcc != 50) && (state->Vcc != 33))
478 /* accept 5V and 3.3V */
481 if (state->flags & SS_RESET) {
482 pr_debug(":RESET\n");
483 pcc_set(sock,(unsigned int)PLD_CFRSTCR,0x101);
485 pcc_set(sock,(unsigned int)PLD_CFRSTCR,0x100);
487 if (state->flags & SS_OUTPUT_ENA){
488 pr_debug(":OUTPUT_ENA\n");
490 pcc_set(sock,(unsigned int)PLD_CFBUFCR,0);
492 pcc_set(sock,(unsigned int)PLD_CFBUFCR,1);
495 if(state->flags & SS_IOCARD){
498 if (state->flags & SS_PWR_AUTO) {
499 pr_debug(":PWR_AUTO");
501 if (state->csc_mask & SS_DETECT)
502 pr_debug(":csc-SS_DETECT");
503 if (state->flags & SS_IOCARD) {
504 if (state->csc_mask & SS_STSCHG)
507 if (state->csc_mask & SS_BATDEAD)
508 pr_debug(":BATDEAD");
509 if (state->csc_mask & SS_BATWARN)
510 pr_debug(":BATWARN");
511 if (state->csc_mask & SS_READY)
518 /*====================================================================*/
520 static int _pcc_set_io_map(u_short sock, struct pccard_io_map *io)
524 pr_debug("m32r_cfc: SetIOMap(%d, %d, %#2.2x, %d ns, "
525 "%#llx-%#llx)\n", sock, io->map, io->flags,
526 io->speed, (unsigned long long)io->start,
527 (unsigned long long)io->stop);
533 /*====================================================================*/
535 static int _pcc_set_mem_map(u_short sock, struct pccard_mem_map *mem)
538 u_char map = mem->map;
540 pcc_socket_t *t = &socket[sock];
542 pr_debug("m32r_cfc: SetMemMap(%d, %d, %#2.2x, %d ns, "
543 "%#llx, %#x)\n", sock, map, mem->flags,
544 mem->speed, (unsigned long long)mem->static_start,
550 if ((map > MAX_WIN) || (mem->card_start > 0x3ffffff)){
557 if ((mem->flags & MAP_ACTIVE) == 0) {
558 t->current_space = as_none;
565 if (mem->flags & MAP_ATTRIB) {
566 t->current_space = as_attr;
568 t->current_space = as_comm;
574 addr = t->mapaddr + (mem->card_start & M32R_PCC_MAPMASK);
575 mem->static_start = addr + mem->card_start;
581 #if 0 /* driver model ordering issue */
582 /*======================================================================
584 Routines for accessing socket information and register dumps via
587 ======================================================================*/
589 static ssize_t show_info(struct class_device *class_dev, char *buf)
591 pcc_socket_t *s = container_of(class_dev, struct pcc_socket,
594 return sprintf(buf, "type: %s\nbase addr: 0x%08lx\n",
595 pcc[s->type].name, s->base);
598 static ssize_t show_exca(struct class_device *class_dev, char *buf)
605 static CLASS_DEVICE_ATTR(info, S_IRUGO, show_info, NULL);
606 static CLASS_DEVICE_ATTR(exca, S_IRUGO, show_exca, NULL);
609 /*====================================================================*/
611 /* this is horribly ugly... proper locking needs to be done here at
613 #define LOCKED(x) do { \
615 unsigned long flags; \
616 spin_lock_irqsave(&pcc_lock, flags); \
618 spin_unlock_irqrestore(&pcc_lock, flags); \
623 static int pcc_get_status(struct pcmcia_socket *s, u_int *value)
625 unsigned int sock = container_of(s, struct pcc_socket, socket)->number;
627 if (socket[sock].flags & IS_ALIVE) {
628 dev_dbg(&s->dev, "pcc_get_status: sock(%d) -EINVAL\n", sock);
632 dev_dbg(&s->dev, "pcc_get_status: sock(%d)\n", sock);
633 LOCKED(_pcc_get_status(sock, value));
636 static int pcc_set_socket(struct pcmcia_socket *s, socket_state_t *state)
638 unsigned int sock = container_of(s, struct pcc_socket, socket)->number;
640 if (socket[sock].flags & IS_ALIVE) {
641 dev_dbg(&s->dev, "pcc_set_socket: sock(%d) -EINVAL\n", sock);
644 dev_dbg(&s->dev, "pcc_set_socket: sock(%d)\n", sock);
645 LOCKED(_pcc_set_socket(sock, state));
648 static int pcc_set_io_map(struct pcmcia_socket *s, struct pccard_io_map *io)
650 unsigned int sock = container_of(s, struct pcc_socket, socket)->number;
652 if (socket[sock].flags & IS_ALIVE) {
653 dev_dbg(&s->dev, "pcc_set_io_map: sock(%d) -EINVAL\n", sock);
656 dev_dbg(&s->dev, "pcc_set_io_map: sock(%d)\n", sock);
657 LOCKED(_pcc_set_io_map(sock, io));
660 static int pcc_set_mem_map(struct pcmcia_socket *s, struct pccard_mem_map *mem)
662 unsigned int sock = container_of(s, struct pcc_socket, socket)->number;
664 if (socket[sock].flags & IS_ALIVE) {
665 dev_dbg(&s->dev, "pcc_set_mem_map: sock(%d) -EINVAL\n", sock);
668 dev_dbg(&s->dev, "pcc_set_mem_map: sock(%d)\n", sock);
669 LOCKED(_pcc_set_mem_map(sock, mem));
672 static int pcc_init(struct pcmcia_socket *s)
674 dev_dbg(&s->dev, "pcc_init()\n");
678 static struct pccard_operations pcc_operations = {
680 .get_status = pcc_get_status,
681 .set_socket = pcc_set_socket,
682 .set_io_map = pcc_set_io_map,
683 .set_mem_map = pcc_set_mem_map,
687 /*====================================================================*/
689 static struct platform_driver pcc_driver = {
692 .owner = THIS_MODULE,
696 static struct platform_device pcc_device = {
701 /*====================================================================*/
703 static int __init init_m32r_pcc(void)
707 ret = platform_driver_register(&pcc_driver);
711 ret = platform_device_register(&pcc_device);
713 platform_driver_unregister(&pcc_driver);
717 #if defined(CONFIG_PLAT_MAPPI2) || defined(CONFIG_PLAT_MAPPI3)
718 pcc_set(0, (unsigned int)PLD_CFCR0, 0x0f0f);
719 pcc_set(0, (unsigned int)PLD_CFCR1, 0x0200);
724 #if !defined(CONFIG_PLAT_USRV)
725 add_pcc_socket(M32R_PCC0_BASE, PLD_IRQ_CFC_INSERT, CFC_ATTR_MAPBASE,
727 #else /* CONFIG_PLAT_USRV */
732 for (i = 0 ; i < M32R_MAX_PCC ; i++) {
733 base = (ulong)PLD_CFRSTCR;
734 base = base | (i << 8);
735 ioaddr = (i + 1) << 12;
736 mapaddr = CFC_ATTR_MAPBASE | (i << 20);
737 add_pcc_socket(base, 0, mapaddr, ioaddr);
740 #endif /* CONFIG_PLAT_USRV */
742 if (pcc_sockets == 0) {
743 printk("socket is not found.\n");
744 platform_device_unregister(&pcc_device);
745 platform_driver_unregister(&pcc_driver);
749 /* Set up interrupt handler(s) */
751 for (i = 0 ; i < pcc_sockets ; i++) {
752 socket[i].socket.dev.parent = &pcc_device.dev;
753 socket[i].socket.ops = &pcc_operations;
754 socket[i].socket.resource_ops = &pccard_static_ops;
755 socket[i].socket.owner = THIS_MODULE;
756 socket[i].number = i;
757 ret = pcmcia_register_socket(&socket[i].socket);
759 socket[i].flags |= IS_REGISTERED;
761 #if 0 /* driver model ordering issue */
762 class_device_create_file(&socket[i].socket.dev,
763 &class_device_attr_info);
764 class_device_create_file(&socket[i].socket.dev,
765 &class_device_attr_exca);
769 /* Finally, schedule a polling interrupt */
770 if (poll_interval != 0) {
771 poll_timer.function = pcc_interrupt_wrapper;
773 init_timer(&poll_timer);
774 poll_timer.expires = jiffies + poll_interval;
775 add_timer(&poll_timer);
779 } /* init_m32r_pcc */
781 static void __exit exit_m32r_pcc(void)
785 for (i = 0; i < pcc_sockets; i++)
786 if (socket[i].flags & IS_REGISTERED)
787 pcmcia_unregister_socket(&socket[i].socket);
789 platform_device_unregister(&pcc_device);
790 if (poll_interval != 0)
791 del_timer_sync(&poll_timer);
793 platform_driver_unregister(&pcc_driver);
794 } /* exit_m32r_pcc */
796 module_init(init_m32r_pcc);
797 module_exit(exit_m32r_pcc);
798 MODULE_LICENSE("Dual MPL/GPL");
799 /*====================================================================*/