drivers/perf/arm_pmu.c

   1 #undef DEBUG
   2
   3 /*
   4  * ARM performance counter support.
   5  *
   6  * Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles
   7  * Copyright (C) 2010 ARM Ltd., Will Deacon <will.deacon@arm.com>
   8  *
   9  * This code is based on the sparc64 perf event code, which is in turn based
  10  * on the x86 code.
  11  */
  12 #define pr_fmt(fmt) "hw perfevents: " fmt
  13
  14 #include <linux/bitmap.h>
  15 #include <linux/cpumask.h>
  16 #include <linux/cpu_pm.h>
  17 #include <linux/export.h>
  18 #include <linux/kernel.h>
  19 #include <linux/of_device.h>
  20 #include <linux/perf/arm_pmu.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/slab.h>
  23 #include <linux/sched/clock.h>
  24 #include <linux/spinlock.h>
  25 #include <linux/irq.h>
  26 #include <linux/irqdesc.h>
  27
  28 #include <asm/cputype.h>
  29 #include <asm/irq_regs.h>
  30
  31 static int
  32 armpmu_map_cache_event(const unsigned (*cache_map)
  33                                       [PERF_COUNT_HW_CACHE_MAX]
  34                                       [PERF_COUNT_HW_CACHE_OP_MAX]
  35                                       [PERF_COUNT_HW_CACHE_RESULT_MAX],
  36                        u64 config)
  37 {
  38         unsigned int cache_type, cache_op, cache_result, ret;
  39
  40         cache_type = (config >>  0) & 0xff;
  41         if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
  42                 return -EINVAL;
  43
  44         cache_op = (config >>  8) & 0xff;
  45         if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
  46                 return -EINVAL;
  47
  48         cache_result = (config >> 16) & 0xff;
  49         if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
  50                 return -EINVAL;
  51
  52         ret = (int)(*cache_map)[cache_type][cache_op][cache_result];
  53
  54         if (ret == CACHE_OP_UNSUPPORTED)
  55                 return -ENOENT;
  56
  57         return ret;
  58 }
  59
  60 static int
  61 armpmu_map_hw_event(const unsigned (*event_map)[PERF_COUNT_HW_MAX], u64 config)
  62 {
  63         int mapping;
  64
  65         if (config >= PERF_COUNT_HW_MAX)
  66                 return -EINVAL;
  67
  68         mapping = (*event_map)[config];
  69         return mapping == HW_OP_UNSUPPORTED ? -ENOENT : mapping;
  70 }
  71
  72 static int
  73 armpmu_map_raw_event(u32 raw_event_mask, u64 config)
  74 {
  75         return (int)(config & raw_event_mask);
  76 }
  77
  78 int
  79 armpmu_map_event(struct perf_event *event,
  80                  const unsigned (*event_map)[PERF_COUNT_HW_MAX],
  81                  const unsigned (*cache_map)
  82                                 [PERF_COUNT_HW_CACHE_MAX]
  83                                 [PERF_COUNT_HW_CACHE_OP_MAX]
  84                                 [PERF_COUNT_HW_CACHE_RESULT_MAX],
  85                  u32 raw_event_mask)
  86 {
  87         u64 config = event->attr.config;
  88         int type = event->attr.type;
  89
  90         if (type == event->pmu->type)
  91                 return armpmu_map_raw_event(raw_event_mask, config);
  92
  93         switch (type) {
  94         case PERF_TYPE_HARDWARE:
  95                 return armpmu_map_hw_event(event_map, config);
  96         case PERF_TYPE_HW_CACHE:
  97                 return armpmu_map_cache_event(cache_map, config);
  98         case PERF_TYPE_RAW:
  99                 return armpmu_map_raw_event(raw_event_mask, config);
 100         }
 101
 102         return -ENOENT;
 103 }
 104
 105 int armpmu_event_set_period(struct perf_event *event)
 106 {
 107         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 108         struct hw_perf_event *hwc = &event->hw;
 109         s64 left = local64_read(&hwc->period_left);
 110         s64 period = hwc->sample_period;
 111         int ret = 0;
 112
 113         if (unlikely(left <= -period)) {
 114                 left = period;
 115                 local64_set(&hwc->period_left, left);
 116                 hwc->last_period = period;
 117                 ret = 1;
 118         }
 119
 120         if (unlikely(left <= 0)) {
 121                 left += period;
 122                 local64_set(&hwc->period_left, left);
 123                 hwc->last_period = period;
 124                 ret = 1;
 125         }
 126
 127         /*
 128          * Limit the maximum period to prevent the counter value
 129          * from overtaking the one we are about to program. In
 130          * effect we are reducing max_period to account for
 131          * interrupt latency (and we are being very conservative).
 132          */
 133         if (left > (armpmu->max_period >> 1))
 134                 left = armpmu->max_period >> 1;
 135
 136         local64_set(&hwc->prev_count, (u64)-left);
 137
 138         armpmu->write_counter(event, (u64)(-left) & 0xffffffff);
 139
 140         perf_event_update_userpage(event);
 141
 142         return ret;
 143 }
 144
 145 u64 armpmu_event_update(struct perf_event *event)
 146 {
 147         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 148         struct hw_perf_event *hwc = &event->hw;
 149         u64 delta, prev_raw_count, new_raw_count;
 150
 151 again:
 152         prev_raw_count = local64_read(&hwc->prev_count);
 153         new_raw_count = armpmu->read_counter(event);
 154
 155         if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
 156                              new_raw_count) != prev_raw_count)
 157                 goto again;
 158
 159         delta = (new_raw_count - prev_raw_count) & armpmu->max_period;
 160
 161         local64_add(delta, &event->count);
 162         local64_sub(delta, &hwc->period_left);
 163
 164         return new_raw_count;
 165 }
 166
 167 static void
 168 armpmu_read(struct perf_event *event)
 169 {
 170         armpmu_event_update(event);
 171 }
 172
 173 static void
 174 armpmu_stop(struct perf_event *event, int flags)
 175 {
 176         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 177         struct hw_perf_event *hwc = &event->hw;
 178
 179         /*
 180          * ARM pmu always has to update the counter, so ignore
 181          * PERF_EF_UPDATE, see comments in armpmu_start().
 182          */
 183         if (!(hwc->state & PERF_HES_STOPPED)) {
 184                 armpmu->disable(event);
 185                 armpmu_event_update(event);
 186                 hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
 187         }
 188 }
 189
 190 static void armpmu_start(struct perf_event *event, int flags)
 191 {
 192         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 193         struct hw_perf_event *hwc = &event->hw;
 194
 195         /*
 196          * ARM pmu always has to reprogram the period, so ignore
 197          * PERF_EF_RELOAD, see the comment below.
 198          */
 199         if (flags & PERF_EF_RELOAD)
 200                 WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
 201
 202         hwc->state = 0;
 203         /*
 204          * Set the period again. Some counters can't be stopped, so when we
 205          * were stopped we simply disabled the IRQ source and the counter
 206          * may have been left counting. If we don't do this step then we may
 207          * get an interrupt too soon or *way* too late if the overflow has
 208          * happened since disabling.
 209          */
 210         armpmu_event_set_period(event);
 211         armpmu->enable(event);
 212 }
 213
 214 static void
 215 armpmu_del(struct perf_event *event, int flags)
 216 {
 217         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 218         struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
 219         struct hw_perf_event *hwc = &event->hw;
 220         int idx = hwc->idx;
 221
 222         armpmu_stop(event, PERF_EF_UPDATE);
 223         hw_events->events[idx] = NULL;
 224         clear_bit(idx, hw_events->used_mask);
 225         if (armpmu->clear_event_idx)
 226                 armpmu->clear_event_idx(hw_events, event);
 227
 228         perf_event_update_userpage(event);
 229 }
 230
 231 static int
 232 armpmu_add(struct perf_event *event, int flags)
 233 {
 234         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 235         struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
 236         struct hw_perf_event *hwc = &event->hw;
 237         int idx;
 238
 239         /* An event following a process won't be stopped earlier */
 240         if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus))
 241                 return -ENOENT;
 242
 243         /* If we don't have a space for the counter then finish early. */
 244         idx = armpmu->get_event_idx(hw_events, event);
 245         if (idx < 0)
 246                 return idx;
 247
 248         /*
 249          * If there is an event in the counter we are going to use then make
 250          * sure it is disabled.
 251          */
 252         event->hw.idx = idx;
 253         armpmu->disable(event);
 254         hw_events->events[idx] = event;
 255
 256         hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
 257         if (flags & PERF_EF_START)
 258                 armpmu_start(event, PERF_EF_RELOAD);
 259
 260         /* Propagate our changes to the userspace mapping. */
 261         perf_event_update_userpage(event);
 262
 263         return 0;
 264 }
 265
 266 static int
 267 validate_event(struct pmu *pmu, struct pmu_hw_events *hw_events,
 268                                struct perf_event *event)
 269 {
 270         struct arm_pmu *armpmu;
 271
 272         if (is_software_event(event))
 273                 return 1;
 274
 275         /*
 276          * Reject groups spanning multiple HW PMUs (e.g. CPU + CCI). The
 277          * core perf code won't check that the pmu->ctx == leader->ctx
 278          * until after pmu->event_init(event).
 279          */
 280         if (event->pmu != pmu)
 281                 return 0;
 282
 283         if (event->state < PERF_EVENT_STATE_OFF)
 284                 return 1;
 285
 286         if (event->state == PERF_EVENT_STATE_OFF && !event->attr.enable_on_exec)
 287                 return 1;
 288
 289         armpmu = to_arm_pmu(event->pmu);
 290         return armpmu->get_event_idx(hw_events, event) >= 0;
 291 }
 292
 293 static int
 294 validate_group(struct perf_event *event)
 295 {
 296         struct perf_event *sibling, *leader = event->group_leader;
 297         struct pmu_hw_events fake_pmu;
 298
 299         /*
 300          * Initialise the fake PMU. We only need to populate the
 301          * used_mask for the purposes of validation.
 302          */
 303         memset(&fake_pmu.used_mask, 0, sizeof(fake_pmu.used_mask));
 304
 305         if (!validate_event(event->pmu, &fake_pmu, leader))
 306                 return -EINVAL;
 307
 308         list_for_each_entry(sibling, &leader->sibling_list, group_entry) {
 309                 if (!validate_event(event->pmu, &fake_pmu, sibling))
 310                         return -EINVAL;
 311         }
 312
 313         if (!validate_event(event->pmu, &fake_pmu, event))
 314                 return -EINVAL;
 315
 316         return 0;
 317 }
 318
 319 static irqreturn_t armpmu_dispatch_irq(int irq, void *dev)
 320 {
 321         struct arm_pmu *armpmu;
 322         struct platform_device *plat_device;
 323         struct arm_pmu_platdata *plat;
 324         int ret;
 325         u64 start_clock, finish_clock;
 326
 327         /*
 328          * we request the IRQ with a (possibly percpu) struct arm_pmu**, but
 329          * the handlers expect a struct arm_pmu*. The percpu_irq framework will
 330          * do any necessary shifting, we just need to perform the first
 331          * dereference.
 332          */
 333         armpmu = *(void **)dev;
 334         plat_device = armpmu->plat_device;
 335         plat = dev_get_platdata(&plat_device->dev);
 336
 337         start_clock = sched_clock();
 338         if (plat && plat->handle_irq)
 339                 ret = plat->handle_irq(irq, armpmu, armpmu->handle_irq);
 340         else
 341                 ret = armpmu->handle_irq(irq, armpmu);
 342         finish_clock = sched_clock();
 343
 344         perf_sample_event_took(finish_clock - start_clock);
 345         return ret;
 346 }
 347
 348 static int
 349 event_requires_mode_exclusion(struct perf_event_attr *attr)
 350 {
 351         return attr->exclude_idle || attr->exclude_user ||
 352                attr->exclude_kernel || attr->exclude_hv;
 353 }
 354
 355 static int
 356 __hw_perf_event_init(struct perf_event *event)
 357 {
 358         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 359         struct hw_perf_event *hwc = &event->hw;
 360         int mapping;
 361
 362         mapping = armpmu->map_event(event);
 363
 364         if (mapping < 0) {
 365                 pr_debug("event %x:%llx not supported\n", event->attr.type,
 366                          event->attr.config);
 367                 return mapping;
 368         }
 369
 370         /*
 371          * We don't assign an index until we actually place the event onto
 372          * hardware. Use -1 to signify that we haven't decided where to put it
 373          * yet. For SMP systems, each core has it's own PMU so we can't do any
 374          * clever allocation or constraints checking at this point.
 375          */
 376         hwc->idx                = -1;
 377         hwc->config_base        = 0;
 378         hwc->config             = 0;
 379         hwc->event_base         = 0;
 380
 381         /*
 382          * Check whether we need to exclude the counter from certain modes.
 383          */
 384         if ((!armpmu->set_event_filter ||
 385              armpmu->set_event_filter(hwc, &event->attr)) &&
 386              event_requires_mode_exclusion(&event->attr)) {
 387                 pr_debug("ARM performance counters do not support "
 388                          "mode exclusion\n");
 389                 return -EOPNOTSUPP;
 390         }
 391
 392         /*
 393          * Store the event encoding into the config_base field.
 394          */
 395         hwc->config_base            |= (unsigned long)mapping;
 396
 397         if (!is_sampling_event(event)) {
 398                 /*
 399                  * For non-sampling runs, limit the sample_period to half
 400                  * of the counter width. That way, the new counter value
 401                  * is far less likely to overtake the previous one unless
 402                  * you have some serious IRQ latency issues.
 403                  */
 404                 hwc->sample_period  = armpmu->max_period >> 1;
 405                 hwc->last_period    = hwc->sample_period;
 406                 local64_set(&hwc->period_left, hwc->sample_period);
 407         }
 408
 409         if (event->group_leader != event) {
 410                 if (validate_group(event) != 0)
 411                         return -EINVAL;
 412         }
 413
 414         return 0;
 415 }
 416
 417 static int armpmu_event_init(struct perf_event *event)
 418 {
 419         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 420
 421         /*
 422          * Reject CPU-affine events for CPUs that are of a different class to
 423          * that which this PMU handles. Process-following events (where
 424          * event->cpu == -1) can be migrated between CPUs, and thus we have to
 425          * reject them later (in armpmu_add) if they're scheduled on a
 426          * different class of CPU.
 427          */
 428         if (event->cpu != -1 &&
 429                 !cpumask_test_cpu(event->cpu, &armpmu->supported_cpus))
 430                 return -ENOENT;
 431
 432         /* does not support taken branch sampling */
 433         if (has_branch_stack(event))
 434                 return -EOPNOTSUPP;
 435
 436         if (armpmu->map_event(event) == -ENOENT)
 437                 return -ENOENT;
 438
 439         return __hw_perf_event_init(event);
 440 }
 441
 442 static void armpmu_enable(struct pmu *pmu)
 443 {
 444         struct arm_pmu *armpmu = to_arm_pmu(pmu);
 445         struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
 446         int enabled = bitmap_weight(hw_events->used_mask, armpmu->num_events);
 447
 448         /* For task-bound events we may be called on other CPUs */
 449         if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus))
 450                 return;
 451
 452         if (enabled)
 453                 armpmu->start(armpmu);
 454 }
 455
 456 static void armpmu_disable(struct pmu *pmu)
 457 {
 458         struct arm_pmu *armpmu = to_arm_pmu(pmu);
 459
 460         /* For task-bound events we may be called on other CPUs */
 461         if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus))
 462                 return;
 463
 464         armpmu->stop(armpmu);
 465 }
 466
 467 /*
 468  * In heterogeneous systems, events are specific to a particular
 469  * microarchitecture, and aren't suitable for another. Thus, only match CPUs of
 470  * the same microarchitecture.
 471  */
 472 static int armpmu_filter_match(struct perf_event *event)
 473 {
 474         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 475         unsigned int cpu = smp_processor_id();
 476         return cpumask_test_cpu(cpu, &armpmu->supported_cpus);
 477 }
 478
 479 static ssize_t armpmu_cpumask_show(struct device *dev,
 480                                    struct device_attribute *attr, char *buf)
 481 {
 482         struct arm_pmu *armpmu = to_arm_pmu(dev_get_drvdata(dev));
 483         return cpumap_print_to_pagebuf(true, buf, &armpmu->supported_cpus);
 484 }
 485
 486 static DEVICE_ATTR(cpus, S_IRUGO, armpmu_cpumask_show, NULL);
 487
 488 static struct attribute *armpmu_common_attrs[] = {
 489         &dev_attr_cpus.attr,
 490         NULL,
 491 };
 492
 493 static struct attribute_group armpmu_common_attr_group = {
 494         .attrs = armpmu_common_attrs,
 495 };
 496
 497 /* Set at runtime when we know what CPU type we are. */
 498 static struct arm_pmu *__oprofile_cpu_pmu;
 499
 500 /*
 501  * Despite the names, these two functions are CPU-specific and are used
 502  * by the OProfile/perf code.
 503  */
 504 const char *perf_pmu_name(void)
 505 {
 506         if (!__oprofile_cpu_pmu)
 507                 return NULL;
 508
 509         return __oprofile_cpu_pmu->name;
 510 }
 511 EXPORT_SYMBOL_GPL(perf_pmu_name);
 512
 513 int perf_num_counters(void)
 514 {
 515         int max_events = 0;
 516
 517         if (__oprofile_cpu_pmu != NULL)
 518                 max_events = __oprofile_cpu_pmu->num_events;
 519
 520         return max_events;
 521 }
 522 EXPORT_SYMBOL_GPL(perf_num_counters);
 523
 524 static void cpu_pmu_free_irqs(struct arm_pmu *cpu_pmu)
 525 {
 526         int cpu;
 527         struct pmu_hw_events __percpu *hw_events = cpu_pmu->hw_events;
 528
 529         for_each_cpu(cpu, &cpu_pmu->supported_cpus) {
 530                 int irq = per_cpu(hw_events->irq, cpu);
 531                 if (!irq)
 532                         continue;
 533
 534                 if (irq_is_percpu(irq)) {
 535                         free_percpu_irq(irq, &hw_events->percpu_pmu);
 536                         break;
 537                 }
 538
 539                 if (!cpumask_test_and_clear_cpu(cpu, &cpu_pmu->active_irqs))
 540                         continue;
 541
 542                 free_irq(irq, per_cpu_ptr(&hw_events->percpu_pmu, cpu));
 543         }
 544 }
 545
 546 static int cpu_pmu_request_irqs(struct arm_pmu *cpu_pmu, irq_handler_t handler)
 547 {
 548         int cpu, err;
 549         struct pmu_hw_events __percpu *hw_events = cpu_pmu->hw_events;
 550
 551         for_each_cpu(cpu, &cpu_pmu->supported_cpus) {
 552                 int irq = per_cpu(hw_events->irq, cpu);
 553                 if (!irq)
 554                         continue;
 555
 556                 if (irq_is_percpu(irq)) {
 557                         err = request_percpu_irq(irq, handler, "arm-pmu",
 558                                                  &hw_events->percpu_pmu);
 559                         if (err) {
 560                                 pr_err("unable to request IRQ%d for ARM PMU counters\n",
 561                                         irq);
 562                         }
 563
 564                         return err;
 565                 }
 566
 567                 err = request_irq(irq, handler,
 568                                   IRQF_NOBALANCING | IRQF_NO_THREAD, "arm-pmu",
 569                                   per_cpu_ptr(&hw_events->percpu_pmu, cpu));
 570                 if (err) {
 571                         pr_err("unable to request IRQ%d for ARM PMU counters\n",
 572                                 irq);
 573                         return err;
 574                 }
 575
 576                 cpumask_set_cpu(cpu, &cpu_pmu->active_irqs);
 577         }
 578
 579         return 0;
 580 }
 581
 582 static int armpmu_get_cpu_irq(struct arm_pmu *pmu, int cpu)
 583 {
 584         struct pmu_hw_events __percpu *hw_events = pmu->hw_events;
 585         return per_cpu(hw_events->irq, cpu);
 586 }
 587
 588 /*
 589  * PMU hardware loses all context when a CPU goes offline.
 590  * When a CPU is hotplugged back in, since some hardware registers are
 591  * UNKNOWN at reset, the PMU must be explicitly reset to avoid reading
 592  * junk values out of them.
 593  */
 594 static int arm_perf_starting_cpu(unsigned int cpu, struct hlist_node *node)
 595 {
 596         struct arm_pmu *pmu = hlist_entry_safe(node, struct arm_pmu, node);
 597         int irq;
 598
 599         if (!cpumask_test_cpu(cpu, &pmu->supported_cpus))
 600                 return 0;
 601         if (pmu->reset)
 602                 pmu->reset(pmu);
 603
 604         irq = armpmu_get_cpu_irq(pmu, cpu);
 605         if (irq) {
 606                 if (irq_is_percpu(irq)) {
 607                         enable_percpu_irq(irq, IRQ_TYPE_NONE);
 608                         return 0;
 609                 }
 610
 611                 if (irq_force_affinity(irq, cpumask_of(cpu)) &&
 612                     num_possible_cpus() > 1) {
 613                         pr_warn("unable to set irq affinity (irq=%d, cpu=%u)\n",
 614                                 irq, cpu);
 615                 }
 616         }
 617
 618         return 0;
 619 }
 620
 621 static int arm_perf_teardown_cpu(unsigned int cpu, struct hlist_node *node)
 622 {
 623         struct arm_pmu *pmu = hlist_entry_safe(node, struct arm_pmu, node);
 624         int irq;
 625
 626         if (!cpumask_test_cpu(cpu, &pmu->supported_cpus))
 627                 return 0;
 628
 629         irq = armpmu_get_cpu_irq(pmu, cpu);
 630         if (irq && irq_is_percpu(irq))
 631                 disable_percpu_irq(irq);
 632
 633         return 0;
 634 }
 635
 636 #ifdef CONFIG_CPU_PM
 637 static void cpu_pm_pmu_setup(struct arm_pmu *armpmu, unsigned long cmd)
 638 {
 639         struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
 640         struct perf_event *event;
 641         int idx;
 642
 643         for (idx = 0; idx < armpmu->num_events; idx++) {
 644                 /*
 645                  * If the counter is not used skip it, there is no
 646                  * need of stopping/restarting it.
 647                  */
 648                 if (!test_bit(idx, hw_events->used_mask))
 649                         continue;
 650
 651                 event = hw_events->events[idx];
 652
 653                 switch (cmd) {
 654                 case CPU_PM_ENTER:
 655                         /*
 656                          * Stop and update the counter
 657                          */
 658                         armpmu_stop(event, PERF_EF_UPDATE);
 659                         break;
 660                 case CPU_PM_EXIT:
 661                 case CPU_PM_ENTER_FAILED:
 662                          /*
 663                           * Restore and enable the counter.
 664                           * armpmu_start() indirectly calls
 665                           *
 666                           * perf_event_update_userpage()
 667                           *
 668                           * that requires RCU read locking to be functional,
 669                           * wrap the call within RCU_NONIDLE to make the
 670                           * RCU subsystem aware this cpu is not idle from
 671                           * an RCU perspective for the armpmu_start() call
 672                           * duration.
 673                           */
 674                         RCU_NONIDLE(armpmu_start(event, PERF_EF_RELOAD));
 675                         break;
 676                 default:
 677                         break;
 678                 }
 679         }
 680 }
 681
 682 static int cpu_pm_pmu_notify(struct notifier_block *b, unsigned long cmd,
 683                              void *v)
 684 {
 685         struct arm_pmu *armpmu = container_of(b, struct arm_pmu, cpu_pm_nb);
 686         struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
 687         int enabled = bitmap_weight(hw_events->used_mask, armpmu->num_events);
 688
 689         if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus))
 690                 return NOTIFY_DONE;
 691
 692         /*
 693          * Always reset the PMU registers on power-up even if
 694          * there are no events running.
 695          */
 696         if (cmd == CPU_PM_EXIT && armpmu->reset)
 697                 armpmu->reset(armpmu);
 698
 699         if (!enabled)
 700                 return NOTIFY_OK;
 701
 702         switch (cmd) {
 703         case CPU_PM_ENTER:
 704                 armpmu->stop(armpmu);
 705                 cpu_pm_pmu_setup(armpmu, cmd);
 706                 break;
 707         case CPU_PM_EXIT:
 708                 cpu_pm_pmu_setup(armpmu, cmd);
 709         case CPU_PM_ENTER_FAILED:
 710                 armpmu->start(armpmu);
 711                 break;
 712         default:
 713                 return NOTIFY_DONE;
 714         }
 715
 716         return NOTIFY_OK;
 717 }
 718
 719 static int cpu_pm_pmu_register(struct arm_pmu *cpu_pmu)
 720 {
 721         cpu_pmu->cpu_pm_nb.notifier_call = cpu_pm_pmu_notify;
 722         return cpu_pm_register_notifier(&cpu_pmu->cpu_pm_nb);
 723 }
 724
 725 static void cpu_pm_pmu_unregister(struct arm_pmu *cpu_pmu)
 726 {
 727         cpu_pm_unregister_notifier(&cpu_pmu->cpu_pm_nb);
 728 }
 729 #else
 730 static inline int cpu_pm_pmu_register(struct arm_pmu *cpu_pmu) { return 0; }
 731 static inline void cpu_pm_pmu_unregister(struct arm_pmu *cpu_pmu) { }
 732 #endif
 733
 734 static int cpu_pmu_init(struct arm_pmu *cpu_pmu)
 735 {
 736         int err;
 737
 738         err = cpu_pmu_request_irqs(cpu_pmu, armpmu_dispatch_irq);
 739         if (err)
 740                 goto out;
 741
 742         err = cpuhp_state_add_instance(CPUHP_AP_PERF_ARM_STARTING,
 743                                        &cpu_pmu->node);
 744         if (err)
 745                 goto out;
 746
 747         err = cpu_pm_pmu_register(cpu_pmu);
 748         if (err)
 749                 goto out_unregister;
 750
 751         return 0;
 752
 753 out_unregister:
 754         cpuhp_state_remove_instance_nocalls(CPUHP_AP_PERF_ARM_STARTING,
 755                                             &cpu_pmu->node);
 756 out:
 757         cpu_pmu_free_irqs(cpu_pmu);
 758         return err;
 759 }
 760
 761 static void cpu_pmu_destroy(struct arm_pmu *cpu_pmu)
 762 {
 763         cpu_pm_pmu_unregister(cpu_pmu);
 764         cpuhp_state_remove_instance_nocalls(CPUHP_AP_PERF_ARM_STARTING,
 765                                             &cpu_pmu->node);
 766 }
 767
 768 /*
 769  * CPU PMU identification and probing.
 770  */
 771 static int probe_current_pmu(struct arm_pmu *pmu,
 772                              const struct pmu_probe_info *info)
 773 {
 774         int cpu = get_cpu();
 775         unsigned int cpuid = read_cpuid_id();
 776         int ret = -ENODEV;
 777
 778         pr_info("probing PMU on CPU %d\n", cpu);
 779
 780         for (; info->init != NULL; info++) {
 781                 if ((cpuid & info->mask) != info->cpuid)
 782                         continue;
 783                 ret = info->init(pmu);
 784                 break;
 785         }
 786
 787         put_cpu();
 788         return ret;
 789 }
 790
 791 static int pmu_parse_percpu_irq(struct arm_pmu *pmu, int irq)
 792 {
 793         int cpu, ret;
 794         struct pmu_hw_events __percpu *hw_events = pmu->hw_events;
 795
 796         ret = irq_get_percpu_devid_partition(irq, &pmu->supported_cpus);
 797         if (ret)
 798                 return ret;
 799
 800         for_each_cpu(cpu, &pmu->supported_cpus)
 801                 per_cpu(hw_events->irq, cpu) = irq;
 802
 803         return 0;
 804 }
 805
 806 static bool pmu_has_irq_affinity(struct device_node *node)
 807 {
 808         return !!of_find_property(node, "interrupt-affinity", NULL);
 809 }
 810
 811 static int pmu_parse_irq_affinity(struct device_node *node, int i)
 812 {
 813         struct device_node *dn;
 814         int cpu;
 815
 816         /*
 817          * If we don't have an interrupt-affinity property, we guess irq
 818          * affinity matches our logical CPU order, as we used to assume.
 819          * This is fragile, so we'll warn in pmu_parse_irqs().
 820          */
 821         if (!pmu_has_irq_affinity(node))
 822                 return i;
 823
 824         dn = of_parse_phandle(node, "interrupt-affinity", i);
 825         if (!dn) {
 826                 pr_warn("failed to parse interrupt-affinity[%d] for %s\n",
 827                         i, node->name);
 828                 return -EINVAL;
 829         }
 830
 831         /* Now look up the logical CPU number */
 832         for_each_possible_cpu(cpu) {
 833                 struct device_node *cpu_dn;
 834
 835                 cpu_dn = of_cpu_device_node_get(cpu);
 836                 of_node_put(cpu_dn);
 837
 838                 if (dn == cpu_dn)
 839                         break;
 840         }
 841
 842         if (cpu >= nr_cpu_ids) {
 843                 pr_warn("failed to find logical CPU for %s\n", dn->name);
 844         }
 845
 846         of_node_put(dn);
 847
 848         return cpu;
 849 }
 850
 851 static int pmu_parse_irqs(struct arm_pmu *pmu)
 852 {
 853         int i = 0, irqs;
 854         struct platform_device *pdev = pmu->plat_device;
 855         struct pmu_hw_events __percpu *hw_events = pmu->hw_events;
 856
 857         irqs = platform_irq_count(pdev);
 858         if (irqs < 0) {
 859                 pr_err("unable to count PMU IRQs\n");
 860                 return irqs;
 861         }
 862
 863         /*
 864          * In this case we have no idea which CPUs are covered by the PMU.
 865          * To match our prior behaviour, we assume all CPUs in this case.
 866          */
 867         if (irqs == 0) {
 868                 pr_warn("no irqs for PMU, sampling events not supported\n");
 869                 pmu->pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;
 870                 cpumask_setall(&pmu->supported_cpus);
 871                 return 0;
 872         }
 873
 874         if (irqs == 1) {
 875                 int irq = platform_get_irq(pdev, 0);
 876                 if (irq && irq_is_percpu(irq))
 877                         return pmu_parse_percpu_irq(pmu, irq);
 878         }
 879
 880         if (!pmu_has_irq_affinity(pdev->dev.of_node)) {
 881                 pr_warn("no interrupt-affinity property for %s, guessing.\n",
 882                         of_node_full_name(pdev->dev.of_node));
 883         }
 884
 885         /*
 886          * Some platforms have all PMU IRQs OR'd into a single IRQ, with a
 887          * special platdata function that attempts to demux them.
 888          */
 889         if (dev_get_platdata(&pdev->dev))
 890                 cpumask_setall(&pmu->supported_cpus);
 891
 892         for (i = 0; i < irqs; i++) {
 893                 int cpu, irq;
 894
 895                 irq = platform_get_irq(pdev, i);
 896                 if (WARN_ON(irq <= 0))
 897                         continue;
 898
 899                 if (irq_is_percpu(irq)) {
 900                         pr_warn("multiple PPIs or mismatched SPI/PPI detected\n");
 901                         return -EINVAL;
 902                 }
 903
 904                 cpu = pmu_parse_irq_affinity(pdev->dev.of_node, i);
 905                 if (cpu < 0)
 906                         return cpu;
 907                 if (cpu >= nr_cpu_ids)
 908                         continue;
 909
 910                 if (per_cpu(hw_events->irq, cpu)) {
 911                         pr_warn("multiple PMU IRQs for the same CPU detected\n");
 912                         return -EINVAL;
 913                 }
 914
 915                 per_cpu(hw_events->irq, cpu) = irq;
 916                 cpumask_set_cpu(cpu, &pmu->supported_cpus);
 917         }
 918
 919         return 0;
 920 }
 921
 922 static struct arm_pmu *armpmu_alloc(void)
 923 {
 924         struct arm_pmu *pmu;
 925         int cpu;
 926
 927         pmu = kzalloc(sizeof(*pmu), GFP_KERNEL);
 928         if (!pmu) {
 929                 pr_info("failed to allocate PMU device!\n");
 930                 goto out;
 931         }
 932
 933         pmu->hw_events = alloc_percpu(struct pmu_hw_events);
 934         if (!pmu->hw_events) {
 935                 pr_info("failed to allocate per-cpu PMU data.\n");
 936                 goto out_free_pmu;
 937         }
 938
 939         pmu->pmu = (struct pmu) {
 940                 .pmu_enable     = armpmu_enable,
 941                 .pmu_disable    = armpmu_disable,
 942                 .event_init     = armpmu_event_init,
 943                 .add            = armpmu_add,
 944                 .del            = armpmu_del,
 945                 .start          = armpmu_start,
 946                 .stop           = armpmu_stop,
 947                 .read           = armpmu_read,
 948                 .filter_match   = armpmu_filter_match,
 949                 .attr_groups    = pmu->attr_groups,
 950                 /*
 951                  * This is a CPU PMU potentially in a heterogeneous
 952                  * configuration (e.g. big.LITTLE). This is not an uncore PMU,
 953                  * and we have taken ctx sharing into account (e.g. with our
 954                  * pmu::filter_match callback and pmu::event_init group
 955                  * validation).
 956                  */
 957                 .capabilities   = PERF_PMU_CAP_HETEROGENEOUS_CPUS,
 958         };
 959
 960         pmu->attr_groups[ARMPMU_ATTR_GROUP_COMMON] =
 961                 &armpmu_common_attr_group;
 962
 963         for_each_possible_cpu(cpu) {
 964                 struct pmu_hw_events *events;
 965
 966                 events = per_cpu_ptr(pmu->hw_events, cpu);
 967                 raw_spin_lock_init(&events->pmu_lock);
 968                 events->percpu_pmu = pmu;
 969         }
 970
 971         return pmu;
 972
 973 out_free_pmu:
 974         kfree(pmu);
 975 out:
 976         return NULL;
 977 }
 978
 979 static void armpmu_free(struct arm_pmu *pmu)
 980 {
 981         free_percpu(pmu->hw_events);
 982         kfree(pmu);
 983 }
 984
 985 int arm_pmu_device_probe(struct platform_device *pdev,
 986                          const struct of_device_id *of_table,
 987                          const struct pmu_probe_info *probe_table)
 988 {
 989         const struct of_device_id *of_id;
 990         armpmu_init_fn init_fn;
 991         struct device_node *node = pdev->dev.of_node;
 992         struct arm_pmu *pmu;
 993         int ret = -ENODEV;
 994
 995         pmu = armpmu_alloc();
 996         if (!pmu)
 997                 return -ENOMEM;
 998
 999         pmu->plat_device = pdev;
1000
1001         ret = pmu_parse_irqs(pmu);
1002         if (ret)
1003                 goto out_free;
1004
1005         if (node && (of_id = of_match_node(of_table, pdev->dev.of_node))) {
1006                 init_fn = of_id->data;
1007
1008                 pmu->secure_access = of_property_read_bool(pdev->dev.of_node,
1009                                                            "secure-reg-access");
1010
1011                 /* arm64 systems boot only as non-secure */
1012                 if (IS_ENABLED(CONFIG_ARM64) && pmu->secure_access) {
1013                         pr_warn("ignoring \"secure-reg-access\" property for arm64\n");
1014                         pmu->secure_access = false;
1015                 }
1016
1017                 ret = init_fn(pmu);
1018         } else if (probe_table) {
1019                 cpumask_setall(&pmu->supported_cpus);
1020                 ret = probe_current_pmu(pmu, probe_table);
1021         }
1022
1023         if (ret) {
1024                 pr_info("%s: failed to probe PMU!\n", of_node_full_name(node));
1025                 goto out_free;
1026         }
1027
1028
1029         ret = cpu_pmu_init(pmu);
1030         if (ret)
1031                 goto out_free;
1032
1033         ret = perf_pmu_register(&pmu->pmu, pmu->name, -1);
1034         if (ret)
1035                 goto out_destroy;
1036
1037         if (!__oprofile_cpu_pmu)
1038                 __oprofile_cpu_pmu = pmu;
1039
1040         pr_info("enabled with %s PMU driver, %d counters available\n",
1041                         pmu->name, pmu->num_events);
1042
1043         return 0;
1044
1045 out_destroy:
1046         cpu_pmu_destroy(pmu);
1047 out_free:
1048         pr_info("%s: failed to register PMU devices!\n",
1049                 of_node_full_name(node));
1050         armpmu_free(pmu);
1051         return ret;
1052 }
1053
1054 static int arm_pmu_hp_init(void)
1055 {
1056         int ret;
1057
1058         ret = cpuhp_setup_state_multi(CPUHP_AP_PERF_ARM_STARTING,
1059                                       "perf/arm/pmu:starting",
1060                                       arm_perf_starting_cpu,
1061                                       arm_perf_teardown_cpu);
1062         if (ret)
1063                 pr_err("CPU hotplug notifier for ARM PMU could not be registered: %d\n",
1064                        ret);
1065         return ret;
1066 }
1067 subsys_initcall(arm_pmu_hp_init);