4 * ARM performance counter support.
6 * Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles
7 * Copyright (C) 2010 ARM Ltd., Will Deacon <will.deacon@arm.com>
9 * This code is based on the sparc64 perf event code, which is in turn based
12 #define pr_fmt(fmt) "hw perfevents: " fmt
14 #include <linux/bitmap.h>
15 #include <linux/cpumask.h>
16 #include <linux/cpu_pm.h>
17 #include <linux/export.h>
18 #include <linux/kernel.h>
19 #include <linux/of_device.h>
20 #include <linux/perf/arm_pmu.h>
21 #include <linux/platform_device.h>
22 #include <linux/slab.h>
23 #include <linux/sched/clock.h>
24 #include <linux/spinlock.h>
25 #include <linux/irq.h>
26 #include <linux/irqdesc.h>
28 #include <asm/cputype.h>
29 #include <asm/irq_regs.h>
32 armpmu_map_cache_event(const unsigned (*cache_map)
33 [PERF_COUNT_HW_CACHE_MAX]
34 [PERF_COUNT_HW_CACHE_OP_MAX]
35 [PERF_COUNT_HW_CACHE_RESULT_MAX],
38 unsigned int cache_type, cache_op, cache_result, ret;
40 cache_type = (config >> 0) & 0xff;
41 if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
44 cache_op = (config >> 8) & 0xff;
45 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
48 cache_result = (config >> 16) & 0xff;
49 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
52 ret = (int)(*cache_map)[cache_type][cache_op][cache_result];
54 if (ret == CACHE_OP_UNSUPPORTED)
61 armpmu_map_hw_event(const unsigned (*event_map)[PERF_COUNT_HW_MAX], u64 config)
65 if (config >= PERF_COUNT_HW_MAX)
68 mapping = (*event_map)[config];
69 return mapping == HW_OP_UNSUPPORTED ? -ENOENT : mapping;
73 armpmu_map_raw_event(u32 raw_event_mask, u64 config)
75 return (int)(config & raw_event_mask);
79 armpmu_map_event(struct perf_event *event,
80 const unsigned (*event_map)[PERF_COUNT_HW_MAX],
81 const unsigned (*cache_map)
82 [PERF_COUNT_HW_CACHE_MAX]
83 [PERF_COUNT_HW_CACHE_OP_MAX]
84 [PERF_COUNT_HW_CACHE_RESULT_MAX],
87 u64 config = event->attr.config;
88 int type = event->attr.type;
90 if (type == event->pmu->type)
91 return armpmu_map_raw_event(raw_event_mask, config);
94 case PERF_TYPE_HARDWARE:
95 return armpmu_map_hw_event(event_map, config);
96 case PERF_TYPE_HW_CACHE:
97 return armpmu_map_cache_event(cache_map, config);
99 return armpmu_map_raw_event(raw_event_mask, config);
105 int armpmu_event_set_period(struct perf_event *event)
107 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
108 struct hw_perf_event *hwc = &event->hw;
109 s64 left = local64_read(&hwc->period_left);
110 s64 period = hwc->sample_period;
113 if (unlikely(left <= -period)) {
115 local64_set(&hwc->period_left, left);
116 hwc->last_period = period;
120 if (unlikely(left <= 0)) {
122 local64_set(&hwc->period_left, left);
123 hwc->last_period = period;
128 * Limit the maximum period to prevent the counter value
129 * from overtaking the one we are about to program. In
130 * effect we are reducing max_period to account for
131 * interrupt latency (and we are being very conservative).
133 if (left > (armpmu->max_period >> 1))
134 left = armpmu->max_period >> 1;
136 local64_set(&hwc->prev_count, (u64)-left);
138 armpmu->write_counter(event, (u64)(-left) & 0xffffffff);
140 perf_event_update_userpage(event);
145 u64 armpmu_event_update(struct perf_event *event)
147 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
148 struct hw_perf_event *hwc = &event->hw;
149 u64 delta, prev_raw_count, new_raw_count;
152 prev_raw_count = local64_read(&hwc->prev_count);
153 new_raw_count = armpmu->read_counter(event);
155 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
156 new_raw_count) != prev_raw_count)
159 delta = (new_raw_count - prev_raw_count) & armpmu->max_period;
161 local64_add(delta, &event->count);
162 local64_sub(delta, &hwc->period_left);
164 return new_raw_count;
168 armpmu_read(struct perf_event *event)
170 armpmu_event_update(event);
174 armpmu_stop(struct perf_event *event, int flags)
176 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
177 struct hw_perf_event *hwc = &event->hw;
180 * ARM pmu always has to update the counter, so ignore
181 * PERF_EF_UPDATE, see comments in armpmu_start().
183 if (!(hwc->state & PERF_HES_STOPPED)) {
184 armpmu->disable(event);
185 armpmu_event_update(event);
186 hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
190 static void armpmu_start(struct perf_event *event, int flags)
192 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
193 struct hw_perf_event *hwc = &event->hw;
196 * ARM pmu always has to reprogram the period, so ignore
197 * PERF_EF_RELOAD, see the comment below.
199 if (flags & PERF_EF_RELOAD)
200 WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
204 * Set the period again. Some counters can't be stopped, so when we
205 * were stopped we simply disabled the IRQ source and the counter
206 * may have been left counting. If we don't do this step then we may
207 * get an interrupt too soon or *way* too late if the overflow has
208 * happened since disabling.
210 armpmu_event_set_period(event);
211 armpmu->enable(event);
215 armpmu_del(struct perf_event *event, int flags)
217 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
218 struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
219 struct hw_perf_event *hwc = &event->hw;
222 armpmu_stop(event, PERF_EF_UPDATE);
223 hw_events->events[idx] = NULL;
224 clear_bit(idx, hw_events->used_mask);
225 if (armpmu->clear_event_idx)
226 armpmu->clear_event_idx(hw_events, event);
228 perf_event_update_userpage(event);
232 armpmu_add(struct perf_event *event, int flags)
234 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
235 struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
236 struct hw_perf_event *hwc = &event->hw;
239 /* An event following a process won't be stopped earlier */
240 if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus))
243 /* If we don't have a space for the counter then finish early. */
244 idx = armpmu->get_event_idx(hw_events, event);
249 * If there is an event in the counter we are going to use then make
250 * sure it is disabled.
253 armpmu->disable(event);
254 hw_events->events[idx] = event;
256 hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
257 if (flags & PERF_EF_START)
258 armpmu_start(event, PERF_EF_RELOAD);
260 /* Propagate our changes to the userspace mapping. */
261 perf_event_update_userpage(event);
267 validate_event(struct pmu *pmu, struct pmu_hw_events *hw_events,
268 struct perf_event *event)
270 struct arm_pmu *armpmu;
272 if (is_software_event(event))
276 * Reject groups spanning multiple HW PMUs (e.g. CPU + CCI). The
277 * core perf code won't check that the pmu->ctx == leader->ctx
278 * until after pmu->event_init(event).
280 if (event->pmu != pmu)
283 if (event->state < PERF_EVENT_STATE_OFF)
286 if (event->state == PERF_EVENT_STATE_OFF && !event->attr.enable_on_exec)
289 armpmu = to_arm_pmu(event->pmu);
290 return armpmu->get_event_idx(hw_events, event) >= 0;
294 validate_group(struct perf_event *event)
296 struct perf_event *sibling, *leader = event->group_leader;
297 struct pmu_hw_events fake_pmu;
300 * Initialise the fake PMU. We only need to populate the
301 * used_mask for the purposes of validation.
303 memset(&fake_pmu.used_mask, 0, sizeof(fake_pmu.used_mask));
305 if (!validate_event(event->pmu, &fake_pmu, leader))
308 list_for_each_entry(sibling, &leader->sibling_list, group_entry) {
309 if (!validate_event(event->pmu, &fake_pmu, sibling))
313 if (!validate_event(event->pmu, &fake_pmu, event))
319 static struct arm_pmu_platdata *armpmu_get_platdata(struct arm_pmu *armpmu)
321 struct platform_device *pdev = armpmu->plat_device;
323 return pdev ? dev_get_platdata(&pdev->dev) : NULL;
326 static irqreturn_t armpmu_dispatch_irq(int irq, void *dev)
328 struct arm_pmu *armpmu;
329 struct arm_pmu_platdata *plat;
331 u64 start_clock, finish_clock;
334 * we request the IRQ with a (possibly percpu) struct arm_pmu**, but
335 * the handlers expect a struct arm_pmu*. The percpu_irq framework will
336 * do any necessary shifting, we just need to perform the first
339 armpmu = *(void **)dev;
341 plat = armpmu_get_platdata(armpmu);
343 start_clock = sched_clock();
344 if (plat && plat->handle_irq)
345 ret = plat->handle_irq(irq, armpmu, armpmu->handle_irq);
347 ret = armpmu->handle_irq(irq, armpmu);
348 finish_clock = sched_clock();
350 perf_sample_event_took(finish_clock - start_clock);
355 event_requires_mode_exclusion(struct perf_event_attr *attr)
357 return attr->exclude_idle || attr->exclude_user ||
358 attr->exclude_kernel || attr->exclude_hv;
362 __hw_perf_event_init(struct perf_event *event)
364 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
365 struct hw_perf_event *hwc = &event->hw;
368 mapping = armpmu->map_event(event);
371 pr_debug("event %x:%llx not supported\n", event->attr.type,
377 * We don't assign an index until we actually place the event onto
378 * hardware. Use -1 to signify that we haven't decided where to put it
379 * yet. For SMP systems, each core has it's own PMU so we can't do any
380 * clever allocation or constraints checking at this point.
383 hwc->config_base = 0;
388 * Check whether we need to exclude the counter from certain modes.
390 if ((!armpmu->set_event_filter ||
391 armpmu->set_event_filter(hwc, &event->attr)) &&
392 event_requires_mode_exclusion(&event->attr)) {
393 pr_debug("ARM performance counters do not support "
399 * Store the event encoding into the config_base field.
401 hwc->config_base |= (unsigned long)mapping;
403 if (!is_sampling_event(event)) {
405 * For non-sampling runs, limit the sample_period to half
406 * of the counter width. That way, the new counter value
407 * is far less likely to overtake the previous one unless
408 * you have some serious IRQ latency issues.
410 hwc->sample_period = armpmu->max_period >> 1;
411 hwc->last_period = hwc->sample_period;
412 local64_set(&hwc->period_left, hwc->sample_period);
415 if (event->group_leader != event) {
416 if (validate_group(event) != 0)
423 static int armpmu_event_init(struct perf_event *event)
425 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
428 * Reject CPU-affine events for CPUs that are of a different class to
429 * that which this PMU handles. Process-following events (where
430 * event->cpu == -1) can be migrated between CPUs, and thus we have to
431 * reject them later (in armpmu_add) if they're scheduled on a
432 * different class of CPU.
434 if (event->cpu != -1 &&
435 !cpumask_test_cpu(event->cpu, &armpmu->supported_cpus))
438 /* does not support taken branch sampling */
439 if (has_branch_stack(event))
442 if (armpmu->map_event(event) == -ENOENT)
445 return __hw_perf_event_init(event);
448 static void armpmu_enable(struct pmu *pmu)
450 struct arm_pmu *armpmu = to_arm_pmu(pmu);
451 struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
452 int enabled = bitmap_weight(hw_events->used_mask, armpmu->num_events);
454 /* For task-bound events we may be called on other CPUs */
455 if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus))
459 armpmu->start(armpmu);
462 static void armpmu_disable(struct pmu *pmu)
464 struct arm_pmu *armpmu = to_arm_pmu(pmu);
466 /* For task-bound events we may be called on other CPUs */
467 if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus))
470 armpmu->stop(armpmu);
474 * In heterogeneous systems, events are specific to a particular
475 * microarchitecture, and aren't suitable for another. Thus, only match CPUs of
476 * the same microarchitecture.
478 static int armpmu_filter_match(struct perf_event *event)
480 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
481 unsigned int cpu = smp_processor_id();
482 return cpumask_test_cpu(cpu, &armpmu->supported_cpus);
485 static ssize_t armpmu_cpumask_show(struct device *dev,
486 struct device_attribute *attr, char *buf)
488 struct arm_pmu *armpmu = to_arm_pmu(dev_get_drvdata(dev));
489 return cpumap_print_to_pagebuf(true, buf, &armpmu->supported_cpus);
492 static DEVICE_ATTR(cpus, S_IRUGO, armpmu_cpumask_show, NULL);
494 static struct attribute *armpmu_common_attrs[] = {
499 static struct attribute_group armpmu_common_attr_group = {
500 .attrs = armpmu_common_attrs,
503 /* Set at runtime when we know what CPU type we are. */
504 static struct arm_pmu *__oprofile_cpu_pmu;
507 * Despite the names, these two functions are CPU-specific and are used
508 * by the OProfile/perf code.
510 const char *perf_pmu_name(void)
512 if (!__oprofile_cpu_pmu)
515 return __oprofile_cpu_pmu->name;
517 EXPORT_SYMBOL_GPL(perf_pmu_name);
519 int perf_num_counters(void)
523 if (__oprofile_cpu_pmu != NULL)
524 max_events = __oprofile_cpu_pmu->num_events;
528 EXPORT_SYMBOL_GPL(perf_num_counters);
530 static void armpmu_free_irqs(struct arm_pmu *armpmu)
533 struct pmu_hw_events __percpu *hw_events = armpmu->hw_events;
535 for_each_cpu(cpu, &armpmu->supported_cpus) {
536 int irq = per_cpu(hw_events->irq, cpu);
540 if (irq_is_percpu(irq)) {
541 free_percpu_irq(irq, &hw_events->percpu_pmu);
545 if (!cpumask_test_and_clear_cpu(cpu, &armpmu->active_irqs))
548 free_irq(irq, per_cpu_ptr(&hw_events->percpu_pmu, cpu));
552 static int armpmu_request_irqs(struct arm_pmu *armpmu)
555 struct pmu_hw_events __percpu *hw_events = armpmu->hw_events;
556 const irq_handler_t handler = armpmu_dispatch_irq;
558 for_each_cpu(cpu, &armpmu->supported_cpus) {
559 int irq = per_cpu(hw_events->irq, cpu);
563 if (irq_is_percpu(irq)) {
564 err = request_percpu_irq(irq, handler, "arm-pmu",
565 &hw_events->percpu_pmu);
567 pr_err("unable to request IRQ%d for ARM PMU counters\n",
574 err = request_irq(irq, handler,
575 IRQF_NOBALANCING | IRQF_NO_THREAD, "arm-pmu",
576 per_cpu_ptr(&hw_events->percpu_pmu, cpu));
578 pr_err("unable to request IRQ%d for ARM PMU counters\n",
583 cpumask_set_cpu(cpu, &armpmu->active_irqs);
589 static int armpmu_get_cpu_irq(struct arm_pmu *pmu, int cpu)
591 struct pmu_hw_events __percpu *hw_events = pmu->hw_events;
592 return per_cpu(hw_events->irq, cpu);
596 * PMU hardware loses all context when a CPU goes offline.
597 * When a CPU is hotplugged back in, since some hardware registers are
598 * UNKNOWN at reset, the PMU must be explicitly reset to avoid reading
599 * junk values out of them.
601 static int arm_perf_starting_cpu(unsigned int cpu, struct hlist_node *node)
603 struct arm_pmu *pmu = hlist_entry_safe(node, struct arm_pmu, node);
606 if (!cpumask_test_cpu(cpu, &pmu->supported_cpus))
611 irq = armpmu_get_cpu_irq(pmu, cpu);
613 if (irq_is_percpu(irq)) {
614 enable_percpu_irq(irq, IRQ_TYPE_NONE);
618 if (irq_force_affinity(irq, cpumask_of(cpu)) &&
619 num_possible_cpus() > 1) {
620 pr_warn("unable to set irq affinity (irq=%d, cpu=%u)\n",
628 static int arm_perf_teardown_cpu(unsigned int cpu, struct hlist_node *node)
630 struct arm_pmu *pmu = hlist_entry_safe(node, struct arm_pmu, node);
633 if (!cpumask_test_cpu(cpu, &pmu->supported_cpus))
636 irq = armpmu_get_cpu_irq(pmu, cpu);
637 if (irq && irq_is_percpu(irq))
638 disable_percpu_irq(irq);
644 static void cpu_pm_pmu_setup(struct arm_pmu *armpmu, unsigned long cmd)
646 struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
647 struct perf_event *event;
650 for (idx = 0; idx < armpmu->num_events; idx++) {
652 * If the counter is not used skip it, there is no
653 * need of stopping/restarting it.
655 if (!test_bit(idx, hw_events->used_mask))
658 event = hw_events->events[idx];
663 * Stop and update the counter
665 armpmu_stop(event, PERF_EF_UPDATE);
668 case CPU_PM_ENTER_FAILED:
670 * Restore and enable the counter.
671 * armpmu_start() indirectly calls
673 * perf_event_update_userpage()
675 * that requires RCU read locking to be functional,
676 * wrap the call within RCU_NONIDLE to make the
677 * RCU subsystem aware this cpu is not idle from
678 * an RCU perspective for the armpmu_start() call
681 RCU_NONIDLE(armpmu_start(event, PERF_EF_RELOAD));
689 static int cpu_pm_pmu_notify(struct notifier_block *b, unsigned long cmd,
692 struct arm_pmu *armpmu = container_of(b, struct arm_pmu, cpu_pm_nb);
693 struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
694 int enabled = bitmap_weight(hw_events->used_mask, armpmu->num_events);
696 if (!cpumask_test_cpu(smp_processor_id(), &armpmu->supported_cpus))
700 * Always reset the PMU registers on power-up even if
701 * there are no events running.
703 if (cmd == CPU_PM_EXIT && armpmu->reset)
704 armpmu->reset(armpmu);
711 armpmu->stop(armpmu);
712 cpu_pm_pmu_setup(armpmu, cmd);
715 cpu_pm_pmu_setup(armpmu, cmd);
716 case CPU_PM_ENTER_FAILED:
717 armpmu->start(armpmu);
726 static int cpu_pm_pmu_register(struct arm_pmu *cpu_pmu)
728 cpu_pmu->cpu_pm_nb.notifier_call = cpu_pm_pmu_notify;
729 return cpu_pm_register_notifier(&cpu_pmu->cpu_pm_nb);
732 static void cpu_pm_pmu_unregister(struct arm_pmu *cpu_pmu)
734 cpu_pm_unregister_notifier(&cpu_pmu->cpu_pm_nb);
737 static inline int cpu_pm_pmu_register(struct arm_pmu *cpu_pmu) { return 0; }
738 static inline void cpu_pm_pmu_unregister(struct arm_pmu *cpu_pmu) { }
741 static int cpu_pmu_init(struct arm_pmu *cpu_pmu)
745 err = armpmu_request_irqs(cpu_pmu);
749 err = cpuhp_state_add_instance(CPUHP_AP_PERF_ARM_STARTING,
754 err = cpu_pm_pmu_register(cpu_pmu);
761 cpuhp_state_remove_instance_nocalls(CPUHP_AP_PERF_ARM_STARTING,
764 armpmu_free_irqs(cpu_pmu);
768 static void cpu_pmu_destroy(struct arm_pmu *cpu_pmu)
770 cpu_pm_pmu_unregister(cpu_pmu);
771 cpuhp_state_remove_instance_nocalls(CPUHP_AP_PERF_ARM_STARTING,
776 * CPU PMU identification and probing.
778 static int probe_current_pmu(struct arm_pmu *pmu,
779 const struct pmu_probe_info *info)
782 unsigned int cpuid = read_cpuid_id();
785 pr_info("probing PMU on CPU %d\n", cpu);
787 for (; info->init != NULL; info++) {
788 if ((cpuid & info->mask) != info->cpuid)
790 ret = info->init(pmu);
798 static int pmu_parse_percpu_irq(struct arm_pmu *pmu, int irq)
801 struct pmu_hw_events __percpu *hw_events = pmu->hw_events;
803 ret = irq_get_percpu_devid_partition(irq, &pmu->supported_cpus);
807 for_each_cpu(cpu, &pmu->supported_cpus)
808 per_cpu(hw_events->irq, cpu) = irq;
813 static bool pmu_has_irq_affinity(struct device_node *node)
815 return !!of_find_property(node, "interrupt-affinity", NULL);
818 static int pmu_parse_irq_affinity(struct device_node *node, int i)
820 struct device_node *dn;
824 * If we don't have an interrupt-affinity property, we guess irq
825 * affinity matches our logical CPU order, as we used to assume.
826 * This is fragile, so we'll warn in pmu_parse_irqs().
828 if (!pmu_has_irq_affinity(node))
831 dn = of_parse_phandle(node, "interrupt-affinity", i);
833 pr_warn("failed to parse interrupt-affinity[%d] for %s\n",
838 /* Now look up the logical CPU number */
839 for_each_possible_cpu(cpu) {
840 struct device_node *cpu_dn;
842 cpu_dn = of_cpu_device_node_get(cpu);
849 if (cpu >= nr_cpu_ids) {
850 pr_warn("failed to find logical CPU for %s\n", dn->name);
858 static int pmu_parse_irqs(struct arm_pmu *pmu)
861 struct platform_device *pdev = pmu->plat_device;
862 struct pmu_hw_events __percpu *hw_events = pmu->hw_events;
864 irqs = platform_irq_count(pdev);
866 pr_err("unable to count PMU IRQs\n");
871 * In this case we have no idea which CPUs are covered by the PMU.
872 * To match our prior behaviour, we assume all CPUs in this case.
875 pr_warn("no irqs for PMU, sampling events not supported\n");
876 pmu->pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT;
877 cpumask_setall(&pmu->supported_cpus);
882 int irq = platform_get_irq(pdev, 0);
883 if (irq && irq_is_percpu(irq))
884 return pmu_parse_percpu_irq(pmu, irq);
887 if (!pmu_has_irq_affinity(pdev->dev.of_node)) {
888 pr_warn("no interrupt-affinity property for %s, guessing.\n",
889 of_node_full_name(pdev->dev.of_node));
893 * Some platforms have all PMU IRQs OR'd into a single IRQ, with a
894 * special platdata function that attempts to demux them.
896 if (dev_get_platdata(&pdev->dev))
897 cpumask_setall(&pmu->supported_cpus);
899 for (i = 0; i < irqs; i++) {
902 irq = platform_get_irq(pdev, i);
903 if (WARN_ON(irq <= 0))
906 if (irq_is_percpu(irq)) {
907 pr_warn("multiple PPIs or mismatched SPI/PPI detected\n");
911 cpu = pmu_parse_irq_affinity(pdev->dev.of_node, i);
914 if (cpu >= nr_cpu_ids)
917 if (per_cpu(hw_events->irq, cpu)) {
918 pr_warn("multiple PMU IRQs for the same CPU detected\n");
922 per_cpu(hw_events->irq, cpu) = irq;
923 cpumask_set_cpu(cpu, &pmu->supported_cpus);
929 static struct arm_pmu *armpmu_alloc(void)
934 pmu = kzalloc(sizeof(*pmu), GFP_KERNEL);
936 pr_info("failed to allocate PMU device!\n");
940 pmu->hw_events = alloc_percpu(struct pmu_hw_events);
941 if (!pmu->hw_events) {
942 pr_info("failed to allocate per-cpu PMU data.\n");
946 pmu->pmu = (struct pmu) {
947 .pmu_enable = armpmu_enable,
948 .pmu_disable = armpmu_disable,
949 .event_init = armpmu_event_init,
952 .start = armpmu_start,
955 .filter_match = armpmu_filter_match,
956 .attr_groups = pmu->attr_groups,
958 * This is a CPU PMU potentially in a heterogeneous
959 * configuration (e.g. big.LITTLE). This is not an uncore PMU,
960 * and we have taken ctx sharing into account (e.g. with our
961 * pmu::filter_match callback and pmu::event_init group
964 .capabilities = PERF_PMU_CAP_HETEROGENEOUS_CPUS,
967 pmu->attr_groups[ARMPMU_ATTR_GROUP_COMMON] =
968 &armpmu_common_attr_group;
970 for_each_possible_cpu(cpu) {
971 struct pmu_hw_events *events;
973 events = per_cpu_ptr(pmu->hw_events, cpu);
974 raw_spin_lock_init(&events->pmu_lock);
975 events->percpu_pmu = pmu;
986 static void armpmu_free(struct arm_pmu *pmu)
988 free_percpu(pmu->hw_events);
992 int armpmu_register(struct arm_pmu *pmu)
996 ret = cpu_pmu_init(pmu);
1000 ret = perf_pmu_register(&pmu->pmu, pmu->name, -1);
1004 if (!__oprofile_cpu_pmu)
1005 __oprofile_cpu_pmu = pmu;
1007 pr_info("enabled with %s PMU driver, %d counters available\n",
1008 pmu->name, pmu->num_events);
1013 cpu_pmu_destroy(pmu);
1017 int arm_pmu_device_probe(struct platform_device *pdev,
1018 const struct of_device_id *of_table,
1019 const struct pmu_probe_info *probe_table)
1021 const struct of_device_id *of_id;
1022 armpmu_init_fn init_fn;
1023 struct device_node *node = pdev->dev.of_node;
1024 struct arm_pmu *pmu;
1027 pmu = armpmu_alloc();
1031 pmu->plat_device = pdev;
1033 ret = pmu_parse_irqs(pmu);
1037 if (node && (of_id = of_match_node(of_table, pdev->dev.of_node))) {
1038 init_fn = of_id->data;
1040 pmu->secure_access = of_property_read_bool(pdev->dev.of_node,
1041 "secure-reg-access");
1043 /* arm64 systems boot only as non-secure */
1044 if (IS_ENABLED(CONFIG_ARM64) && pmu->secure_access) {
1045 pr_warn("ignoring \"secure-reg-access\" property for arm64\n");
1046 pmu->secure_access = false;
1050 } else if (probe_table) {
1051 cpumask_setall(&pmu->supported_cpus);
1052 ret = probe_current_pmu(pmu, probe_table);
1056 pr_info("%s: failed to probe PMU!\n", of_node_full_name(node));
1060 ret = armpmu_register(pmu);
1067 pr_info("%s: failed to register PMU devices!\n",
1068 of_node_full_name(node));
1073 static int arm_pmu_hp_init(void)
1077 ret = cpuhp_setup_state_multi(CPUHP_AP_PERF_ARM_STARTING,
1078 "perf/arm/pmu:starting",
1079 arm_perf_starting_cpu,
1080 arm_perf_teardown_cpu);
1082 pr_err("CPU hotplug notifier for ARM PMU could not be registered: %d\n",
1086 subsys_initcall(arm_pmu_hp_init);