2 * Driver for Broadcom BCM2835 GPIO unit (pinctrl + GPIO)
4 * Copyright (C) 2012 Chris Boot, Simon Arlott, Stephen Warren
6 * This driver is inspired by:
7 * pinctrl-nomadik.c, please see original file for copyright information
8 * pinctrl-tegra.c, please see original file for copyright information
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
21 #include <linux/bitmap.h>
22 #include <linux/bug.h>
23 #include <linux/delay.h>
24 #include <linux/device.h>
25 #include <linux/err.h>
26 #include <linux/gpio/driver.h>
28 #include <linux/irq.h>
29 #include <linux/irqdesc.h>
30 #include <linux/module.h>
31 #include <linux/of_address.h>
33 #include <linux/of_irq.h>
34 #include <linux/pinctrl/consumer.h>
35 #include <linux/pinctrl/machine.h>
36 #include <linux/pinctrl/pinconf.h>
37 #include <linux/pinctrl/pinctrl.h>
38 #include <linux/pinctrl/pinmux.h>
39 #include <linux/platform_device.h>
40 #include <linux/seq_file.h>
41 #include <linux/slab.h>
42 #include <linux/spinlock.h>
43 #include <linux/types.h>
45 #define MODULE_NAME "pinctrl-bcm2835"
46 #define BCM2835_NUM_GPIOS 54
47 #define BCM2835_NUM_BANKS 2
48 #define BCM2835_NUM_IRQS 3
50 #define BCM2835_PIN_BITMAP_SZ \
51 DIV_ROUND_UP(BCM2835_NUM_GPIOS, sizeof(unsigned long) * 8)
53 /* GPIO register offsets */
54 #define GPFSEL0 0x0 /* Function Select */
55 #define GPSET0 0x1c /* Pin Output Set */
56 #define GPCLR0 0x28 /* Pin Output Clear */
57 #define GPLEV0 0x34 /* Pin Level */
58 #define GPEDS0 0x40 /* Pin Event Detect Status */
59 #define GPREN0 0x4c /* Pin Rising Edge Detect Enable */
60 #define GPFEN0 0x58 /* Pin Falling Edge Detect Enable */
61 #define GPHEN0 0x64 /* Pin High Detect Enable */
62 #define GPLEN0 0x70 /* Pin Low Detect Enable */
63 #define GPAREN0 0x7c /* Pin Async Rising Edge Detect */
64 #define GPAFEN0 0x88 /* Pin Async Falling Edge Detect */
65 #define GPPUD 0x94 /* Pin Pull-up/down Enable */
66 #define GPPUDCLK0 0x98 /* Pin Pull-up/down Enable Clock */
68 #define FSEL_REG(p) (GPFSEL0 + (((p) / 10) * 4))
69 #define FSEL_SHIFT(p) (((p) % 10) * 3)
70 #define GPIO_REG_OFFSET(p) ((p) / 32)
71 #define GPIO_REG_SHIFT(p) ((p) % 32)
73 enum bcm2835_pinconf_param {
74 /* argument: bcm2835_pinconf_pull */
75 BCM2835_PINCONF_PARAM_PULL,
78 #define BCM2835_PINCONF_PACK(_param_, _arg_) ((_param_) << 16 | (_arg_))
79 #define BCM2835_PINCONF_UNPACK_PARAM(_conf_) ((_conf_) >> 16)
80 #define BCM2835_PINCONF_UNPACK_ARG(_conf_) ((_conf_) & 0xffff)
82 struct bcm2835_pinctrl {
85 int irq[BCM2835_NUM_IRQS];
87 /* note: locking assumes each bank will have its own unsigned long */
88 unsigned long enabled_irq_map[BCM2835_NUM_BANKS];
89 unsigned int irq_type[BCM2835_NUM_GPIOS];
91 struct pinctrl_dev *pctl_dev;
92 struct gpio_chip gpio_chip;
93 struct pinctrl_gpio_range gpio_range;
95 int irq_group[BCM2835_NUM_IRQS];
96 spinlock_t irq_lock[BCM2835_NUM_BANKS];
99 /* pins are just named GPIO0..GPIO53 */
100 #define BCM2835_GPIO_PIN(a) PINCTRL_PIN(a, "gpio" #a)
101 static struct pinctrl_pin_desc bcm2835_gpio_pins[] = {
112 BCM2835_GPIO_PIN(10),
113 BCM2835_GPIO_PIN(11),
114 BCM2835_GPIO_PIN(12),
115 BCM2835_GPIO_PIN(13),
116 BCM2835_GPIO_PIN(14),
117 BCM2835_GPIO_PIN(15),
118 BCM2835_GPIO_PIN(16),
119 BCM2835_GPIO_PIN(17),
120 BCM2835_GPIO_PIN(18),
121 BCM2835_GPIO_PIN(19),
122 BCM2835_GPIO_PIN(20),
123 BCM2835_GPIO_PIN(21),
124 BCM2835_GPIO_PIN(22),
125 BCM2835_GPIO_PIN(23),
126 BCM2835_GPIO_PIN(24),
127 BCM2835_GPIO_PIN(25),
128 BCM2835_GPIO_PIN(26),
129 BCM2835_GPIO_PIN(27),
130 BCM2835_GPIO_PIN(28),
131 BCM2835_GPIO_PIN(29),
132 BCM2835_GPIO_PIN(30),
133 BCM2835_GPIO_PIN(31),
134 BCM2835_GPIO_PIN(32),
135 BCM2835_GPIO_PIN(33),
136 BCM2835_GPIO_PIN(34),
137 BCM2835_GPIO_PIN(35),
138 BCM2835_GPIO_PIN(36),
139 BCM2835_GPIO_PIN(37),
140 BCM2835_GPIO_PIN(38),
141 BCM2835_GPIO_PIN(39),
142 BCM2835_GPIO_PIN(40),
143 BCM2835_GPIO_PIN(41),
144 BCM2835_GPIO_PIN(42),
145 BCM2835_GPIO_PIN(43),
146 BCM2835_GPIO_PIN(44),
147 BCM2835_GPIO_PIN(45),
148 BCM2835_GPIO_PIN(46),
149 BCM2835_GPIO_PIN(47),
150 BCM2835_GPIO_PIN(48),
151 BCM2835_GPIO_PIN(49),
152 BCM2835_GPIO_PIN(50),
153 BCM2835_GPIO_PIN(51),
154 BCM2835_GPIO_PIN(52),
155 BCM2835_GPIO_PIN(53),
158 /* one pin per group */
159 static const char * const bcm2835_gpio_groups[] = {
217 BCM2835_FSEL_GPIO_IN = 0,
218 BCM2835_FSEL_GPIO_OUT = 1,
219 BCM2835_FSEL_ALT0 = 4,
220 BCM2835_FSEL_ALT1 = 5,
221 BCM2835_FSEL_ALT2 = 6,
222 BCM2835_FSEL_ALT3 = 7,
223 BCM2835_FSEL_ALT4 = 3,
224 BCM2835_FSEL_ALT5 = 2,
225 BCM2835_FSEL_COUNT = 8,
226 BCM2835_FSEL_MASK = 0x7,
229 static const char * const bcm2835_functions[BCM2835_FSEL_COUNT] = {
230 [BCM2835_FSEL_GPIO_IN] = "gpio_in",
231 [BCM2835_FSEL_GPIO_OUT] = "gpio_out",
232 [BCM2835_FSEL_ALT0] = "alt0",
233 [BCM2835_FSEL_ALT1] = "alt1",
234 [BCM2835_FSEL_ALT2] = "alt2",
235 [BCM2835_FSEL_ALT3] = "alt3",
236 [BCM2835_FSEL_ALT4] = "alt4",
237 [BCM2835_FSEL_ALT5] = "alt5",
240 static const char * const irq_type_names[] = {
241 [IRQ_TYPE_NONE] = "none",
242 [IRQ_TYPE_EDGE_RISING] = "edge-rising",
243 [IRQ_TYPE_EDGE_FALLING] = "edge-falling",
244 [IRQ_TYPE_EDGE_BOTH] = "edge-both",
245 [IRQ_TYPE_LEVEL_HIGH] = "level-high",
246 [IRQ_TYPE_LEVEL_LOW] = "level-low",
249 static inline u32 bcm2835_gpio_rd(struct bcm2835_pinctrl *pc, unsigned reg)
251 return readl(pc->base + reg);
254 static inline void bcm2835_gpio_wr(struct bcm2835_pinctrl *pc, unsigned reg,
257 writel(val, pc->base + reg);
260 static inline int bcm2835_gpio_get_bit(struct bcm2835_pinctrl *pc, unsigned reg,
263 reg += GPIO_REG_OFFSET(bit) * 4;
264 return (bcm2835_gpio_rd(pc, reg) >> GPIO_REG_SHIFT(bit)) & 1;
267 /* note NOT a read/modify/write cycle */
268 static inline void bcm2835_gpio_set_bit(struct bcm2835_pinctrl *pc,
269 unsigned reg, unsigned bit)
271 reg += GPIO_REG_OFFSET(bit) * 4;
272 bcm2835_gpio_wr(pc, reg, BIT(GPIO_REG_SHIFT(bit)));
275 static inline enum bcm2835_fsel bcm2835_pinctrl_fsel_get(
276 struct bcm2835_pinctrl *pc, unsigned pin)
278 u32 val = bcm2835_gpio_rd(pc, FSEL_REG(pin));
279 enum bcm2835_fsel status = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK;
281 dev_dbg(pc->dev, "get %08x (%u => %s)\n", val, pin,
282 bcm2835_functions[status]);
287 static inline void bcm2835_pinctrl_fsel_set(
288 struct bcm2835_pinctrl *pc, unsigned pin,
289 enum bcm2835_fsel fsel)
291 u32 val = bcm2835_gpio_rd(pc, FSEL_REG(pin));
292 enum bcm2835_fsel cur = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK;
294 dev_dbg(pc->dev, "read %08x (%u => %s)\n", val, pin,
295 bcm2835_functions[cur]);
300 if (cur != BCM2835_FSEL_GPIO_IN && fsel != BCM2835_FSEL_GPIO_IN) {
301 /* always transition through GPIO_IN */
302 val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin));
303 val |= BCM2835_FSEL_GPIO_IN << FSEL_SHIFT(pin);
305 dev_dbg(pc->dev, "trans %08x (%u <= %s)\n", val, pin,
306 bcm2835_functions[BCM2835_FSEL_GPIO_IN]);
307 bcm2835_gpio_wr(pc, FSEL_REG(pin), val);
310 val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin));
311 val |= fsel << FSEL_SHIFT(pin);
313 dev_dbg(pc->dev, "write %08x (%u <= %s)\n", val, pin,
314 bcm2835_functions[fsel]);
315 bcm2835_gpio_wr(pc, FSEL_REG(pin), val);
318 static int bcm2835_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
320 return pinctrl_gpio_direction_input(chip->base + offset);
323 static int bcm2835_gpio_get(struct gpio_chip *chip, unsigned offset)
325 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
327 return bcm2835_gpio_get_bit(pc, GPLEV0, offset);
330 static int bcm2835_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
332 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
333 enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset);
335 /* Alternative function doesn't clearly provide a direction */
336 if (fsel > BCM2835_FSEL_GPIO_OUT)
339 return (fsel == BCM2835_FSEL_GPIO_IN);
342 static void bcm2835_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
344 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
346 bcm2835_gpio_set_bit(pc, value ? GPSET0 : GPCLR0, offset);
349 static int bcm2835_gpio_direction_output(struct gpio_chip *chip,
350 unsigned offset, int value)
352 bcm2835_gpio_set(chip, offset, value);
353 return pinctrl_gpio_direction_output(chip->base + offset);
356 static struct gpio_chip bcm2835_gpio_chip = {
357 .label = MODULE_NAME,
358 .owner = THIS_MODULE,
359 .request = gpiochip_generic_request,
360 .free = gpiochip_generic_free,
361 .direction_input = bcm2835_gpio_direction_input,
362 .direction_output = bcm2835_gpio_direction_output,
363 .get_direction = bcm2835_gpio_get_direction,
364 .get = bcm2835_gpio_get,
365 .set = bcm2835_gpio_set,
367 .ngpio = BCM2835_NUM_GPIOS,
371 static void bcm2835_gpio_irq_handle_bank(struct bcm2835_pinctrl *pc,
372 unsigned int bank, u32 mask)
374 unsigned long events;
379 events = bcm2835_gpio_rd(pc, GPEDS0 + bank * 4);
381 events &= pc->enabled_irq_map[bank];
382 for_each_set_bit(offset, &events, 32) {
383 gpio = (32 * bank) + offset;
384 /* FIXME: no clue why the code looks up the type here */
385 type = pc->irq_type[gpio];
387 generic_handle_irq(irq_linear_revmap(pc->gpio_chip.irqdomain,
392 static void bcm2835_gpio_irq_handler(struct irq_desc *desc)
394 struct gpio_chip *chip = irq_desc_get_handler_data(desc);
395 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
396 struct irq_chip *host_chip = irq_desc_get_chip(desc);
397 int irq = irq_desc_get_irq(desc);
401 for (i = 0; i < ARRAY_SIZE(pc->irq); i++) {
402 if (pc->irq[i] == irq) {
403 group = pc->irq_group[i];
407 /* This should not happen, every IRQ has a bank */
408 if (i == ARRAY_SIZE(pc->irq))
411 chained_irq_enter(host_chip, desc);
414 case 0: /* IRQ0 covers GPIOs 0-27 */
415 bcm2835_gpio_irq_handle_bank(pc, 0, 0x0fffffff);
417 case 1: /* IRQ1 covers GPIOs 28-45 */
418 bcm2835_gpio_irq_handle_bank(pc, 0, 0xf0000000);
419 bcm2835_gpio_irq_handle_bank(pc, 1, 0x00003fff);
421 case 2: /* IRQ2 covers GPIOs 46-53 */
422 bcm2835_gpio_irq_handle_bank(pc, 1, 0x003fc000);
426 chained_irq_exit(host_chip, desc);
429 static inline void __bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc,
430 unsigned reg, unsigned offset, bool enable)
433 reg += GPIO_REG_OFFSET(offset) * 4;
434 value = bcm2835_gpio_rd(pc, reg);
436 value |= BIT(GPIO_REG_SHIFT(offset));
438 value &= ~(BIT(GPIO_REG_SHIFT(offset)));
439 bcm2835_gpio_wr(pc, reg, value);
442 /* fast path for IRQ handler */
443 static void bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc,
444 unsigned offset, bool enable)
446 switch (pc->irq_type[offset]) {
447 case IRQ_TYPE_EDGE_RISING:
448 __bcm2835_gpio_irq_config(pc, GPREN0, offset, enable);
451 case IRQ_TYPE_EDGE_FALLING:
452 __bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable);
455 case IRQ_TYPE_EDGE_BOTH:
456 __bcm2835_gpio_irq_config(pc, GPREN0, offset, enable);
457 __bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable);
460 case IRQ_TYPE_LEVEL_HIGH:
461 __bcm2835_gpio_irq_config(pc, GPHEN0, offset, enable);
464 case IRQ_TYPE_LEVEL_LOW:
465 __bcm2835_gpio_irq_config(pc, GPLEN0, offset, enable);
470 static void bcm2835_gpio_irq_enable(struct irq_data *data)
472 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
473 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
474 unsigned gpio = irqd_to_hwirq(data);
475 unsigned offset = GPIO_REG_SHIFT(gpio);
476 unsigned bank = GPIO_REG_OFFSET(gpio);
479 spin_lock_irqsave(&pc->irq_lock[bank], flags);
480 set_bit(offset, &pc->enabled_irq_map[bank]);
481 bcm2835_gpio_irq_config(pc, gpio, true);
482 spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
485 static void bcm2835_gpio_irq_disable(struct irq_data *data)
487 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
488 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
489 unsigned gpio = irqd_to_hwirq(data);
490 unsigned offset = GPIO_REG_SHIFT(gpio);
491 unsigned bank = GPIO_REG_OFFSET(gpio);
494 spin_lock_irqsave(&pc->irq_lock[bank], flags);
495 bcm2835_gpio_irq_config(pc, gpio, false);
496 /* Clear events that were latched prior to clearing event sources */
497 bcm2835_gpio_set_bit(pc, GPEDS0, gpio);
498 clear_bit(offset, &pc->enabled_irq_map[bank]);
499 spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
502 static int __bcm2835_gpio_irq_set_type_disabled(struct bcm2835_pinctrl *pc,
503 unsigned offset, unsigned int type)
507 case IRQ_TYPE_EDGE_RISING:
508 case IRQ_TYPE_EDGE_FALLING:
509 case IRQ_TYPE_EDGE_BOTH:
510 case IRQ_TYPE_LEVEL_HIGH:
511 case IRQ_TYPE_LEVEL_LOW:
512 pc->irq_type[offset] = type;
521 /* slower path for reconfiguring IRQ type */
522 static int __bcm2835_gpio_irq_set_type_enabled(struct bcm2835_pinctrl *pc,
523 unsigned offset, unsigned int type)
527 if (pc->irq_type[offset] != type) {
528 bcm2835_gpio_irq_config(pc, offset, false);
529 pc->irq_type[offset] = type;
533 case IRQ_TYPE_EDGE_RISING:
534 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) {
535 /* RISING already enabled, disable FALLING */
536 pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING;
537 bcm2835_gpio_irq_config(pc, offset, false);
538 pc->irq_type[offset] = type;
539 } else if (pc->irq_type[offset] != type) {
540 bcm2835_gpio_irq_config(pc, offset, false);
541 pc->irq_type[offset] = type;
542 bcm2835_gpio_irq_config(pc, offset, true);
546 case IRQ_TYPE_EDGE_FALLING:
547 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) {
548 /* FALLING already enabled, disable RISING */
549 pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING;
550 bcm2835_gpio_irq_config(pc, offset, false);
551 pc->irq_type[offset] = type;
552 } else if (pc->irq_type[offset] != type) {
553 bcm2835_gpio_irq_config(pc, offset, false);
554 pc->irq_type[offset] = type;
555 bcm2835_gpio_irq_config(pc, offset, true);
559 case IRQ_TYPE_EDGE_BOTH:
560 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_RISING) {
561 /* RISING already enabled, enable FALLING too */
562 pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING;
563 bcm2835_gpio_irq_config(pc, offset, true);
564 pc->irq_type[offset] = type;
565 } else if (pc->irq_type[offset] == IRQ_TYPE_EDGE_FALLING) {
566 /* FALLING already enabled, enable RISING too */
567 pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING;
568 bcm2835_gpio_irq_config(pc, offset, true);
569 pc->irq_type[offset] = type;
570 } else if (pc->irq_type[offset] != type) {
571 bcm2835_gpio_irq_config(pc, offset, false);
572 pc->irq_type[offset] = type;
573 bcm2835_gpio_irq_config(pc, offset, true);
577 case IRQ_TYPE_LEVEL_HIGH:
578 case IRQ_TYPE_LEVEL_LOW:
579 if (pc->irq_type[offset] != type) {
580 bcm2835_gpio_irq_config(pc, offset, false);
581 pc->irq_type[offset] = type;
582 bcm2835_gpio_irq_config(pc, offset, true);
592 static int bcm2835_gpio_irq_set_type(struct irq_data *data, unsigned int type)
594 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
595 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
596 unsigned gpio = irqd_to_hwirq(data);
597 unsigned offset = GPIO_REG_SHIFT(gpio);
598 unsigned bank = GPIO_REG_OFFSET(gpio);
602 spin_lock_irqsave(&pc->irq_lock[bank], flags);
604 if (test_bit(offset, &pc->enabled_irq_map[bank]))
605 ret = __bcm2835_gpio_irq_set_type_enabled(pc, gpio, type);
607 ret = __bcm2835_gpio_irq_set_type_disabled(pc, gpio, type);
609 if (type & IRQ_TYPE_EDGE_BOTH)
610 irq_set_handler_locked(data, handle_edge_irq);
612 irq_set_handler_locked(data, handle_level_irq);
614 spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
619 static void bcm2835_gpio_irq_ack(struct irq_data *data)
621 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
622 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
623 unsigned gpio = irqd_to_hwirq(data);
625 bcm2835_gpio_set_bit(pc, GPEDS0, gpio);
628 static struct irq_chip bcm2835_gpio_irq_chip = {
630 .irq_enable = bcm2835_gpio_irq_enable,
631 .irq_disable = bcm2835_gpio_irq_disable,
632 .irq_set_type = bcm2835_gpio_irq_set_type,
633 .irq_ack = bcm2835_gpio_irq_ack,
634 .irq_mask = bcm2835_gpio_irq_disable,
635 .irq_unmask = bcm2835_gpio_irq_enable,
638 static int bcm2835_pctl_get_groups_count(struct pinctrl_dev *pctldev)
640 return ARRAY_SIZE(bcm2835_gpio_groups);
643 static const char *bcm2835_pctl_get_group_name(struct pinctrl_dev *pctldev,
646 return bcm2835_gpio_groups[selector];
649 static int bcm2835_pctl_get_group_pins(struct pinctrl_dev *pctldev,
651 const unsigned **pins,
654 *pins = &bcm2835_gpio_pins[selector].number;
660 static void bcm2835_pctl_pin_dbg_show(struct pinctrl_dev *pctldev,
664 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
665 struct gpio_chip *chip = &pc->gpio_chip;
666 enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset);
667 const char *fname = bcm2835_functions[fsel];
668 int value = bcm2835_gpio_get_bit(pc, GPLEV0, offset);
669 int irq = irq_find_mapping(chip->irqdomain, offset);
671 seq_printf(s, "function %s in %s; irq %d (%s)",
672 fname, value ? "hi" : "lo",
673 irq, irq_type_names[pc->irq_type[offset]]);
676 static void bcm2835_pctl_dt_free_map(struct pinctrl_dev *pctldev,
677 struct pinctrl_map *maps, unsigned num_maps)
681 for (i = 0; i < num_maps; i++)
682 if (maps[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
683 kfree(maps[i].data.configs.configs);
688 static int bcm2835_pctl_dt_node_to_map_func(struct bcm2835_pinctrl *pc,
689 struct device_node *np, u32 pin, u32 fnum,
690 struct pinctrl_map **maps)
692 struct pinctrl_map *map = *maps;
694 if (fnum >= ARRAY_SIZE(bcm2835_functions)) {
695 dev_err(pc->dev, "%s: invalid brcm,function %d\n",
696 of_node_full_name(np), fnum);
700 map->type = PIN_MAP_TYPE_MUX_GROUP;
701 map->data.mux.group = bcm2835_gpio_groups[pin];
702 map->data.mux.function = bcm2835_functions[fnum];
708 static int bcm2835_pctl_dt_node_to_map_pull(struct bcm2835_pinctrl *pc,
709 struct device_node *np, u32 pin, u32 pull,
710 struct pinctrl_map **maps)
712 struct pinctrl_map *map = *maps;
713 unsigned long *configs;
716 dev_err(pc->dev, "%s: invalid brcm,pull %d\n",
717 of_node_full_name(np), pull);
721 configs = kzalloc(sizeof(*configs), GFP_KERNEL);
724 configs[0] = BCM2835_PINCONF_PACK(BCM2835_PINCONF_PARAM_PULL, pull);
726 map->type = PIN_MAP_TYPE_CONFIGS_PIN;
727 map->data.configs.group_or_pin = bcm2835_gpio_pins[pin].name;
728 map->data.configs.configs = configs;
729 map->data.configs.num_configs = 1;
735 static int bcm2835_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
736 struct device_node *np,
737 struct pinctrl_map **map, unsigned *num_maps)
739 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
740 struct property *pins, *funcs, *pulls;
741 int num_pins, num_funcs, num_pulls, maps_per_pin;
742 struct pinctrl_map *maps, *cur_map;
746 pins = of_find_property(np, "brcm,pins", NULL);
748 dev_err(pc->dev, "%s: missing brcm,pins property\n",
749 of_node_full_name(np));
753 funcs = of_find_property(np, "brcm,function", NULL);
754 pulls = of_find_property(np, "brcm,pull", NULL);
756 if (!funcs && !pulls) {
758 "%s: neither brcm,function nor brcm,pull specified\n",
759 of_node_full_name(np));
763 num_pins = pins->length / 4;
764 num_funcs = funcs ? (funcs->length / 4) : 0;
765 num_pulls = pulls ? (pulls->length / 4) : 0;
767 if (num_funcs > 1 && num_funcs != num_pins) {
769 "%s: brcm,function must have 1 or %d entries\n",
770 of_node_full_name(np), num_pins);
774 if (num_pulls > 1 && num_pulls != num_pins) {
776 "%s: brcm,pull must have 1 or %d entries\n",
777 of_node_full_name(np), num_pins);
786 cur_map = maps = kzalloc(num_pins * maps_per_pin * sizeof(*maps),
791 for (i = 0; i < num_pins; i++) {
792 err = of_property_read_u32_index(np, "brcm,pins", i, &pin);
795 if (pin >= ARRAY_SIZE(bcm2835_gpio_pins)) {
796 dev_err(pc->dev, "%s: invalid brcm,pins value %d\n",
797 of_node_full_name(np), pin);
803 err = of_property_read_u32_index(np, "brcm,function",
804 (num_funcs > 1) ? i : 0, &func);
807 err = bcm2835_pctl_dt_node_to_map_func(pc, np, pin,
813 err = of_property_read_u32_index(np, "brcm,pull",
814 (num_pulls > 1) ? i : 0, &pull);
817 err = bcm2835_pctl_dt_node_to_map_pull(pc, np, pin,
825 *num_maps = num_pins * maps_per_pin;
830 bcm2835_pctl_dt_free_map(pctldev, maps, num_pins * maps_per_pin);
834 static const struct pinctrl_ops bcm2835_pctl_ops = {
835 .get_groups_count = bcm2835_pctl_get_groups_count,
836 .get_group_name = bcm2835_pctl_get_group_name,
837 .get_group_pins = bcm2835_pctl_get_group_pins,
838 .pin_dbg_show = bcm2835_pctl_pin_dbg_show,
839 .dt_node_to_map = bcm2835_pctl_dt_node_to_map,
840 .dt_free_map = bcm2835_pctl_dt_free_map,
843 static int bcm2835_pmx_free(struct pinctrl_dev *pctldev,
846 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
848 /* disable by setting to GPIO_IN */
849 bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN);
853 static int bcm2835_pmx_get_functions_count(struct pinctrl_dev *pctldev)
855 return BCM2835_FSEL_COUNT;
858 static const char *bcm2835_pmx_get_function_name(struct pinctrl_dev *pctldev,
861 return bcm2835_functions[selector];
864 static int bcm2835_pmx_get_function_groups(struct pinctrl_dev *pctldev,
866 const char * const **groups,
867 unsigned * const num_groups)
869 /* every pin can do every function */
870 *groups = bcm2835_gpio_groups;
871 *num_groups = ARRAY_SIZE(bcm2835_gpio_groups);
876 static int bcm2835_pmx_set(struct pinctrl_dev *pctldev,
877 unsigned func_selector,
878 unsigned group_selector)
880 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
882 bcm2835_pinctrl_fsel_set(pc, group_selector, func_selector);
887 static void bcm2835_pmx_gpio_disable_free(struct pinctrl_dev *pctldev,
888 struct pinctrl_gpio_range *range,
891 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
893 /* disable by setting to GPIO_IN */
894 bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN);
897 static int bcm2835_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
898 struct pinctrl_gpio_range *range,
902 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
903 enum bcm2835_fsel fsel = input ?
904 BCM2835_FSEL_GPIO_IN : BCM2835_FSEL_GPIO_OUT;
906 bcm2835_pinctrl_fsel_set(pc, offset, fsel);
911 static const struct pinmux_ops bcm2835_pmx_ops = {
912 .free = bcm2835_pmx_free,
913 .get_functions_count = bcm2835_pmx_get_functions_count,
914 .get_function_name = bcm2835_pmx_get_function_name,
915 .get_function_groups = bcm2835_pmx_get_function_groups,
916 .set_mux = bcm2835_pmx_set,
917 .gpio_disable_free = bcm2835_pmx_gpio_disable_free,
918 .gpio_set_direction = bcm2835_pmx_gpio_set_direction,
921 static int bcm2835_pinconf_get(struct pinctrl_dev *pctldev,
922 unsigned pin, unsigned long *config)
924 /* No way to read back config in HW */
928 static int bcm2835_pinconf_set(struct pinctrl_dev *pctldev,
929 unsigned pin, unsigned long *configs,
930 unsigned num_configs)
932 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
933 enum bcm2835_pinconf_param param;
938 for (i = 0; i < num_configs; i++) {
939 param = BCM2835_PINCONF_UNPACK_PARAM(configs[i]);
940 arg = BCM2835_PINCONF_UNPACK_ARG(configs[i]);
942 if (param != BCM2835_PINCONF_PARAM_PULL)
945 off = GPIO_REG_OFFSET(pin);
946 bit = GPIO_REG_SHIFT(pin);
948 bcm2835_gpio_wr(pc, GPPUD, arg & 3);
950 * BCM2835 datasheet say to wait 150 cycles, but not of what.
951 * But the VideoCore firmware delay for this operation
952 * based nearly on the same amount of VPU cycles and this clock
956 bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), BIT(bit));
958 bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), 0);
959 } /* for each config */
964 static const struct pinconf_ops bcm2835_pinconf_ops = {
965 .pin_config_get = bcm2835_pinconf_get,
966 .pin_config_set = bcm2835_pinconf_set,
969 static struct pinctrl_desc bcm2835_pinctrl_desc = {
971 .pins = bcm2835_gpio_pins,
972 .npins = ARRAY_SIZE(bcm2835_gpio_pins),
973 .pctlops = &bcm2835_pctl_ops,
974 .pmxops = &bcm2835_pmx_ops,
975 .confops = &bcm2835_pinconf_ops,
976 .owner = THIS_MODULE,
979 static struct pinctrl_gpio_range bcm2835_pinctrl_gpio_range = {
981 .npins = BCM2835_NUM_GPIOS,
984 static int bcm2835_pinctrl_probe(struct platform_device *pdev)
986 struct device *dev = &pdev->dev;
987 struct device_node *np = dev->of_node;
988 struct bcm2835_pinctrl *pc;
989 struct resource iomem;
991 BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_pins) != BCM2835_NUM_GPIOS);
992 BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_groups) != BCM2835_NUM_GPIOS);
994 pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL);
998 platform_set_drvdata(pdev, pc);
1001 err = of_address_to_resource(np, 0, &iomem);
1003 dev_err(dev, "could not get IO memory\n");
1007 pc->base = devm_ioremap_resource(dev, &iomem);
1008 if (IS_ERR(pc->base))
1009 return PTR_ERR(pc->base);
1011 pc->gpio_chip = bcm2835_gpio_chip;
1012 pc->gpio_chip.parent = dev;
1013 pc->gpio_chip.of_node = np;
1015 for (i = 0; i < BCM2835_NUM_BANKS; i++) {
1016 unsigned long events;
1019 /* clear event detection flags */
1020 bcm2835_gpio_wr(pc, GPREN0 + i * 4, 0);
1021 bcm2835_gpio_wr(pc, GPFEN0 + i * 4, 0);
1022 bcm2835_gpio_wr(pc, GPHEN0 + i * 4, 0);
1023 bcm2835_gpio_wr(pc, GPLEN0 + i * 4, 0);
1024 bcm2835_gpio_wr(pc, GPAREN0 + i * 4, 0);
1025 bcm2835_gpio_wr(pc, GPAFEN0 + i * 4, 0);
1027 /* clear all the events */
1028 events = bcm2835_gpio_rd(pc, GPEDS0 + i * 4);
1029 for_each_set_bit(offset, &events, 32)
1030 bcm2835_gpio_wr(pc, GPEDS0 + i * 4, BIT(offset));
1032 spin_lock_init(&pc->irq_lock[i]);
1035 err = gpiochip_add_data(&pc->gpio_chip, pc);
1037 dev_err(dev, "could not add GPIO chip\n");
1041 err = gpiochip_irqchip_add(&pc->gpio_chip, &bcm2835_gpio_irq_chip,
1042 0, handle_level_irq, IRQ_TYPE_NONE);
1044 dev_info(dev, "could not add irqchip\n");
1048 for (i = 0; i < BCM2835_NUM_IRQS; i++) {
1049 pc->irq[i] = irq_of_parse_and_map(np, i);
1050 pc->irq_group[i] = i;
1052 * Use the same handler for all groups: this is necessary
1053 * since we use one gpiochip to cover all lines - the
1054 * irq handler then needs to figure out which group and
1055 * bank that was firing the IRQ and look up the per-group
1058 gpiochip_set_chained_irqchip(&pc->gpio_chip,
1059 &bcm2835_gpio_irq_chip,
1061 bcm2835_gpio_irq_handler);
1064 pc->pctl_dev = devm_pinctrl_register(dev, &bcm2835_pinctrl_desc, pc);
1065 if (IS_ERR(pc->pctl_dev)) {
1066 gpiochip_remove(&pc->gpio_chip);
1067 return PTR_ERR(pc->pctl_dev);
1070 pc->gpio_range = bcm2835_pinctrl_gpio_range;
1071 pc->gpio_range.base = pc->gpio_chip.base;
1072 pc->gpio_range.gc = &pc->gpio_chip;
1073 pinctrl_add_gpio_range(pc->pctl_dev, &pc->gpio_range);
1078 static int bcm2835_pinctrl_remove(struct platform_device *pdev)
1080 struct bcm2835_pinctrl *pc = platform_get_drvdata(pdev);
1082 gpiochip_remove(&pc->gpio_chip);
1087 static const struct of_device_id bcm2835_pinctrl_match[] = {
1088 { .compatible = "brcm,bcm2835-gpio" },
1091 MODULE_DEVICE_TABLE(of, bcm2835_pinctrl_match);
1093 static struct platform_driver bcm2835_pinctrl_driver = {
1094 .probe = bcm2835_pinctrl_probe,
1095 .remove = bcm2835_pinctrl_remove,
1097 .name = MODULE_NAME,
1098 .of_match_table = bcm2835_pinctrl_match,
1101 module_platform_driver(bcm2835_pinctrl_driver);
1103 MODULE_AUTHOR("Chris Boot, Simon Arlott, Stephen Warren");
1104 MODULE_DESCRIPTION("BCM2835 Pin control driver");
1105 MODULE_LICENSE("GPL");