2 * Driver for Broadcom BCM2835 GPIO unit (pinctrl + GPIO)
4 * Copyright (C) 2012 Chris Boot, Simon Arlott, Stephen Warren
6 * This driver is inspired by:
7 * pinctrl-nomadik.c, please see original file for copyright information
8 * pinctrl-tegra.c, please see original file for copyright information
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
21 #include <linux/bitmap.h>
22 #include <linux/bug.h>
23 #include <linux/delay.h>
24 #include <linux/device.h>
25 #include <linux/err.h>
26 #include <linux/gpio/driver.h>
28 #include <linux/irq.h>
29 #include <linux/irqdesc.h>
30 #include <linux/module.h>
31 #include <linux/of_address.h>
33 #include <linux/of_irq.h>
34 #include <linux/pinctrl/consumer.h>
35 #include <linux/pinctrl/machine.h>
36 #include <linux/pinctrl/pinconf.h>
37 #include <linux/pinctrl/pinctrl.h>
38 #include <linux/pinctrl/pinmux.h>
39 #include <linux/platform_device.h>
40 #include <linux/seq_file.h>
41 #include <linux/slab.h>
42 #include <linux/spinlock.h>
43 #include <linux/types.h>
45 #define MODULE_NAME "pinctrl-bcm2835"
46 #define BCM2835_NUM_GPIOS 54
47 #define BCM2835_NUM_BANKS 2
48 #define BCM2835_NUM_IRQS 3
50 #define BCM2835_PIN_BITMAP_SZ \
51 DIV_ROUND_UP(BCM2835_NUM_GPIOS, sizeof(unsigned long) * 8)
53 /* GPIO register offsets */
54 #define GPFSEL0 0x0 /* Function Select */
55 #define GPSET0 0x1c /* Pin Output Set */
56 #define GPCLR0 0x28 /* Pin Output Clear */
57 #define GPLEV0 0x34 /* Pin Level */
58 #define GPEDS0 0x40 /* Pin Event Detect Status */
59 #define GPREN0 0x4c /* Pin Rising Edge Detect Enable */
60 #define GPFEN0 0x58 /* Pin Falling Edge Detect Enable */
61 #define GPHEN0 0x64 /* Pin High Detect Enable */
62 #define GPLEN0 0x70 /* Pin Low Detect Enable */
63 #define GPAREN0 0x7c /* Pin Async Rising Edge Detect */
64 #define GPAFEN0 0x88 /* Pin Async Falling Edge Detect */
65 #define GPPUD 0x94 /* Pin Pull-up/down Enable */
66 #define GPPUDCLK0 0x98 /* Pin Pull-up/down Enable Clock */
68 #define FSEL_REG(p) (GPFSEL0 + (((p) / 10) * 4))
69 #define FSEL_SHIFT(p) (((p) % 10) * 3)
70 #define GPIO_REG_OFFSET(p) ((p) / 32)
71 #define GPIO_REG_SHIFT(p) ((p) % 32)
73 enum bcm2835_pinconf_param {
74 /* argument: bcm2835_pinconf_pull */
75 BCM2835_PINCONF_PARAM_PULL,
78 enum bcm2835_pinconf_pull {
79 BCM2835_PINCONFIG_PULL_NONE,
80 BCM2835_PINCONFIG_PULL_DOWN,
81 BCM2835_PINCONFIG_PULL_UP,
84 #define BCM2835_PINCONF_PACK(_param_, _arg_) ((_param_) << 16 | (_arg_))
85 #define BCM2835_PINCONF_UNPACK_PARAM(_conf_) ((_conf_) >> 16)
86 #define BCM2835_PINCONF_UNPACK_ARG(_conf_) ((_conf_) & 0xffff)
88 struct bcm2835_pinctrl {
91 int irq[BCM2835_NUM_IRQS];
93 /* note: locking assumes each bank will have its own unsigned long */
94 unsigned long enabled_irq_map[BCM2835_NUM_BANKS];
95 unsigned int irq_type[BCM2835_NUM_GPIOS];
97 struct pinctrl_dev *pctl_dev;
98 struct gpio_chip gpio_chip;
99 struct pinctrl_gpio_range gpio_range;
101 int irq_group[BCM2835_NUM_IRQS];
102 spinlock_t irq_lock[BCM2835_NUM_BANKS];
105 /* pins are just named GPIO0..GPIO53 */
106 #define BCM2835_GPIO_PIN(a) PINCTRL_PIN(a, "gpio" #a)
107 static struct pinctrl_pin_desc bcm2835_gpio_pins[] = {
118 BCM2835_GPIO_PIN(10),
119 BCM2835_GPIO_PIN(11),
120 BCM2835_GPIO_PIN(12),
121 BCM2835_GPIO_PIN(13),
122 BCM2835_GPIO_PIN(14),
123 BCM2835_GPIO_PIN(15),
124 BCM2835_GPIO_PIN(16),
125 BCM2835_GPIO_PIN(17),
126 BCM2835_GPIO_PIN(18),
127 BCM2835_GPIO_PIN(19),
128 BCM2835_GPIO_PIN(20),
129 BCM2835_GPIO_PIN(21),
130 BCM2835_GPIO_PIN(22),
131 BCM2835_GPIO_PIN(23),
132 BCM2835_GPIO_PIN(24),
133 BCM2835_GPIO_PIN(25),
134 BCM2835_GPIO_PIN(26),
135 BCM2835_GPIO_PIN(27),
136 BCM2835_GPIO_PIN(28),
137 BCM2835_GPIO_PIN(29),
138 BCM2835_GPIO_PIN(30),
139 BCM2835_GPIO_PIN(31),
140 BCM2835_GPIO_PIN(32),
141 BCM2835_GPIO_PIN(33),
142 BCM2835_GPIO_PIN(34),
143 BCM2835_GPIO_PIN(35),
144 BCM2835_GPIO_PIN(36),
145 BCM2835_GPIO_PIN(37),
146 BCM2835_GPIO_PIN(38),
147 BCM2835_GPIO_PIN(39),
148 BCM2835_GPIO_PIN(40),
149 BCM2835_GPIO_PIN(41),
150 BCM2835_GPIO_PIN(42),
151 BCM2835_GPIO_PIN(43),
152 BCM2835_GPIO_PIN(44),
153 BCM2835_GPIO_PIN(45),
154 BCM2835_GPIO_PIN(46),
155 BCM2835_GPIO_PIN(47),
156 BCM2835_GPIO_PIN(48),
157 BCM2835_GPIO_PIN(49),
158 BCM2835_GPIO_PIN(50),
159 BCM2835_GPIO_PIN(51),
160 BCM2835_GPIO_PIN(52),
161 BCM2835_GPIO_PIN(53),
164 /* one pin per group */
165 static const char * const bcm2835_gpio_groups[] = {
223 BCM2835_FSEL_GPIO_IN = 0,
224 BCM2835_FSEL_GPIO_OUT = 1,
225 BCM2835_FSEL_ALT0 = 4,
226 BCM2835_FSEL_ALT1 = 5,
227 BCM2835_FSEL_ALT2 = 6,
228 BCM2835_FSEL_ALT3 = 7,
229 BCM2835_FSEL_ALT4 = 3,
230 BCM2835_FSEL_ALT5 = 2,
231 BCM2835_FSEL_COUNT = 8,
232 BCM2835_FSEL_MASK = 0x7,
235 static const char * const bcm2835_functions[BCM2835_FSEL_COUNT] = {
236 [BCM2835_FSEL_GPIO_IN] = "gpio_in",
237 [BCM2835_FSEL_GPIO_OUT] = "gpio_out",
238 [BCM2835_FSEL_ALT0] = "alt0",
239 [BCM2835_FSEL_ALT1] = "alt1",
240 [BCM2835_FSEL_ALT2] = "alt2",
241 [BCM2835_FSEL_ALT3] = "alt3",
242 [BCM2835_FSEL_ALT4] = "alt4",
243 [BCM2835_FSEL_ALT5] = "alt5",
246 static const char * const irq_type_names[] = {
247 [IRQ_TYPE_NONE] = "none",
248 [IRQ_TYPE_EDGE_RISING] = "edge-rising",
249 [IRQ_TYPE_EDGE_FALLING] = "edge-falling",
250 [IRQ_TYPE_EDGE_BOTH] = "edge-both",
251 [IRQ_TYPE_LEVEL_HIGH] = "level-high",
252 [IRQ_TYPE_LEVEL_LOW] = "level-low",
255 static inline u32 bcm2835_gpio_rd(struct bcm2835_pinctrl *pc, unsigned reg)
257 return readl(pc->base + reg);
260 static inline void bcm2835_gpio_wr(struct bcm2835_pinctrl *pc, unsigned reg,
263 writel(val, pc->base + reg);
266 static inline int bcm2835_gpio_get_bit(struct bcm2835_pinctrl *pc, unsigned reg,
269 reg += GPIO_REG_OFFSET(bit) * 4;
270 return (bcm2835_gpio_rd(pc, reg) >> GPIO_REG_SHIFT(bit)) & 1;
273 /* note NOT a read/modify/write cycle */
274 static inline void bcm2835_gpio_set_bit(struct bcm2835_pinctrl *pc,
275 unsigned reg, unsigned bit)
277 reg += GPIO_REG_OFFSET(bit) * 4;
278 bcm2835_gpio_wr(pc, reg, BIT(GPIO_REG_SHIFT(bit)));
281 static inline enum bcm2835_fsel bcm2835_pinctrl_fsel_get(
282 struct bcm2835_pinctrl *pc, unsigned pin)
284 u32 val = bcm2835_gpio_rd(pc, FSEL_REG(pin));
285 enum bcm2835_fsel status = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK;
287 dev_dbg(pc->dev, "get %08x (%u => %s)\n", val, pin,
288 bcm2835_functions[status]);
293 static inline void bcm2835_pinctrl_fsel_set(
294 struct bcm2835_pinctrl *pc, unsigned pin,
295 enum bcm2835_fsel fsel)
297 u32 val = bcm2835_gpio_rd(pc, FSEL_REG(pin));
298 enum bcm2835_fsel cur = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK;
300 dev_dbg(pc->dev, "read %08x (%u => %s)\n", val, pin,
301 bcm2835_functions[cur]);
306 if (cur != BCM2835_FSEL_GPIO_IN && fsel != BCM2835_FSEL_GPIO_IN) {
307 /* always transition through GPIO_IN */
308 val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin));
309 val |= BCM2835_FSEL_GPIO_IN << FSEL_SHIFT(pin);
311 dev_dbg(pc->dev, "trans %08x (%u <= %s)\n", val, pin,
312 bcm2835_functions[BCM2835_FSEL_GPIO_IN]);
313 bcm2835_gpio_wr(pc, FSEL_REG(pin), val);
316 val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin));
317 val |= fsel << FSEL_SHIFT(pin);
319 dev_dbg(pc->dev, "write %08x (%u <= %s)\n", val, pin,
320 bcm2835_functions[fsel]);
321 bcm2835_gpio_wr(pc, FSEL_REG(pin), val);
324 static int bcm2835_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
326 return pinctrl_gpio_direction_input(chip->base + offset);
329 static int bcm2835_gpio_get(struct gpio_chip *chip, unsigned offset)
331 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
333 return bcm2835_gpio_get_bit(pc, GPLEV0, offset);
336 static int bcm2835_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
338 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
339 enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset);
341 /* Alternative function doesn't clearly provide a direction */
342 if (fsel > BCM2835_FSEL_GPIO_OUT)
345 return (fsel == BCM2835_FSEL_GPIO_IN);
348 static void bcm2835_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
350 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
352 bcm2835_gpio_set_bit(pc, value ? GPSET0 : GPCLR0, offset);
355 static int bcm2835_gpio_direction_output(struct gpio_chip *chip,
356 unsigned offset, int value)
358 bcm2835_gpio_set(chip, offset, value);
359 return pinctrl_gpio_direction_output(chip->base + offset);
362 static struct gpio_chip bcm2835_gpio_chip = {
363 .label = MODULE_NAME,
364 .owner = THIS_MODULE,
365 .request = gpiochip_generic_request,
366 .free = gpiochip_generic_free,
367 .direction_input = bcm2835_gpio_direction_input,
368 .direction_output = bcm2835_gpio_direction_output,
369 .get_direction = bcm2835_gpio_get_direction,
370 .get = bcm2835_gpio_get,
371 .set = bcm2835_gpio_set,
373 .ngpio = BCM2835_NUM_GPIOS,
377 static void bcm2835_gpio_irq_handle_bank(struct bcm2835_pinctrl *pc,
378 unsigned int bank, u32 mask)
380 unsigned long events;
385 events = bcm2835_gpio_rd(pc, GPEDS0 + bank * 4);
387 events &= pc->enabled_irq_map[bank];
388 for_each_set_bit(offset, &events, 32) {
389 gpio = (32 * bank) + offset;
390 /* FIXME: no clue why the code looks up the type here */
391 type = pc->irq_type[gpio];
393 generic_handle_irq(irq_linear_revmap(pc->gpio_chip.irqdomain,
398 static void bcm2835_gpio_irq_handler(struct irq_desc *desc)
400 struct gpio_chip *chip = irq_desc_get_handler_data(desc);
401 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
402 struct irq_chip *host_chip = irq_desc_get_chip(desc);
403 int irq = irq_desc_get_irq(desc);
407 for (i = 0; i < ARRAY_SIZE(pc->irq); i++) {
408 if (pc->irq[i] == irq) {
409 group = pc->irq_group[i];
413 /* This should not happen, every IRQ has a bank */
414 if (i == ARRAY_SIZE(pc->irq))
417 chained_irq_enter(host_chip, desc);
420 case 0: /* IRQ0 covers GPIOs 0-27 */
421 bcm2835_gpio_irq_handle_bank(pc, 0, 0x0fffffff);
423 case 1: /* IRQ1 covers GPIOs 28-45 */
424 bcm2835_gpio_irq_handle_bank(pc, 0, 0xf0000000);
425 bcm2835_gpio_irq_handle_bank(pc, 1, 0x00003fff);
427 case 2: /* IRQ2 covers GPIOs 46-53 */
428 bcm2835_gpio_irq_handle_bank(pc, 1, 0x003fc000);
432 chained_irq_exit(host_chip, desc);
435 static inline void __bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc,
436 unsigned reg, unsigned offset, bool enable)
439 reg += GPIO_REG_OFFSET(offset) * 4;
440 value = bcm2835_gpio_rd(pc, reg);
442 value |= BIT(GPIO_REG_SHIFT(offset));
444 value &= ~(BIT(GPIO_REG_SHIFT(offset)));
445 bcm2835_gpio_wr(pc, reg, value);
448 /* fast path for IRQ handler */
449 static void bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc,
450 unsigned offset, bool enable)
452 switch (pc->irq_type[offset]) {
453 case IRQ_TYPE_EDGE_RISING:
454 __bcm2835_gpio_irq_config(pc, GPREN0, offset, enable);
457 case IRQ_TYPE_EDGE_FALLING:
458 __bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable);
461 case IRQ_TYPE_EDGE_BOTH:
462 __bcm2835_gpio_irq_config(pc, GPREN0, offset, enable);
463 __bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable);
466 case IRQ_TYPE_LEVEL_HIGH:
467 __bcm2835_gpio_irq_config(pc, GPHEN0, offset, enable);
470 case IRQ_TYPE_LEVEL_LOW:
471 __bcm2835_gpio_irq_config(pc, GPLEN0, offset, enable);
476 static void bcm2835_gpio_irq_enable(struct irq_data *data)
478 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
479 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
480 unsigned gpio = irqd_to_hwirq(data);
481 unsigned offset = GPIO_REG_SHIFT(gpio);
482 unsigned bank = GPIO_REG_OFFSET(gpio);
485 spin_lock_irqsave(&pc->irq_lock[bank], flags);
486 set_bit(offset, &pc->enabled_irq_map[bank]);
487 bcm2835_gpio_irq_config(pc, gpio, true);
488 spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
491 static void bcm2835_gpio_irq_disable(struct irq_data *data)
493 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
494 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
495 unsigned gpio = irqd_to_hwirq(data);
496 unsigned offset = GPIO_REG_SHIFT(gpio);
497 unsigned bank = GPIO_REG_OFFSET(gpio);
500 spin_lock_irqsave(&pc->irq_lock[bank], flags);
501 bcm2835_gpio_irq_config(pc, gpio, false);
502 /* Clear events that were latched prior to clearing event sources */
503 bcm2835_gpio_set_bit(pc, GPEDS0, gpio);
504 clear_bit(offset, &pc->enabled_irq_map[bank]);
505 spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
508 static int __bcm2835_gpio_irq_set_type_disabled(struct bcm2835_pinctrl *pc,
509 unsigned offset, unsigned int type)
513 case IRQ_TYPE_EDGE_RISING:
514 case IRQ_TYPE_EDGE_FALLING:
515 case IRQ_TYPE_EDGE_BOTH:
516 case IRQ_TYPE_LEVEL_HIGH:
517 case IRQ_TYPE_LEVEL_LOW:
518 pc->irq_type[offset] = type;
527 /* slower path for reconfiguring IRQ type */
528 static int __bcm2835_gpio_irq_set_type_enabled(struct bcm2835_pinctrl *pc,
529 unsigned offset, unsigned int type)
533 if (pc->irq_type[offset] != type) {
534 bcm2835_gpio_irq_config(pc, offset, false);
535 pc->irq_type[offset] = type;
539 case IRQ_TYPE_EDGE_RISING:
540 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) {
541 /* RISING already enabled, disable FALLING */
542 pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING;
543 bcm2835_gpio_irq_config(pc, offset, false);
544 pc->irq_type[offset] = type;
545 } else if (pc->irq_type[offset] != type) {
546 bcm2835_gpio_irq_config(pc, offset, false);
547 pc->irq_type[offset] = type;
548 bcm2835_gpio_irq_config(pc, offset, true);
552 case IRQ_TYPE_EDGE_FALLING:
553 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) {
554 /* FALLING already enabled, disable RISING */
555 pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING;
556 bcm2835_gpio_irq_config(pc, offset, false);
557 pc->irq_type[offset] = type;
558 } else if (pc->irq_type[offset] != type) {
559 bcm2835_gpio_irq_config(pc, offset, false);
560 pc->irq_type[offset] = type;
561 bcm2835_gpio_irq_config(pc, offset, true);
565 case IRQ_TYPE_EDGE_BOTH:
566 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_RISING) {
567 /* RISING already enabled, enable FALLING too */
568 pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING;
569 bcm2835_gpio_irq_config(pc, offset, true);
570 pc->irq_type[offset] = type;
571 } else if (pc->irq_type[offset] == IRQ_TYPE_EDGE_FALLING) {
572 /* FALLING already enabled, enable RISING too */
573 pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING;
574 bcm2835_gpio_irq_config(pc, offset, true);
575 pc->irq_type[offset] = type;
576 } else if (pc->irq_type[offset] != type) {
577 bcm2835_gpio_irq_config(pc, offset, false);
578 pc->irq_type[offset] = type;
579 bcm2835_gpio_irq_config(pc, offset, true);
583 case IRQ_TYPE_LEVEL_HIGH:
584 case IRQ_TYPE_LEVEL_LOW:
585 if (pc->irq_type[offset] != type) {
586 bcm2835_gpio_irq_config(pc, offset, false);
587 pc->irq_type[offset] = type;
588 bcm2835_gpio_irq_config(pc, offset, true);
598 static int bcm2835_gpio_irq_set_type(struct irq_data *data, unsigned int type)
600 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
601 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
602 unsigned gpio = irqd_to_hwirq(data);
603 unsigned offset = GPIO_REG_SHIFT(gpio);
604 unsigned bank = GPIO_REG_OFFSET(gpio);
608 spin_lock_irqsave(&pc->irq_lock[bank], flags);
610 if (test_bit(offset, &pc->enabled_irq_map[bank]))
611 ret = __bcm2835_gpio_irq_set_type_enabled(pc, gpio, type);
613 ret = __bcm2835_gpio_irq_set_type_disabled(pc, gpio, type);
615 if (type & IRQ_TYPE_EDGE_BOTH)
616 irq_set_handler_locked(data, handle_edge_irq);
618 irq_set_handler_locked(data, handle_level_irq);
620 spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
625 static void bcm2835_gpio_irq_ack(struct irq_data *data)
627 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
628 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
629 unsigned gpio = irqd_to_hwirq(data);
631 bcm2835_gpio_set_bit(pc, GPEDS0, gpio);
634 static struct irq_chip bcm2835_gpio_irq_chip = {
636 .irq_enable = bcm2835_gpio_irq_enable,
637 .irq_disable = bcm2835_gpio_irq_disable,
638 .irq_set_type = bcm2835_gpio_irq_set_type,
639 .irq_ack = bcm2835_gpio_irq_ack,
640 .irq_mask = bcm2835_gpio_irq_disable,
641 .irq_unmask = bcm2835_gpio_irq_enable,
644 static int bcm2835_pctl_get_groups_count(struct pinctrl_dev *pctldev)
646 return ARRAY_SIZE(bcm2835_gpio_groups);
649 static const char *bcm2835_pctl_get_group_name(struct pinctrl_dev *pctldev,
652 return bcm2835_gpio_groups[selector];
655 static int bcm2835_pctl_get_group_pins(struct pinctrl_dev *pctldev,
657 const unsigned **pins,
660 *pins = &bcm2835_gpio_pins[selector].number;
666 static void bcm2835_pctl_pin_dbg_show(struct pinctrl_dev *pctldev,
670 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
671 struct gpio_chip *chip = &pc->gpio_chip;
672 enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset);
673 const char *fname = bcm2835_functions[fsel];
674 int value = bcm2835_gpio_get_bit(pc, GPLEV0, offset);
675 int irq = irq_find_mapping(chip->irqdomain, offset);
677 seq_printf(s, "function %s in %s; irq %d (%s)",
678 fname, value ? "hi" : "lo",
679 irq, irq_type_names[pc->irq_type[offset]]);
682 static void bcm2835_pctl_dt_free_map(struct pinctrl_dev *pctldev,
683 struct pinctrl_map *maps, unsigned num_maps)
687 for (i = 0; i < num_maps; i++)
688 if (maps[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
689 kfree(maps[i].data.configs.configs);
694 static int bcm2835_pctl_dt_node_to_map_func(struct bcm2835_pinctrl *pc,
695 struct device_node *np, u32 pin, u32 fnum,
696 struct pinctrl_map **maps)
698 struct pinctrl_map *map = *maps;
700 if (fnum >= ARRAY_SIZE(bcm2835_functions)) {
701 dev_err(pc->dev, "%s: invalid brcm,function %d\n",
702 of_node_full_name(np), fnum);
706 map->type = PIN_MAP_TYPE_MUX_GROUP;
707 map->data.mux.group = bcm2835_gpio_groups[pin];
708 map->data.mux.function = bcm2835_functions[fnum];
714 static int bcm2835_pctl_dt_node_to_map_pull(struct bcm2835_pinctrl *pc,
715 struct device_node *np, u32 pin, u32 pull,
716 struct pinctrl_map **maps)
718 struct pinctrl_map *map = *maps;
719 unsigned long *configs;
722 dev_err(pc->dev, "%s: invalid brcm,pull %d\n",
723 of_node_full_name(np), pull);
727 configs = kzalloc(sizeof(*configs), GFP_KERNEL);
730 configs[0] = BCM2835_PINCONF_PACK(BCM2835_PINCONF_PARAM_PULL, pull);
732 map->type = PIN_MAP_TYPE_CONFIGS_PIN;
733 map->data.configs.group_or_pin = bcm2835_gpio_pins[pin].name;
734 map->data.configs.configs = configs;
735 map->data.configs.num_configs = 1;
741 static int bcm2835_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
742 struct device_node *np,
743 struct pinctrl_map **map, unsigned *num_maps)
745 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
746 struct property *pins, *funcs, *pulls;
747 int num_pins, num_funcs, num_pulls, maps_per_pin;
748 struct pinctrl_map *maps, *cur_map;
752 pins = of_find_property(np, "brcm,pins", NULL);
754 dev_err(pc->dev, "%s: missing brcm,pins property\n",
755 of_node_full_name(np));
759 funcs = of_find_property(np, "brcm,function", NULL);
760 pulls = of_find_property(np, "brcm,pull", NULL);
762 if (!funcs && !pulls) {
764 "%s: neither brcm,function nor brcm,pull specified\n",
765 of_node_full_name(np));
769 num_pins = pins->length / 4;
770 num_funcs = funcs ? (funcs->length / 4) : 0;
771 num_pulls = pulls ? (pulls->length / 4) : 0;
773 if (num_funcs > 1 && num_funcs != num_pins) {
775 "%s: brcm,function must have 1 or %d entries\n",
776 of_node_full_name(np), num_pins);
780 if (num_pulls > 1 && num_pulls != num_pins) {
782 "%s: brcm,pull must have 1 or %d entries\n",
783 of_node_full_name(np), num_pins);
792 cur_map = maps = kzalloc(num_pins * maps_per_pin * sizeof(*maps),
797 for (i = 0; i < num_pins; i++) {
798 err = of_property_read_u32_index(np, "brcm,pins", i, &pin);
801 if (pin >= ARRAY_SIZE(bcm2835_gpio_pins)) {
802 dev_err(pc->dev, "%s: invalid brcm,pins value %d\n",
803 of_node_full_name(np), pin);
809 err = of_property_read_u32_index(np, "brcm,function",
810 (num_funcs > 1) ? i : 0, &func);
813 err = bcm2835_pctl_dt_node_to_map_func(pc, np, pin,
819 err = of_property_read_u32_index(np, "brcm,pull",
820 (num_pulls > 1) ? i : 0, &pull);
823 err = bcm2835_pctl_dt_node_to_map_pull(pc, np, pin,
831 *num_maps = num_pins * maps_per_pin;
836 bcm2835_pctl_dt_free_map(pctldev, maps, num_pins * maps_per_pin);
840 static const struct pinctrl_ops bcm2835_pctl_ops = {
841 .get_groups_count = bcm2835_pctl_get_groups_count,
842 .get_group_name = bcm2835_pctl_get_group_name,
843 .get_group_pins = bcm2835_pctl_get_group_pins,
844 .pin_dbg_show = bcm2835_pctl_pin_dbg_show,
845 .dt_node_to_map = bcm2835_pctl_dt_node_to_map,
846 .dt_free_map = bcm2835_pctl_dt_free_map,
849 static int bcm2835_pmx_free(struct pinctrl_dev *pctldev,
852 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
854 /* disable by setting to GPIO_IN */
855 bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN);
859 static int bcm2835_pmx_get_functions_count(struct pinctrl_dev *pctldev)
861 return BCM2835_FSEL_COUNT;
864 static const char *bcm2835_pmx_get_function_name(struct pinctrl_dev *pctldev,
867 return bcm2835_functions[selector];
870 static int bcm2835_pmx_get_function_groups(struct pinctrl_dev *pctldev,
872 const char * const **groups,
873 unsigned * const num_groups)
875 /* every pin can do every function */
876 *groups = bcm2835_gpio_groups;
877 *num_groups = ARRAY_SIZE(bcm2835_gpio_groups);
882 static int bcm2835_pmx_set(struct pinctrl_dev *pctldev,
883 unsigned func_selector,
884 unsigned group_selector)
886 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
888 bcm2835_pinctrl_fsel_set(pc, group_selector, func_selector);
893 static void bcm2835_pmx_gpio_disable_free(struct pinctrl_dev *pctldev,
894 struct pinctrl_gpio_range *range,
897 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
899 /* disable by setting to GPIO_IN */
900 bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN);
903 static int bcm2835_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
904 struct pinctrl_gpio_range *range,
908 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
909 enum bcm2835_fsel fsel = input ?
910 BCM2835_FSEL_GPIO_IN : BCM2835_FSEL_GPIO_OUT;
912 bcm2835_pinctrl_fsel_set(pc, offset, fsel);
917 static const struct pinmux_ops bcm2835_pmx_ops = {
918 .free = bcm2835_pmx_free,
919 .get_functions_count = bcm2835_pmx_get_functions_count,
920 .get_function_name = bcm2835_pmx_get_function_name,
921 .get_function_groups = bcm2835_pmx_get_function_groups,
922 .set_mux = bcm2835_pmx_set,
923 .gpio_disable_free = bcm2835_pmx_gpio_disable_free,
924 .gpio_set_direction = bcm2835_pmx_gpio_set_direction,
927 static int bcm2835_pinconf_get(struct pinctrl_dev *pctldev,
928 unsigned pin, unsigned long *config)
930 /* No way to read back config in HW */
934 static int bcm2835_pinconf_set(struct pinctrl_dev *pctldev,
935 unsigned pin, unsigned long *configs,
936 unsigned num_configs)
938 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
939 enum bcm2835_pinconf_param param;
944 for (i = 0; i < num_configs; i++) {
945 param = BCM2835_PINCONF_UNPACK_PARAM(configs[i]);
946 arg = BCM2835_PINCONF_UNPACK_ARG(configs[i]);
948 if (param != BCM2835_PINCONF_PARAM_PULL)
951 off = GPIO_REG_OFFSET(pin);
952 bit = GPIO_REG_SHIFT(pin);
954 bcm2835_gpio_wr(pc, GPPUD, arg & 3);
956 * BCM2835 datasheet say to wait 150 cycles, but not of what.
957 * But the VideoCore firmware delay for this operation
958 * based nearly on the same amount of VPU cycles and this clock
962 bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), BIT(bit));
964 bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), 0);
965 } /* for each config */
970 static const struct pinconf_ops bcm2835_pinconf_ops = {
971 .pin_config_get = bcm2835_pinconf_get,
972 .pin_config_set = bcm2835_pinconf_set,
975 static struct pinctrl_desc bcm2835_pinctrl_desc = {
977 .pins = bcm2835_gpio_pins,
978 .npins = ARRAY_SIZE(bcm2835_gpio_pins),
979 .pctlops = &bcm2835_pctl_ops,
980 .pmxops = &bcm2835_pmx_ops,
981 .confops = &bcm2835_pinconf_ops,
982 .owner = THIS_MODULE,
985 static struct pinctrl_gpio_range bcm2835_pinctrl_gpio_range = {
987 .npins = BCM2835_NUM_GPIOS,
990 static int bcm2835_pinctrl_probe(struct platform_device *pdev)
992 struct device *dev = &pdev->dev;
993 struct device_node *np = dev->of_node;
994 struct bcm2835_pinctrl *pc;
995 struct resource iomem;
997 BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_pins) != BCM2835_NUM_GPIOS);
998 BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_groups) != BCM2835_NUM_GPIOS);
1000 pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL);
1004 platform_set_drvdata(pdev, pc);
1007 err = of_address_to_resource(np, 0, &iomem);
1009 dev_err(dev, "could not get IO memory\n");
1013 pc->base = devm_ioremap_resource(dev, &iomem);
1014 if (IS_ERR(pc->base))
1015 return PTR_ERR(pc->base);
1017 pc->gpio_chip = bcm2835_gpio_chip;
1018 pc->gpio_chip.parent = dev;
1019 pc->gpio_chip.of_node = np;
1021 for (i = 0; i < BCM2835_NUM_BANKS; i++) {
1022 unsigned long events;
1025 /* clear event detection flags */
1026 bcm2835_gpio_wr(pc, GPREN0 + i * 4, 0);
1027 bcm2835_gpio_wr(pc, GPFEN0 + i * 4, 0);
1028 bcm2835_gpio_wr(pc, GPHEN0 + i * 4, 0);
1029 bcm2835_gpio_wr(pc, GPLEN0 + i * 4, 0);
1030 bcm2835_gpio_wr(pc, GPAREN0 + i * 4, 0);
1031 bcm2835_gpio_wr(pc, GPAFEN0 + i * 4, 0);
1033 /* clear all the events */
1034 events = bcm2835_gpio_rd(pc, GPEDS0 + i * 4);
1035 for_each_set_bit(offset, &events, 32)
1036 bcm2835_gpio_wr(pc, GPEDS0 + i * 4, BIT(offset));
1038 spin_lock_init(&pc->irq_lock[i]);
1041 err = gpiochip_add_data(&pc->gpio_chip, pc);
1043 dev_err(dev, "could not add GPIO chip\n");
1047 err = gpiochip_irqchip_add(&pc->gpio_chip, &bcm2835_gpio_irq_chip,
1048 0, handle_level_irq, IRQ_TYPE_NONE);
1050 dev_info(dev, "could not add irqchip\n");
1054 for (i = 0; i < BCM2835_NUM_IRQS; i++) {
1055 pc->irq[i] = irq_of_parse_and_map(np, i);
1056 pc->irq_group[i] = i;
1058 * Use the same handler for all groups: this is necessary
1059 * since we use one gpiochip to cover all lines - the
1060 * irq handler then needs to figure out which group and
1061 * bank that was firing the IRQ and look up the per-group
1064 gpiochip_set_chained_irqchip(&pc->gpio_chip,
1065 &bcm2835_gpio_irq_chip,
1067 bcm2835_gpio_irq_handler);
1070 pc->pctl_dev = devm_pinctrl_register(dev, &bcm2835_pinctrl_desc, pc);
1071 if (IS_ERR(pc->pctl_dev)) {
1072 gpiochip_remove(&pc->gpio_chip);
1073 return PTR_ERR(pc->pctl_dev);
1076 pc->gpio_range = bcm2835_pinctrl_gpio_range;
1077 pc->gpio_range.base = pc->gpio_chip.base;
1078 pc->gpio_range.gc = &pc->gpio_chip;
1079 pinctrl_add_gpio_range(pc->pctl_dev, &pc->gpio_range);
1084 static int bcm2835_pinctrl_remove(struct platform_device *pdev)
1086 struct bcm2835_pinctrl *pc = platform_get_drvdata(pdev);
1088 gpiochip_remove(&pc->gpio_chip);
1093 static const struct of_device_id bcm2835_pinctrl_match[] = {
1094 { .compatible = "brcm,bcm2835-gpio" },
1097 MODULE_DEVICE_TABLE(of, bcm2835_pinctrl_match);
1099 static struct platform_driver bcm2835_pinctrl_driver = {
1100 .probe = bcm2835_pinctrl_probe,
1101 .remove = bcm2835_pinctrl_remove,
1103 .name = MODULE_NAME,
1104 .of_match_table = bcm2835_pinctrl_match,
1107 module_platform_driver(bcm2835_pinctrl_driver);
1109 MODULE_AUTHOR("Chris Boot, Simon Arlott, Stephen Warren");
1110 MODULE_DESCRIPTION("BCM2835 Pin control driver");
1111 MODULE_LICENSE("GPL");