2 * Copyright (C) 2015 Broadcom Corporation
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation version 2.
8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9 * kind, whether express or implied; without even the implied warranty
10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 * This file contains the Broadcom Northstar Plus (NSP) GPIO driver that
14 * supports the chipCommonA GPIO controller. Basic PINCONF such as bias,
15 * pull up/down, slew and drive strength are also supported in this driver.
17 * Pins from the chipCommonA GPIO can be individually muxed to GPIO function,
18 * through the interaction with the NSP IOMUX controller.
21 #include <linux/gpio.h>
22 #include <linux/interrupt.h>
24 #include <linux/ioport.h>
25 #include <linux/kernel.h>
26 #include <linux/of_address.h>
27 #include <linux/of_device.h>
28 #include <linux/of_irq.h>
29 #include <linux/pinctrl/pinconf.h>
30 #include <linux/pinctrl/pinconf-generic.h>
31 #include <linux/pinctrl/pinctrl.h>
32 #include <linux/slab.h>
34 #include "../pinctrl-utils.h"
36 #define NSP_CHIP_A_INT_STATUS 0x00
37 #define NSP_CHIP_A_INT_MASK 0x04
38 #define NSP_GPIO_DATA_IN 0x40
39 #define NSP_GPIO_DATA_OUT 0x44
40 #define NSP_GPIO_OUT_EN 0x48
41 #define NSP_GPIO_INT_POLARITY 0x50
42 #define NSP_GPIO_INT_MASK 0x54
43 #define NSP_GPIO_EVENT 0x58
44 #define NSP_GPIO_EVENT_INT_MASK 0x5c
45 #define NSP_GPIO_EVENT_INT_POLARITY 0x64
46 #define NSP_CHIP_A_GPIO_INT_BIT 0x01
48 /* I/O parameters offset for chipcommon A GPIO */
49 #define NSP_GPIO_DRV_CTRL 0x00
50 #define NSP_GPIO_HYSTERESIS_EN 0x10
51 #define NSP_GPIO_SLEW_RATE_EN 0x14
52 #define NSP_PULL_UP_EN 0x18
53 #define NSP_PULL_DOWN_EN 0x1c
54 #define GPIO_DRV_STRENGTH_BITS 0x03
59 * @dev: pointer to device
60 * @base: I/O register base for nsp GPIO controller
61 * @io_ctrl: I/O register base for PINCONF support outside the GPIO block
63 * @pctl: pointer to pinctrl_dev
64 * @pctldesc: pinctrl descriptor
65 * @irq_domain: pointer to irq domain
66 * @lock: lock to protect access to I/O registers
71 void __iomem *io_ctrl;
73 struct pinctrl_dev *pctl;
74 struct pinctrl_desc pctldesc;
75 struct irq_domain *irq_domain;
84 static inline struct nsp_gpio *to_nsp_gpio(struct gpio_chip *gc)
86 return container_of(gc, struct nsp_gpio, gc);
90 * Mapping from PINCONF pins to GPIO pins is 1-to-1
92 static inline unsigned nsp_pin_to_gpio(unsigned pin)
98 * nsp_set_bit - set or clear one bit (corresponding to the GPIO pin) in a
101 * @nsp_gpio: nsp GPIO device
102 * @base_type: reg base to modify
103 * @reg: register offset
107 static inline void nsp_set_bit(struct nsp_gpio *chip, enum base_type address,
108 unsigned int reg, unsigned gpio, bool set)
111 void __iomem *base_address;
113 if (address == IO_CTRL)
114 base_address = chip->io_ctrl;
116 base_address = chip->base;
118 val = readl(base_address + reg);
124 writel(val, base_address + reg);
128 * nsp_get_bit - get one bit (corresponding to the GPIO pin) in a
131 static inline bool nsp_get_bit(struct nsp_gpio *chip, enum base_type address,
132 unsigned int reg, unsigned gpio)
134 if (address == IO_CTRL)
135 return !!(readl(chip->io_ctrl + reg) & BIT(gpio));
137 return !!(readl(chip->base + reg) & BIT(gpio));
140 static irqreturn_t nsp_gpio_irq_handler(int irq, void *data)
142 struct nsp_gpio *chip = (struct nsp_gpio *)data;
143 struct gpio_chip gc = chip->gc;
145 unsigned long int_bits = 0;
148 /* go through the entire GPIOs and handle all interrupts */
149 int_status = readl(chip->base + NSP_CHIP_A_INT_STATUS);
150 if (int_status & NSP_CHIP_A_GPIO_INT_BIT) {
151 unsigned int event, level;
153 /* Get level and edge interrupts */
154 event = readl(chip->base + NSP_GPIO_EVENT_INT_MASK) &
155 readl(chip->base + NSP_GPIO_EVENT);
156 level = readl(chip->base + NSP_GPIO_DATA_IN) ^
157 readl(chip->base + NSP_GPIO_INT_POLARITY);
158 level &= readl(chip->base + NSP_GPIO_INT_MASK);
159 int_bits = level | event;
161 for_each_set_bit(bit, &int_bits, gc.ngpio) {
163 * Clear the interrupt before invoking the
164 * handler, so we do not leave any window
166 writel(BIT(bit), chip->base + NSP_GPIO_EVENT);
168 irq_linear_revmap(chip->irq_domain, bit));
172 return int_bits ? IRQ_HANDLED : IRQ_NONE;
175 static void nsp_gpio_irq_ack(struct irq_data *d)
177 struct nsp_gpio *chip = irq_data_get_irq_chip_data(d);
178 unsigned gpio = d->hwirq;
182 trigger_type = irq_get_trigger_type(d->irq);
183 if (trigger_type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
184 nsp_set_bit(chip, REG, NSP_GPIO_EVENT, gpio, val);
188 * nsp_gpio_irq_set_mask - mask/unmask a GPIO interrupt
191 * @unmask: mask/unmask GPIO interrupt
193 static void nsp_gpio_irq_set_mask(struct irq_data *d, bool unmask)
195 struct nsp_gpio *chip = irq_data_get_irq_chip_data(d);
196 unsigned gpio = d->hwirq;
199 trigger_type = irq_get_trigger_type(d->irq);
200 if (trigger_type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
201 nsp_set_bit(chip, REG, NSP_GPIO_EVENT_INT_MASK, gpio, unmask);
203 nsp_set_bit(chip, REG, NSP_GPIO_INT_MASK, gpio, unmask);
206 static void nsp_gpio_irq_mask(struct irq_data *d)
208 struct nsp_gpio *chip = irq_data_get_irq_chip_data(d);
211 spin_lock_irqsave(&chip->lock, flags);
212 nsp_gpio_irq_set_mask(d, false);
213 spin_unlock_irqrestore(&chip->lock, flags);
216 static void nsp_gpio_irq_unmask(struct irq_data *d)
218 struct nsp_gpio *chip = irq_data_get_irq_chip_data(d);
221 spin_lock_irqsave(&chip->lock, flags);
222 nsp_gpio_irq_set_mask(d, true);
223 spin_unlock_irqrestore(&chip->lock, flags);
226 static int nsp_gpio_irq_set_type(struct irq_data *d, unsigned int type)
228 struct nsp_gpio *chip = irq_data_get_irq_chip_data(d);
229 unsigned gpio = d->hwirq;
234 spin_lock_irqsave(&chip->lock, flags);
235 falling = nsp_get_bit(chip, REG, NSP_GPIO_EVENT_INT_POLARITY, gpio);
236 level_low = nsp_get_bit(chip, REG, NSP_GPIO_INT_POLARITY, gpio);
238 switch (type & IRQ_TYPE_SENSE_MASK) {
239 case IRQ_TYPE_EDGE_RISING:
243 case IRQ_TYPE_EDGE_FALLING:
247 case IRQ_TYPE_LEVEL_HIGH:
251 case IRQ_TYPE_LEVEL_LOW:
256 dev_err(chip->dev, "invalid GPIO IRQ type 0x%x\n",
258 spin_unlock_irqrestore(&chip->lock, flags);
262 nsp_set_bit(chip, REG, NSP_GPIO_EVENT_INT_POLARITY, gpio, falling);
263 nsp_set_bit(chip, REG, NSP_GPIO_INT_POLARITY, gpio, level_low);
264 spin_unlock_irqrestore(&chip->lock, flags);
266 dev_dbg(chip->dev, "gpio:%u level_low:%s falling:%s\n", gpio,
267 level_low ? "true" : "false", falling ? "true" : "false");
271 static struct irq_chip nsp_gpio_irq_chip = {
273 .irq_enable = nsp_gpio_irq_unmask,
274 .irq_disable = nsp_gpio_irq_mask,
275 .irq_ack = nsp_gpio_irq_ack,
276 .irq_mask = nsp_gpio_irq_mask,
277 .irq_unmask = nsp_gpio_irq_unmask,
278 .irq_set_type = nsp_gpio_irq_set_type,
282 * Request the nsp IOMUX pinmux controller to mux individual pins to GPIO
284 static int nsp_gpio_request(struct gpio_chip *gc, unsigned offset)
286 unsigned gpio = gc->base + offset;
288 return pinctrl_request_gpio(gpio);
291 static void nsp_gpio_free(struct gpio_chip *gc, unsigned offset)
293 unsigned gpio = gc->base + offset;
295 pinctrl_free_gpio(gpio);
298 static int nsp_gpio_direction_input(struct gpio_chip *gc, unsigned gpio)
300 struct nsp_gpio *chip = to_nsp_gpio(gc);
303 spin_lock_irqsave(&chip->lock, flags);
304 nsp_set_bit(chip, REG, NSP_GPIO_OUT_EN, gpio, false);
305 spin_unlock_irqrestore(&chip->lock, flags);
307 dev_dbg(chip->dev, "gpio:%u set input\n", gpio);
311 static int nsp_gpio_direction_output(struct gpio_chip *gc, unsigned gpio,
314 struct nsp_gpio *chip = to_nsp_gpio(gc);
317 spin_lock_irqsave(&chip->lock, flags);
318 nsp_set_bit(chip, REG, NSP_GPIO_OUT_EN, gpio, true);
319 nsp_set_bit(chip, REG, NSP_GPIO_DATA_OUT, gpio, !!(val));
320 spin_unlock_irqrestore(&chip->lock, flags);
322 dev_dbg(chip->dev, "gpio:%u set output, value:%d\n", gpio, val);
326 static void nsp_gpio_set(struct gpio_chip *gc, unsigned gpio, int val)
328 struct nsp_gpio *chip = to_nsp_gpio(gc);
331 spin_lock_irqsave(&chip->lock, flags);
332 nsp_set_bit(chip, REG, NSP_GPIO_DATA_OUT, gpio, !!(val));
333 spin_unlock_irqrestore(&chip->lock, flags);
335 dev_dbg(chip->dev, "gpio:%u set, value:%d\n", gpio, val);
338 static int nsp_gpio_get(struct gpio_chip *gc, unsigned gpio)
340 struct nsp_gpio *chip = to_nsp_gpio(gc);
342 return !!(readl(chip->base + NSP_GPIO_DATA_IN) & BIT(gpio));
345 static int nsp_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
347 struct nsp_gpio *chip = to_nsp_gpio(gc);
349 return irq_linear_revmap(chip->irq_domain, offset);
352 static int nsp_get_groups_count(struct pinctrl_dev *pctldev)
358 * Only one group: "gpio_grp", since this local pinctrl device only performs
359 * GPIO specific PINCONF configurations
361 static const char *nsp_get_group_name(struct pinctrl_dev *pctldev,
367 static const struct pinctrl_ops nsp_pctrl_ops = {
368 .get_groups_count = nsp_get_groups_count,
369 .get_group_name = nsp_get_group_name,
370 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
371 .dt_free_map = pinctrl_utils_dt_free_map,
374 static int nsp_gpio_set_slew(struct nsp_gpio *chip, unsigned gpio, u16 slew)
377 nsp_set_bit(chip, IO_CTRL, NSP_GPIO_SLEW_RATE_EN, gpio, true);
379 nsp_set_bit(chip, IO_CTRL, NSP_GPIO_SLEW_RATE_EN, gpio, false);
384 static int nsp_gpio_set_pull(struct nsp_gpio *chip, unsigned gpio,
385 bool pull_up, bool pull_down)
389 spin_lock_irqsave(&chip->lock, flags);
390 nsp_set_bit(chip, IO_CTRL, NSP_PULL_DOWN_EN, gpio, pull_down);
391 nsp_set_bit(chip, IO_CTRL, NSP_PULL_UP_EN, gpio, pull_up);
392 spin_unlock_irqrestore(&chip->lock, flags);
394 dev_dbg(chip->dev, "gpio:%u set pullup:%d pulldown: %d\n",
395 gpio, pull_up, pull_down);
399 static void nsp_gpio_get_pull(struct nsp_gpio *chip, unsigned gpio,
400 bool *pull_up, bool *pull_down)
404 spin_lock_irqsave(&chip->lock, flags);
405 *pull_up = nsp_get_bit(chip, IO_CTRL, NSP_PULL_UP_EN, gpio);
406 *pull_down = nsp_get_bit(chip, IO_CTRL, NSP_PULL_DOWN_EN, gpio);
407 spin_unlock_irqrestore(&chip->lock, flags);
410 static int nsp_gpio_set_strength(struct nsp_gpio *chip, unsigned gpio,
413 u32 offset, shift, i;
417 /* make sure drive strength is supported */
418 if (strength < 2 || strength > 16 || (strength % 2))
422 offset = NSP_GPIO_DRV_CTRL;
423 dev_dbg(chip->dev, "gpio:%u set drive strength:%d mA\n", gpio,
425 spin_lock_irqsave(&chip->lock, flags);
426 strength = (strength / 2) - 1;
427 for (i = GPIO_DRV_STRENGTH_BITS; i > 0; i--) {
428 val = readl(chip->io_ctrl + offset);
430 val |= ((strength >> (i-1)) & 0x1) << shift;
431 writel(val, chip->io_ctrl + offset);
434 spin_unlock_irqrestore(&chip->lock, flags);
439 static int nsp_gpio_get_strength(struct nsp_gpio *chip, unsigned gpio,
442 unsigned int i, offset, shift;
446 offset = NSP_GPIO_DRV_CTRL;
449 spin_lock_irqsave(&chip->lock, flags);
451 for (i = (GPIO_DRV_STRENGTH_BITS - 1); i >= 0; i--) {
452 val = readl(chip->io_ctrl + offset) & BIT(shift);
454 *strength += (val << i);
459 *strength = (*strength + 1) * 2;
460 spin_unlock_irqrestore(&chip->lock, flags);
465 int nsp_pin_config_group_get(struct pinctrl_dev *pctldev, unsigned selector,
466 unsigned long *config)
471 int nsp_pin_config_group_set(struct pinctrl_dev *pctldev, unsigned selector,
472 unsigned long *configs, unsigned num_configs)
477 static int nsp_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin,
478 unsigned long *config)
480 struct nsp_gpio *chip = pinctrl_dev_get_drvdata(pctldev);
481 enum pin_config_param param = pinconf_to_config_param(*config);
484 bool pull_up, pull_down;
487 gpio = nsp_pin_to_gpio(pin);
489 case PIN_CONFIG_BIAS_DISABLE:
490 nsp_gpio_get_pull(chip, gpio, &pull_up, &pull_down);
491 if ((pull_up == false) && (pull_down == false))
496 case PIN_CONFIG_BIAS_PULL_UP:
497 nsp_gpio_get_pull(chip, gpio, &pull_up, &pull_down);
503 case PIN_CONFIG_BIAS_PULL_DOWN:
504 nsp_gpio_get_pull(chip, gpio, &pull_up, &pull_down);
510 case PIN_CONFIG_DRIVE_STRENGTH:
511 ret = nsp_gpio_get_strength(chip, gpio, &arg);
514 *config = pinconf_to_config_packed(param, arg);
522 static int nsp_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin,
523 unsigned long *configs, unsigned num_configs)
525 struct nsp_gpio *chip = pinctrl_dev_get_drvdata(pctldev);
526 enum pin_config_param param;
528 unsigned int i, gpio;
531 gpio = nsp_pin_to_gpio(pin);
532 for (i = 0; i < num_configs; i++) {
533 param = pinconf_to_config_param(configs[i]);
534 arg = pinconf_to_config_argument(configs[i]);
537 case PIN_CONFIG_BIAS_DISABLE:
538 ret = nsp_gpio_set_pull(chip, gpio, false, false);
543 case PIN_CONFIG_BIAS_PULL_UP:
544 ret = nsp_gpio_set_pull(chip, gpio, true, false);
549 case PIN_CONFIG_BIAS_PULL_DOWN:
550 ret = nsp_gpio_set_pull(chip, gpio, false, true);
555 case PIN_CONFIG_DRIVE_STRENGTH:
556 ret = nsp_gpio_set_strength(chip, gpio, arg);
561 case PIN_CONFIG_SLEW_RATE:
562 ret = nsp_gpio_set_slew(chip, gpio, arg);
568 dev_err(chip->dev, "invalid configuration\n");
577 static const struct pinconf_ops nsp_pconf_ops = {
579 .pin_config_get = nsp_pin_config_get,
580 .pin_config_set = nsp_pin_config_set,
581 .pin_config_group_get = nsp_pin_config_group_get,
582 .pin_config_group_set = nsp_pin_config_group_set,
586 * NSP GPIO controller supports some PINCONF related configurations such as
587 * pull up, pull down, slew and drive strength, when the pin is configured
590 * Here a local pinctrl device is created with simple 1-to-1 pin mapping to the
593 static int nsp_gpio_register_pinconf(struct nsp_gpio *chip)
595 struct pinctrl_desc *pctldesc = &chip->pctldesc;
596 struct pinctrl_pin_desc *pins;
597 struct gpio_chip *gc = &chip->gc;
600 pins = devm_kcalloc(chip->dev, gc->ngpio, sizeof(*pins), GFP_KERNEL);
603 for (i = 0; i < gc->ngpio; i++) {
605 pins[i].name = devm_kasprintf(chip->dev, GFP_KERNEL,
610 pctldesc->name = dev_name(chip->dev);
611 pctldesc->pctlops = &nsp_pctrl_ops;
612 pctldesc->pins = pins;
613 pctldesc->npins = gc->ngpio;
614 pctldesc->confops = &nsp_pconf_ops;
616 chip->pctl = pinctrl_register(pctldesc, chip->dev, chip);
617 if (IS_ERR(chip->pctl)) {
618 dev_err(chip->dev, "unable to register pinctrl device\n");
619 return PTR_ERR(chip->pctl);
625 static const struct of_device_id nsp_gpio_of_match[] = {
626 {.compatible = "brcm,nsp-gpio-a",},
630 static int nsp_gpio_probe(struct platform_device *pdev)
632 struct device *dev = &pdev->dev;
633 struct resource *res;
634 struct nsp_gpio *chip;
635 struct gpio_chip *gc;
639 if (of_property_read_u32(pdev->dev.of_node, "ngpios", &val)) {
640 dev_err(&pdev->dev, "Missing ngpios OF property\n");
644 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
649 platform_set_drvdata(pdev, chip);
651 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
652 chip->base = devm_ioremap_resource(dev, res);
653 if (IS_ERR(chip->base)) {
654 dev_err(dev, "unable to map I/O memory\n");
655 return PTR_ERR(chip->base);
658 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
659 chip->io_ctrl = devm_ioremap_resource(dev, res);
660 if (IS_ERR(chip->io_ctrl)) {
661 dev_err(dev, "unable to map I/O memory\n");
662 return PTR_ERR(chip->io_ctrl);
665 spin_lock_init(&chip->lock);
668 gc->can_sleep = false;
670 gc->label = dev_name(dev);
672 gc->of_node = dev->of_node;
673 gc->request = nsp_gpio_request;
674 gc->free = nsp_gpio_free;
675 gc->direction_input = nsp_gpio_direction_input;
676 gc->direction_output = nsp_gpio_direction_output;
677 gc->set = nsp_gpio_set;
678 gc->get = nsp_gpio_get;
679 gc->to_irq = nsp_gpio_to_irq;
681 /* optional GPIO interrupt support */
682 irq = platform_get_irq(pdev, 0);
684 /* Create irq domain so that each pin can be assigned an IRQ.*/
685 chip->irq_domain = irq_domain_add_linear(gc->of_node, gc->ngpio,
686 &irq_domain_simple_ops,
688 if (!chip->irq_domain) {
689 dev_err(&pdev->dev, "Couldn't allocate IRQ domain\n");
693 /* Map each gpio to an IRQ and set the handler for gpiolib. */
694 for (count = 0; count < gc->ngpio; count++) {
695 int irq = irq_create_mapping(chip->irq_domain, count);
697 irq_set_chip_and_handler(irq, &nsp_gpio_irq_chip,
699 set_irq_flags(irq, IRQF_VALID);
700 irq_set_chip_data(irq, chip);
703 /* Install ISR for this GPIO controller. */
704 ret = devm_request_irq(&pdev->dev, irq, nsp_gpio_irq_handler,
705 IRQF_SHARED, "gpio-a", chip);
707 dev_err(&pdev->dev, "Unable to request IRQ%d: %d\n",
709 goto err_rm_gpiochip;
712 val = readl(chip->base + NSP_CHIP_A_INT_MASK);
713 val = val | NSP_CHIP_A_GPIO_INT_BIT;
714 writel(val, (chip->base + NSP_CHIP_A_INT_MASK));
717 ret = gpiochip_add(gc);
719 dev_err(dev, "unable to add GPIO chip\n");
723 ret = nsp_gpio_register_pinconf(chip);
725 dev_err(dev, "unable to register pinconf\n");
726 goto err_rm_gpiochip;
737 static struct platform_driver nsp_gpio_driver = {
739 .name = "nsp-gpio-a",
740 .of_match_table = nsp_gpio_of_match,
742 .probe = nsp_gpio_probe,
745 static int __init nsp_gpio_init(void)
747 return platform_driver_probe(&nsp_gpio_driver, nsp_gpio_probe);
749 arch_initcall_sync(nsp_gpio_init);