2 * Core driver for the imx pin controller
4 * Copyright (C) 2012 Freescale Semiconductor, Inc.
5 * Copyright (C) 2012 Linaro Ltd.
7 * Author: Dong Aisheng <dong.aisheng@linaro.org>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
15 #include <linux/err.h>
16 #include <linux/init.h>
18 #include <linux/mfd/syscon.h>
20 #include <linux/of_device.h>
21 #include <linux/of_address.h>
22 #include <linux/pinctrl/machine.h>
23 #include <linux/pinctrl/pinconf.h>
24 #include <linux/pinctrl/pinctrl.h>
25 #include <linux/pinctrl/pinmux.h>
26 #include <linux/slab.h>
27 #include <linux/regmap.h>
30 #include "../pinmux.h"
31 #include "pinctrl-imx.h"
33 /* The bits in CONFIG cell defined in binding doc*/
34 #define IMX_NO_PAD_CTL 0x80000000 /* no pin config need */
35 #define IMX_PAD_SION 0x40000000 /* set SION */
38 * @dev: a pointer back to containing device
39 * @base: the offset to the controller in virtual memory
43 struct pinctrl_dev *pctl;
45 void __iomem *input_sel_base;
46 struct imx_pinctrl_soc_info *info;
49 static inline const struct group_desc *imx_pinctrl_find_group_by_name(
50 struct pinctrl_dev *pctldev,
53 const struct group_desc *grp = NULL;
56 for (i = 0; i < pctldev->num_groups; i++) {
57 grp = pinctrl_generic_get_group(pctldev, i);
58 if (grp && !strcmp(grp->name, name))
65 static void imx_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
68 seq_printf(s, "%s", dev_name(pctldev->dev));
71 static int imx_dt_node_to_map(struct pinctrl_dev *pctldev,
72 struct device_node *np,
73 struct pinctrl_map **map, unsigned *num_maps)
75 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
76 struct imx_pinctrl_soc_info *info = ipctl->info;
77 const struct group_desc *grp;
78 struct pinctrl_map *new_map;
79 struct device_node *parent;
84 * first find the group of this node and check if we need create
85 * config maps for pins
87 grp = imx_pinctrl_find_group_by_name(pctldev, np->name);
89 dev_err(info->dev, "unable to find group for node %s\n",
94 for (i = 0; i < grp->num_pins; i++) {
95 struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i];
97 if (!(pin->config & IMX_NO_PAD_CTL))
101 new_map = kmalloc(sizeof(struct pinctrl_map) * map_num, GFP_KERNEL);
109 parent = of_get_parent(np);
114 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
115 new_map[0].data.mux.function = parent->name;
116 new_map[0].data.mux.group = np->name;
119 /* create config map */
121 for (i = j = 0; i < grp->num_pins; i++) {
122 struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i];
124 if (!(pin->config & IMX_NO_PAD_CTL)) {
125 new_map[j].type = PIN_MAP_TYPE_CONFIGS_PIN;
126 new_map[j].data.configs.group_or_pin =
127 pin_get_name(pctldev, pin->pin);
128 new_map[j].data.configs.configs = &pin->config;
129 new_map[j].data.configs.num_configs = 1;
134 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
135 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
140 static void imx_dt_free_map(struct pinctrl_dev *pctldev,
141 struct pinctrl_map *map, unsigned num_maps)
146 static const struct pinctrl_ops imx_pctrl_ops = {
147 .get_groups_count = pinctrl_generic_get_group_count,
148 .get_group_name = pinctrl_generic_get_group_name,
149 .get_group_pins = pinctrl_generic_get_group_pins,
150 .pin_dbg_show = imx_pin_dbg_show,
151 .dt_node_to_map = imx_dt_node_to_map,
152 .dt_free_map = imx_dt_free_map,
156 static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
159 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
160 struct imx_pinctrl_soc_info *info = ipctl->info;
161 const struct imx_pin_reg *pin_reg;
162 unsigned int npins, pin_id;
164 struct group_desc *grp = NULL;
165 struct function_desc *func = NULL;
168 * Configure the mux mode for each pin in the group for a specific
171 grp = pinctrl_generic_get_group(pctldev, group);
175 func = pinmux_generic_get_function(pctldev, selector);
179 npins = grp->num_pins;
181 dev_dbg(ipctl->dev, "enable function %s group %s\n",
182 func->name, grp->name);
184 for (i = 0; i < npins; i++) {
185 struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i];
188 pin_reg = &info->pin_regs[pin_id];
190 if (pin_reg->mux_reg == -1) {
191 dev_dbg(ipctl->dev, "Pin(%s) does not support mux function\n",
192 info->pins[pin_id].name);
196 if (info->flags & SHARE_MUX_CONF_REG) {
198 reg = readl(ipctl->base + pin_reg->mux_reg);
200 reg |= (pin->mux_mode << 20);
201 writel(reg, ipctl->base + pin_reg->mux_reg);
203 writel(pin->mux_mode, ipctl->base + pin_reg->mux_reg);
205 dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
206 pin_reg->mux_reg, pin->mux_mode);
209 * If the select input value begins with 0xff, it's a quirky
210 * select input and the value should be interpreted as below.
212 * | 0xff | shift | width | select |
213 * It's used to work around the problem that the select
214 * input for some pin is not implemented in the select
215 * input register but in some general purpose register.
216 * We encode the select input value, width and shift of
217 * the bit field into input_val cell of pin function ID
218 * in device tree, and then decode them here for setting
219 * up the select input bits in general purpose register.
221 if (pin->input_val >> 24 == 0xff) {
222 u32 val = pin->input_val;
223 u8 select = val & 0xff;
224 u8 width = (val >> 8) & 0xff;
225 u8 shift = (val >> 16) & 0xff;
226 u32 mask = ((1 << width) - 1) << shift;
228 * The input_reg[i] here is actually some IOMUXC general
229 * purpose register, not regular select input register.
231 val = readl(ipctl->base + pin->input_reg);
233 val |= select << shift;
234 writel(val, ipctl->base + pin->input_reg);
235 } else if (pin->input_reg) {
237 * Regular select input register can never be at offset
238 * 0, and we only print register value for regular case.
240 if (ipctl->input_sel_base)
241 writel(pin->input_val, ipctl->input_sel_base +
244 writel(pin->input_val, ipctl->base +
247 "==>select_input: offset 0x%x val 0x%x\n",
248 pin->input_reg, pin->input_val);
255 static int imx_pmx_gpio_request_enable(struct pinctrl_dev *pctldev,
256 struct pinctrl_gpio_range *range, unsigned offset)
258 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
259 struct imx_pinctrl_soc_info *info = ipctl->info;
260 const struct imx_pin_reg *pin_reg;
261 struct group_desc *grp;
262 struct imx_pin *imx_pin;
263 unsigned int pin, group;
266 /* Currently implementation only for shared mux/conf register */
267 if (!(info->flags & SHARE_MUX_CONF_REG))
270 pin_reg = &info->pin_regs[offset];
271 if (pin_reg->mux_reg == -1)
274 /* Find the pinctrl config with GPIO mux mode for the requested pin */
275 for (group = 0; group < pctldev->num_groups; group++) {
276 grp = pinctrl_generic_get_group(pctldev, group);
279 for (pin = 0; pin < grp->num_pins; pin++) {
280 imx_pin = &((struct imx_pin *)(grp->data))[pin];
281 if (imx_pin->pin == offset && !imx_pin->mux_mode)
289 reg = readl(ipctl->base + pin_reg->mux_reg);
291 reg |= imx_pin->config;
292 writel(reg, ipctl->base + pin_reg->mux_reg);
297 static void imx_pmx_gpio_disable_free(struct pinctrl_dev *pctldev,
298 struct pinctrl_gpio_range *range, unsigned offset)
300 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
301 struct imx_pinctrl_soc_info *info = ipctl->info;
302 const struct imx_pin_reg *pin_reg;
306 * Only Vybrid has the input/output buffer enable flags (IBE/OBE)
307 * They are part of the shared mux/conf register.
309 if (!(info->flags & SHARE_MUX_CONF_REG))
312 pin_reg = &info->pin_regs[offset];
313 if (pin_reg->mux_reg == -1)
316 /* Clear IBE/OBE/PUE to disable the pin (Hi-Z) */
317 reg = readl(ipctl->base + pin_reg->mux_reg);
319 writel(reg, ipctl->base + pin_reg->mux_reg);
322 static int imx_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
323 struct pinctrl_gpio_range *range, unsigned offset, bool input)
325 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
326 struct imx_pinctrl_soc_info *info = ipctl->info;
327 const struct imx_pin_reg *pin_reg;
331 * Only Vybrid has the input/output buffer enable flags (IBE/OBE)
332 * They are part of the shared mux/conf register.
334 if (!(info->flags & SHARE_MUX_CONF_REG))
337 pin_reg = &info->pin_regs[offset];
338 if (pin_reg->mux_reg == -1)
341 /* IBE always enabled allows us to read the value "on the wire" */
342 reg = readl(ipctl->base + pin_reg->mux_reg);
347 writel(reg, ipctl->base + pin_reg->mux_reg);
352 static const struct pinmux_ops imx_pmx_ops = {
353 .get_functions_count = pinmux_generic_get_function_count,
354 .get_function_name = pinmux_generic_get_function_name,
355 .get_function_groups = pinmux_generic_get_function_groups,
356 .set_mux = imx_pmx_set,
357 .gpio_request_enable = imx_pmx_gpio_request_enable,
358 .gpio_disable_free = imx_pmx_gpio_disable_free,
359 .gpio_set_direction = imx_pmx_gpio_set_direction,
362 static int imx_pinconf_get(struct pinctrl_dev *pctldev,
363 unsigned pin_id, unsigned long *config)
365 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
366 struct imx_pinctrl_soc_info *info = ipctl->info;
367 const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id];
369 if (pin_reg->conf_reg == -1) {
370 dev_err(info->dev, "Pin(%s) does not support config function\n",
371 info->pins[pin_id].name);
375 *config = readl(ipctl->base + pin_reg->conf_reg);
377 if (info->flags & SHARE_MUX_CONF_REG)
383 static int imx_pinconf_set(struct pinctrl_dev *pctldev,
384 unsigned pin_id, unsigned long *configs,
385 unsigned num_configs)
387 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
388 struct imx_pinctrl_soc_info *info = ipctl->info;
389 const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id];
392 if (pin_reg->conf_reg == -1) {
393 dev_err(info->dev, "Pin(%s) does not support config function\n",
394 info->pins[pin_id].name);
398 dev_dbg(ipctl->dev, "pinconf set pin %s\n",
399 info->pins[pin_id].name);
401 for (i = 0; i < num_configs; i++) {
402 if (info->flags & SHARE_MUX_CONF_REG) {
404 reg = readl(ipctl->base + pin_reg->conf_reg);
407 writel(reg, ipctl->base + pin_reg->conf_reg);
409 writel(configs[i], ipctl->base + pin_reg->conf_reg);
411 dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%lx\n",
412 pin_reg->conf_reg, configs[i]);
413 } /* for each config */
418 static void imx_pinconf_dbg_show(struct pinctrl_dev *pctldev,
419 struct seq_file *s, unsigned pin_id)
421 struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
422 struct imx_pinctrl_soc_info *info = ipctl->info;
423 const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id];
424 unsigned long config;
426 if (!pin_reg || pin_reg->conf_reg == -1) {
427 seq_printf(s, "N/A");
431 config = readl(ipctl->base + pin_reg->conf_reg);
432 seq_printf(s, "0x%lx", config);
435 static void imx_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
436 struct seq_file *s, unsigned group)
438 struct group_desc *grp;
439 unsigned long config;
443 if (group > pctldev->num_groups)
447 grp = pinctrl_generic_get_group(pctldev, group);
451 for (i = 0; i < grp->num_pins; i++) {
452 struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i];
454 name = pin_get_name(pctldev, pin->pin);
455 ret = imx_pinconf_get(pctldev, pin->pin, &config);
458 seq_printf(s, " %s: 0x%lx\n", name, config);
462 static const struct pinconf_ops imx_pinconf_ops = {
463 .pin_config_get = imx_pinconf_get,
464 .pin_config_set = imx_pinconf_set,
465 .pin_config_dbg_show = imx_pinconf_dbg_show,
466 .pin_config_group_dbg_show = imx_pinconf_group_dbg_show,
470 * Each pin represented in fsl,pins consists of 5 u32 PIN_FUNC_ID and
471 * 1 u32 CONFIG, so 24 types in total for each pin.
473 #define FSL_PIN_SIZE 24
474 #define SHARE_FSL_PIN_SIZE 20
476 static int imx_pinctrl_parse_groups(struct device_node *np,
477 struct group_desc *grp,
478 struct imx_pinctrl_soc_info *info,
486 dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
488 if (info->flags & SHARE_MUX_CONF_REG)
489 pin_size = SHARE_FSL_PIN_SIZE;
491 pin_size = FSL_PIN_SIZE;
492 /* Initialise group */
493 grp->name = np->name;
496 * the binding format is fsl,pins = <PIN_FUNC_ID CONFIG ...>,
497 * do sanity check and calculate pins number
499 list = of_get_property(np, "fsl,pins", &size);
501 dev_err(info->dev, "no fsl,pins property in node %s\n", np->full_name);
505 /* we do not check return since it's safe node passed down */
506 if (!size || size % pin_size) {
507 dev_err(info->dev, "Invalid fsl,pins property in node %s\n", np->full_name);
511 grp->num_pins = size / pin_size;
512 grp->data = devm_kzalloc(info->dev, grp->num_pins *
513 sizeof(struct imx_pin), GFP_KERNEL);
514 grp->pins = devm_kzalloc(info->dev, grp->num_pins *
515 sizeof(unsigned int), GFP_KERNEL);
516 if (!grp->pins || !grp->data)
519 for (i = 0; i < grp->num_pins; i++) {
520 u32 mux_reg = be32_to_cpu(*list++);
523 struct imx_pin_reg *pin_reg;
524 struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i];
526 if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg)
529 if (info->flags & SHARE_MUX_CONF_REG) {
532 conf_reg = be32_to_cpu(*list++);
537 pin_id = (mux_reg != -1) ? mux_reg / 4 : conf_reg / 4;
538 pin_reg = &info->pin_regs[pin_id];
540 grp->pins[i] = pin_id;
541 pin_reg->mux_reg = mux_reg;
542 pin_reg->conf_reg = conf_reg;
543 pin->input_reg = be32_to_cpu(*list++);
544 pin->mux_mode = be32_to_cpu(*list++);
545 pin->input_val = be32_to_cpu(*list++);
547 /* SION bit is in mux register */
548 config = be32_to_cpu(*list++);
549 if (config & IMX_PAD_SION)
550 pin->mux_mode |= IOMUXC_CONFIG_SION;
551 pin->config = config & ~IMX_PAD_SION;
553 dev_dbg(info->dev, "%s: 0x%x 0x%08lx", info->pins[pin_id].name,
554 pin->mux_mode, pin->config);
560 static int imx_pinctrl_parse_functions(struct device_node *np,
561 struct imx_pinctrl *ipctl,
564 struct pinctrl_dev *pctl = ipctl->pctl;
565 struct imx_pinctrl_soc_info *info = ipctl->info;
566 struct device_node *child;
567 struct function_desc *func;
568 struct group_desc *grp;
571 dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
573 func = pinmux_generic_get_function(pctl, index);
577 /* Initialise function */
578 func->name = np->name;
579 func->num_group_names = of_get_child_count(np);
580 if (func->num_group_names == 0) {
581 dev_err(info->dev, "no groups defined in %s\n", np->full_name);
584 func->group_names = devm_kzalloc(info->dev,
585 func->num_group_names *
586 sizeof(char *), GFP_KERNEL);
588 for_each_child_of_node(np, child) {
589 func->group_names[i] = child->name;
591 grp = devm_kzalloc(info->dev, sizeof(struct group_desc),
596 mutex_lock(&info->mutex);
597 radix_tree_insert(&pctl->pin_group_tree,
598 info->group_index++, grp);
599 mutex_unlock(&info->mutex);
601 imx_pinctrl_parse_groups(child, grp, info, i++);
608 * Check if the DT contains pins in the direct child nodes. This indicates the
609 * newer DT format to store pins. This function returns true if the first found
610 * fsl,pins property is in a child of np. Otherwise false is returned.
612 static bool imx_pinctrl_dt_is_flat_functions(struct device_node *np)
614 struct device_node *function_np;
615 struct device_node *pinctrl_np;
617 for_each_child_of_node(np, function_np) {
618 if (of_property_read_bool(function_np, "fsl,pins"))
621 for_each_child_of_node(function_np, pinctrl_np) {
622 if (of_property_read_bool(pinctrl_np, "fsl,pins"))
630 static int imx_pinctrl_probe_dt(struct platform_device *pdev,
631 struct imx_pinctrl *ipctl)
633 struct device_node *np = pdev->dev.of_node;
634 struct device_node *child;
635 struct pinctrl_dev *pctl = ipctl->pctl;
636 struct imx_pinctrl_soc_info *info = ipctl->info;
644 flat_funcs = imx_pinctrl_dt_is_flat_functions(np);
648 nfuncs = of_get_child_count(np);
650 dev_err(&pdev->dev, "no functions defined\n");
655 for (i = 0; i < nfuncs; i++) {
656 struct function_desc *function;
658 function = devm_kzalloc(&pdev->dev, sizeof(*function),
663 mutex_lock(&info->mutex);
664 radix_tree_insert(&pctl->pin_function_tree, i, function);
665 mutex_unlock(&info->mutex);
667 pctl->num_functions = nfuncs;
669 info->group_index = 0;
671 pctl->num_groups = of_get_child_count(np);
673 pctl->num_groups = 0;
674 for_each_child_of_node(np, child)
675 pctl->num_groups += of_get_child_count(child);
679 imx_pinctrl_parse_functions(np, ipctl, 0);
682 for_each_child_of_node(np, child)
683 imx_pinctrl_parse_functions(child, ipctl, i++);
690 * imx_free_resources() - free memory used by this driver
691 * @info: info driver instance
693 static void imx_free_resources(struct imx_pinctrl *ipctl)
696 pinctrl_unregister(ipctl->pctl);
699 int imx_pinctrl_probe(struct platform_device *pdev,
700 struct imx_pinctrl_soc_info *info)
702 struct regmap_config config = { .name = "gpr" };
703 struct device_node *dev_np = pdev->dev.of_node;
704 struct pinctrl_desc *imx_pinctrl_desc;
705 struct device_node *np;
706 struct imx_pinctrl *ipctl;
707 struct resource *res;
711 if (!info || !info->pins || !info->npins) {
712 dev_err(&pdev->dev, "wrong pinctrl info\n");
715 info->dev = &pdev->dev;
717 if (info->gpr_compatible) {
718 gpr = syscon_regmap_lookup_by_compatible(info->gpr_compatible);
720 regmap_attach_dev(&pdev->dev, gpr, &config);
723 /* Create state holders etc for this driver */
724 ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL);
728 info->pin_regs = devm_kmalloc(&pdev->dev, sizeof(*info->pin_regs) *
729 info->npins, GFP_KERNEL);
733 for (i = 0; i < info->npins; i++) {
734 info->pin_regs[i].mux_reg = -1;
735 info->pin_regs[i].conf_reg = -1;
738 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
739 ipctl->base = devm_ioremap_resource(&pdev->dev, res);
740 if (IS_ERR(ipctl->base))
741 return PTR_ERR(ipctl->base);
743 if (of_property_read_bool(dev_np, "fsl,input-sel")) {
744 np = of_parse_phandle(dev_np, "fsl,input-sel", 0);
746 dev_err(&pdev->dev, "iomuxc fsl,input-sel property not found\n");
750 ipctl->input_sel_base = of_iomap(np, 0);
752 if (!ipctl->input_sel_base) {
754 "iomuxc input select base address not found\n");
759 imx_pinctrl_desc = devm_kzalloc(&pdev->dev, sizeof(*imx_pinctrl_desc),
761 if (!imx_pinctrl_desc)
764 imx_pinctrl_desc->name = dev_name(&pdev->dev);
765 imx_pinctrl_desc->pins = info->pins;
766 imx_pinctrl_desc->npins = info->npins;
767 imx_pinctrl_desc->pctlops = &imx_pctrl_ops;
768 imx_pinctrl_desc->pmxops = &imx_pmx_ops;
769 imx_pinctrl_desc->confops = &imx_pinconf_ops;
770 imx_pinctrl_desc->owner = THIS_MODULE;
772 mutex_init(&info->mutex);
775 ipctl->dev = info->dev;
776 platform_set_drvdata(pdev, ipctl);
777 ret = devm_pinctrl_register_and_init(&pdev->dev,
778 imx_pinctrl_desc, ipctl,
781 dev_err(&pdev->dev, "could not register IMX pinctrl driver\n");
785 ret = imx_pinctrl_probe_dt(pdev, ipctl);
787 dev_err(&pdev->dev, "fail to probe dt properties\n");
791 dev_info(&pdev->dev, "initialized IMX pinctrl driver\n");
796 imx_free_resources(ipctl);