2 * Cherryview/Braswell pinctrl driver
4 * Copyright (C) 2014, Intel Corporation
5 * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
7 * This driver is based on the original Cherryview GPIO driver by
8 * Ning Li <ning.li@intel.com>
9 * Alan Cox <alan@linux.intel.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 #include <linux/dmi.h>
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/init.h>
20 #include <linux/types.h>
21 #include <linux/gpio.h>
22 #include <linux/gpio/driver.h>
23 #include <linux/acpi.h>
24 #include <linux/pinctrl/pinctrl.h>
25 #include <linux/pinctrl/pinmux.h>
26 #include <linux/pinctrl/pinconf.h>
27 #include <linux/pinctrl/pinconf-generic.h>
28 #include <linux/platform_device.h>
30 #define CHV_INTSTAT 0x300
31 #define CHV_INTMASK 0x380
33 #define FAMILY_PAD_REGS_OFF 0x4400
34 #define FAMILY_PAD_REGS_SIZE 0x400
35 #define MAX_FAMILY_PAD_GPIO_NO 15
36 #define GPIO_REGS_SIZE 8
38 #define CHV_PADCTRL0 0x000
39 #define CHV_PADCTRL0_INTSEL_SHIFT 28
40 #define CHV_PADCTRL0_INTSEL_MASK (0xf << CHV_PADCTRL0_INTSEL_SHIFT)
41 #define CHV_PADCTRL0_TERM_UP BIT(23)
42 #define CHV_PADCTRL0_TERM_SHIFT 20
43 #define CHV_PADCTRL0_TERM_MASK (7 << CHV_PADCTRL0_TERM_SHIFT)
44 #define CHV_PADCTRL0_TERM_20K 1
45 #define CHV_PADCTRL0_TERM_5K 2
46 #define CHV_PADCTRL0_TERM_1K 4
47 #define CHV_PADCTRL0_PMODE_SHIFT 16
48 #define CHV_PADCTRL0_PMODE_MASK (0xf << CHV_PADCTRL0_PMODE_SHIFT)
49 #define CHV_PADCTRL0_GPIOEN BIT(15)
50 #define CHV_PADCTRL0_GPIOCFG_SHIFT 8
51 #define CHV_PADCTRL0_GPIOCFG_MASK (7 << CHV_PADCTRL0_GPIOCFG_SHIFT)
52 #define CHV_PADCTRL0_GPIOCFG_GPIO 0
53 #define CHV_PADCTRL0_GPIOCFG_GPO 1
54 #define CHV_PADCTRL0_GPIOCFG_GPI 2
55 #define CHV_PADCTRL0_GPIOCFG_HIZ 3
56 #define CHV_PADCTRL0_GPIOTXSTATE BIT(1)
57 #define CHV_PADCTRL0_GPIORXSTATE BIT(0)
59 #define CHV_PADCTRL1 0x004
60 #define CHV_PADCTRL1_CFGLOCK BIT(31)
61 #define CHV_PADCTRL1_INVRXTX_SHIFT 4
62 #define CHV_PADCTRL1_INVRXTX_MASK (0xf << CHV_PADCTRL1_INVRXTX_SHIFT)
63 #define CHV_PADCTRL1_INVRXTX_TXENABLE (2 << CHV_PADCTRL1_INVRXTX_SHIFT)
64 #define CHV_PADCTRL1_ODEN BIT(3)
65 #define CHV_PADCTRL1_INVRXTX_RXDATA (4 << CHV_PADCTRL1_INVRXTX_SHIFT)
66 #define CHV_PADCTRL1_INTWAKECFG_MASK 7
67 #define CHV_PADCTRL1_INTWAKECFG_FALLING 1
68 #define CHV_PADCTRL1_INTWAKECFG_RISING 2
69 #define CHV_PADCTRL1_INTWAKECFG_BOTH 3
70 #define CHV_PADCTRL1_INTWAKECFG_LEVEL 4
73 * struct chv_alternate_function - A per group or per pin alternate function
74 * @pin: Pin number (only used in per pin configs)
75 * @mode: Mode the pin should be set in
76 * @invert_oe: Invert OE for this pin
78 struct chv_alternate_function {
85 * struct chv_pincgroup - describes a CHV pin group
86 * @name: Name of the group
87 * @pins: An array of pins in this group
88 * @npins: Number of pins in this group
89 * @altfunc: Alternate function applied to all pins in this group
90 * @overrides: Alternate function override per pin or %NULL if not used
91 * @noverrides: Number of per pin alternate function overrides if
98 struct chv_alternate_function altfunc;
99 const struct chv_alternate_function *overrides;
104 * struct chv_function - A CHV pinmux function
105 * @name: Name of the function
106 * @groups: An array of groups for this function
107 * @ngroups: Number of groups in @groups
109 struct chv_function {
111 const char * const *groups;
116 * struct chv_gpio_pinrange - A range of pins that can be used as GPIOs
117 * @base: Start pin number
118 * @npins: Number of pins in this range
120 struct chv_gpio_pinrange {
126 * struct chv_community - A community specific configuration
127 * @uid: ACPI _UID used to match the community
128 * @pins: All pins in this community
129 * @npins: Number of pins
130 * @groups: All groups in this community
131 * @ngroups: Number of groups
132 * @functions: All functions in this community
133 * @nfunctions: Number of functions
134 * @ngpios: Number of GPIOs in this community
135 * @gpio_ranges: An array of GPIO ranges in this community
136 * @ngpio_ranges: Number of GPIO ranges
137 * @ngpios: Total number of GPIOs in this community
138 * @nirqs: Total number of IRQs this community can generate
140 struct chv_community {
142 const struct pinctrl_pin_desc *pins;
144 const struct chv_pingroup *groups;
146 const struct chv_function *functions;
148 const struct chv_gpio_pinrange *gpio_ranges;
154 struct chv_pin_context {
160 * struct chv_pinctrl - CHV pinctrl private structure
161 * @dev: Pointer to the parent device
162 * @pctldesc: Pin controller description
163 * @pctldev: Pointer to the pin controller device
164 * @chip: GPIO chip in this pin controller
165 * @regs: MMIO registers
166 * @intr_lines: Stores mapping between 16 HW interrupt wires and GPIO
167 * offset (in GPIO number space)
168 * @community: Community this pinctrl instance represents
170 * The first group in @groups is expected to contain all pins that can be
175 struct pinctrl_desc pctldesc;
176 struct pinctrl_dev *pctldev;
177 struct gpio_chip chip;
179 unsigned intr_lines[16];
180 const struct chv_community *community;
182 struct chv_pin_context *saved_pin_context;
185 #define ALTERNATE_FUNCTION(p, m, i) \
192 #define PIN_GROUP(n, p, m, i) \
196 .npins = ARRAY_SIZE((p)), \
197 .altfunc.mode = (m), \
198 .altfunc.invert_oe = (i), \
201 #define PIN_GROUP_WITH_OVERRIDE(n, p, m, i, o) \
205 .npins = ARRAY_SIZE((p)), \
206 .altfunc.mode = (m), \
207 .altfunc.invert_oe = (i), \
209 .noverrides = ARRAY_SIZE((o)), \
212 #define FUNCTION(n, g) \
216 .ngroups = ARRAY_SIZE((g)), \
219 #define GPIO_PINRANGE(start, end) \
222 .npins = (end) - (start) + 1, \
225 static const struct pinctrl_pin_desc southwest_pins[] = {
226 PINCTRL_PIN(0, "FST_SPI_D2"),
227 PINCTRL_PIN(1, "FST_SPI_D0"),
228 PINCTRL_PIN(2, "FST_SPI_CLK"),
229 PINCTRL_PIN(3, "FST_SPI_D3"),
230 PINCTRL_PIN(4, "FST_SPI_CS1_B"),
231 PINCTRL_PIN(5, "FST_SPI_D1"),
232 PINCTRL_PIN(6, "FST_SPI_CS0_B"),
233 PINCTRL_PIN(7, "FST_SPI_CS2_B"),
235 PINCTRL_PIN(15, "UART1_RTS_B"),
236 PINCTRL_PIN(16, "UART1_RXD"),
237 PINCTRL_PIN(17, "UART2_RXD"),
238 PINCTRL_PIN(18, "UART1_CTS_B"),
239 PINCTRL_PIN(19, "UART2_RTS_B"),
240 PINCTRL_PIN(20, "UART1_TXD"),
241 PINCTRL_PIN(21, "UART2_TXD"),
242 PINCTRL_PIN(22, "UART2_CTS_B"),
244 PINCTRL_PIN(30, "MF_HDA_CLK"),
245 PINCTRL_PIN(31, "MF_HDA_RSTB"),
246 PINCTRL_PIN(32, "MF_HDA_SDIO"),
247 PINCTRL_PIN(33, "MF_HDA_SDO"),
248 PINCTRL_PIN(34, "MF_HDA_DOCKRSTB"),
249 PINCTRL_PIN(35, "MF_HDA_SYNC"),
250 PINCTRL_PIN(36, "MF_HDA_SDI1"),
251 PINCTRL_PIN(37, "MF_HDA_DOCKENB"),
253 PINCTRL_PIN(45, "I2C5_SDA"),
254 PINCTRL_PIN(46, "I2C4_SDA"),
255 PINCTRL_PIN(47, "I2C6_SDA"),
256 PINCTRL_PIN(48, "I2C5_SCL"),
257 PINCTRL_PIN(49, "I2C_NFC_SDA"),
258 PINCTRL_PIN(50, "I2C4_SCL"),
259 PINCTRL_PIN(51, "I2C6_SCL"),
260 PINCTRL_PIN(52, "I2C_NFC_SCL"),
262 PINCTRL_PIN(60, "I2C1_SDA"),
263 PINCTRL_PIN(61, "I2C0_SDA"),
264 PINCTRL_PIN(62, "I2C2_SDA"),
265 PINCTRL_PIN(63, "I2C1_SCL"),
266 PINCTRL_PIN(64, "I2C3_SDA"),
267 PINCTRL_PIN(65, "I2C0_SCL"),
268 PINCTRL_PIN(66, "I2C2_SCL"),
269 PINCTRL_PIN(67, "I2C3_SCL"),
271 PINCTRL_PIN(75, "SATA_GP0"),
272 PINCTRL_PIN(76, "SATA_GP1"),
273 PINCTRL_PIN(77, "SATA_LEDN"),
274 PINCTRL_PIN(78, "SATA_GP2"),
275 PINCTRL_PIN(79, "MF_SMB_ALERTB"),
276 PINCTRL_PIN(80, "SATA_GP3"),
277 PINCTRL_PIN(81, "MF_SMB_CLK"),
278 PINCTRL_PIN(82, "MF_SMB_DATA"),
280 PINCTRL_PIN(90, "PCIE_CLKREQ0B"),
281 PINCTRL_PIN(91, "PCIE_CLKREQ1B"),
282 PINCTRL_PIN(92, "GP_SSP_2_CLK"),
283 PINCTRL_PIN(93, "PCIE_CLKREQ2B"),
284 PINCTRL_PIN(94, "GP_SSP_2_RXD"),
285 PINCTRL_PIN(95, "PCIE_CLKREQ3B"),
286 PINCTRL_PIN(96, "GP_SSP_2_FS"),
287 PINCTRL_PIN(97, "GP_SSP_2_TXD"),
290 static const unsigned southwest_fspi_pins[] = { 0, 1, 2, 3, 4, 5, 6, 7 };
291 static const unsigned southwest_uart0_pins[] = { 16, 20 };
292 static const unsigned southwest_uart1_pins[] = { 15, 16, 18, 20 };
293 static const unsigned southwest_uart2_pins[] = { 17, 19, 21, 22 };
294 static const unsigned southwest_i2c0_pins[] = { 61, 65 };
295 static const unsigned southwest_hda_pins[] = { 30, 31, 32, 33, 34, 35, 36, 37 };
296 static const unsigned southwest_lpe_pins[] = {
297 30, 31, 32, 33, 34, 35, 36, 37, 92, 94, 96, 97,
299 static const unsigned southwest_i2c1_pins[] = { 60, 63 };
300 static const unsigned southwest_i2c2_pins[] = { 62, 66 };
301 static const unsigned southwest_i2c3_pins[] = { 64, 67 };
302 static const unsigned southwest_i2c4_pins[] = { 46, 50 };
303 static const unsigned southwest_i2c5_pins[] = { 45, 48 };
304 static const unsigned southwest_i2c6_pins[] = { 47, 51 };
305 static const unsigned southwest_i2c_nfc_pins[] = { 49, 52 };
306 static const unsigned southwest_smbus_pins[] = { 79, 81, 82 };
307 static const unsigned southwest_spi3_pins[] = { 76, 79, 80, 81, 82 };
309 /* LPE I2S TXD pins need to have invert_oe set */
310 static const struct chv_alternate_function southwest_lpe_altfuncs[] = {
311 ALTERNATE_FUNCTION(30, 1, true),
312 ALTERNATE_FUNCTION(34, 1, true),
313 ALTERNATE_FUNCTION(97, 1, true),
317 * Two spi3 chipselects are available in different mode than the main spi3
318 * functionality, which is using mode 1.
320 static const struct chv_alternate_function southwest_spi3_altfuncs[] = {
321 ALTERNATE_FUNCTION(76, 3, false),
322 ALTERNATE_FUNCTION(80, 3, false),
325 static const struct chv_pingroup southwest_groups[] = {
326 PIN_GROUP("uart0_grp", southwest_uart0_pins, 2, false),
327 PIN_GROUP("uart1_grp", southwest_uart1_pins, 1, false),
328 PIN_GROUP("uart2_grp", southwest_uart2_pins, 1, false),
329 PIN_GROUP("hda_grp", southwest_hda_pins, 2, false),
330 PIN_GROUP("i2c0_grp", southwest_i2c0_pins, 1, true),
331 PIN_GROUP("i2c1_grp", southwest_i2c1_pins, 1, true),
332 PIN_GROUP("i2c2_grp", southwest_i2c2_pins, 1, true),
333 PIN_GROUP("i2c3_grp", southwest_i2c3_pins, 1, true),
334 PIN_GROUP("i2c4_grp", southwest_i2c4_pins, 1, true),
335 PIN_GROUP("i2c5_grp", southwest_i2c5_pins, 1, true),
336 PIN_GROUP("i2c6_grp", southwest_i2c6_pins, 1, true),
337 PIN_GROUP("i2c_nfc_grp", southwest_i2c_nfc_pins, 2, true),
339 PIN_GROUP_WITH_OVERRIDE("lpe_grp", southwest_lpe_pins, 1, false,
340 southwest_lpe_altfuncs),
341 PIN_GROUP_WITH_OVERRIDE("spi3_grp", southwest_spi3_pins, 2, false,
342 southwest_spi3_altfuncs),
345 static const char * const southwest_uart0_groups[] = { "uart0_grp" };
346 static const char * const southwest_uart1_groups[] = { "uart1_grp" };
347 static const char * const southwest_uart2_groups[] = { "uart2_grp" };
348 static const char * const southwest_hda_groups[] = { "hda_grp" };
349 static const char * const southwest_lpe_groups[] = { "lpe_grp" };
350 static const char * const southwest_i2c0_groups[] = { "i2c0_grp" };
351 static const char * const southwest_i2c1_groups[] = { "i2c1_grp" };
352 static const char * const southwest_i2c2_groups[] = { "i2c2_grp" };
353 static const char * const southwest_i2c3_groups[] = { "i2c3_grp" };
354 static const char * const southwest_i2c4_groups[] = { "i2c4_grp" };
355 static const char * const southwest_i2c5_groups[] = { "i2c5_grp" };
356 static const char * const southwest_i2c6_groups[] = { "i2c6_grp" };
357 static const char * const southwest_i2c_nfc_groups[] = { "i2c_nfc_grp" };
358 static const char * const southwest_spi3_groups[] = { "spi3_grp" };
361 * Only do pinmuxing for certain LPSS devices for now. Rest of the pins are
362 * enabled only as GPIOs.
364 static const struct chv_function southwest_functions[] = {
365 FUNCTION("uart0", southwest_uart0_groups),
366 FUNCTION("uart1", southwest_uart1_groups),
367 FUNCTION("uart2", southwest_uart2_groups),
368 FUNCTION("hda", southwest_hda_groups),
369 FUNCTION("lpe", southwest_lpe_groups),
370 FUNCTION("i2c0", southwest_i2c0_groups),
371 FUNCTION("i2c1", southwest_i2c1_groups),
372 FUNCTION("i2c2", southwest_i2c2_groups),
373 FUNCTION("i2c3", southwest_i2c3_groups),
374 FUNCTION("i2c4", southwest_i2c4_groups),
375 FUNCTION("i2c5", southwest_i2c5_groups),
376 FUNCTION("i2c6", southwest_i2c6_groups),
377 FUNCTION("i2c_nfc", southwest_i2c_nfc_groups),
378 FUNCTION("spi3", southwest_spi3_groups),
381 static const struct chv_gpio_pinrange southwest_gpio_ranges[] = {
383 GPIO_PINRANGE(15, 22),
384 GPIO_PINRANGE(30, 37),
385 GPIO_PINRANGE(45, 52),
386 GPIO_PINRANGE(60, 67),
387 GPIO_PINRANGE(75, 82),
388 GPIO_PINRANGE(90, 97),
391 static const struct chv_community southwest_community = {
393 .pins = southwest_pins,
394 .npins = ARRAY_SIZE(southwest_pins),
395 .groups = southwest_groups,
396 .ngroups = ARRAY_SIZE(southwest_groups),
397 .functions = southwest_functions,
398 .nfunctions = ARRAY_SIZE(southwest_functions),
399 .gpio_ranges = southwest_gpio_ranges,
400 .ngpio_ranges = ARRAY_SIZE(southwest_gpio_ranges),
401 .ngpios = ARRAY_SIZE(southwest_pins),
403 * Southwest community can benerate GPIO interrupts only for the
404 * first 8 interrupts. The upper half (8-15) can only be used to
410 static const struct pinctrl_pin_desc north_pins[] = {
411 PINCTRL_PIN(0, "GPIO_DFX_0"),
412 PINCTRL_PIN(1, "GPIO_DFX_3"),
413 PINCTRL_PIN(2, "GPIO_DFX_7"),
414 PINCTRL_PIN(3, "GPIO_DFX_1"),
415 PINCTRL_PIN(4, "GPIO_DFX_5"),
416 PINCTRL_PIN(5, "GPIO_DFX_4"),
417 PINCTRL_PIN(6, "GPIO_DFX_8"),
418 PINCTRL_PIN(7, "GPIO_DFX_2"),
419 PINCTRL_PIN(8, "GPIO_DFX_6"),
421 PINCTRL_PIN(15, "GPIO_SUS0"),
422 PINCTRL_PIN(16, "SEC_GPIO_SUS10"),
423 PINCTRL_PIN(17, "GPIO_SUS3"),
424 PINCTRL_PIN(18, "GPIO_SUS7"),
425 PINCTRL_PIN(19, "GPIO_SUS1"),
426 PINCTRL_PIN(20, "GPIO_SUS5"),
427 PINCTRL_PIN(21, "SEC_GPIO_SUS11"),
428 PINCTRL_PIN(22, "GPIO_SUS4"),
429 PINCTRL_PIN(23, "SEC_GPIO_SUS8"),
430 PINCTRL_PIN(24, "GPIO_SUS2"),
431 PINCTRL_PIN(25, "GPIO_SUS6"),
432 PINCTRL_PIN(26, "CX_PREQ_B"),
433 PINCTRL_PIN(27, "SEC_GPIO_SUS9"),
435 PINCTRL_PIN(30, "TRST_B"),
436 PINCTRL_PIN(31, "TCK"),
437 PINCTRL_PIN(32, "PROCHOT_B"),
438 PINCTRL_PIN(33, "SVIDO_DATA"),
439 PINCTRL_PIN(34, "TMS"),
440 PINCTRL_PIN(35, "CX_PRDY_B_2"),
441 PINCTRL_PIN(36, "TDO_2"),
442 PINCTRL_PIN(37, "CX_PRDY_B"),
443 PINCTRL_PIN(38, "SVIDO_ALERT_B"),
444 PINCTRL_PIN(39, "TDO"),
445 PINCTRL_PIN(40, "SVIDO_CLK"),
446 PINCTRL_PIN(41, "TDI"),
448 PINCTRL_PIN(45, "GP_CAMERASB_05"),
449 PINCTRL_PIN(46, "GP_CAMERASB_02"),
450 PINCTRL_PIN(47, "GP_CAMERASB_08"),
451 PINCTRL_PIN(48, "GP_CAMERASB_00"),
452 PINCTRL_PIN(49, "GP_CAMERASB_06"),
453 PINCTRL_PIN(50, "GP_CAMERASB_10"),
454 PINCTRL_PIN(51, "GP_CAMERASB_03"),
455 PINCTRL_PIN(52, "GP_CAMERASB_09"),
456 PINCTRL_PIN(53, "GP_CAMERASB_01"),
457 PINCTRL_PIN(54, "GP_CAMERASB_07"),
458 PINCTRL_PIN(55, "GP_CAMERASB_11"),
459 PINCTRL_PIN(56, "GP_CAMERASB_04"),
461 PINCTRL_PIN(60, "PANEL0_BKLTEN"),
462 PINCTRL_PIN(61, "HV_DDI0_HPD"),
463 PINCTRL_PIN(62, "HV_DDI2_DDC_SDA"),
464 PINCTRL_PIN(63, "PANEL1_BKLTCTL"),
465 PINCTRL_PIN(64, "HV_DDI1_HPD"),
466 PINCTRL_PIN(65, "PANEL0_BKLTCTL"),
467 PINCTRL_PIN(66, "HV_DDI0_DDC_SDA"),
468 PINCTRL_PIN(67, "HV_DDI2_DDC_SCL"),
469 PINCTRL_PIN(68, "HV_DDI2_HPD"),
470 PINCTRL_PIN(69, "PANEL1_VDDEN"),
471 PINCTRL_PIN(70, "PANEL1_BKLTEN"),
472 PINCTRL_PIN(71, "HV_DDI0_DDC_SCL"),
473 PINCTRL_PIN(72, "PANEL0_VDDEN"),
476 static const struct chv_gpio_pinrange north_gpio_ranges[] = {
478 GPIO_PINRANGE(15, 27),
479 GPIO_PINRANGE(30, 41),
480 GPIO_PINRANGE(45, 56),
481 GPIO_PINRANGE(60, 72),
484 static const struct chv_community north_community = {
487 .npins = ARRAY_SIZE(north_pins),
488 .gpio_ranges = north_gpio_ranges,
489 .ngpio_ranges = ARRAY_SIZE(north_gpio_ranges),
490 .ngpios = ARRAY_SIZE(north_pins),
492 * North community can benerate GPIO interrupts only for the first
493 * 8 interrupts. The upper half (8-15) can only be used to trigger
499 static const struct pinctrl_pin_desc east_pins[] = {
500 PINCTRL_PIN(0, "PMU_SLP_S3_B"),
501 PINCTRL_PIN(1, "PMU_BATLOW_B"),
502 PINCTRL_PIN(2, "SUS_STAT_B"),
503 PINCTRL_PIN(3, "PMU_SLP_S0IX_B"),
504 PINCTRL_PIN(4, "PMU_AC_PRESENT"),
505 PINCTRL_PIN(5, "PMU_PLTRST_B"),
506 PINCTRL_PIN(6, "PMU_SUSCLK"),
507 PINCTRL_PIN(7, "PMU_SLP_LAN_B"),
508 PINCTRL_PIN(8, "PMU_PWRBTN_B"),
509 PINCTRL_PIN(9, "PMU_SLP_S4_B"),
510 PINCTRL_PIN(10, "PMU_WAKE_B"),
511 PINCTRL_PIN(11, "PMU_WAKE_LAN_B"),
513 PINCTRL_PIN(15, "MF_ISH_GPIO_3"),
514 PINCTRL_PIN(16, "MF_ISH_GPIO_7"),
515 PINCTRL_PIN(17, "MF_ISH_I2C1_SCL"),
516 PINCTRL_PIN(18, "MF_ISH_GPIO_1"),
517 PINCTRL_PIN(19, "MF_ISH_GPIO_5"),
518 PINCTRL_PIN(20, "MF_ISH_GPIO_9"),
519 PINCTRL_PIN(21, "MF_ISH_GPIO_0"),
520 PINCTRL_PIN(22, "MF_ISH_GPIO_4"),
521 PINCTRL_PIN(23, "MF_ISH_GPIO_8"),
522 PINCTRL_PIN(24, "MF_ISH_GPIO_2"),
523 PINCTRL_PIN(25, "MF_ISH_GPIO_6"),
524 PINCTRL_PIN(26, "MF_ISH_I2C1_SDA"),
527 static const struct chv_gpio_pinrange east_gpio_ranges[] = {
528 GPIO_PINRANGE(0, 11),
529 GPIO_PINRANGE(15, 26),
532 static const struct chv_community east_community = {
535 .npins = ARRAY_SIZE(east_pins),
536 .gpio_ranges = east_gpio_ranges,
537 .ngpio_ranges = ARRAY_SIZE(east_gpio_ranges),
538 .ngpios = ARRAY_SIZE(east_pins),
542 static const struct pinctrl_pin_desc southeast_pins[] = {
543 PINCTRL_PIN(0, "MF_PLT_CLK0"),
544 PINCTRL_PIN(1, "PWM1"),
545 PINCTRL_PIN(2, "MF_PLT_CLK1"),
546 PINCTRL_PIN(3, "MF_PLT_CLK4"),
547 PINCTRL_PIN(4, "MF_PLT_CLK3"),
548 PINCTRL_PIN(5, "PWM0"),
549 PINCTRL_PIN(6, "MF_PLT_CLK5"),
550 PINCTRL_PIN(7, "MF_PLT_CLK2"),
552 PINCTRL_PIN(15, "SDMMC2_D3_CD_B"),
553 PINCTRL_PIN(16, "SDMMC1_CLK"),
554 PINCTRL_PIN(17, "SDMMC1_D0"),
555 PINCTRL_PIN(18, "SDMMC2_D1"),
556 PINCTRL_PIN(19, "SDMMC2_CLK"),
557 PINCTRL_PIN(20, "SDMMC1_D2"),
558 PINCTRL_PIN(21, "SDMMC2_D2"),
559 PINCTRL_PIN(22, "SDMMC2_CMD"),
560 PINCTRL_PIN(23, "SDMMC1_CMD"),
561 PINCTRL_PIN(24, "SDMMC1_D1"),
562 PINCTRL_PIN(25, "SDMMC2_D0"),
563 PINCTRL_PIN(26, "SDMMC1_D3_CD_B"),
565 PINCTRL_PIN(30, "SDMMC3_D1"),
566 PINCTRL_PIN(31, "SDMMC3_CLK"),
567 PINCTRL_PIN(32, "SDMMC3_D3"),
568 PINCTRL_PIN(33, "SDMMC3_D2"),
569 PINCTRL_PIN(34, "SDMMC3_CMD"),
570 PINCTRL_PIN(35, "SDMMC3_D0"),
572 PINCTRL_PIN(45, "MF_LPC_AD2"),
573 PINCTRL_PIN(46, "LPC_CLKRUNB"),
574 PINCTRL_PIN(47, "MF_LPC_AD0"),
575 PINCTRL_PIN(48, "LPC_FRAMEB"),
576 PINCTRL_PIN(49, "MF_LPC_CLKOUT1"),
577 PINCTRL_PIN(50, "MF_LPC_AD3"),
578 PINCTRL_PIN(51, "MF_LPC_CLKOUT0"),
579 PINCTRL_PIN(52, "MF_LPC_AD1"),
581 PINCTRL_PIN(60, "SPI1_MISO"),
582 PINCTRL_PIN(61, "SPI1_CSO_B"),
583 PINCTRL_PIN(62, "SPI1_CLK"),
584 PINCTRL_PIN(63, "MMC1_D6"),
585 PINCTRL_PIN(64, "SPI1_MOSI"),
586 PINCTRL_PIN(65, "MMC1_D5"),
587 PINCTRL_PIN(66, "SPI1_CS1_B"),
588 PINCTRL_PIN(67, "MMC1_D4_SD_WE"),
589 PINCTRL_PIN(68, "MMC1_D7"),
590 PINCTRL_PIN(69, "MMC1_RCLK"),
592 PINCTRL_PIN(75, "USB_OC1_B"),
593 PINCTRL_PIN(76, "PMU_RESETBUTTON_B"),
594 PINCTRL_PIN(77, "GPIO_ALERT"),
595 PINCTRL_PIN(78, "SDMMC3_PWR_EN_B"),
596 PINCTRL_PIN(79, "ILB_SERIRQ"),
597 PINCTRL_PIN(80, "USB_OC0_B"),
598 PINCTRL_PIN(81, "SDMMC3_CD_B"),
599 PINCTRL_PIN(82, "SPKR"),
600 PINCTRL_PIN(83, "SUSPWRDNACK"),
601 PINCTRL_PIN(84, "SPARE_PIN"),
602 PINCTRL_PIN(85, "SDMMC3_1P8_EN"),
605 static const unsigned southeast_pwm0_pins[] = { 5 };
606 static const unsigned southeast_pwm1_pins[] = { 1 };
607 static const unsigned southeast_sdmmc1_pins[] = {
608 16, 17, 20, 23, 24, 26, 63, 65, 67, 68, 69,
610 static const unsigned southeast_sdmmc2_pins[] = { 15, 18, 19, 21, 22, 25 };
611 static const unsigned southeast_sdmmc3_pins[] = {
612 30, 31, 32, 33, 34, 35, 78, 81, 85,
614 static const unsigned southeast_spi1_pins[] = { 60, 61, 62, 64, 66 };
615 static const unsigned southeast_spi2_pins[] = { 2, 3, 4, 6, 7 };
617 static const struct chv_pingroup southeast_groups[] = {
618 PIN_GROUP("pwm0_grp", southeast_pwm0_pins, 1, false),
619 PIN_GROUP("pwm1_grp", southeast_pwm1_pins, 1, false),
620 PIN_GROUP("sdmmc1_grp", southeast_sdmmc1_pins, 1, false),
621 PIN_GROUP("sdmmc2_grp", southeast_sdmmc2_pins, 1, false),
622 PIN_GROUP("sdmmc3_grp", southeast_sdmmc3_pins, 1, false),
623 PIN_GROUP("spi1_grp", southeast_spi1_pins, 1, false),
624 PIN_GROUP("spi2_grp", southeast_spi2_pins, 4, false),
627 static const char * const southeast_pwm0_groups[] = { "pwm0_grp" };
628 static const char * const southeast_pwm1_groups[] = { "pwm1_grp" };
629 static const char * const southeast_sdmmc1_groups[] = { "sdmmc1_grp" };
630 static const char * const southeast_sdmmc2_groups[] = { "sdmmc2_grp" };
631 static const char * const southeast_sdmmc3_groups[] = { "sdmmc3_grp" };
632 static const char * const southeast_spi1_groups[] = { "spi1_grp" };
633 static const char * const southeast_spi2_groups[] = { "spi2_grp" };
635 static const struct chv_function southeast_functions[] = {
636 FUNCTION("pwm0", southeast_pwm0_groups),
637 FUNCTION("pwm1", southeast_pwm1_groups),
638 FUNCTION("sdmmc1", southeast_sdmmc1_groups),
639 FUNCTION("sdmmc2", southeast_sdmmc2_groups),
640 FUNCTION("sdmmc3", southeast_sdmmc3_groups),
641 FUNCTION("spi1", southeast_spi1_groups),
642 FUNCTION("spi2", southeast_spi2_groups),
645 static const struct chv_gpio_pinrange southeast_gpio_ranges[] = {
647 GPIO_PINRANGE(15, 26),
648 GPIO_PINRANGE(30, 35),
649 GPIO_PINRANGE(45, 52),
650 GPIO_PINRANGE(60, 69),
651 GPIO_PINRANGE(75, 85),
654 static const struct chv_community southeast_community = {
656 .pins = southeast_pins,
657 .npins = ARRAY_SIZE(southeast_pins),
658 .groups = southeast_groups,
659 .ngroups = ARRAY_SIZE(southeast_groups),
660 .functions = southeast_functions,
661 .nfunctions = ARRAY_SIZE(southeast_functions),
662 .gpio_ranges = southeast_gpio_ranges,
663 .ngpio_ranges = ARRAY_SIZE(southeast_gpio_ranges),
664 .ngpios = ARRAY_SIZE(southeast_pins),
668 static const struct chv_community *chv_communities[] = {
669 &southwest_community,
672 &southeast_community,
676 * Lock to serialize register accesses
678 * Due to a silicon issue, a shared lock must be used to prevent
679 * concurrent accesses across the 4 GPIO controllers.
681 * See Intel Atom Z8000 Processor Series Specification Update (Rev. 005),
682 * errata #CHT34, for further information.
684 static DEFINE_RAW_SPINLOCK(chv_lock);
686 static void __iomem *chv_padreg(struct chv_pinctrl *pctrl, unsigned offset,
689 unsigned family_no = offset / MAX_FAMILY_PAD_GPIO_NO;
690 unsigned pad_no = offset % MAX_FAMILY_PAD_GPIO_NO;
692 offset = FAMILY_PAD_REGS_OFF + FAMILY_PAD_REGS_SIZE * family_no +
693 GPIO_REGS_SIZE * pad_no;
695 return pctrl->regs + offset + reg;
698 static void chv_writel(u32 value, void __iomem *reg)
701 /* simple readback to confirm the bus transferring done */
705 /* When Pad Cfg is locked, driver can only change GPIOTXState or GPIORXState */
706 static bool chv_pad_locked(struct chv_pinctrl *pctrl, unsigned offset)
710 reg = chv_padreg(pctrl, offset, CHV_PADCTRL1);
711 return readl(reg) & CHV_PADCTRL1_CFGLOCK;
714 static int chv_get_groups_count(struct pinctrl_dev *pctldev)
716 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
718 return pctrl->community->ngroups;
721 static const char *chv_get_group_name(struct pinctrl_dev *pctldev,
724 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
726 return pctrl->community->groups[group].name;
729 static int chv_get_group_pins(struct pinctrl_dev *pctldev, unsigned group,
730 const unsigned **pins, unsigned *npins)
732 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
734 *pins = pctrl->community->groups[group].pins;
735 *npins = pctrl->community->groups[group].npins;
739 static void chv_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
742 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
747 raw_spin_lock_irqsave(&chv_lock, flags);
749 ctrl0 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0));
750 ctrl1 = readl(chv_padreg(pctrl, offset, CHV_PADCTRL1));
751 locked = chv_pad_locked(pctrl, offset);
753 raw_spin_unlock_irqrestore(&chv_lock, flags);
755 if (ctrl0 & CHV_PADCTRL0_GPIOEN) {
756 seq_puts(s, "GPIO ");
760 mode = ctrl0 & CHV_PADCTRL0_PMODE_MASK;
761 mode >>= CHV_PADCTRL0_PMODE_SHIFT;
763 seq_printf(s, "mode %d ", mode);
766 seq_printf(s, "0x%08x 0x%08x", ctrl0, ctrl1);
769 seq_puts(s, " [LOCKED]");
772 static const struct pinctrl_ops chv_pinctrl_ops = {
773 .get_groups_count = chv_get_groups_count,
774 .get_group_name = chv_get_group_name,
775 .get_group_pins = chv_get_group_pins,
776 .pin_dbg_show = chv_pin_dbg_show,
779 static int chv_get_functions_count(struct pinctrl_dev *pctldev)
781 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
783 return pctrl->community->nfunctions;
786 static const char *chv_get_function_name(struct pinctrl_dev *pctldev,
789 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
791 return pctrl->community->functions[function].name;
794 static int chv_get_function_groups(struct pinctrl_dev *pctldev,
796 const char * const **groups,
797 unsigned * const ngroups)
799 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
801 *groups = pctrl->community->functions[function].groups;
802 *ngroups = pctrl->community->functions[function].ngroups;
806 static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned function,
809 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
810 const struct chv_pingroup *grp;
814 grp = &pctrl->community->groups[group];
816 raw_spin_lock_irqsave(&chv_lock, flags);
818 /* Check first that the pad is not locked */
819 for (i = 0; i < grp->npins; i++) {
820 if (chv_pad_locked(pctrl, grp->pins[i])) {
821 dev_warn(pctrl->dev, "unable to set mode for locked pin %u\n",
823 raw_spin_unlock_irqrestore(&chv_lock, flags);
828 for (i = 0; i < grp->npins; i++) {
829 const struct chv_alternate_function *altfunc = &grp->altfunc;
830 int pin = grp->pins[i];
834 /* Check if there is pin-specific config */
835 if (grp->overrides) {
838 for (j = 0; j < grp->noverrides; j++) {
839 if (grp->overrides[j].pin == pin) {
840 altfunc = &grp->overrides[j];
846 reg = chv_padreg(pctrl, pin, CHV_PADCTRL0);
848 /* Disable GPIO mode */
849 value &= ~CHV_PADCTRL0_GPIOEN;
850 /* Set to desired mode */
851 value &= ~CHV_PADCTRL0_PMODE_MASK;
852 value |= altfunc->mode << CHV_PADCTRL0_PMODE_SHIFT;
853 chv_writel(value, reg);
855 /* Update for invert_oe */
856 reg = chv_padreg(pctrl, pin, CHV_PADCTRL1);
857 value = readl(reg) & ~CHV_PADCTRL1_INVRXTX_MASK;
858 if (altfunc->invert_oe)
859 value |= CHV_PADCTRL1_INVRXTX_TXENABLE;
860 chv_writel(value, reg);
862 dev_dbg(pctrl->dev, "configured pin %u mode %u OE %sinverted\n",
863 pin, altfunc->mode, altfunc->invert_oe ? "" : "not ");
866 raw_spin_unlock_irqrestore(&chv_lock, flags);
871 static int chv_gpio_request_enable(struct pinctrl_dev *pctldev,
872 struct pinctrl_gpio_range *range,
875 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
880 raw_spin_lock_irqsave(&chv_lock, flags);
882 if (chv_pad_locked(pctrl, offset)) {
883 value = readl(chv_padreg(pctrl, offset, CHV_PADCTRL0));
884 if (!(value & CHV_PADCTRL0_GPIOEN)) {
885 /* Locked so cannot enable */
886 raw_spin_unlock_irqrestore(&chv_lock, flags);
892 /* Reset the interrupt mapping */
893 for (i = 0; i < ARRAY_SIZE(pctrl->intr_lines); i++) {
894 if (pctrl->intr_lines[i] == offset) {
895 pctrl->intr_lines[i] = 0;
900 /* Disable interrupt generation */
901 reg = chv_padreg(pctrl, offset, CHV_PADCTRL1);
903 value &= ~CHV_PADCTRL1_INTWAKECFG_MASK;
904 value &= ~CHV_PADCTRL1_INVRXTX_MASK;
905 chv_writel(value, reg);
907 reg = chv_padreg(pctrl, offset, CHV_PADCTRL0);
911 * If the pin is in HiZ mode (both TX and RX buffers are
912 * disabled) we turn it to be input now.
914 if ((value & CHV_PADCTRL0_GPIOCFG_MASK) ==
915 (CHV_PADCTRL0_GPIOCFG_HIZ << CHV_PADCTRL0_GPIOCFG_SHIFT)) {
916 value &= ~CHV_PADCTRL0_GPIOCFG_MASK;
917 value |= CHV_PADCTRL0_GPIOCFG_GPI <<
918 CHV_PADCTRL0_GPIOCFG_SHIFT;
921 /* Switch to a GPIO mode */
922 value |= CHV_PADCTRL0_GPIOEN;
923 chv_writel(value, reg);
926 raw_spin_unlock_irqrestore(&chv_lock, flags);
931 static void chv_gpio_disable_free(struct pinctrl_dev *pctldev,
932 struct pinctrl_gpio_range *range,
935 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
940 raw_spin_lock_irqsave(&chv_lock, flags);
942 reg = chv_padreg(pctrl, offset, CHV_PADCTRL0);
943 value = readl(reg) & ~CHV_PADCTRL0_GPIOEN;
944 chv_writel(value, reg);
946 raw_spin_unlock_irqrestore(&chv_lock, flags);
949 static int chv_gpio_set_direction(struct pinctrl_dev *pctldev,
950 struct pinctrl_gpio_range *range,
951 unsigned offset, bool input)
953 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
954 void __iomem *reg = chv_padreg(pctrl, offset, CHV_PADCTRL0);
958 raw_spin_lock_irqsave(&chv_lock, flags);
960 ctrl0 = readl(reg) & ~CHV_PADCTRL0_GPIOCFG_MASK;
962 ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPI << CHV_PADCTRL0_GPIOCFG_SHIFT;
964 ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPO << CHV_PADCTRL0_GPIOCFG_SHIFT;
965 chv_writel(ctrl0, reg);
967 raw_spin_unlock_irqrestore(&chv_lock, flags);
972 static const struct pinmux_ops chv_pinmux_ops = {
973 .get_functions_count = chv_get_functions_count,
974 .get_function_name = chv_get_function_name,
975 .get_function_groups = chv_get_function_groups,
976 .set_mux = chv_pinmux_set_mux,
977 .gpio_request_enable = chv_gpio_request_enable,
978 .gpio_disable_free = chv_gpio_disable_free,
979 .gpio_set_direction = chv_gpio_set_direction,
982 static int chv_config_get(struct pinctrl_dev *pctldev, unsigned pin,
983 unsigned long *config)
985 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
986 enum pin_config_param param = pinconf_to_config_param(*config);
992 raw_spin_lock_irqsave(&chv_lock, flags);
993 ctrl0 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
994 ctrl1 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL1));
995 raw_spin_unlock_irqrestore(&chv_lock, flags);
997 term = (ctrl0 & CHV_PADCTRL0_TERM_MASK) >> CHV_PADCTRL0_TERM_SHIFT;
1000 case PIN_CONFIG_BIAS_DISABLE:
1005 case PIN_CONFIG_BIAS_PULL_UP:
1006 if (!(ctrl0 & CHV_PADCTRL0_TERM_UP))
1010 case CHV_PADCTRL0_TERM_20K:
1013 case CHV_PADCTRL0_TERM_5K:
1016 case CHV_PADCTRL0_TERM_1K:
1023 case PIN_CONFIG_BIAS_PULL_DOWN:
1024 if (!term || (ctrl0 & CHV_PADCTRL0_TERM_UP))
1028 case CHV_PADCTRL0_TERM_20K:
1031 case CHV_PADCTRL0_TERM_5K:
1038 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
1039 if (!(ctrl1 & CHV_PADCTRL1_ODEN))
1043 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: {
1046 cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
1047 cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT;
1048 if (cfg != CHV_PADCTRL0_GPIOCFG_HIZ)
1058 *config = pinconf_to_config_packed(param, arg);
1062 static int chv_config_set_pull(struct chv_pinctrl *pctrl, unsigned pin,
1063 enum pin_config_param param, u32 arg)
1065 void __iomem *reg = chv_padreg(pctrl, pin, CHV_PADCTRL0);
1066 unsigned long flags;
1069 raw_spin_lock_irqsave(&chv_lock, flags);
1073 case PIN_CONFIG_BIAS_DISABLE:
1074 ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP);
1077 case PIN_CONFIG_BIAS_PULL_UP:
1078 ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP);
1082 /* For 1k there is only pull up */
1083 pull = CHV_PADCTRL0_TERM_1K << CHV_PADCTRL0_TERM_SHIFT;
1086 pull = CHV_PADCTRL0_TERM_5K << CHV_PADCTRL0_TERM_SHIFT;
1089 pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT;
1092 raw_spin_unlock_irqrestore(&chv_lock, flags);
1096 ctrl0 |= CHV_PADCTRL0_TERM_UP | pull;
1099 case PIN_CONFIG_BIAS_PULL_DOWN:
1100 ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP);
1104 pull = CHV_PADCTRL0_TERM_5K << CHV_PADCTRL0_TERM_SHIFT;
1107 pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT;
1110 raw_spin_unlock_irqrestore(&chv_lock, flags);
1118 raw_spin_unlock_irqrestore(&chv_lock, flags);
1122 chv_writel(ctrl0, reg);
1123 raw_spin_unlock_irqrestore(&chv_lock, flags);
1128 static int chv_config_set_oden(struct chv_pinctrl *pctrl, unsigned int pin,
1131 void __iomem *reg = chv_padreg(pctrl, pin, CHV_PADCTRL1);
1132 unsigned long flags;
1135 raw_spin_lock_irqsave(&chv_lock, flags);
1139 ctrl1 |= CHV_PADCTRL1_ODEN;
1141 ctrl1 &= ~CHV_PADCTRL1_ODEN;
1143 chv_writel(ctrl1, reg);
1144 raw_spin_unlock_irqrestore(&chv_lock, flags);
1149 static int chv_config_set(struct pinctrl_dev *pctldev, unsigned pin,
1150 unsigned long *configs, unsigned nconfigs)
1152 struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
1153 enum pin_config_param param;
1157 if (chv_pad_locked(pctrl, pin))
1160 for (i = 0; i < nconfigs; i++) {
1161 param = pinconf_to_config_param(configs[i]);
1162 arg = pinconf_to_config_argument(configs[i]);
1165 case PIN_CONFIG_BIAS_DISABLE:
1166 case PIN_CONFIG_BIAS_PULL_UP:
1167 case PIN_CONFIG_BIAS_PULL_DOWN:
1168 ret = chv_config_set_pull(pctrl, pin, param, arg);
1173 case PIN_CONFIG_DRIVE_PUSH_PULL:
1174 ret = chv_config_set_oden(pctrl, pin, false);
1179 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
1180 ret = chv_config_set_oden(pctrl, pin, true);
1189 dev_dbg(pctrl->dev, "pin %d set config %d arg %u\n", pin,
1196 static int chv_config_group_get(struct pinctrl_dev *pctldev,
1198 unsigned long *config)
1200 const unsigned int *pins;
1204 ret = chv_get_group_pins(pctldev, group, &pins, &npins);
1208 ret = chv_config_get(pctldev, pins[0], config);
1215 static int chv_config_group_set(struct pinctrl_dev *pctldev,
1216 unsigned int group, unsigned long *configs,
1217 unsigned int num_configs)
1219 const unsigned int *pins;
1223 ret = chv_get_group_pins(pctldev, group, &pins, &npins);
1227 for (i = 0; i < npins; i++) {
1228 ret = chv_config_set(pctldev, pins[i], configs, num_configs);
1236 static const struct pinconf_ops chv_pinconf_ops = {
1238 .pin_config_set = chv_config_set,
1239 .pin_config_get = chv_config_get,
1240 .pin_config_group_get = chv_config_group_get,
1241 .pin_config_group_set = chv_config_group_set,
1244 static struct pinctrl_desc chv_pinctrl_desc = {
1245 .pctlops = &chv_pinctrl_ops,
1246 .pmxops = &chv_pinmux_ops,
1247 .confops = &chv_pinconf_ops,
1248 .owner = THIS_MODULE,
1251 static unsigned chv_gpio_offset_to_pin(struct chv_pinctrl *pctrl,
1254 return pctrl->community->pins[offset].number;
1257 static int chv_gpio_get(struct gpio_chip *chip, unsigned offset)
1259 struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
1260 int pin = chv_gpio_offset_to_pin(pctrl, offset);
1261 unsigned long flags;
1264 raw_spin_lock_irqsave(&chv_lock, flags);
1265 ctrl0 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
1266 raw_spin_unlock_irqrestore(&chv_lock, flags);
1268 cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
1269 cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT;
1271 if (cfg == CHV_PADCTRL0_GPIOCFG_GPO)
1272 return !!(ctrl0 & CHV_PADCTRL0_GPIOTXSTATE);
1273 return !!(ctrl0 & CHV_PADCTRL0_GPIORXSTATE);
1276 static void chv_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1278 struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
1279 unsigned pin = chv_gpio_offset_to_pin(pctrl, offset);
1280 unsigned long flags;
1284 raw_spin_lock_irqsave(&chv_lock, flags);
1286 reg = chv_padreg(pctrl, pin, CHV_PADCTRL0);
1290 ctrl0 |= CHV_PADCTRL0_GPIOTXSTATE;
1292 ctrl0 &= ~CHV_PADCTRL0_GPIOTXSTATE;
1294 chv_writel(ctrl0, reg);
1296 raw_spin_unlock_irqrestore(&chv_lock, flags);
1299 static int chv_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
1301 struct chv_pinctrl *pctrl = gpiochip_get_data(chip);
1302 unsigned pin = chv_gpio_offset_to_pin(pctrl, offset);
1303 u32 ctrl0, direction;
1304 unsigned long flags;
1306 raw_spin_lock_irqsave(&chv_lock, flags);
1307 ctrl0 = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
1308 raw_spin_unlock_irqrestore(&chv_lock, flags);
1310 direction = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK;
1311 direction >>= CHV_PADCTRL0_GPIOCFG_SHIFT;
1313 return direction != CHV_PADCTRL0_GPIOCFG_GPO;
1316 static int chv_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
1318 return pinctrl_gpio_direction_input(chip->base + offset);
1321 static int chv_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
1324 chv_gpio_set(chip, offset, value);
1325 return pinctrl_gpio_direction_output(chip->base + offset);
1328 static const struct gpio_chip chv_gpio_chip = {
1329 .owner = THIS_MODULE,
1330 .request = gpiochip_generic_request,
1331 .free = gpiochip_generic_free,
1332 .get_direction = chv_gpio_get_direction,
1333 .direction_input = chv_gpio_direction_input,
1334 .direction_output = chv_gpio_direction_output,
1335 .get = chv_gpio_get,
1336 .set = chv_gpio_set,
1339 static void chv_gpio_irq_ack(struct irq_data *d)
1341 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1342 struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
1343 int pin = chv_gpio_offset_to_pin(pctrl, irqd_to_hwirq(d));
1346 raw_spin_lock(&chv_lock);
1348 intr_line = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
1349 intr_line &= CHV_PADCTRL0_INTSEL_MASK;
1350 intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT;
1351 chv_writel(BIT(intr_line), pctrl->regs + CHV_INTSTAT);
1353 raw_spin_unlock(&chv_lock);
1356 static void chv_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
1358 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1359 struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
1360 int pin = chv_gpio_offset_to_pin(pctrl, irqd_to_hwirq(d));
1361 u32 value, intr_line;
1362 unsigned long flags;
1364 raw_spin_lock_irqsave(&chv_lock, flags);
1366 intr_line = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
1367 intr_line &= CHV_PADCTRL0_INTSEL_MASK;
1368 intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT;
1370 value = readl(pctrl->regs + CHV_INTMASK);
1372 value &= ~BIT(intr_line);
1374 value |= BIT(intr_line);
1375 chv_writel(value, pctrl->regs + CHV_INTMASK);
1377 raw_spin_unlock_irqrestore(&chv_lock, flags);
1380 static void chv_gpio_irq_mask(struct irq_data *d)
1382 chv_gpio_irq_mask_unmask(d, true);
1385 static void chv_gpio_irq_unmask(struct irq_data *d)
1387 chv_gpio_irq_mask_unmask(d, false);
1390 static unsigned chv_gpio_irq_startup(struct irq_data *d)
1393 * Check if the interrupt has been requested with 0 as triggering
1394 * type. In that case it is assumed that the current values
1395 * programmed to the hardware are used (e.g BIOS configured
1398 * In that case ->irq_set_type() will never be called so we need to
1399 * read back the values from hardware now, set correct flow handler
1400 * and update mappings before the interrupt is being used.
1402 if (irqd_get_trigger_type(d) == IRQ_TYPE_NONE) {
1403 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1404 struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
1405 unsigned offset = irqd_to_hwirq(d);
1406 int pin = chv_gpio_offset_to_pin(pctrl, offset);
1407 irq_flow_handler_t handler;
1408 unsigned long flags;
1411 raw_spin_lock_irqsave(&chv_lock, flags);
1412 intsel = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
1413 intsel &= CHV_PADCTRL0_INTSEL_MASK;
1414 intsel >>= CHV_PADCTRL0_INTSEL_SHIFT;
1416 value = readl(chv_padreg(pctrl, pin, CHV_PADCTRL1));
1417 if (value & CHV_PADCTRL1_INTWAKECFG_LEVEL)
1418 handler = handle_level_irq;
1420 handler = handle_edge_irq;
1422 if (!pctrl->intr_lines[intsel]) {
1423 irq_set_handler_locked(d, handler);
1424 pctrl->intr_lines[intsel] = offset;
1426 raw_spin_unlock_irqrestore(&chv_lock, flags);
1429 chv_gpio_irq_unmask(d);
1433 static int chv_gpio_irq_type(struct irq_data *d, unsigned type)
1435 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1436 struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
1437 unsigned offset = irqd_to_hwirq(d);
1438 int pin = chv_gpio_offset_to_pin(pctrl, offset);
1439 unsigned long flags;
1442 raw_spin_lock_irqsave(&chv_lock, flags);
1445 * Pins which can be used as shared interrupt are configured in
1446 * BIOS. Driver trusts BIOS configurations and assigns different
1447 * handler according to the irq type.
1449 * Driver needs to save the mapping between each pin and
1450 * its interrupt line.
1451 * 1. If the pin cfg is locked in BIOS:
1452 * Trust BIOS has programmed IntWakeCfg bits correctly,
1453 * driver just needs to save the mapping.
1454 * 2. If the pin cfg is not locked in BIOS:
1455 * Driver programs the IntWakeCfg bits and save the mapping.
1457 if (!chv_pad_locked(pctrl, pin)) {
1458 void __iomem *reg = chv_padreg(pctrl, pin, CHV_PADCTRL1);
1461 value &= ~CHV_PADCTRL1_INTWAKECFG_MASK;
1462 value &= ~CHV_PADCTRL1_INVRXTX_MASK;
1464 if (type & IRQ_TYPE_EDGE_BOTH) {
1465 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
1466 value |= CHV_PADCTRL1_INTWAKECFG_BOTH;
1467 else if (type & IRQ_TYPE_EDGE_RISING)
1468 value |= CHV_PADCTRL1_INTWAKECFG_RISING;
1469 else if (type & IRQ_TYPE_EDGE_FALLING)
1470 value |= CHV_PADCTRL1_INTWAKECFG_FALLING;
1471 } else if (type & IRQ_TYPE_LEVEL_MASK) {
1472 value |= CHV_PADCTRL1_INTWAKECFG_LEVEL;
1473 if (type & IRQ_TYPE_LEVEL_LOW)
1474 value |= CHV_PADCTRL1_INVRXTX_RXDATA;
1477 chv_writel(value, reg);
1480 value = readl(chv_padreg(pctrl, pin, CHV_PADCTRL0));
1481 value &= CHV_PADCTRL0_INTSEL_MASK;
1482 value >>= CHV_PADCTRL0_INTSEL_SHIFT;
1484 pctrl->intr_lines[value] = offset;
1486 if (type & IRQ_TYPE_EDGE_BOTH)
1487 irq_set_handler_locked(d, handle_edge_irq);
1488 else if (type & IRQ_TYPE_LEVEL_MASK)
1489 irq_set_handler_locked(d, handle_level_irq);
1491 raw_spin_unlock_irqrestore(&chv_lock, flags);
1496 static struct irq_chip chv_gpio_irqchip = {
1498 .irq_startup = chv_gpio_irq_startup,
1499 .irq_ack = chv_gpio_irq_ack,
1500 .irq_mask = chv_gpio_irq_mask,
1501 .irq_unmask = chv_gpio_irq_unmask,
1502 .irq_set_type = chv_gpio_irq_type,
1503 .flags = IRQCHIP_SKIP_SET_WAKE,
1506 static void chv_gpio_irq_handler(struct irq_desc *desc)
1508 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
1509 struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
1510 struct irq_chip *chip = irq_desc_get_chip(desc);
1511 unsigned long pending;
1514 chained_irq_enter(chip, desc);
1516 pending = readl(pctrl->regs + CHV_INTSTAT);
1517 for_each_set_bit(intr_line, &pending, pctrl->community->nirqs) {
1518 unsigned irq, offset;
1520 offset = pctrl->intr_lines[intr_line];
1521 irq = irq_find_mapping(gc->irqdomain, offset);
1522 generic_handle_irq(irq);
1525 chained_irq_exit(chip, desc);
1529 * Certain machines seem to hardcode Linux IRQ numbers in their ACPI
1530 * tables. Since we leave GPIOs that are not capable of generating
1531 * interrupts out of the irqdomain the numbering will be different and
1532 * cause devices using the hardcoded IRQ numbers fail. In order not to
1533 * break such machines we will only mask pins from irqdomain if the machine
1534 * is not listed below.
1536 static const struct dmi_system_id chv_no_valid_mask[] = {
1538 /* See https://bugzilla.kernel.org/show_bug.cgi?id=194945 */
1539 .ident = "Acer Chromebook (CYAN)",
1541 DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
1542 DMI_MATCH(DMI_PRODUCT_NAME, "Edgar"),
1543 DMI_MATCH(DMI_BIOS_DATE, "05/21/2016"),
1548 static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq)
1550 const struct chv_gpio_pinrange *range;
1551 struct gpio_chip *chip = &pctrl->chip;
1552 bool need_valid_mask = !dmi_check_system(chv_no_valid_mask);
1555 *chip = chv_gpio_chip;
1557 chip->ngpio = pctrl->community->ngpios;
1558 chip->label = dev_name(pctrl->dev);
1559 chip->parent = pctrl->dev;
1561 chip->irq_need_valid_mask = need_valid_mask;
1563 ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl);
1565 dev_err(pctrl->dev, "Failed to register gpiochip\n");
1569 for (i = 0, offset = 0; i < pctrl->community->ngpio_ranges; i++) {
1570 range = &pctrl->community->gpio_ranges[i];
1571 ret = gpiochip_add_pin_range(chip, dev_name(pctrl->dev), offset,
1572 range->base, range->npins);
1574 dev_err(pctrl->dev, "failed to add GPIO pin range\n");
1578 offset += range->npins;
1581 /* Do not add GPIOs that can only generate GPEs to the IRQ domain */
1582 for (i = 0; i < pctrl->community->npins; i++) {
1583 const struct pinctrl_pin_desc *desc;
1586 desc = &pctrl->community->pins[i];
1588 intsel = readl(chv_padreg(pctrl, desc->number, CHV_PADCTRL0));
1589 intsel &= CHV_PADCTRL0_INTSEL_MASK;
1590 intsel >>= CHV_PADCTRL0_INTSEL_SHIFT;
1592 if (need_valid_mask && intsel >= pctrl->community->nirqs)
1593 clear_bit(i, chip->irq_valid_mask);
1596 /* Clear all interrupts */
1597 chv_writel(0xffff, pctrl->regs + CHV_INTSTAT);
1599 ret = gpiochip_irqchip_add(chip, &chv_gpio_irqchip, 0,
1600 handle_bad_irq, IRQ_TYPE_NONE);
1602 dev_err(pctrl->dev, "failed to add IRQ chip\n");
1606 gpiochip_set_chained_irqchip(chip, &chv_gpio_irqchip, irq,
1607 chv_gpio_irq_handler);
1611 static int chv_pinctrl_probe(struct platform_device *pdev)
1613 struct chv_pinctrl *pctrl;
1614 struct acpi_device *adev;
1615 struct resource *res;
1618 adev = ACPI_COMPANION(&pdev->dev);
1622 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
1626 for (i = 0; i < ARRAY_SIZE(chv_communities); i++)
1627 if (!strcmp(adev->pnp.unique_id, chv_communities[i]->uid)) {
1628 pctrl->community = chv_communities[i];
1631 if (i == ARRAY_SIZE(chv_communities))
1634 pctrl->dev = &pdev->dev;
1636 #ifdef CONFIG_PM_SLEEP
1637 pctrl->saved_pin_context = devm_kcalloc(pctrl->dev,
1638 pctrl->community->npins, sizeof(*pctrl->saved_pin_context),
1640 if (!pctrl->saved_pin_context)
1644 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1645 pctrl->regs = devm_ioremap_resource(&pdev->dev, res);
1646 if (IS_ERR(pctrl->regs))
1647 return PTR_ERR(pctrl->regs);
1649 irq = platform_get_irq(pdev, 0);
1651 dev_err(&pdev->dev, "failed to get interrupt number\n");
1655 pctrl->pctldesc = chv_pinctrl_desc;
1656 pctrl->pctldesc.name = dev_name(&pdev->dev);
1657 pctrl->pctldesc.pins = pctrl->community->pins;
1658 pctrl->pctldesc.npins = pctrl->community->npins;
1660 pctrl->pctldev = devm_pinctrl_register(&pdev->dev, &pctrl->pctldesc,
1662 if (IS_ERR(pctrl->pctldev)) {
1663 dev_err(&pdev->dev, "failed to register pinctrl driver\n");
1664 return PTR_ERR(pctrl->pctldev);
1667 ret = chv_gpio_probe(pctrl, irq);
1671 platform_set_drvdata(pdev, pctrl);
1676 #ifdef CONFIG_PM_SLEEP
1677 static int chv_pinctrl_suspend_noirq(struct device *dev)
1679 struct platform_device *pdev = to_platform_device(dev);
1680 struct chv_pinctrl *pctrl = platform_get_drvdata(pdev);
1681 unsigned long flags;
1684 raw_spin_lock_irqsave(&chv_lock, flags);
1686 pctrl->saved_intmask = readl(pctrl->regs + CHV_INTMASK);
1688 for (i = 0; i < pctrl->community->npins; i++) {
1689 const struct pinctrl_pin_desc *desc;
1690 struct chv_pin_context *ctx;
1693 desc = &pctrl->community->pins[i];
1694 if (chv_pad_locked(pctrl, desc->number))
1697 ctx = &pctrl->saved_pin_context[i];
1699 reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL0);
1700 ctx->padctrl0 = readl(reg) & ~CHV_PADCTRL0_GPIORXSTATE;
1702 reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL1);
1703 ctx->padctrl1 = readl(reg);
1706 raw_spin_unlock_irqrestore(&chv_lock, flags);
1711 static int chv_pinctrl_resume_noirq(struct device *dev)
1713 struct platform_device *pdev = to_platform_device(dev);
1714 struct chv_pinctrl *pctrl = platform_get_drvdata(pdev);
1715 unsigned long flags;
1718 raw_spin_lock_irqsave(&chv_lock, flags);
1721 * Mask all interrupts before restoring per-pin configuration
1722 * registers because we don't know in which state BIOS left them
1723 * upon exiting suspend.
1725 chv_writel(0, pctrl->regs + CHV_INTMASK);
1727 for (i = 0; i < pctrl->community->npins; i++) {
1728 const struct pinctrl_pin_desc *desc;
1729 const struct chv_pin_context *ctx;
1733 desc = &pctrl->community->pins[i];
1734 if (chv_pad_locked(pctrl, desc->number))
1737 ctx = &pctrl->saved_pin_context[i];
1739 /* Only restore if our saved state differs from the current */
1740 reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL0);
1741 val = readl(reg) & ~CHV_PADCTRL0_GPIORXSTATE;
1742 if (ctx->padctrl0 != val) {
1743 chv_writel(ctx->padctrl0, reg);
1744 dev_dbg(pctrl->dev, "restored pin %2u ctrl0 0x%08x\n",
1745 desc->number, readl(reg));
1748 reg = chv_padreg(pctrl, desc->number, CHV_PADCTRL1);
1750 if (ctx->padctrl1 != val) {
1751 chv_writel(ctx->padctrl1, reg);
1752 dev_dbg(pctrl->dev, "restored pin %2u ctrl1 0x%08x\n",
1753 desc->number, readl(reg));
1758 * Now that all pins are restored to known state, we can restore
1759 * the interrupt mask register as well.
1761 chv_writel(0xffff, pctrl->regs + CHV_INTSTAT);
1762 chv_writel(pctrl->saved_intmask, pctrl->regs + CHV_INTMASK);
1764 raw_spin_unlock_irqrestore(&chv_lock, flags);
1770 static const struct dev_pm_ops chv_pinctrl_pm_ops = {
1771 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(chv_pinctrl_suspend_noirq,
1772 chv_pinctrl_resume_noirq)
1775 static const struct acpi_device_id chv_pinctrl_acpi_match[] = {
1779 MODULE_DEVICE_TABLE(acpi, chv_pinctrl_acpi_match);
1781 static struct platform_driver chv_pinctrl_driver = {
1782 .probe = chv_pinctrl_probe,
1784 .name = "cherryview-pinctrl",
1785 .pm = &chv_pinctrl_pm_ops,
1786 .acpi_match_table = chv_pinctrl_acpi_match,
1790 static int __init chv_pinctrl_init(void)
1792 return platform_driver_register(&chv_pinctrl_driver);
1794 subsys_initcall(chv_pinctrl_init);
1796 static void __exit chv_pinctrl_exit(void)
1798 platform_driver_unregister(&chv_pinctrl_driver);
1800 module_exit(chv_pinctrl_exit);
1802 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
1803 MODULE_DESCRIPTION("Intel Cherryview/Braswell pinctrl driver");
1804 MODULE_LICENSE("GPL v2");