drivers/pinctrl/intel/pinctrl-intel.c

   1 /*
   2  * Intel pinctrl/GPIO core driver.
   3  *
   4  * Copyright (C) 2015, Intel Corporation
   5  * Authors: Mathias Nyman <mathias.nyman@linux.intel.com>
   6  *          Mika Westerberg <mika.westerberg@linux.intel.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/gpio/driver.h>
  16 #include <linux/log2.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/pinctrl/pinctrl.h>
  19 #include <linux/pinctrl/pinmux.h>
  20 #include <linux/pinctrl/pinconf.h>
  21 #include <linux/pinctrl/pinconf-generic.h>
  22
  23 #include "../core.h"
  24 #include "pinctrl-intel.h"
  25
  26 /* Offset from regs */
  27 #define REVID                           0x000
  28 #define REVID_SHIFT                     16
  29 #define REVID_MASK                      GENMASK(31, 16)
  30
  31 #define PADBAR                          0x00c
  32 #define GPI_IS                          0x100
  33 #define GPI_GPE_STS                     0x140
  34 #define GPI_GPE_EN                      0x160
  35
  36 #define PADOWN_BITS                     4
  37 #define PADOWN_SHIFT(p)                 ((p) % 8 * PADOWN_BITS)
  38 #define PADOWN_MASK(p)                  (0xf << PADOWN_SHIFT(p))
  39 #define PADOWN_GPP(p)                   ((p) / 8)
  40
  41 /* Offset from pad_regs */
  42 #define PADCFG0                         0x000
  43 #define PADCFG0_RXEVCFG_SHIFT           25
  44 #define PADCFG0_RXEVCFG_MASK            (3 << PADCFG0_RXEVCFG_SHIFT)
  45 #define PADCFG0_RXEVCFG_LEVEL           0
  46 #define PADCFG0_RXEVCFG_EDGE            1
  47 #define PADCFG0_RXEVCFG_DISABLED        2
  48 #define PADCFG0_RXEVCFG_EDGE_BOTH       3
  49 #define PADCFG0_PREGFRXSEL              BIT(24)
  50 #define PADCFG0_RXINV                   BIT(23)
  51 #define PADCFG0_GPIROUTIOXAPIC          BIT(20)
  52 #define PADCFG0_GPIROUTSCI              BIT(19)
  53 #define PADCFG0_GPIROUTSMI              BIT(18)
  54 #define PADCFG0_GPIROUTNMI              BIT(17)
  55 #define PADCFG0_PMODE_SHIFT             10
  56 #define PADCFG0_PMODE_MASK              (0xf << PADCFG0_PMODE_SHIFT)
  57 #define PADCFG0_GPIORXDIS               BIT(9)
  58 #define PADCFG0_GPIOTXDIS               BIT(8)
  59 #define PADCFG0_GPIORXSTATE             BIT(1)
  60 #define PADCFG0_GPIOTXSTATE             BIT(0)
  61
  62 #define PADCFG1                         0x004
  63 #define PADCFG1_TERM_UP                 BIT(13)
  64 #define PADCFG1_TERM_SHIFT              10
  65 #define PADCFG1_TERM_MASK               (7 << PADCFG1_TERM_SHIFT)
  66 #define PADCFG1_TERM_20K                4
  67 #define PADCFG1_TERM_2K                 3
  68 #define PADCFG1_TERM_5K                 2
  69 #define PADCFG1_TERM_1K                 1
  70
  71 #define PADCFG2                         0x008
  72 #define PADCFG2_DEBEN                   BIT(0)
  73 #define PADCFG2_DEBOUNCE_SHIFT          1
  74 #define PADCFG2_DEBOUNCE_MASK           GENMASK(4, 1)
  75
  76 #define DEBOUNCE_PERIOD                 31250 /* ns */
  77
  78 struct intel_pad_context {
  79         u32 padcfg0;
  80         u32 padcfg1;
  81         u32 padcfg2;
  82 };
  83
  84 struct intel_community_context {
  85         u32 *intmask;
  86 };
  87
  88 struct intel_pinctrl_context {
  89         struct intel_pad_context *pads;
  90         struct intel_community_context *communities;
  91 };
  92
  93 /**
  94  * struct intel_pinctrl - Intel pinctrl private structure
  95  * @dev: Pointer to the device structure
  96  * @lock: Lock to serialize register access
  97  * @pctldesc: Pin controller description
  98  * @pctldev: Pointer to the pin controller device
  99  * @chip: GPIO chip in this pin controller
 100  * @soc: SoC/PCH specific pin configuration data
 101  * @communities: All communities in this pin controller
 102  * @ncommunities: Number of communities in this pin controller
 103  * @context: Configuration saved over system sleep
 104  * @irq: pinctrl/GPIO chip irq number
 105  */
 106 struct intel_pinctrl {
 107         struct device *dev;
 108         raw_spinlock_t lock;
 109         struct pinctrl_desc pctldesc;
 110         struct pinctrl_dev *pctldev;
 111         struct gpio_chip chip;
 112         const struct intel_pinctrl_soc_data *soc;
 113         struct intel_community *communities;
 114         size_t ncommunities;
 115         struct intel_pinctrl_context context;
 116         int irq;
 117 };
 118
 119 #define pin_to_padno(c, p)      ((p) - (c)->pin_base)
 120
 121 static struct intel_community *intel_get_community(struct intel_pinctrl *pctrl,
 122                                                    unsigned pin)
 123 {
 124         struct intel_community *community;
 125         int i;
 126
 127         for (i = 0; i < pctrl->ncommunities; i++) {
 128                 community = &pctrl->communities[i];
 129                 if (pin >= community->pin_base &&
 130                     pin < community->pin_base + community->npins)
 131                         return community;
 132         }
 133
 134         dev_warn(pctrl->dev, "failed to find community for pin %u\n", pin);
 135         return NULL;
 136 }
 137
 138 static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl, unsigned pin,
 139                                       unsigned reg)
 140 {
 141         const struct intel_community *community;
 142         unsigned padno;
 143         size_t nregs;
 144
 145         community = intel_get_community(pctrl, pin);
 146         if (!community)
 147                 return NULL;
 148
 149         padno = pin_to_padno(community, pin);
 150         nregs = (community->features & PINCTRL_FEATURE_DEBOUNCE) ? 4 : 2;
 151
 152         if (reg == PADCFG2 && !(community->features & PINCTRL_FEATURE_DEBOUNCE))
 153                 return NULL;
 154
 155         return community->pad_regs + reg + padno * nregs * 4;
 156 }
 157
 158 static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned pin)
 159 {
 160         const struct intel_community *community;
 161         unsigned padno, gpp, offset, group;
 162         void __iomem *padown;
 163
 164         community = intel_get_community(pctrl, pin);
 165         if (!community)
 166                 return false;
 167         if (!community->padown_offset)
 168                 return true;
 169
 170         padno = pin_to_padno(community, pin);
 171         group = padno / community->gpp_size;
 172         gpp = PADOWN_GPP(padno % community->gpp_size);
 173         offset = community->padown_offset + 0x10 * group + gpp * 4;
 174         padown = community->regs + offset;
 175
 176         return !(readl(padown) & PADOWN_MASK(padno));
 177 }
 178
 179 static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned pin)
 180 {
 181         const struct intel_community *community;
 182         unsigned padno, gpp, offset;
 183         void __iomem *hostown;
 184
 185         community = intel_get_community(pctrl, pin);
 186         if (!community)
 187                 return true;
 188         if (!community->hostown_offset)
 189                 return false;
 190
 191         padno = pin_to_padno(community, pin);
 192         gpp = padno / community->gpp_size;
 193         offset = community->hostown_offset + gpp * 4;
 194         hostown = community->regs + offset;
 195
 196         return !(readl(hostown) & BIT(padno % community->gpp_size));
 197 }
 198
 199 static bool intel_pad_locked(struct intel_pinctrl *pctrl, unsigned pin)
 200 {
 201         struct intel_community *community;
 202         unsigned padno, gpp, offset;
 203         u32 value;
 204
 205         community = intel_get_community(pctrl, pin);
 206         if (!community)
 207                 return true;
 208         if (!community->padcfglock_offset)
 209                 return false;
 210
 211         padno = pin_to_padno(community, pin);
 212         gpp = padno / community->gpp_size;
 213
 214         /*
 215          * If PADCFGLOCK and PADCFGLOCKTX bits are both clear for this pad,
 216          * the pad is considered unlocked. Any other case means that it is
 217          * either fully or partially locked and we don't touch it.
 218          */
 219         offset = community->padcfglock_offset + gpp * 8;
 220         value = readl(community->regs + offset);
 221         if (value & BIT(pin % community->gpp_size))
 222                 return true;
 223
 224         offset = community->padcfglock_offset + 4 + gpp * 8;
 225         value = readl(community->regs + offset);
 226         if (value & BIT(pin % community->gpp_size))
 227                 return true;
 228
 229         return false;
 230 }
 231
 232 static bool intel_pad_usable(struct intel_pinctrl *pctrl, unsigned pin)
 233 {
 234         return intel_pad_owned_by_host(pctrl, pin) &&
 235                 !intel_pad_locked(pctrl, pin);
 236 }
 237
 238 static int intel_get_groups_count(struct pinctrl_dev *pctldev)
 239 {
 240         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 241
 242         return pctrl->soc->ngroups;
 243 }
 244
 245 static const char *intel_get_group_name(struct pinctrl_dev *pctldev,
 246                                       unsigned group)
 247 {
 248         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 249
 250         return pctrl->soc->groups[group].name;
 251 }
 252
 253 static int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned group,
 254                               const unsigned **pins, unsigned *npins)
 255 {
 256         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 257
 258         *pins = pctrl->soc->groups[group].pins;
 259         *npins = pctrl->soc->groups[group].npins;
 260         return 0;
 261 }
 262
 263 static void intel_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
 264                                unsigned pin)
 265 {
 266         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 267         void __iomem *padcfg;
 268         u32 cfg0, cfg1, mode;
 269         bool locked, acpi;
 270
 271         if (!intel_pad_owned_by_host(pctrl, pin)) {
 272                 seq_puts(s, "not available");
 273                 return;
 274         }
 275
 276         cfg0 = readl(intel_get_padcfg(pctrl, pin, PADCFG0));
 277         cfg1 = readl(intel_get_padcfg(pctrl, pin, PADCFG1));
 278
 279         mode = (cfg0 & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT;
 280         if (!mode)
 281                 seq_puts(s, "GPIO ");
 282         else
 283                 seq_printf(s, "mode %d ", mode);
 284
 285         seq_printf(s, "0x%08x 0x%08x", cfg0, cfg1);
 286
 287         /* Dump the additional PADCFG registers if available */
 288         padcfg = intel_get_padcfg(pctrl, pin, PADCFG2);
 289         if (padcfg)
 290                 seq_printf(s, " 0x%08x", readl(padcfg));
 291
 292         locked = intel_pad_locked(pctrl, pin);
 293         acpi = intel_pad_acpi_mode(pctrl, pin);
 294
 295         if (locked || acpi) {
 296                 seq_puts(s, " [");
 297                 if (locked) {
 298                         seq_puts(s, "LOCKED");
 299                         if (acpi)
 300                                 seq_puts(s, ", ");
 301                 }
 302                 if (acpi)
 303                         seq_puts(s, "ACPI");
 304                 seq_puts(s, "]");
 305         }
 306 }
 307
 308 static const struct pinctrl_ops intel_pinctrl_ops = {
 309         .get_groups_count = intel_get_groups_count,
 310         .get_group_name = intel_get_group_name,
 311         .get_group_pins = intel_get_group_pins,
 312         .pin_dbg_show = intel_pin_dbg_show,
 313 };
 314
 315 static int intel_get_functions_count(struct pinctrl_dev *pctldev)
 316 {
 317         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 318
 319         return pctrl->soc->nfunctions;
 320 }
 321
 322 static const char *intel_get_function_name(struct pinctrl_dev *pctldev,
 323                                            unsigned function)
 324 {
 325         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 326
 327         return pctrl->soc->functions[function].name;
 328 }
 329
 330 static int intel_get_function_groups(struct pinctrl_dev *pctldev,
 331                                      unsigned function,
 332                                      const char * const **groups,
 333                                      unsigned * const ngroups)
 334 {
 335         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 336
 337         *groups = pctrl->soc->functions[function].groups;
 338         *ngroups = pctrl->soc->functions[function].ngroups;
 339         return 0;
 340 }
 341
 342 static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned function,
 343                                 unsigned group)
 344 {
 345         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 346         const struct intel_pingroup *grp = &pctrl->soc->groups[group];
 347         unsigned long flags;
 348         int i;
 349
 350         raw_spin_lock_irqsave(&pctrl->lock, flags);
 351
 352         /*
 353          * All pins in the groups needs to be accessible and writable
 354          * before we can enable the mux for this group.
 355          */
 356         for (i = 0; i < grp->npins; i++) {
 357                 if (!intel_pad_usable(pctrl, grp->pins[i])) {
 358                         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 359                         return -EBUSY;
 360                 }
 361         }
 362
 363         /* Now enable the mux setting for each pin in the group */
 364         for (i = 0; i < grp->npins; i++) {
 365                 void __iomem *padcfg0;
 366                 u32 value;
 367
 368                 padcfg0 = intel_get_padcfg(pctrl, grp->pins[i], PADCFG0);
 369                 value = readl(padcfg0);
 370
 371                 value &= ~PADCFG0_PMODE_MASK;
 372                 value |= grp->mode << PADCFG0_PMODE_SHIFT;
 373
 374                 writel(value, padcfg0);
 375         }
 376
 377         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 378
 379         return 0;
 380 }
 381
 382 static void __intel_gpio_set_direction(void __iomem *padcfg0, bool input)
 383 {
 384         u32 value;
 385
 386         value = readl(padcfg0);
 387         if (input) {
 388                 value &= ~PADCFG0_GPIORXDIS;
 389                 value |= PADCFG0_GPIOTXDIS;
 390         } else {
 391                 value &= ~PADCFG0_GPIOTXDIS;
 392                 value |= PADCFG0_GPIORXDIS;
 393         }
 394         writel(value, padcfg0);
 395 }
 396
 397 static int intel_gpio_request_enable(struct pinctrl_dev *pctldev,
 398                                      struct pinctrl_gpio_range *range,
 399                                      unsigned pin)
 400 {
 401         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 402         void __iomem *padcfg0;
 403         unsigned long flags;
 404         u32 value;
 405
 406         raw_spin_lock_irqsave(&pctrl->lock, flags);
 407
 408         if (!intel_pad_usable(pctrl, pin)) {
 409                 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 410                 return -EBUSY;
 411         }
 412
 413         padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
 414         /* Put the pad into GPIO mode */
 415         value = readl(padcfg0) & ~PADCFG0_PMODE_MASK;
 416         /* Disable SCI/SMI/NMI generation */
 417         value &= ~(PADCFG0_GPIROUTIOXAPIC | PADCFG0_GPIROUTSCI);
 418         value &= ~(PADCFG0_GPIROUTSMI | PADCFG0_GPIROUTNMI);
 419         writel(value, padcfg0);
 420
 421         /* Disable TX buffer and enable RX (this will be input) */
 422         __intel_gpio_set_direction(padcfg0, true);
 423
 424         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 425
 426         return 0;
 427 }
 428
 429 static int intel_gpio_set_direction(struct pinctrl_dev *pctldev,
 430                                     struct pinctrl_gpio_range *range,
 431                                     unsigned pin, bool input)
 432 {
 433         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 434         void __iomem *padcfg0;
 435         unsigned long flags;
 436
 437         raw_spin_lock_irqsave(&pctrl->lock, flags);
 438
 439         padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
 440         __intel_gpio_set_direction(padcfg0, input);
 441
 442         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 443
 444         return 0;
 445 }
 446
 447 static const struct pinmux_ops intel_pinmux_ops = {
 448         .get_functions_count = intel_get_functions_count,
 449         .get_function_name = intel_get_function_name,
 450         .get_function_groups = intel_get_function_groups,
 451         .set_mux = intel_pinmux_set_mux,
 452         .gpio_request_enable = intel_gpio_request_enable,
 453         .gpio_set_direction = intel_gpio_set_direction,
 454 };
 455
 456 static int intel_config_get(struct pinctrl_dev *pctldev, unsigned pin,
 457                             unsigned long *config)
 458 {
 459         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 460         enum pin_config_param param = pinconf_to_config_param(*config);
 461         const struct intel_community *community;
 462         u32 value, term;
 463         u32 arg = 0;
 464
 465         if (!intel_pad_owned_by_host(pctrl, pin))
 466                 return -ENOTSUPP;
 467
 468         community = intel_get_community(pctrl, pin);
 469         value = readl(intel_get_padcfg(pctrl, pin, PADCFG1));
 470         term = (value & PADCFG1_TERM_MASK) >> PADCFG1_TERM_SHIFT;
 471
 472         switch (param) {
 473         case PIN_CONFIG_BIAS_DISABLE:
 474                 if (term)
 475                         return -EINVAL;
 476                 break;
 477
 478         case PIN_CONFIG_BIAS_PULL_UP:
 479                 if (!term || !(value & PADCFG1_TERM_UP))
 480                         return -EINVAL;
 481
 482                 switch (term) {
 483                 case PADCFG1_TERM_1K:
 484                         arg = 1000;
 485                         break;
 486                 case PADCFG1_TERM_2K:
 487                         arg = 2000;
 488                         break;
 489                 case PADCFG1_TERM_5K:
 490                         arg = 5000;
 491                         break;
 492                 case PADCFG1_TERM_20K:
 493                         arg = 20000;
 494                         break;
 495                 }
 496
 497                 break;
 498
 499         case PIN_CONFIG_BIAS_PULL_DOWN:
 500                 if (!term || value & PADCFG1_TERM_UP)
 501                         return -EINVAL;
 502
 503                 switch (term) {
 504                 case PADCFG1_TERM_1K:
 505                         if (!(community->features & PINCTRL_FEATURE_1K_PD))
 506                                 return -EINVAL;
 507                         arg = 1000;
 508                         break;
 509                 case PADCFG1_TERM_5K:
 510                         arg = 5000;
 511                         break;
 512                 case PADCFG1_TERM_20K:
 513                         arg = 20000;
 514                         break;
 515                 }
 516
 517                 break;
 518
 519         case PIN_CONFIG_INPUT_DEBOUNCE: {
 520                 void __iomem *padcfg2;
 521                 u32 v;
 522
 523                 padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2);
 524                 if (!padcfg2)
 525                         return -ENOTSUPP;
 526
 527                 v = readl(padcfg2);
 528                 if (!(v & PADCFG2_DEBEN))
 529                         return -EINVAL;
 530
 531                 v = (v & PADCFG2_DEBOUNCE_MASK) >> PADCFG2_DEBOUNCE_SHIFT;
 532                 arg = BIT(v) * DEBOUNCE_PERIOD / 1000;
 533
 534                 break;
 535         }
 536
 537         default:
 538                 return -ENOTSUPP;
 539         }
 540
 541         *config = pinconf_to_config_packed(param, arg);
 542         return 0;
 543 }
 544
 545 static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned pin,
 546                                  unsigned long config)
 547 {
 548         unsigned param = pinconf_to_config_param(config);
 549         unsigned arg = pinconf_to_config_argument(config);
 550         const struct intel_community *community;
 551         void __iomem *padcfg1;
 552         unsigned long flags;
 553         int ret = 0;
 554         u32 value;
 555
 556         raw_spin_lock_irqsave(&pctrl->lock, flags);
 557
 558         community = intel_get_community(pctrl, pin);
 559         padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1);
 560         value = readl(padcfg1);
 561
 562         switch (param) {
 563         case PIN_CONFIG_BIAS_DISABLE:
 564                 value &= ~(PADCFG1_TERM_MASK | PADCFG1_TERM_UP);
 565                 break;
 566
 567         case PIN_CONFIG_BIAS_PULL_UP:
 568                 value &= ~PADCFG1_TERM_MASK;
 569
 570                 value |= PADCFG1_TERM_UP;
 571
 572                 switch (arg) {
 573                 case 20000:
 574                         value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
 575                         break;
 576                 case 5000:
 577                         value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
 578                         break;
 579                 case 2000:
 580                         value |= PADCFG1_TERM_2K << PADCFG1_TERM_SHIFT;
 581                         break;
 582                 case 1000:
 583                         value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT;
 584                         break;
 585                 default:
 586                         ret = -EINVAL;
 587                 }
 588
 589                 break;
 590
 591         case PIN_CONFIG_BIAS_PULL_DOWN:
 592                 value &= ~(PADCFG1_TERM_UP | PADCFG1_TERM_MASK);
 593
 594                 switch (arg) {
 595                 case 20000:
 596                         value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
 597                         break;
 598                 case 5000:
 599                         value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
 600                         break;
 601                 case 1000:
 602                         if (!(community->features & PINCTRL_FEATURE_1K_PD)) {
 603                                 ret = -EINVAL;
 604                                 break;
 605                         }
 606                         value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT;
 607                         break;
 608                 default:
 609                         ret = -EINVAL;
 610                 }
 611
 612                 break;
 613         }
 614
 615         if (!ret)
 616                 writel(value, padcfg1);
 617
 618         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 619
 620         return ret;
 621 }
 622
 623 static int intel_config_set_debounce(struct intel_pinctrl *pctrl, unsigned pin,
 624                                      unsigned debounce)
 625 {
 626         void __iomem *padcfg0, *padcfg2;
 627         unsigned long flags;
 628         u32 value0, value2;
 629         int ret = 0;
 630
 631         padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2);
 632         if (!padcfg2)
 633                 return -ENOTSUPP;
 634
 635         padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
 636
 637         raw_spin_lock_irqsave(&pctrl->lock, flags);
 638
 639         value0 = readl(padcfg0);
 640         value2 = readl(padcfg2);
 641
 642         /* Disable glitch filter and debouncer */
 643         value0 &= ~PADCFG0_PREGFRXSEL;
 644         value2 &= ~(PADCFG2_DEBEN | PADCFG2_DEBOUNCE_MASK);
 645
 646         if (debounce) {
 647                 unsigned long v;
 648
 649                 v = order_base_2(debounce * 1000 / DEBOUNCE_PERIOD);
 650                 if (v < 3 || v > 15) {
 651                         ret = -EINVAL;
 652                         goto exit_unlock;
 653                 } else {
 654                         /* Enable glitch filter and debouncer */
 655                         value0 |= PADCFG0_PREGFRXSEL;
 656                         value2 |= v << PADCFG2_DEBOUNCE_SHIFT;
 657                         value2 |= PADCFG2_DEBEN;
 658                 }
 659         }
 660
 661         writel(value0, padcfg0);
 662         writel(value2, padcfg2);
 663
 664 exit_unlock:
 665         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 666
 667         return ret;
 668 }
 669
 670 static int intel_config_set(struct pinctrl_dev *pctldev, unsigned pin,
 671                           unsigned long *configs, unsigned nconfigs)
 672 {
 673         struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 674         int i, ret;
 675
 676         if (!intel_pad_usable(pctrl, pin))
 677                 return -ENOTSUPP;
 678
 679         for (i = 0; i < nconfigs; i++) {
 680                 switch (pinconf_to_config_param(configs[i])) {
 681                 case PIN_CONFIG_BIAS_DISABLE:
 682                 case PIN_CONFIG_BIAS_PULL_UP:
 683                 case PIN_CONFIG_BIAS_PULL_DOWN:
 684                         ret = intel_config_set_pull(pctrl, pin, configs[i]);
 685                         if (ret)
 686                                 return ret;
 687                         break;
 688
 689                 case PIN_CONFIG_INPUT_DEBOUNCE:
 690                         ret = intel_config_set_debounce(pctrl, pin,
 691                                 pinconf_to_config_argument(configs[i]));
 692                         if (ret)
 693                                 return ret;
 694                         break;
 695
 696                 default:
 697                         return -ENOTSUPP;
 698                 }
 699         }
 700
 701         return 0;
 702 }
 703
 704 static const struct pinconf_ops intel_pinconf_ops = {
 705         .is_generic = true,
 706         .pin_config_get = intel_config_get,
 707         .pin_config_set = intel_config_set,
 708 };
 709
 710 static const struct pinctrl_desc intel_pinctrl_desc = {
 711         .pctlops = &intel_pinctrl_ops,
 712         .pmxops = &intel_pinmux_ops,
 713         .confops = &intel_pinconf_ops,
 714         .owner = THIS_MODULE,
 715 };
 716
 717 static int intel_gpio_get(struct gpio_chip *chip, unsigned offset)
 718 {
 719         struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
 720         void __iomem *reg;
 721
 722         reg = intel_get_padcfg(pctrl, offset, PADCFG0);
 723         if (!reg)
 724                 return -EINVAL;
 725
 726         return !!(readl(reg) & PADCFG0_GPIORXSTATE);
 727 }
 728
 729 static void intel_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 730 {
 731         struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
 732         void __iomem *reg;
 733
 734         reg = intel_get_padcfg(pctrl, offset, PADCFG0);
 735         if (reg) {
 736                 unsigned long flags;
 737                 u32 padcfg0;
 738
 739                 raw_spin_lock_irqsave(&pctrl->lock, flags);
 740                 padcfg0 = readl(reg);
 741                 if (value)
 742                         padcfg0 |= PADCFG0_GPIOTXSTATE;
 743                 else
 744                         padcfg0 &= ~PADCFG0_GPIOTXSTATE;
 745                 writel(padcfg0, reg);
 746                 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 747         }
 748 }
 749
 750 static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
 751 {
 752         return pinctrl_gpio_direction_input(chip->base + offset);
 753 }
 754
 755 static int intel_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
 756                                        int value)
 757 {
 758         intel_gpio_set(chip, offset, value);
 759         return pinctrl_gpio_direction_output(chip->base + offset);
 760 }
 761
 762 static const struct gpio_chip intel_gpio_chip = {
 763         .owner = THIS_MODULE,
 764         .request = gpiochip_generic_request,
 765         .free = gpiochip_generic_free,
 766         .direction_input = intel_gpio_direction_input,
 767         .direction_output = intel_gpio_direction_output,
 768         .get = intel_gpio_get,
 769         .set = intel_gpio_set,
 770         .set_config = gpiochip_generic_config,
 771 };
 772
 773 static void intel_gpio_irq_ack(struct irq_data *d)
 774 {
 775         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 776         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
 777         const struct intel_community *community;
 778         unsigned pin = irqd_to_hwirq(d);
 779
 780         raw_spin_lock(&pctrl->lock);
 781
 782         community = intel_get_community(pctrl, pin);
 783         if (community) {
 784                 unsigned padno = pin_to_padno(community, pin);
 785                 unsigned gpp_offset = padno % community->gpp_size;
 786                 unsigned gpp = padno / community->gpp_size;
 787
 788                 writel(BIT(gpp_offset), community->regs + GPI_IS + gpp * 4);
 789         }
 790
 791         raw_spin_unlock(&pctrl->lock);
 792 }
 793
 794 static void intel_gpio_irq_enable(struct irq_data *d)
 795 {
 796         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 797         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
 798         const struct intel_community *community;
 799         unsigned pin = irqd_to_hwirq(d);
 800         unsigned long flags;
 801
 802         raw_spin_lock_irqsave(&pctrl->lock, flags);
 803
 804         community = intel_get_community(pctrl, pin);
 805         if (community) {
 806                 unsigned padno = pin_to_padno(community, pin);
 807                 unsigned gpp_size = community->gpp_size;
 808                 unsigned gpp_offset = padno % gpp_size;
 809                 unsigned gpp = padno / gpp_size;
 810                 u32 value;
 811
 812                 /* Clear interrupt status first to avoid unexpected interrupt */
 813                 writel(BIT(gpp_offset), community->regs + GPI_IS + gpp * 4);
 814
 815                 value = readl(community->regs + community->ie_offset + gpp * 4);
 816                 value |= BIT(gpp_offset);
 817                 writel(value, community->regs + community->ie_offset + gpp * 4);
 818         }
 819
 820         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 821 }
 822
 823 static void intel_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
 824 {
 825         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 826         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
 827         const struct intel_community *community;
 828         unsigned pin = irqd_to_hwirq(d);
 829         unsigned long flags;
 830
 831         raw_spin_lock_irqsave(&pctrl->lock, flags);
 832
 833         community = intel_get_community(pctrl, pin);
 834         if (community) {
 835                 unsigned padno = pin_to_padno(community, pin);
 836                 unsigned gpp_offset = padno % community->gpp_size;
 837                 unsigned gpp = padno / community->gpp_size;
 838                 void __iomem *reg;
 839                 u32 value;
 840
 841                 reg = community->regs + community->ie_offset + gpp * 4;
 842                 value = readl(reg);
 843                 if (mask)
 844                         value &= ~BIT(gpp_offset);
 845                 else
 846                         value |= BIT(gpp_offset);
 847                 writel(value, reg);
 848         }
 849
 850         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 851 }
 852
 853 static void intel_gpio_irq_mask(struct irq_data *d)
 854 {
 855         intel_gpio_irq_mask_unmask(d, true);
 856 }
 857
 858 static void intel_gpio_irq_unmask(struct irq_data *d)
 859 {
 860         intel_gpio_irq_mask_unmask(d, false);
 861 }
 862
 863 static int intel_gpio_irq_type(struct irq_data *d, unsigned type)
 864 {
 865         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 866         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
 867         unsigned pin = irqd_to_hwirq(d);
 868         unsigned long flags;
 869         void __iomem *reg;
 870         u32 value;
 871
 872         reg = intel_get_padcfg(pctrl, pin, PADCFG0);
 873         if (!reg)
 874                 return -EINVAL;
 875
 876         /*
 877          * If the pin is in ACPI mode it is still usable as a GPIO but it
 878          * cannot be used as IRQ because GPI_IS status bit will not be
 879          * updated by the host controller hardware.
 880          */
 881         if (intel_pad_acpi_mode(pctrl, pin)) {
 882                 dev_warn(pctrl->dev, "pin %u cannot be used as IRQ\n", pin);
 883                 return -EPERM;
 884         }
 885
 886         raw_spin_lock_irqsave(&pctrl->lock, flags);
 887
 888         value = readl(reg);
 889
 890         value &= ~(PADCFG0_RXEVCFG_MASK | PADCFG0_RXINV);
 891
 892         if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
 893                 value |= PADCFG0_RXEVCFG_EDGE_BOTH << PADCFG0_RXEVCFG_SHIFT;
 894         } else if (type & IRQ_TYPE_EDGE_FALLING) {
 895                 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT;
 896                 value |= PADCFG0_RXINV;
 897         } else if (type & IRQ_TYPE_EDGE_RISING) {
 898                 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT;
 899         } else if (type & IRQ_TYPE_LEVEL_MASK) {
 900                 if (type & IRQ_TYPE_LEVEL_LOW)
 901                         value |= PADCFG0_RXINV;
 902         } else {
 903                 value |= PADCFG0_RXEVCFG_DISABLED << PADCFG0_RXEVCFG_SHIFT;
 904         }
 905
 906         writel(value, reg);
 907
 908         if (type & IRQ_TYPE_EDGE_BOTH)
 909                 irq_set_handler_locked(d, handle_edge_irq);
 910         else if (type & IRQ_TYPE_LEVEL_MASK)
 911                 irq_set_handler_locked(d, handle_level_irq);
 912
 913         raw_spin_unlock_irqrestore(&pctrl->lock, flags);
 914
 915         return 0;
 916 }
 917
 918 static int intel_gpio_irq_wake(struct irq_data *d, unsigned int on)
 919 {
 920         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 921         struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
 922         unsigned pin = irqd_to_hwirq(d);
 923
 924         if (on)
 925                 enable_irq_wake(pctrl->irq);
 926         else
 927                 disable_irq_wake(pctrl->irq);
 928
 929         dev_dbg(pctrl->dev, "%sable wake for pin %u\n", on ? "en" : "dis", pin);
 930         return 0;
 931 }
 932
 933 static irqreturn_t intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl,
 934         const struct intel_community *community)
 935 {
 936         struct gpio_chip *gc = &pctrl->chip;
 937         irqreturn_t ret = IRQ_NONE;
 938         int gpp;
 939
 940         for (gpp = 0; gpp < community->ngpps; gpp++) {
 941                 unsigned long pending, enabled, gpp_offset;
 942
 943                 pending = readl(community->regs + GPI_IS + gpp * 4);
 944                 enabled = readl(community->regs + community->ie_offset +
 945                                 gpp * 4);
 946
 947                 /* Only interrupts that are enabled */
 948                 pending &= enabled;
 949
 950                 for_each_set_bit(gpp_offset, &pending, community->gpp_size) {
 951                         unsigned padno, irq;
 952
 953                         /*
 954                          * The last group in community can have less pins
 955                          * than NPADS_IN_GPP.
 956                          */
 957                         padno = gpp_offset + gpp * community->gpp_size;
 958                         if (padno >= community->npins)
 959                                 break;
 960
 961                         irq = irq_find_mapping(gc->irqdomain,
 962                                                community->pin_base + padno);
 963                         generic_handle_irq(irq);
 964
 965                         ret |= IRQ_HANDLED;
 966                 }
 967         }
 968
 969         return ret;
 970 }
 971
 972 static irqreturn_t intel_gpio_irq(int irq, void *data)
 973 {
 974         const struct intel_community *community;
 975         struct intel_pinctrl *pctrl = data;
 976         irqreturn_t ret = IRQ_NONE;
 977         int i;
 978
 979         /* Need to check all communities for pending interrupts */
 980         for (i = 0; i < pctrl->ncommunities; i++) {
 981                 community = &pctrl->communities[i];
 982                 ret |= intel_gpio_community_irq_handler(pctrl, community);
 983         }
 984
 985         return ret;
 986 }
 987
 988 static struct irq_chip intel_gpio_irqchip = {
 989         .name = "intel-gpio",
 990         .irq_enable = intel_gpio_irq_enable,
 991         .irq_ack = intel_gpio_irq_ack,
 992         .irq_mask = intel_gpio_irq_mask,
 993         .irq_unmask = intel_gpio_irq_unmask,
 994         .irq_set_type = intel_gpio_irq_type,
 995         .irq_set_wake = intel_gpio_irq_wake,
 996 };
 997
 998 static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq)
 999 {
1000         int ret;
1001
1002         pctrl->chip = intel_gpio_chip;
1003
1004         pctrl->chip.ngpio = pctrl->soc->npins;
1005         pctrl->chip.label = dev_name(pctrl->dev);
1006         pctrl->chip.parent = pctrl->dev;
1007         pctrl->chip.base = -1;
1008         pctrl->irq = irq;
1009
1010         ret = devm_gpiochip_add_data(pctrl->dev, &pctrl->chip, pctrl);
1011         if (ret) {
1012                 dev_err(pctrl->dev, "failed to register gpiochip\n");
1013                 return ret;
1014         }
1015
1016         ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev),
1017                                      0, 0, pctrl->soc->npins);
1018         if (ret) {
1019                 dev_err(pctrl->dev, "failed to add GPIO pin range\n");
1020                 return ret;
1021         }
1022
1023         /*
1024          * We need to request the interrupt here (instead of providing chip
1025          * to the irq directly) because on some platforms several GPIO
1026          * controllers share the same interrupt line.
1027          */
1028         ret = devm_request_irq(pctrl->dev, irq, intel_gpio_irq,
1029                                IRQF_SHARED | IRQF_NO_THREAD,
1030                                dev_name(pctrl->dev), pctrl);
1031         if (ret) {
1032                 dev_err(pctrl->dev, "failed to request interrupt\n");
1033                 return ret;
1034         }
1035
1036         ret = gpiochip_irqchip_add(&pctrl->chip, &intel_gpio_irqchip, 0,
1037                                    handle_bad_irq, IRQ_TYPE_NONE);
1038         if (ret) {
1039                 dev_err(pctrl->dev, "failed to add irqchip\n");
1040                 return ret;
1041         }
1042
1043         gpiochip_set_chained_irqchip(&pctrl->chip, &intel_gpio_irqchip, irq,
1044                                      NULL);
1045         return 0;
1046 }
1047
1048 static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl)
1049 {
1050 #ifdef CONFIG_PM_SLEEP
1051         const struct intel_pinctrl_soc_data *soc = pctrl->soc;
1052         struct intel_community_context *communities;
1053         struct intel_pad_context *pads;
1054         int i;
1055
1056         pads = devm_kcalloc(pctrl->dev, soc->npins, sizeof(*pads), GFP_KERNEL);
1057         if (!pads)
1058                 return -ENOMEM;
1059
1060         communities = devm_kcalloc(pctrl->dev, pctrl->ncommunities,
1061                                    sizeof(*communities), GFP_KERNEL);
1062         if (!communities)
1063                 return -ENOMEM;
1064
1065
1066         for (i = 0; i < pctrl->ncommunities; i++) {
1067                 struct intel_community *community = &pctrl->communities[i];
1068                 u32 *intmask;
1069
1070                 intmask = devm_kcalloc(pctrl->dev, community->ngpps,
1071                                        sizeof(*intmask), GFP_KERNEL);
1072                 if (!intmask)
1073                         return -ENOMEM;
1074
1075                 communities[i].intmask = intmask;
1076         }
1077
1078         pctrl->context.pads = pads;
1079         pctrl->context.communities = communities;
1080 #endif
1081
1082         return 0;
1083 }
1084
1085 int intel_pinctrl_probe(struct platform_device *pdev,
1086                         const struct intel_pinctrl_soc_data *soc_data)
1087 {
1088         struct intel_pinctrl *pctrl;
1089         int i, ret, irq;
1090
1091         if (!soc_data)
1092                 return -EINVAL;
1093
1094         pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
1095         if (!pctrl)
1096                 return -ENOMEM;
1097
1098         pctrl->dev = &pdev->dev;
1099         pctrl->soc = soc_data;
1100         raw_spin_lock_init(&pctrl->lock);
1101
1102         /*
1103          * Make a copy of the communities which we can use to hold pointers
1104          * to the registers.
1105          */
1106         pctrl->ncommunities = pctrl->soc->ncommunities;
1107         pctrl->communities = devm_kcalloc(&pdev->dev, pctrl->ncommunities,
1108                                   sizeof(*pctrl->communities), GFP_KERNEL);
1109         if (!pctrl->communities)
1110                 return -ENOMEM;
1111
1112         for (i = 0; i < pctrl->ncommunities; i++) {
1113                 struct intel_community *community = &pctrl->communities[i];
1114                 struct resource *res;
1115                 void __iomem *regs;
1116                 u32 padbar;
1117
1118                 *community = pctrl->soc->communities[i];
1119
1120                 res = platform_get_resource(pdev, IORESOURCE_MEM,
1121                                             community->barno);
1122                 regs = devm_ioremap_resource(&pdev->dev, res);
1123                 if (IS_ERR(regs))
1124                         return PTR_ERR(regs);
1125
1126                 /*
1127                  * Determine community features based on the revision if
1128                  * not specified already.
1129                  */
1130                 if (!community->features) {
1131                         u32 rev;
1132
1133                         rev = (readl(regs + REVID) & REVID_MASK) >> REVID_SHIFT;
1134                         if (rev >= 0x94) {
1135                                 community->features |= PINCTRL_FEATURE_DEBOUNCE;
1136                                 community->features |= PINCTRL_FEATURE_1K_PD;
1137                         }
1138                 }
1139
1140                 /* Read offset of the pad configuration registers */
1141                 padbar = readl(regs + PADBAR);
1142
1143                 community->regs = regs;
1144                 community->pad_regs = regs + padbar;
1145                 community->ngpps = DIV_ROUND_UP(community->npins,
1146                                                 community->gpp_size);
1147         }
1148
1149         irq = platform_get_irq(pdev, 0);
1150         if (irq < 0) {
1151                 dev_err(&pdev->dev, "failed to get interrupt number\n");
1152                 return irq;
1153         }
1154
1155         ret = intel_pinctrl_pm_init(pctrl);
1156         if (ret)
1157                 return ret;
1158
1159         pctrl->pctldesc = intel_pinctrl_desc;
1160         pctrl->pctldesc.name = dev_name(&pdev->dev);
1161         pctrl->pctldesc.pins = pctrl->soc->pins;
1162         pctrl->pctldesc.npins = pctrl->soc->npins;
1163
1164         pctrl->pctldev = devm_pinctrl_register(&pdev->dev, &pctrl->pctldesc,
1165                                                pctrl);
1166         if (IS_ERR(pctrl->pctldev)) {
1167                 dev_err(&pdev->dev, "failed to register pinctrl driver\n");
1168                 return PTR_ERR(pctrl->pctldev);
1169         }
1170
1171         ret = intel_gpio_probe(pctrl, irq);
1172         if (ret)
1173                 return ret;
1174
1175         platform_set_drvdata(pdev, pctrl);
1176
1177         return 0;
1178 }
1179 EXPORT_SYMBOL_GPL(intel_pinctrl_probe);
1180
1181 #ifdef CONFIG_PM_SLEEP
1182 static bool intel_pinctrl_should_save(struct intel_pinctrl *pctrl, unsigned pin)
1183 {
1184         const struct pin_desc *pd = pin_desc_get(pctrl->pctldev, pin);
1185
1186         if (!pd || !intel_pad_usable(pctrl, pin))
1187                 return false;
1188
1189         /*
1190          * Only restore the pin if it is actually in use by the kernel (or
1191          * by userspace). It is possible that some pins are used by the
1192          * BIOS during resume and those are not always locked down so leave
1193          * them alone.
1194          */
1195         if (pd->mux_owner || pd->gpio_owner ||
1196             gpiochip_line_is_irq(&pctrl->chip, pin))
1197                 return true;
1198
1199         return false;
1200 }
1201
1202 int intel_pinctrl_suspend(struct device *dev)
1203 {
1204         struct platform_device *pdev = to_platform_device(dev);
1205         struct intel_pinctrl *pctrl = platform_get_drvdata(pdev);
1206         struct intel_community_context *communities;
1207         struct intel_pad_context *pads;
1208         int i;
1209
1210         pads = pctrl->context.pads;
1211         for (i = 0; i < pctrl->soc->npins; i++) {
1212                 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1213                 void __iomem *padcfg;
1214                 u32 val;
1215
1216                 if (!intel_pinctrl_should_save(pctrl, desc->number))
1217                         continue;
1218
1219                 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG0));
1220                 pads[i].padcfg0 = val & ~PADCFG0_GPIORXSTATE;
1221                 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG1));
1222                 pads[i].padcfg1 = val;
1223
1224                 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG2);
1225                 if (padcfg)
1226                         pads[i].padcfg2 = readl(padcfg);
1227         }
1228
1229         communities = pctrl->context.communities;
1230         for (i = 0; i < pctrl->ncommunities; i++) {
1231                 struct intel_community *community = &pctrl->communities[i];
1232                 void __iomem *base;
1233                 unsigned gpp;
1234
1235                 base = community->regs + community->ie_offset;
1236                 for (gpp = 0; gpp < community->ngpps; gpp++)
1237                         communities[i].intmask[gpp] = readl(base + gpp * 4);
1238         }
1239
1240         return 0;
1241 }
1242 EXPORT_SYMBOL_GPL(intel_pinctrl_suspend);
1243
1244 static void intel_gpio_irq_init(struct intel_pinctrl *pctrl)
1245 {
1246         size_t i;
1247
1248         for (i = 0; i < pctrl->ncommunities; i++) {
1249                 const struct intel_community *community;
1250                 void __iomem *base;
1251                 unsigned gpp;
1252
1253                 community = &pctrl->communities[i];
1254                 base = community->regs;
1255
1256                 for (gpp = 0; gpp < community->ngpps; gpp++) {
1257                         /* Mask and clear all interrupts */
1258                         writel(0, base + community->ie_offset + gpp * 4);
1259                         writel(0xffff, base + GPI_IS + gpp * 4);
1260                 }
1261         }
1262 }
1263
1264 int intel_pinctrl_resume(struct device *dev)
1265 {
1266         struct platform_device *pdev = to_platform_device(dev);
1267         struct intel_pinctrl *pctrl = platform_get_drvdata(pdev);
1268         const struct intel_community_context *communities;
1269         const struct intel_pad_context *pads;
1270         int i;
1271
1272         /* Mask all interrupts */
1273         intel_gpio_irq_init(pctrl);
1274
1275         pads = pctrl->context.pads;
1276         for (i = 0; i < pctrl->soc->npins; i++) {
1277                 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1278                 void __iomem *padcfg;
1279                 u32 val;
1280
1281                 if (!intel_pinctrl_should_save(pctrl, desc->number))
1282                         continue;
1283
1284                 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG0);
1285                 val = readl(padcfg) & ~PADCFG0_GPIORXSTATE;
1286                 if (val != pads[i].padcfg0) {
1287                         writel(pads[i].padcfg0, padcfg);
1288                         dev_dbg(dev, "restored pin %u padcfg0 %#08x\n",
1289                                 desc->number, readl(padcfg));
1290                 }
1291
1292                 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG1);
1293                 val = readl(padcfg);
1294                 if (val != pads[i].padcfg1) {
1295                         writel(pads[i].padcfg1, padcfg);
1296                         dev_dbg(dev, "restored pin %u padcfg1 %#08x\n",
1297                                 desc->number, readl(padcfg));
1298                 }
1299
1300                 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG2);
1301                 if (padcfg) {
1302                         val = readl(padcfg);
1303                         if (val != pads[i].padcfg2) {
1304                                 writel(pads[i].padcfg2, padcfg);
1305                                 dev_dbg(dev, "restored pin %u padcfg2 %#08x\n",
1306                                         desc->number, readl(padcfg));
1307                         }
1308                 }
1309         }
1310
1311         communities = pctrl->context.communities;
1312         for (i = 0; i < pctrl->ncommunities; i++) {
1313                 struct intel_community *community = &pctrl->communities[i];
1314                 void __iomem *base;
1315                 unsigned gpp;
1316
1317                 base = community->regs + community->ie_offset;
1318                 for (gpp = 0; gpp < community->ngpps; gpp++) {
1319                         writel(communities[i].intmask[gpp], base + gpp * 4);
1320                         dev_dbg(dev, "restored mask %d/%u %#08x\n", i, gpp,
1321                                 readl(base + gpp * 4));
1322                 }
1323         }
1324
1325         return 0;
1326 }
1327 EXPORT_SYMBOL_GPL(intel_pinctrl_resume);
1328 #endif
1329
1330 MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>");
1331 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
1332 MODULE_DESCRIPTION("Intel pinctrl/GPIO core driver");
1333 MODULE_LICENSE("GPL v2");