2 * Intel pinctrl/GPIO core driver.
4 * Copyright (C) 2015, Intel Corporation
5 * Authors: Mathias Nyman <mathias.nyman@linux.intel.com>
6 * Mika Westerberg <mika.westerberg@linux.intel.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/module.h>
14 #include <linux/interrupt.h>
15 #include <linux/gpio/driver.h>
16 #include <linux/log2.h>
17 #include <linux/platform_device.h>
18 #include <linux/pinctrl/pinctrl.h>
19 #include <linux/pinctrl/pinmux.h>
20 #include <linux/pinctrl/pinconf.h>
21 #include <linux/pinctrl/pinconf-generic.h>
24 #include "pinctrl-intel.h"
26 /* Offset from regs */
28 #define REVID_SHIFT 16
29 #define REVID_MASK GENMASK(31, 16)
33 #define GPI_GPE_STS 0x140
34 #define GPI_GPE_EN 0x160
37 #define PADOWN_SHIFT(p) ((p) % 8 * PADOWN_BITS)
38 #define PADOWN_MASK(p) (0xf << PADOWN_SHIFT(p))
39 #define PADOWN_GPP(p) ((p) / 8)
41 /* Offset from pad_regs */
43 #define PADCFG0_RXEVCFG_SHIFT 25
44 #define PADCFG0_RXEVCFG_MASK (3 << PADCFG0_RXEVCFG_SHIFT)
45 #define PADCFG0_RXEVCFG_LEVEL 0
46 #define PADCFG0_RXEVCFG_EDGE 1
47 #define PADCFG0_RXEVCFG_DISABLED 2
48 #define PADCFG0_RXEVCFG_EDGE_BOTH 3
49 #define PADCFG0_PREGFRXSEL BIT(24)
50 #define PADCFG0_RXINV BIT(23)
51 #define PADCFG0_GPIROUTIOXAPIC BIT(20)
52 #define PADCFG0_GPIROUTSCI BIT(19)
53 #define PADCFG0_GPIROUTSMI BIT(18)
54 #define PADCFG0_GPIROUTNMI BIT(17)
55 #define PADCFG0_PMODE_SHIFT 10
56 #define PADCFG0_PMODE_MASK (0xf << PADCFG0_PMODE_SHIFT)
57 #define PADCFG0_GPIORXDIS BIT(9)
58 #define PADCFG0_GPIOTXDIS BIT(8)
59 #define PADCFG0_GPIORXSTATE BIT(1)
60 #define PADCFG0_GPIOTXSTATE BIT(0)
63 #define PADCFG1_TERM_UP BIT(13)
64 #define PADCFG1_TERM_SHIFT 10
65 #define PADCFG1_TERM_MASK (7 << PADCFG1_TERM_SHIFT)
66 #define PADCFG1_TERM_20K 4
67 #define PADCFG1_TERM_2K 3
68 #define PADCFG1_TERM_5K 2
69 #define PADCFG1_TERM_1K 1
72 #define PADCFG2_DEBEN BIT(0)
73 #define PADCFG2_DEBOUNCE_SHIFT 1
74 #define PADCFG2_DEBOUNCE_MASK GENMASK(4, 1)
76 #define DEBOUNCE_PERIOD 31250 /* ns */
78 struct intel_pad_context {
84 struct intel_community_context {
88 struct intel_pinctrl_context {
89 struct intel_pad_context *pads;
90 struct intel_community_context *communities;
94 * struct intel_pinctrl - Intel pinctrl private structure
95 * @dev: Pointer to the device structure
96 * @lock: Lock to serialize register access
97 * @pctldesc: Pin controller description
98 * @pctldev: Pointer to the pin controller device
99 * @chip: GPIO chip in this pin controller
100 * @soc: SoC/PCH specific pin configuration data
101 * @communities: All communities in this pin controller
102 * @ncommunities: Number of communities in this pin controller
103 * @context: Configuration saved over system sleep
104 * @irq: pinctrl/GPIO chip irq number
106 struct intel_pinctrl {
109 struct pinctrl_desc pctldesc;
110 struct pinctrl_dev *pctldev;
111 struct gpio_chip chip;
112 const struct intel_pinctrl_soc_data *soc;
113 struct intel_community *communities;
115 struct intel_pinctrl_context context;
119 #define pin_to_padno(c, p) ((p) - (c)->pin_base)
121 static struct intel_community *intel_get_community(struct intel_pinctrl *pctrl,
124 struct intel_community *community;
127 for (i = 0; i < pctrl->ncommunities; i++) {
128 community = &pctrl->communities[i];
129 if (pin >= community->pin_base &&
130 pin < community->pin_base + community->npins)
134 dev_warn(pctrl->dev, "failed to find community for pin %u\n", pin);
138 static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl, unsigned pin,
141 const struct intel_community *community;
145 community = intel_get_community(pctrl, pin);
149 padno = pin_to_padno(community, pin);
150 nregs = (community->features & PINCTRL_FEATURE_DEBOUNCE) ? 4 : 2;
152 if (reg == PADCFG2 && !(community->features & PINCTRL_FEATURE_DEBOUNCE))
155 return community->pad_regs + reg + padno * nregs * 4;
158 static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned pin)
160 const struct intel_community *community;
161 unsigned padno, gpp, offset, group;
162 void __iomem *padown;
164 community = intel_get_community(pctrl, pin);
167 if (!community->padown_offset)
170 padno = pin_to_padno(community, pin);
171 group = padno / community->gpp_size;
172 gpp = PADOWN_GPP(padno % community->gpp_size);
173 offset = community->padown_offset + 0x10 * group + gpp * 4;
174 padown = community->regs + offset;
176 return !(readl(padown) & PADOWN_MASK(padno));
179 static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned pin)
181 const struct intel_community *community;
182 unsigned padno, gpp, offset;
183 void __iomem *hostown;
185 community = intel_get_community(pctrl, pin);
188 if (!community->hostown_offset)
191 padno = pin_to_padno(community, pin);
192 gpp = padno / community->gpp_size;
193 offset = community->hostown_offset + gpp * 4;
194 hostown = community->regs + offset;
196 return !(readl(hostown) & BIT(padno % community->gpp_size));
199 static bool intel_pad_locked(struct intel_pinctrl *pctrl, unsigned pin)
201 struct intel_community *community;
202 unsigned padno, gpp, offset;
205 community = intel_get_community(pctrl, pin);
208 if (!community->padcfglock_offset)
211 padno = pin_to_padno(community, pin);
212 gpp = padno / community->gpp_size;
215 * If PADCFGLOCK and PADCFGLOCKTX bits are both clear for this pad,
216 * the pad is considered unlocked. Any other case means that it is
217 * either fully or partially locked and we don't touch it.
219 offset = community->padcfglock_offset + gpp * 8;
220 value = readl(community->regs + offset);
221 if (value & BIT(pin % community->gpp_size))
224 offset = community->padcfglock_offset + 4 + gpp * 8;
225 value = readl(community->regs + offset);
226 if (value & BIT(pin % community->gpp_size))
232 static bool intel_pad_usable(struct intel_pinctrl *pctrl, unsigned pin)
234 return intel_pad_owned_by_host(pctrl, pin) &&
235 !intel_pad_locked(pctrl, pin);
238 static int intel_get_groups_count(struct pinctrl_dev *pctldev)
240 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
242 return pctrl->soc->ngroups;
245 static const char *intel_get_group_name(struct pinctrl_dev *pctldev,
248 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
250 return pctrl->soc->groups[group].name;
253 static int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned group,
254 const unsigned **pins, unsigned *npins)
256 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
258 *pins = pctrl->soc->groups[group].pins;
259 *npins = pctrl->soc->groups[group].npins;
263 static void intel_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
266 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
267 void __iomem *padcfg;
268 u32 cfg0, cfg1, mode;
271 if (!intel_pad_owned_by_host(pctrl, pin)) {
272 seq_puts(s, "not available");
276 cfg0 = readl(intel_get_padcfg(pctrl, pin, PADCFG0));
277 cfg1 = readl(intel_get_padcfg(pctrl, pin, PADCFG1));
279 mode = (cfg0 & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT;
281 seq_puts(s, "GPIO ");
283 seq_printf(s, "mode %d ", mode);
285 seq_printf(s, "0x%08x 0x%08x", cfg0, cfg1);
287 /* Dump the additional PADCFG registers if available */
288 padcfg = intel_get_padcfg(pctrl, pin, PADCFG2);
290 seq_printf(s, " 0x%08x", readl(padcfg));
292 locked = intel_pad_locked(pctrl, pin);
293 acpi = intel_pad_acpi_mode(pctrl, pin);
295 if (locked || acpi) {
298 seq_puts(s, "LOCKED");
308 static const struct pinctrl_ops intel_pinctrl_ops = {
309 .get_groups_count = intel_get_groups_count,
310 .get_group_name = intel_get_group_name,
311 .get_group_pins = intel_get_group_pins,
312 .pin_dbg_show = intel_pin_dbg_show,
315 static int intel_get_functions_count(struct pinctrl_dev *pctldev)
317 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
319 return pctrl->soc->nfunctions;
322 static const char *intel_get_function_name(struct pinctrl_dev *pctldev,
325 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
327 return pctrl->soc->functions[function].name;
330 static int intel_get_function_groups(struct pinctrl_dev *pctldev,
332 const char * const **groups,
333 unsigned * const ngroups)
335 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
337 *groups = pctrl->soc->functions[function].groups;
338 *ngroups = pctrl->soc->functions[function].ngroups;
342 static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned function,
345 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
346 const struct intel_pingroup *grp = &pctrl->soc->groups[group];
350 raw_spin_lock_irqsave(&pctrl->lock, flags);
353 * All pins in the groups needs to be accessible and writable
354 * before we can enable the mux for this group.
356 for (i = 0; i < grp->npins; i++) {
357 if (!intel_pad_usable(pctrl, grp->pins[i])) {
358 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
363 /* Now enable the mux setting for each pin in the group */
364 for (i = 0; i < grp->npins; i++) {
365 void __iomem *padcfg0;
368 padcfg0 = intel_get_padcfg(pctrl, grp->pins[i], PADCFG0);
369 value = readl(padcfg0);
371 value &= ~PADCFG0_PMODE_MASK;
372 value |= grp->mode << PADCFG0_PMODE_SHIFT;
374 writel(value, padcfg0);
377 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
382 static void __intel_gpio_set_direction(void __iomem *padcfg0, bool input)
386 value = readl(padcfg0);
388 value &= ~PADCFG0_GPIORXDIS;
389 value |= PADCFG0_GPIOTXDIS;
391 value &= ~PADCFG0_GPIOTXDIS;
392 value |= PADCFG0_GPIORXDIS;
394 writel(value, padcfg0);
397 static int intel_gpio_request_enable(struct pinctrl_dev *pctldev,
398 struct pinctrl_gpio_range *range,
401 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
402 void __iomem *padcfg0;
406 raw_spin_lock_irqsave(&pctrl->lock, flags);
408 if (!intel_pad_usable(pctrl, pin)) {
409 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
413 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
414 /* Put the pad into GPIO mode */
415 value = readl(padcfg0) & ~PADCFG0_PMODE_MASK;
416 /* Disable SCI/SMI/NMI generation */
417 value &= ~(PADCFG0_GPIROUTIOXAPIC | PADCFG0_GPIROUTSCI);
418 value &= ~(PADCFG0_GPIROUTSMI | PADCFG0_GPIROUTNMI);
419 writel(value, padcfg0);
421 /* Disable TX buffer and enable RX (this will be input) */
422 __intel_gpio_set_direction(padcfg0, true);
424 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
429 static int intel_gpio_set_direction(struct pinctrl_dev *pctldev,
430 struct pinctrl_gpio_range *range,
431 unsigned pin, bool input)
433 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
434 void __iomem *padcfg0;
437 raw_spin_lock_irqsave(&pctrl->lock, flags);
439 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
440 __intel_gpio_set_direction(padcfg0, input);
442 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
447 static const struct pinmux_ops intel_pinmux_ops = {
448 .get_functions_count = intel_get_functions_count,
449 .get_function_name = intel_get_function_name,
450 .get_function_groups = intel_get_function_groups,
451 .set_mux = intel_pinmux_set_mux,
452 .gpio_request_enable = intel_gpio_request_enable,
453 .gpio_set_direction = intel_gpio_set_direction,
456 static int intel_config_get(struct pinctrl_dev *pctldev, unsigned pin,
457 unsigned long *config)
459 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
460 enum pin_config_param param = pinconf_to_config_param(*config);
461 const struct intel_community *community;
465 if (!intel_pad_owned_by_host(pctrl, pin))
468 community = intel_get_community(pctrl, pin);
469 value = readl(intel_get_padcfg(pctrl, pin, PADCFG1));
470 term = (value & PADCFG1_TERM_MASK) >> PADCFG1_TERM_SHIFT;
473 case PIN_CONFIG_BIAS_DISABLE:
478 case PIN_CONFIG_BIAS_PULL_UP:
479 if (!term || !(value & PADCFG1_TERM_UP))
483 case PADCFG1_TERM_1K:
486 case PADCFG1_TERM_2K:
489 case PADCFG1_TERM_5K:
492 case PADCFG1_TERM_20K:
499 case PIN_CONFIG_BIAS_PULL_DOWN:
500 if (!term || value & PADCFG1_TERM_UP)
504 case PADCFG1_TERM_1K:
505 if (!(community->features & PINCTRL_FEATURE_1K_PD))
509 case PADCFG1_TERM_5K:
512 case PADCFG1_TERM_20K:
519 case PIN_CONFIG_INPUT_DEBOUNCE: {
520 void __iomem *padcfg2;
523 padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2);
528 if (!(v & PADCFG2_DEBEN))
531 v = (v & PADCFG2_DEBOUNCE_MASK) >> PADCFG2_DEBOUNCE_SHIFT;
532 arg = BIT(v) * DEBOUNCE_PERIOD / 1000;
541 *config = pinconf_to_config_packed(param, arg);
545 static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned pin,
546 unsigned long config)
548 unsigned param = pinconf_to_config_param(config);
549 unsigned arg = pinconf_to_config_argument(config);
550 const struct intel_community *community;
551 void __iomem *padcfg1;
556 raw_spin_lock_irqsave(&pctrl->lock, flags);
558 community = intel_get_community(pctrl, pin);
559 padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1);
560 value = readl(padcfg1);
563 case PIN_CONFIG_BIAS_DISABLE:
564 value &= ~(PADCFG1_TERM_MASK | PADCFG1_TERM_UP);
567 case PIN_CONFIG_BIAS_PULL_UP:
568 value &= ~PADCFG1_TERM_MASK;
570 value |= PADCFG1_TERM_UP;
574 value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
577 value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
580 value |= PADCFG1_TERM_2K << PADCFG1_TERM_SHIFT;
583 value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT;
591 case PIN_CONFIG_BIAS_PULL_DOWN:
592 value &= ~(PADCFG1_TERM_UP | PADCFG1_TERM_MASK);
596 value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
599 value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
602 if (!(community->features & PINCTRL_FEATURE_1K_PD)) {
606 value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT;
616 writel(value, padcfg1);
618 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
623 static int intel_config_set_debounce(struct intel_pinctrl *pctrl, unsigned pin,
626 void __iomem *padcfg0, *padcfg2;
631 padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2);
635 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
637 raw_spin_lock_irqsave(&pctrl->lock, flags);
639 value0 = readl(padcfg0);
640 value2 = readl(padcfg2);
642 /* Disable glitch filter and debouncer */
643 value0 &= ~PADCFG0_PREGFRXSEL;
644 value2 &= ~(PADCFG2_DEBEN | PADCFG2_DEBOUNCE_MASK);
649 v = order_base_2(debounce * 1000 / DEBOUNCE_PERIOD);
650 if (v < 3 || v > 15) {
654 /* Enable glitch filter and debouncer */
655 value0 |= PADCFG0_PREGFRXSEL;
656 value2 |= v << PADCFG2_DEBOUNCE_SHIFT;
657 value2 |= PADCFG2_DEBEN;
661 writel(value0, padcfg0);
662 writel(value2, padcfg2);
665 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
670 static int intel_config_set(struct pinctrl_dev *pctldev, unsigned pin,
671 unsigned long *configs, unsigned nconfigs)
673 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
676 if (!intel_pad_usable(pctrl, pin))
679 for (i = 0; i < nconfigs; i++) {
680 switch (pinconf_to_config_param(configs[i])) {
681 case PIN_CONFIG_BIAS_DISABLE:
682 case PIN_CONFIG_BIAS_PULL_UP:
683 case PIN_CONFIG_BIAS_PULL_DOWN:
684 ret = intel_config_set_pull(pctrl, pin, configs[i]);
689 case PIN_CONFIG_INPUT_DEBOUNCE:
690 ret = intel_config_set_debounce(pctrl, pin,
691 pinconf_to_config_argument(configs[i]));
704 static const struct pinconf_ops intel_pinconf_ops = {
706 .pin_config_get = intel_config_get,
707 .pin_config_set = intel_config_set,
710 static const struct pinctrl_desc intel_pinctrl_desc = {
711 .pctlops = &intel_pinctrl_ops,
712 .pmxops = &intel_pinmux_ops,
713 .confops = &intel_pinconf_ops,
714 .owner = THIS_MODULE,
717 static int intel_gpio_get(struct gpio_chip *chip, unsigned offset)
719 struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
722 reg = intel_get_padcfg(pctrl, offset, PADCFG0);
726 return !!(readl(reg) & PADCFG0_GPIORXSTATE);
729 static void intel_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
731 struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
734 reg = intel_get_padcfg(pctrl, offset, PADCFG0);
739 raw_spin_lock_irqsave(&pctrl->lock, flags);
740 padcfg0 = readl(reg);
742 padcfg0 |= PADCFG0_GPIOTXSTATE;
744 padcfg0 &= ~PADCFG0_GPIOTXSTATE;
745 writel(padcfg0, reg);
746 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
750 static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
752 return pinctrl_gpio_direction_input(chip->base + offset);
755 static int intel_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
758 intel_gpio_set(chip, offset, value);
759 return pinctrl_gpio_direction_output(chip->base + offset);
762 static const struct gpio_chip intel_gpio_chip = {
763 .owner = THIS_MODULE,
764 .request = gpiochip_generic_request,
765 .free = gpiochip_generic_free,
766 .direction_input = intel_gpio_direction_input,
767 .direction_output = intel_gpio_direction_output,
768 .get = intel_gpio_get,
769 .set = intel_gpio_set,
770 .set_config = gpiochip_generic_config,
773 static void intel_gpio_irq_ack(struct irq_data *d)
775 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
776 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
777 const struct intel_community *community;
778 unsigned pin = irqd_to_hwirq(d);
780 raw_spin_lock(&pctrl->lock);
782 community = intel_get_community(pctrl, pin);
784 unsigned padno = pin_to_padno(community, pin);
785 unsigned gpp_offset = padno % community->gpp_size;
786 unsigned gpp = padno / community->gpp_size;
788 writel(BIT(gpp_offset), community->regs + GPI_IS + gpp * 4);
791 raw_spin_unlock(&pctrl->lock);
794 static void intel_gpio_irq_enable(struct irq_data *d)
796 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
797 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
798 const struct intel_community *community;
799 unsigned pin = irqd_to_hwirq(d);
802 raw_spin_lock_irqsave(&pctrl->lock, flags);
804 community = intel_get_community(pctrl, pin);
806 unsigned padno = pin_to_padno(community, pin);
807 unsigned gpp_size = community->gpp_size;
808 unsigned gpp_offset = padno % gpp_size;
809 unsigned gpp = padno / gpp_size;
812 /* Clear interrupt status first to avoid unexpected interrupt */
813 writel(BIT(gpp_offset), community->regs + GPI_IS + gpp * 4);
815 value = readl(community->regs + community->ie_offset + gpp * 4);
816 value |= BIT(gpp_offset);
817 writel(value, community->regs + community->ie_offset + gpp * 4);
820 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
823 static void intel_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
825 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
826 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
827 const struct intel_community *community;
828 unsigned pin = irqd_to_hwirq(d);
831 raw_spin_lock_irqsave(&pctrl->lock, flags);
833 community = intel_get_community(pctrl, pin);
835 unsigned padno = pin_to_padno(community, pin);
836 unsigned gpp_offset = padno % community->gpp_size;
837 unsigned gpp = padno / community->gpp_size;
841 reg = community->regs + community->ie_offset + gpp * 4;
844 value &= ~BIT(gpp_offset);
846 value |= BIT(gpp_offset);
850 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
853 static void intel_gpio_irq_mask(struct irq_data *d)
855 intel_gpio_irq_mask_unmask(d, true);
858 static void intel_gpio_irq_unmask(struct irq_data *d)
860 intel_gpio_irq_mask_unmask(d, false);
863 static int intel_gpio_irq_type(struct irq_data *d, unsigned type)
865 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
866 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
867 unsigned pin = irqd_to_hwirq(d);
872 reg = intel_get_padcfg(pctrl, pin, PADCFG0);
877 * If the pin is in ACPI mode it is still usable as a GPIO but it
878 * cannot be used as IRQ because GPI_IS status bit will not be
879 * updated by the host controller hardware.
881 if (intel_pad_acpi_mode(pctrl, pin)) {
882 dev_warn(pctrl->dev, "pin %u cannot be used as IRQ\n", pin);
886 raw_spin_lock_irqsave(&pctrl->lock, flags);
890 value &= ~(PADCFG0_RXEVCFG_MASK | PADCFG0_RXINV);
892 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
893 value |= PADCFG0_RXEVCFG_EDGE_BOTH << PADCFG0_RXEVCFG_SHIFT;
894 } else if (type & IRQ_TYPE_EDGE_FALLING) {
895 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT;
896 value |= PADCFG0_RXINV;
897 } else if (type & IRQ_TYPE_EDGE_RISING) {
898 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT;
899 } else if (type & IRQ_TYPE_LEVEL_MASK) {
900 if (type & IRQ_TYPE_LEVEL_LOW)
901 value |= PADCFG0_RXINV;
903 value |= PADCFG0_RXEVCFG_DISABLED << PADCFG0_RXEVCFG_SHIFT;
908 if (type & IRQ_TYPE_EDGE_BOTH)
909 irq_set_handler_locked(d, handle_edge_irq);
910 else if (type & IRQ_TYPE_LEVEL_MASK)
911 irq_set_handler_locked(d, handle_level_irq);
913 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
918 static int intel_gpio_irq_wake(struct irq_data *d, unsigned int on)
920 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
921 struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
922 unsigned pin = irqd_to_hwirq(d);
925 enable_irq_wake(pctrl->irq);
927 disable_irq_wake(pctrl->irq);
929 dev_dbg(pctrl->dev, "%sable wake for pin %u\n", on ? "en" : "dis", pin);
933 static irqreturn_t intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl,
934 const struct intel_community *community)
936 struct gpio_chip *gc = &pctrl->chip;
937 irqreturn_t ret = IRQ_NONE;
940 for (gpp = 0; gpp < community->ngpps; gpp++) {
941 unsigned long pending, enabled, gpp_offset;
943 pending = readl(community->regs + GPI_IS + gpp * 4);
944 enabled = readl(community->regs + community->ie_offset +
947 /* Only interrupts that are enabled */
950 for_each_set_bit(gpp_offset, &pending, community->gpp_size) {
954 * The last group in community can have less pins
957 padno = gpp_offset + gpp * community->gpp_size;
958 if (padno >= community->npins)
961 irq = irq_find_mapping(gc->irqdomain,
962 community->pin_base + padno);
963 generic_handle_irq(irq);
972 static irqreturn_t intel_gpio_irq(int irq, void *data)
974 const struct intel_community *community;
975 struct intel_pinctrl *pctrl = data;
976 irqreturn_t ret = IRQ_NONE;
979 /* Need to check all communities for pending interrupts */
980 for (i = 0; i < pctrl->ncommunities; i++) {
981 community = &pctrl->communities[i];
982 ret |= intel_gpio_community_irq_handler(pctrl, community);
988 static struct irq_chip intel_gpio_irqchip = {
989 .name = "intel-gpio",
990 .irq_enable = intel_gpio_irq_enable,
991 .irq_ack = intel_gpio_irq_ack,
992 .irq_mask = intel_gpio_irq_mask,
993 .irq_unmask = intel_gpio_irq_unmask,
994 .irq_set_type = intel_gpio_irq_type,
995 .irq_set_wake = intel_gpio_irq_wake,
998 static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq)
1002 pctrl->chip = intel_gpio_chip;
1004 pctrl->chip.ngpio = pctrl->soc->npins;
1005 pctrl->chip.label = dev_name(pctrl->dev);
1006 pctrl->chip.parent = pctrl->dev;
1007 pctrl->chip.base = -1;
1010 ret = devm_gpiochip_add_data(pctrl->dev, &pctrl->chip, pctrl);
1012 dev_err(pctrl->dev, "failed to register gpiochip\n");
1016 ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev),
1017 0, 0, pctrl->soc->npins);
1019 dev_err(pctrl->dev, "failed to add GPIO pin range\n");
1024 * We need to request the interrupt here (instead of providing chip
1025 * to the irq directly) because on some platforms several GPIO
1026 * controllers share the same interrupt line.
1028 ret = devm_request_irq(pctrl->dev, irq, intel_gpio_irq,
1029 IRQF_SHARED | IRQF_NO_THREAD,
1030 dev_name(pctrl->dev), pctrl);
1032 dev_err(pctrl->dev, "failed to request interrupt\n");
1036 ret = gpiochip_irqchip_add(&pctrl->chip, &intel_gpio_irqchip, 0,
1037 handle_bad_irq, IRQ_TYPE_NONE);
1039 dev_err(pctrl->dev, "failed to add irqchip\n");
1043 gpiochip_set_chained_irqchip(&pctrl->chip, &intel_gpio_irqchip, irq,
1048 static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl)
1050 #ifdef CONFIG_PM_SLEEP
1051 const struct intel_pinctrl_soc_data *soc = pctrl->soc;
1052 struct intel_community_context *communities;
1053 struct intel_pad_context *pads;
1056 pads = devm_kcalloc(pctrl->dev, soc->npins, sizeof(*pads), GFP_KERNEL);
1060 communities = devm_kcalloc(pctrl->dev, pctrl->ncommunities,
1061 sizeof(*communities), GFP_KERNEL);
1066 for (i = 0; i < pctrl->ncommunities; i++) {
1067 struct intel_community *community = &pctrl->communities[i];
1070 intmask = devm_kcalloc(pctrl->dev, community->ngpps,
1071 sizeof(*intmask), GFP_KERNEL);
1075 communities[i].intmask = intmask;
1078 pctrl->context.pads = pads;
1079 pctrl->context.communities = communities;
1085 int intel_pinctrl_probe(struct platform_device *pdev,
1086 const struct intel_pinctrl_soc_data *soc_data)
1088 struct intel_pinctrl *pctrl;
1094 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
1098 pctrl->dev = &pdev->dev;
1099 pctrl->soc = soc_data;
1100 raw_spin_lock_init(&pctrl->lock);
1103 * Make a copy of the communities which we can use to hold pointers
1106 pctrl->ncommunities = pctrl->soc->ncommunities;
1107 pctrl->communities = devm_kcalloc(&pdev->dev, pctrl->ncommunities,
1108 sizeof(*pctrl->communities), GFP_KERNEL);
1109 if (!pctrl->communities)
1112 for (i = 0; i < pctrl->ncommunities; i++) {
1113 struct intel_community *community = &pctrl->communities[i];
1114 struct resource *res;
1118 *community = pctrl->soc->communities[i];
1120 res = platform_get_resource(pdev, IORESOURCE_MEM,
1122 regs = devm_ioremap_resource(&pdev->dev, res);
1124 return PTR_ERR(regs);
1127 * Determine community features based on the revision if
1128 * not specified already.
1130 if (!community->features) {
1133 rev = (readl(regs + REVID) & REVID_MASK) >> REVID_SHIFT;
1135 community->features |= PINCTRL_FEATURE_DEBOUNCE;
1136 community->features |= PINCTRL_FEATURE_1K_PD;
1140 /* Read offset of the pad configuration registers */
1141 padbar = readl(regs + PADBAR);
1143 community->regs = regs;
1144 community->pad_regs = regs + padbar;
1145 community->ngpps = DIV_ROUND_UP(community->npins,
1146 community->gpp_size);
1149 irq = platform_get_irq(pdev, 0);
1151 dev_err(&pdev->dev, "failed to get interrupt number\n");
1155 ret = intel_pinctrl_pm_init(pctrl);
1159 pctrl->pctldesc = intel_pinctrl_desc;
1160 pctrl->pctldesc.name = dev_name(&pdev->dev);
1161 pctrl->pctldesc.pins = pctrl->soc->pins;
1162 pctrl->pctldesc.npins = pctrl->soc->npins;
1164 pctrl->pctldev = devm_pinctrl_register(&pdev->dev, &pctrl->pctldesc,
1166 if (IS_ERR(pctrl->pctldev)) {
1167 dev_err(&pdev->dev, "failed to register pinctrl driver\n");
1168 return PTR_ERR(pctrl->pctldev);
1171 ret = intel_gpio_probe(pctrl, irq);
1175 platform_set_drvdata(pdev, pctrl);
1179 EXPORT_SYMBOL_GPL(intel_pinctrl_probe);
1181 #ifdef CONFIG_PM_SLEEP
1182 static bool intel_pinctrl_should_save(struct intel_pinctrl *pctrl, unsigned pin)
1184 const struct pin_desc *pd = pin_desc_get(pctrl->pctldev, pin);
1186 if (!pd || !intel_pad_usable(pctrl, pin))
1190 * Only restore the pin if it is actually in use by the kernel (or
1191 * by userspace). It is possible that some pins are used by the
1192 * BIOS during resume and those are not always locked down so leave
1195 if (pd->mux_owner || pd->gpio_owner ||
1196 gpiochip_line_is_irq(&pctrl->chip, pin))
1202 int intel_pinctrl_suspend(struct device *dev)
1204 struct platform_device *pdev = to_platform_device(dev);
1205 struct intel_pinctrl *pctrl = platform_get_drvdata(pdev);
1206 struct intel_community_context *communities;
1207 struct intel_pad_context *pads;
1210 pads = pctrl->context.pads;
1211 for (i = 0; i < pctrl->soc->npins; i++) {
1212 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1213 void __iomem *padcfg;
1216 if (!intel_pinctrl_should_save(pctrl, desc->number))
1219 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG0));
1220 pads[i].padcfg0 = val & ~PADCFG0_GPIORXSTATE;
1221 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG1));
1222 pads[i].padcfg1 = val;
1224 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG2);
1226 pads[i].padcfg2 = readl(padcfg);
1229 communities = pctrl->context.communities;
1230 for (i = 0; i < pctrl->ncommunities; i++) {
1231 struct intel_community *community = &pctrl->communities[i];
1235 base = community->regs + community->ie_offset;
1236 for (gpp = 0; gpp < community->ngpps; gpp++)
1237 communities[i].intmask[gpp] = readl(base + gpp * 4);
1242 EXPORT_SYMBOL_GPL(intel_pinctrl_suspend);
1244 static void intel_gpio_irq_init(struct intel_pinctrl *pctrl)
1248 for (i = 0; i < pctrl->ncommunities; i++) {
1249 const struct intel_community *community;
1253 community = &pctrl->communities[i];
1254 base = community->regs;
1256 for (gpp = 0; gpp < community->ngpps; gpp++) {
1257 /* Mask and clear all interrupts */
1258 writel(0, base + community->ie_offset + gpp * 4);
1259 writel(0xffff, base + GPI_IS + gpp * 4);
1264 int intel_pinctrl_resume(struct device *dev)
1266 struct platform_device *pdev = to_platform_device(dev);
1267 struct intel_pinctrl *pctrl = platform_get_drvdata(pdev);
1268 const struct intel_community_context *communities;
1269 const struct intel_pad_context *pads;
1272 /* Mask all interrupts */
1273 intel_gpio_irq_init(pctrl);
1275 pads = pctrl->context.pads;
1276 for (i = 0; i < pctrl->soc->npins; i++) {
1277 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1278 void __iomem *padcfg;
1281 if (!intel_pinctrl_should_save(pctrl, desc->number))
1284 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG0);
1285 val = readl(padcfg) & ~PADCFG0_GPIORXSTATE;
1286 if (val != pads[i].padcfg0) {
1287 writel(pads[i].padcfg0, padcfg);
1288 dev_dbg(dev, "restored pin %u padcfg0 %#08x\n",
1289 desc->number, readl(padcfg));
1292 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG1);
1293 val = readl(padcfg);
1294 if (val != pads[i].padcfg1) {
1295 writel(pads[i].padcfg1, padcfg);
1296 dev_dbg(dev, "restored pin %u padcfg1 %#08x\n",
1297 desc->number, readl(padcfg));
1300 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG2);
1302 val = readl(padcfg);
1303 if (val != pads[i].padcfg2) {
1304 writel(pads[i].padcfg2, padcfg);
1305 dev_dbg(dev, "restored pin %u padcfg2 %#08x\n",
1306 desc->number, readl(padcfg));
1311 communities = pctrl->context.communities;
1312 for (i = 0; i < pctrl->ncommunities; i++) {
1313 struct intel_community *community = &pctrl->communities[i];
1317 base = community->regs + community->ie_offset;
1318 for (gpp = 0; gpp < community->ngpps; gpp++) {
1319 writel(communities[i].intmask[gpp], base + gpp * 4);
1320 dev_dbg(dev, "restored mask %d/%u %#08x\n", i, gpp,
1321 readl(base + gpp * 4));
1327 EXPORT_SYMBOL_GPL(intel_pinctrl_resume);
1330 MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>");
1331 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
1332 MODULE_DESCRIPTION("Intel pinctrl/GPIO core driver");
1333 MODULE_LICENSE("GPL v2");