2 * mt65xx pinctrl driver based on Allwinner A1X pinctrl driver.
3 * Copyright (c) 2014 MediaTek Inc.
4 * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
17 #include <linux/gpio.h>
18 #include <linux/module.h>
20 #include <linux/of_address.h>
21 #include <linux/of_device.h>
22 #include <linux/of_irq.h>
23 #include <linux/pinctrl/consumer.h>
24 #include <linux/pinctrl/machine.h>
25 #include <linux/pinctrl/pinconf.h>
26 #include <linux/pinctrl/pinconf-generic.h>
27 #include <linux/pinctrl/pinctrl.h>
28 #include <linux/pinctrl/pinmux.h>
29 #include <linux/platform_device.h>
30 #include <linux/slab.h>
31 #include <linux/bitops.h>
32 #include <linux/regmap.h>
33 #include <linux/mfd/syscon.h>
34 #include <linux/delay.h>
35 #include <dt-bindings/pinctrl/mt65xx.h>
38 #include "../pinconf.h"
39 #include "../pinctrl-utils.h"
40 #include "pinctrl-mtk-common.h"
42 #define MAX_GPIO_MODE_PER_REG 5
43 #define GPIO_MODE_BITS 3
45 static const char * const mtk_gpio_functions[] = {
46 "func0", "func1", "func2", "func3",
47 "func4", "func5", "func6", "func7",
51 * There are two base address for pull related configuration
52 * in mt8135, and different GPIO pins use different base address.
53 * When pin number greater than type1_start and less than type1_end,
54 * should use the second base address.
56 static struct regmap *mtk_get_regmap(struct mtk_pinctrl *pctl,
59 if (pin >= pctl->devdata->type1_start && pin < pctl->devdata->type1_end)
64 static unsigned int mtk_get_port(struct mtk_pinctrl *pctl, unsigned long pin)
66 /* Different SoC has different mask and port shift. */
67 return ((pin >> 4) & pctl->devdata->port_mask)
68 << pctl->devdata->port_shf;
71 static int mtk_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
72 struct pinctrl_gpio_range *range, unsigned offset,
75 unsigned int reg_addr;
77 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
79 reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dir_offset;
80 bit = BIT(offset & 0xf);
83 /* Different SoC has different alignment offset. */
84 reg_addr = CLR_ADDR(reg_addr, pctl);
86 reg_addr = SET_ADDR(reg_addr, pctl);
88 regmap_write(mtk_get_regmap(pctl, offset), reg_addr, bit);
92 static void mtk_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
94 unsigned int reg_addr;
96 struct mtk_pinctrl *pctl = dev_get_drvdata(chip->dev);
98 reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dout_offset;
99 bit = BIT(offset & 0xf);
102 reg_addr = SET_ADDR(reg_addr, pctl);
104 reg_addr = CLR_ADDR(reg_addr, pctl);
106 regmap_write(mtk_get_regmap(pctl, offset), reg_addr, bit);
109 static void mtk_pconf_set_ies_smt(struct mtk_pinctrl *pctl, unsigned pin,
110 int value, enum pin_config_param param)
112 unsigned int reg_addr, offset;
115 bit = BIT(pin & 0xf);
117 if (param == PIN_CONFIG_INPUT_ENABLE)
118 offset = pctl->devdata->ies_offset;
120 offset = pctl->devdata->smt_offset;
123 reg_addr = SET_ADDR(mtk_get_port(pctl, pin) + offset, pctl);
125 reg_addr = CLR_ADDR(mtk_get_port(pctl, pin) + offset, pctl);
127 regmap_write(mtk_get_regmap(pctl, pin), reg_addr, bit);
130 static const struct mtk_pin_drv_grp *mtk_find_pin_drv_grp_by_pin(
131 struct mtk_pinctrl *pctl, unsigned long pin) {
134 for (i = 0; i < pctl->devdata->n_pin_drv_grps; i++) {
135 const struct mtk_pin_drv_grp *pin_drv =
136 pctl->devdata->pin_drv_grp + i;
137 if (pin == pin_drv->pin)
144 static int mtk_pconf_set_driving(struct mtk_pinctrl *pctl,
145 unsigned int pin, unsigned char driving)
147 const struct mtk_pin_drv_grp *pin_drv;
149 unsigned int bits, mask, shift;
150 const struct mtk_drv_group_desc *drv_grp;
152 if (pin >= pctl->devdata->npins)
155 pin_drv = mtk_find_pin_drv_grp_by_pin(pctl, pin);
156 if (!pin_drv || pin_drv->grp > pctl->devdata->n_grp_cls)
159 drv_grp = pctl->devdata->grp_desc + pin_drv->grp;
160 if (driving >= drv_grp->min_drv && driving <= drv_grp->max_drv
161 && !(driving % drv_grp->step)) {
162 val = driving / drv_grp->step - 1;
163 bits = drv_grp->high_bit - drv_grp->low_bit + 1;
164 mask = BIT(bits) - 1;
165 shift = pin_drv->bit + drv_grp->low_bit;
168 return regmap_update_bits(mtk_get_regmap(pctl, pin),
169 pin_drv->offset, mask, val);
175 static int mtk_pconf_set_pull_select(struct mtk_pinctrl *pctl,
176 unsigned int pin, bool enable, bool isup, unsigned int arg)
179 unsigned int reg_pullen, reg_pullsel;
182 /* Some pins' pull setting are very different,
183 * they have separate pull up/down bit, R0 and R1
184 * resistor bit, so we need this special handle.
186 if (pctl->devdata->spec_pull_set) {
187 ret = pctl->devdata->spec_pull_set(mtk_get_regmap(pctl, pin),
188 pin, pctl->devdata->port_align, isup, arg);
193 /* For generic pull config, default arg value should be 0 or 1. */
194 if (arg != 0 && arg != 1) {
195 dev_err(pctl->dev, "invalid pull-up argument %d on pin %d .\n",
200 bit = BIT(pin & 0xf);
202 reg_pullen = SET_ADDR(mtk_get_port(pctl, pin) +
203 pctl->devdata->pullen_offset, pctl);
205 reg_pullen = CLR_ADDR(mtk_get_port(pctl, pin) +
206 pctl->devdata->pullen_offset, pctl);
209 reg_pullsel = SET_ADDR(mtk_get_port(pctl, pin) +
210 pctl->devdata->pullsel_offset, pctl);
212 reg_pullsel = CLR_ADDR(mtk_get_port(pctl, pin) +
213 pctl->devdata->pullsel_offset, pctl);
215 regmap_write(mtk_get_regmap(pctl, pin), reg_pullen, bit);
216 regmap_write(mtk_get_regmap(pctl, pin), reg_pullsel, bit);
220 static int mtk_pconf_parse_conf(struct pinctrl_dev *pctldev,
221 unsigned int pin, enum pin_config_param param,
222 enum pin_config_param arg)
224 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
227 case PIN_CONFIG_BIAS_DISABLE:
228 mtk_pconf_set_pull_select(pctl, pin, false, false, arg);
230 case PIN_CONFIG_BIAS_PULL_UP:
231 mtk_pconf_set_pull_select(pctl, pin, true, true, arg);
233 case PIN_CONFIG_BIAS_PULL_DOWN:
234 mtk_pconf_set_pull_select(pctl, pin, true, false, arg);
236 case PIN_CONFIG_INPUT_ENABLE:
237 mtk_pconf_set_ies_smt(pctl, pin, arg, param);
239 case PIN_CONFIG_OUTPUT:
240 mtk_gpio_set(pctl->chip, pin, arg);
241 mtk_pmx_gpio_set_direction(pctldev, NULL, pin, false);
243 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
244 mtk_pconf_set_ies_smt(pctl, pin, arg, param);
246 case PIN_CONFIG_DRIVE_STRENGTH:
247 mtk_pconf_set_driving(pctl, pin, arg);
256 static int mtk_pconf_group_get(struct pinctrl_dev *pctldev,
258 unsigned long *config)
260 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
262 *config = pctl->groups[group].config;
267 static int mtk_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
268 unsigned long *configs, unsigned num_configs)
270 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
271 struct mtk_pinctrl_group *g = &pctl->groups[group];
274 for (i = 0; i < num_configs; i++) {
275 mtk_pconf_parse_conf(pctldev, g->pin,
276 pinconf_to_config_param(configs[i]),
277 pinconf_to_config_argument(configs[i]));
279 g->config = configs[i];
285 static const struct pinconf_ops mtk_pconf_ops = {
286 .pin_config_group_get = mtk_pconf_group_get,
287 .pin_config_group_set = mtk_pconf_group_set,
290 static struct mtk_pinctrl_group *
291 mtk_pctrl_find_group_by_pin(struct mtk_pinctrl *pctl, u32 pin)
295 for (i = 0; i < pctl->ngroups; i++) {
296 struct mtk_pinctrl_group *grp = pctl->groups + i;
305 static const struct mtk_desc_function *mtk_pctrl_find_function_by_pin(
306 struct mtk_pinctrl *pctl, u32 pin_num, u32 fnum)
308 const struct mtk_desc_pin *pin = pctl->devdata->pins + pin_num;
309 const struct mtk_desc_function *func = pin->functions;
311 while (func && func->name) {
312 if (func->muxval == fnum)
320 static bool mtk_pctrl_is_function_valid(struct mtk_pinctrl *pctl,
321 u32 pin_num, u32 fnum)
325 for (i = 0; i < pctl->devdata->npins; i++) {
326 const struct mtk_desc_pin *pin = pctl->devdata->pins + i;
328 if (pin->pin.number == pin_num) {
329 const struct mtk_desc_function *func =
332 while (func && func->name) {
333 if (func->muxval == fnum)
345 static int mtk_pctrl_dt_node_to_map_func(struct mtk_pinctrl *pctl,
346 u32 pin, u32 fnum, struct mtk_pinctrl_group *grp,
347 struct pinctrl_map **map, unsigned *reserved_maps,
352 if (*num_maps == *reserved_maps)
355 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
356 (*map)[*num_maps].data.mux.group = grp->name;
358 ret = mtk_pctrl_is_function_valid(pctl, pin, fnum);
360 dev_err(pctl->dev, "invalid function %d on pin %d .\n",
365 (*map)[*num_maps].data.mux.function = mtk_gpio_functions[fnum];
371 static int mtk_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
372 struct device_node *node,
373 struct pinctrl_map **map,
374 unsigned *reserved_maps,
377 struct property *pins;
378 u32 pinfunc, pin, func;
379 int num_pins, num_funcs, maps_per_pin;
380 unsigned long *configs;
381 unsigned int num_configs;
384 unsigned reserve = 0;
385 struct mtk_pinctrl_group *grp;
386 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
388 pins = of_find_property(node, "pinmux", NULL);
390 dev_err(pctl->dev, "missing pins property in node %s .\n",
395 err = pinconf_generic_parse_dt_config(node, &configs, &num_configs);
399 num_pins = pins->length / sizeof(u32);
400 num_funcs = num_pins;
404 if (has_config && num_pins >= 1)
407 if (!num_pins || !maps_per_pin)
410 reserve = num_pins * maps_per_pin;
412 err = pinctrl_utils_reserve_map(pctldev, map,
413 reserved_maps, num_maps, reserve);
417 for (i = 0; i < num_pins; i++) {
418 err = of_property_read_u32_index(node, "pinmux",
423 pin = MTK_GET_PIN_NO(pinfunc);
424 func = MTK_GET_PIN_FUNC(pinfunc);
426 if (pin >= pctl->devdata->npins ||
427 func >= ARRAY_SIZE(mtk_gpio_functions)) {
428 dev_err(pctl->dev, "invalid pins value.\n");
433 grp = mtk_pctrl_find_group_by_pin(pctl, pin);
435 dev_err(pctl->dev, "unable to match pin %d to group\n",
440 err = mtk_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map,
441 reserved_maps, num_maps);
446 err = pinctrl_utils_add_map_configs(pctldev, map,
447 reserved_maps, num_maps, grp->name,
448 configs, num_configs,
449 PIN_MAP_TYPE_CONFIGS_GROUP);
461 static int mtk_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
462 struct device_node *np_config,
463 struct pinctrl_map **map, unsigned *num_maps)
465 struct device_node *np;
466 unsigned reserved_maps;
473 for_each_child_of_node(np_config, np) {
474 ret = mtk_pctrl_dt_subnode_to_map(pctldev, np, map,
475 &reserved_maps, num_maps);
477 pinctrl_utils_dt_free_map(pctldev, *map, *num_maps);
485 static int mtk_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
487 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
489 return pctl->ngroups;
492 static const char *mtk_pctrl_get_group_name(struct pinctrl_dev *pctldev,
495 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
497 return pctl->groups[group].name;
500 static int mtk_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
502 const unsigned **pins,
505 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
507 *pins = (unsigned *)&pctl->groups[group].pin;
513 static const struct pinctrl_ops mtk_pctrl_ops = {
514 .dt_node_to_map = mtk_pctrl_dt_node_to_map,
515 .dt_free_map = pinctrl_utils_dt_free_map,
516 .get_groups_count = mtk_pctrl_get_groups_count,
517 .get_group_name = mtk_pctrl_get_group_name,
518 .get_group_pins = mtk_pctrl_get_group_pins,
521 static int mtk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
523 return ARRAY_SIZE(mtk_gpio_functions);
526 static const char *mtk_pmx_get_func_name(struct pinctrl_dev *pctldev,
529 return mtk_gpio_functions[selector];
532 static int mtk_pmx_get_func_groups(struct pinctrl_dev *pctldev,
534 const char * const **groups,
535 unsigned * const num_groups)
537 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
539 *groups = pctl->grp_names;
540 *num_groups = pctl->ngroups;
545 static int mtk_pmx_set_mode(struct pinctrl_dev *pctldev,
546 unsigned long pin, unsigned long mode)
548 unsigned int reg_addr;
551 unsigned int mask = (1L << GPIO_MODE_BITS) - 1;
552 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
554 reg_addr = ((pin / MAX_GPIO_MODE_PER_REG) << pctl->devdata->port_shf)
555 + pctl->devdata->pinmux_offset;
557 bit = pin % MAX_GPIO_MODE_PER_REG;
558 mask <<= (GPIO_MODE_BITS * bit);
559 val = (mode << (GPIO_MODE_BITS * bit));
560 return regmap_update_bits(mtk_get_regmap(pctl, pin),
561 reg_addr, mask, val);
564 static const struct mtk_desc_pin *
565 mtk_find_pin_by_eint_num(struct mtk_pinctrl *pctl, unsigned int eint_num)
568 const struct mtk_desc_pin *pin;
570 for (i = 0; i < pctl->devdata->npins; i++) {
571 pin = pctl->devdata->pins + i;
572 if (pin->eint.eintnum == eint_num)
579 static int mtk_pmx_set_mux(struct pinctrl_dev *pctldev,
584 const struct mtk_desc_function *desc;
585 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
586 struct mtk_pinctrl_group *g = pctl->groups + group;
588 ret = mtk_pctrl_is_function_valid(pctl, g->pin, function);
590 dev_err(pctl->dev, "invaild function %d on group %d .\n",
595 desc = mtk_pctrl_find_function_by_pin(pctl, g->pin, function);
598 mtk_pmx_set_mode(pctldev, g->pin, desc->muxval);
602 static const struct pinmux_ops mtk_pmx_ops = {
603 .get_functions_count = mtk_pmx_get_funcs_cnt,
604 .get_function_name = mtk_pmx_get_func_name,
605 .get_function_groups = mtk_pmx_get_func_groups,
606 .set_mux = mtk_pmx_set_mux,
607 .gpio_set_direction = mtk_pmx_gpio_set_direction,
610 static int mtk_gpio_request(struct gpio_chip *chip, unsigned offset)
612 return pinctrl_request_gpio(chip->base + offset);
615 static void mtk_gpio_free(struct gpio_chip *chip, unsigned offset)
617 pinctrl_free_gpio(chip->base + offset);
620 static int mtk_gpio_direction_input(struct gpio_chip *chip,
623 return pinctrl_gpio_direction_input(chip->base + offset);
626 static int mtk_gpio_direction_output(struct gpio_chip *chip,
627 unsigned offset, int value)
629 mtk_gpio_set(chip, offset, value);
630 return pinctrl_gpio_direction_output(chip->base + offset);
633 static int mtk_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
635 unsigned int reg_addr;
637 unsigned int read_val = 0;
639 struct mtk_pinctrl *pctl = dev_get_drvdata(chip->dev);
641 reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dir_offset;
642 bit = BIT(offset & 0xf);
643 regmap_read(pctl->regmap1, reg_addr, &read_val);
644 return !!(read_val & bit);
647 static int mtk_gpio_get(struct gpio_chip *chip, unsigned offset)
649 unsigned int reg_addr;
651 unsigned int read_val = 0;
652 struct mtk_pinctrl *pctl = dev_get_drvdata(chip->dev);
654 if (mtk_gpio_get_direction(chip, offset))
655 reg_addr = mtk_get_port(pctl, offset) +
656 pctl->devdata->dout_offset;
658 reg_addr = mtk_get_port(pctl, offset) +
659 pctl->devdata->din_offset;
661 bit = BIT(offset & 0xf);
662 regmap_read(pctl->regmap1, reg_addr, &read_val);
663 return !!(read_val & bit);
666 static int mtk_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
668 const struct mtk_desc_pin *pin;
669 struct mtk_pinctrl *pctl = dev_get_drvdata(chip->dev);
672 pin = pctl->devdata->pins + offset;
673 if (pin->eint.eintnum == NO_EINT_SUPPORT)
676 irq = irq_find_mapping(pctl->domain, pin->eint.eintnum);
683 static int mtk_pinctrl_irq_request_resources(struct irq_data *d)
685 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
686 const struct mtk_desc_pin *pin;
689 pin = mtk_find_pin_by_eint_num(pctl, d->hwirq);
692 dev_err(pctl->dev, "Can not find pin\n");
696 ret = gpiochip_lock_as_irq(pctl->chip, pin->pin.number);
698 dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n",
703 /* set mux to INT mode */
704 mtk_pmx_set_mode(pctl->pctl_dev, pin->pin.number, pin->eint.eintmux);
709 static void mtk_pinctrl_irq_release_resources(struct irq_data *d)
711 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
712 const struct mtk_desc_pin *pin;
714 pin = mtk_find_pin_by_eint_num(pctl, d->hwirq);
717 dev_err(pctl->dev, "Can not find pin\n");
721 gpiochip_unlock_as_irq(pctl->chip, pin->pin.number);
724 static void __iomem *mtk_eint_get_offset(struct mtk_pinctrl *pctl,
725 unsigned int eint_num, unsigned int offset)
727 unsigned int eint_base = 0;
730 if (eint_num >= pctl->devdata->ap_num)
731 eint_base = pctl->devdata->ap_num;
733 reg = pctl->eint_reg_base + offset + ((eint_num - eint_base) / 32) * 4;
739 * mtk_can_en_debounce: Check the EINT number is able to enable debounce or not
740 * @eint_num: the EINT number to setmtk_pinctrl
742 static unsigned int mtk_eint_can_en_debounce(struct mtk_pinctrl *pctl,
743 unsigned int eint_num)
746 unsigned int bit = BIT(eint_num % 32);
747 const struct mtk_eint_offsets *eint_offsets =
748 &pctl->devdata->eint_offsets;
750 void __iomem *reg = mtk_eint_get_offset(pctl, eint_num,
753 if (readl(reg) & bit)
754 sens = MT_LEVEL_SENSITIVE;
756 sens = MT_EDGE_SENSITIVE;
758 if ((eint_num < pctl->devdata->db_cnt) && (sens != MT_EDGE_SENSITIVE))
765 * mtk_eint_get_mask: To get the eint mask
766 * @eint_num: the EINT number to get
768 static unsigned int mtk_eint_get_mask(struct mtk_pinctrl *pctl,
769 unsigned int eint_num)
771 unsigned int bit = BIT(eint_num % 32);
772 const struct mtk_eint_offsets *eint_offsets =
773 &pctl->devdata->eint_offsets;
775 void __iomem *reg = mtk_eint_get_offset(pctl, eint_num,
778 return !!(readl(reg) & bit);
781 static void mtk_eint_mask(struct irq_data *d)
783 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
784 const struct mtk_eint_offsets *eint_offsets =
785 &pctl->devdata->eint_offsets;
786 u32 mask = BIT(d->hwirq & 0x1f);
787 void __iomem *reg = mtk_eint_get_offset(pctl, d->hwirq,
788 eint_offsets->mask_set);
793 static void mtk_eint_unmask(struct irq_data *d)
795 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
796 const struct mtk_eint_offsets *eint_offsets =
797 &pctl->devdata->eint_offsets;
798 u32 mask = BIT(d->hwirq & 0x1f);
799 void __iomem *reg = mtk_eint_get_offset(pctl, d->hwirq,
800 eint_offsets->mask_clr);
805 static int mtk_gpio_set_debounce(struct gpio_chip *chip, unsigned offset,
808 struct mtk_pinctrl *pctl = dev_get_drvdata(chip->dev);
809 int eint_num, virq, eint_offset;
810 unsigned int set_offset, bit, clr_bit, clr_offset, rst, i, unmask, dbnc;
811 static const unsigned int dbnc_arr[] = {0 , 1, 16, 32, 64, 128, 256};
812 const struct mtk_desc_pin *pin;
815 pin = pctl->devdata->pins + offset;
816 if (pin->eint.eintnum == NO_EINT_SUPPORT)
819 eint_num = pin->eint.eintnum;
820 virq = irq_find_mapping(pctl->domain, eint_num);
821 eint_offset = (eint_num % 4) * 8;
822 d = irq_get_irq_data(virq);
824 set_offset = (eint_num / 4) * 4 + pctl->devdata->eint_offsets.dbnc_set;
825 clr_offset = (eint_num / 4) * 4 + pctl->devdata->eint_offsets.dbnc_clr;
826 if (!mtk_eint_can_en_debounce(pctl, eint_num))
829 dbnc = ARRAY_SIZE(dbnc_arr);
830 for (i = 0; i < ARRAY_SIZE(dbnc_arr); i++) {
831 if (debounce <= dbnc_arr[i]) {
837 if (!mtk_eint_get_mask(pctl, eint_num)) {
842 clr_bit = 0xff << eint_offset;
843 writel(clr_bit, pctl->eint_reg_base + clr_offset);
845 bit = ((dbnc << EINT_DBNC_SET_DBNC_BITS) | EINT_DBNC_SET_EN) <<
847 rst = EINT_DBNC_RST_BIT << eint_offset;
848 writel(rst | bit, pctl->eint_reg_base + set_offset);
850 /* Delay a while (more than 2T) to wait for hw debounce counter reset
859 static struct gpio_chip mtk_gpio_chip = {
860 .owner = THIS_MODULE,
861 .request = mtk_gpio_request,
862 .free = mtk_gpio_free,
863 .direction_input = mtk_gpio_direction_input,
864 .direction_output = mtk_gpio_direction_output,
867 .to_irq = mtk_gpio_to_irq,
868 .set_debounce = mtk_gpio_set_debounce,
869 .of_gpio_n_cells = 2,
872 static int mtk_eint_set_type(struct irq_data *d,
875 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
876 const struct mtk_eint_offsets *eint_offsets =
877 &pctl->devdata->eint_offsets;
878 u32 mask = BIT(d->hwirq & 0x1f);
881 if (((type & IRQ_TYPE_EDGE_BOTH) && (type & IRQ_TYPE_LEVEL_MASK)) ||
882 ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) ||
883 ((type & IRQ_TYPE_LEVEL_MASK) == IRQ_TYPE_LEVEL_MASK)) {
884 dev_err(pctl->dev, "Can't configure IRQ%d (EINT%lu) for type 0x%X\n",
885 d->irq, d->hwirq, type);
889 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING)) {
890 reg = mtk_eint_get_offset(pctl, d->hwirq,
891 eint_offsets->pol_clr);
894 reg = mtk_eint_get_offset(pctl, d->hwirq,
895 eint_offsets->pol_set);
899 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
900 reg = mtk_eint_get_offset(pctl, d->hwirq,
901 eint_offsets->sens_clr);
904 reg = mtk_eint_get_offset(pctl, d->hwirq,
905 eint_offsets->sens_set);
912 static void mtk_eint_ack(struct irq_data *d)
914 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
915 const struct mtk_eint_offsets *eint_offsets =
916 &pctl->devdata->eint_offsets;
917 u32 mask = BIT(d->hwirq & 0x1f);
918 void __iomem *reg = mtk_eint_get_offset(pctl, d->hwirq,
924 static struct irq_chip mtk_pinctrl_irq_chip = {
926 .irq_mask = mtk_eint_mask,
927 .irq_unmask = mtk_eint_unmask,
928 .irq_ack = mtk_eint_ack,
929 .irq_set_type = mtk_eint_set_type,
930 .irq_request_resources = mtk_pinctrl_irq_request_resources,
931 .irq_release_resources = mtk_pinctrl_irq_release_resources,
934 static unsigned int mtk_eint_init(struct mtk_pinctrl *pctl)
936 const struct mtk_eint_offsets *eint_offsets =
937 &pctl->devdata->eint_offsets;
938 void __iomem *reg = pctl->eint_reg_base + eint_offsets->dom_en;
941 for (i = 0; i < pctl->devdata->ap_num; i += 32) {
942 writel(0xffffffff, reg);
949 mtk_eint_debounce_process(struct mtk_pinctrl *pctl, int index)
951 unsigned int rst, ctrl_offset;
952 unsigned int bit, dbnc;
953 const struct mtk_eint_offsets *eint_offsets =
954 &pctl->devdata->eint_offsets;
956 ctrl_offset = (index / 4) * 4 + eint_offsets->dbnc_ctrl;
957 dbnc = readl(pctl->eint_reg_base + ctrl_offset);
958 bit = EINT_DBNC_SET_EN << ((index % 4) * 8);
959 if ((bit & dbnc) > 0) {
960 ctrl_offset = (index / 4) * 4 + eint_offsets->dbnc_set;
961 rst = EINT_DBNC_RST_BIT << ((index % 4) * 8);
962 writel(rst, pctl->eint_reg_base + ctrl_offset);
966 static void mtk_eint_irq_handler(unsigned irq, struct irq_desc *desc)
968 struct irq_chip *chip = irq_get_chip(irq);
969 struct mtk_pinctrl *pctl = irq_get_handler_data(irq);
970 unsigned int status, eint_num;
971 int offset, index, virq;
972 const struct mtk_eint_offsets *eint_offsets =
973 &pctl->devdata->eint_offsets;
974 void __iomem *reg = mtk_eint_get_offset(pctl, 0, eint_offsets->stat);
976 chained_irq_enter(chip, desc);
977 for (eint_num = 0; eint_num < pctl->devdata->ap_num; eint_num += 32) {
981 offset = __ffs(status);
982 index = eint_num + offset;
983 virq = irq_find_mapping(pctl->domain, index);
984 status &= ~BIT(offset);
986 generic_handle_irq(virq);
988 if (index < pctl->devdata->db_cnt)
989 mtk_eint_debounce_process(pctl , index);
992 chained_irq_exit(chip, desc);
995 static int mtk_pctrl_build_state(struct platform_device *pdev)
997 struct mtk_pinctrl *pctl = platform_get_drvdata(pdev);
1000 pctl->ngroups = pctl->devdata->npins;
1002 /* Allocate groups */
1003 pctl->groups = devm_kzalloc(&pdev->dev,
1004 pctl->ngroups * sizeof(*pctl->groups),
1009 /* We assume that one pin is one group, use pin name as group name. */
1010 pctl->grp_names = devm_kzalloc(&pdev->dev,
1011 pctl->ngroups * sizeof(*pctl->grp_names),
1013 if (!pctl->grp_names)
1016 for (i = 0; i < pctl->devdata->npins; i++) {
1017 const struct mtk_desc_pin *pin = pctl->devdata->pins + i;
1018 struct mtk_pinctrl_group *group = pctl->groups + i;
1020 group->name = pin->pin.name;
1021 group->pin = pin->pin.number;
1023 pctl->grp_names[i] = pin->pin.name;
1029 static struct pinctrl_desc mtk_pctrl_desc = {
1030 .confops = &mtk_pconf_ops,
1031 .pctlops = &mtk_pctrl_ops,
1032 .pmxops = &mtk_pmx_ops,
1035 int mtk_pctrl_init(struct platform_device *pdev,
1036 const struct mtk_pinctrl_devdata *data)
1038 struct pinctrl_pin_desc *pins;
1039 struct mtk_pinctrl *pctl;
1040 struct device_node *np = pdev->dev.of_node, *node;
1041 struct property *prop;
1042 struct resource *res;
1045 pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
1049 platform_set_drvdata(pdev, pctl);
1051 prop = of_find_property(np, "pins-are-numbered", NULL);
1053 dev_err(&pdev->dev, "only support pins-are-numbered format\n", ret);
1057 node = of_parse_phandle(np, "mediatek,pctl-regmap", 0);
1059 pctl->regmap1 = syscon_node_to_regmap(node);
1060 if (IS_ERR(pctl->regmap1))
1061 return PTR_ERR(pctl->regmap1);
1064 /* Only 8135 has two base addr, other SoCs have only one. */
1065 node = of_parse_phandle(np, "mediatek,pctl-regmap", 1);
1067 pctl->regmap2 = syscon_node_to_regmap(node);
1068 if (IS_ERR(pctl->regmap2))
1069 return PTR_ERR(pctl->regmap2);
1072 pctl->devdata = data;
1073 ret = mtk_pctrl_build_state(pdev);
1075 dev_err(&pdev->dev, "build state failed: %d\n", ret);
1079 pins = devm_kzalloc(&pdev->dev,
1080 pctl->devdata->npins * sizeof(*pins),
1085 for (i = 0; i < pctl->devdata->npins; i++)
1086 pins[i] = pctl->devdata->pins[i].pin;
1087 mtk_pctrl_desc.name = dev_name(&pdev->dev);
1088 mtk_pctrl_desc.owner = THIS_MODULE;
1089 mtk_pctrl_desc.pins = pins;
1090 mtk_pctrl_desc.npins = pctl->devdata->npins;
1091 pctl->dev = &pdev->dev;
1092 pctl->pctl_dev = pinctrl_register(&mtk_pctrl_desc, &pdev->dev, pctl);
1093 if (!pctl->pctl_dev) {
1094 dev_err(&pdev->dev, "couldn't register pinctrl driver\n");
1098 pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL);
1104 pctl->chip = &mtk_gpio_chip;
1105 pctl->chip->ngpio = pctl->devdata->npins;
1106 pctl->chip->label = dev_name(&pdev->dev);
1107 pctl->chip->dev = &pdev->dev;
1108 pctl->chip->base = 0;
1110 ret = gpiochip_add(pctl->chip);
1116 /* Register the GPIO to pin mappings. */
1117 ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev),
1118 0, 0, pctl->devdata->npins);
1124 /* Get EINT register base from dts. */
1125 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1127 dev_err(&pdev->dev, "Unable to get Pinctrl resource\n");
1132 pctl->eint_reg_base = devm_ioremap_resource(&pdev->dev, res);
1133 if (IS_ERR(pctl->eint_reg_base)) {
1138 irq = irq_of_parse_and_map(np, 0);
1140 dev_err(&pdev->dev, "couldn't parse and map irq\n");
1145 pctl->domain = irq_domain_add_linear(np,
1146 pctl->devdata->ap_num, &irq_domain_simple_ops, NULL);
1147 if (!pctl->domain) {
1148 dev_err(&pdev->dev, "Couldn't register IRQ domain\n");
1153 mtk_eint_init(pctl);
1154 for (i = 0; i < pctl->devdata->ap_num; i++) {
1155 int virq = irq_create_mapping(pctl->domain, i);
1157 irq_set_chip_and_handler(virq, &mtk_pinctrl_irq_chip,
1159 irq_set_chip_data(virq, pctl);
1160 set_irq_flags(virq, IRQF_VALID);
1163 irq_set_chained_handler(irq, mtk_eint_irq_handler);
1164 irq_set_handler_data(irq, pctl);
1165 set_irq_flags(irq, IRQF_VALID);
1169 gpiochip_remove(pctl->chip);
1171 pinctrl_unregister(pctl->pctl_dev);
1175 MODULE_LICENSE("GPL");
1176 MODULE_DESCRIPTION("MediaTek Pinctrl Driver");
1177 MODULE_AUTHOR("Hongzhou Yang <hongzhou.yang@mediatek.com>");