2 * Marvell MVEBU pinctrl driver
4 * Authors: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
5 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
13 #ifndef __PINCTRL_MVEBU_H__
14 #define __PINCTRL_MVEBU_H__
17 * struct mvebu_mpp_ctrl_data - private data for the mpp ctrl operations
18 * @base: base address of pinctrl hardware
20 struct mvebu_mpp_ctrl_data {
25 * struct mvebu_mpp_ctrl - describe a mpp control
26 * @name: name of the control group
27 * @pid: first pin id handled by this control
28 * @npins: number of pins controlled by this control
29 * @mpp_get: (optional) special function to get mpp setting
30 * @mpp_set: (optional) special function to set mpp setting
31 * @mpp_gpio_req: (optional) special function to request gpio
32 * @mpp_gpio_dir: (optional) special function to set gpio direction
34 * A mpp_ctrl describes a muxable unit, e.g. pin, group of pins, or
35 * internal function, inside the SoC. Each muxable unit can be switched
36 * between two or more different settings, e.g. assign mpp pin 13 to
39 * The mpp_get/_set functions are mandatory and are used to get/set a
40 * specific mode. The optional mpp_gpio_req/_dir functions can be used
41 * to allow pin settings with varying gpio pins.
43 struct mvebu_mpp_ctrl {
48 int (*mpp_get)(struct mvebu_mpp_ctrl_data *data, unsigned pid,
49 unsigned long *config);
50 int (*mpp_set)(struct mvebu_mpp_ctrl_data *data, unsigned pid,
51 unsigned long config);
52 int (*mpp_gpio_req)(struct mvebu_mpp_ctrl_data *data, unsigned pid);
53 int (*mpp_gpio_dir)(struct mvebu_mpp_ctrl_data *data, unsigned pid,
58 * struct mvebu_mpp_ctrl_setting - describe a mpp ctrl setting
59 * @val: ctrl setting value
60 * @name: ctrl setting name, e.g. uart2, spi0 - unique per mpp_mode
61 * @subname: (optional) additional ctrl setting name, e.g. rts, cts
62 * @variant: (optional) variant identifier mask
63 * @flags: (private) flags to store gpi/gpo/gpio capabilities
65 * A ctrl_setting describes a specific internal mux function that a mpp pin
66 * can be switched to. The value (val) will be written in the corresponding
67 * register for common mpp pin configuration registers on MVEBU. SoC specific
68 * mpp_get/_set function may use val to distinguish between different settings.
70 * The name will be used to switch to this setting in DT description, e.g.
71 * marvell,function = "uart2". subname is only for debugging purposes.
73 * If name is one of "gpi", "gpo", "gpio" gpio capabilities are
74 * parsed during initialization and stored in flags.
76 * The variant can be used to combine different revisions of one SoC to a
77 * common pinctrl driver. It is matched (AND) with variant of soc_info to
78 * determine if a setting is available on the current SoC revision.
80 struct mvebu_mpp_ctrl_setting {
86 #define MVEBU_SETTING_GPO (1 << 0)
87 #define MVEBU_SETTING_GPI (1 << 1)
91 * struct mvebu_mpp_mode - link ctrl and settings
92 * @pid: first pin id handled by this mode
93 * @settings: list of settings available for this mode
95 * A mode connects all available settings with the corresponding mpp_ctrl
98 struct mvebu_mpp_mode {
100 struct mvebu_mpp_ctrl_setting *settings;
104 * struct mvebu_pinctrl_soc_info - SoC specific info passed to pinctrl-mvebu
105 * @variant: variant mask of soc_info
106 * @controls: list of available mvebu_mpp_ctrls
107 * @control_data: optional array, one entry for each control
108 * @ncontrols: number of available mvebu_mpp_ctrls
109 * @modes: list of available mvebu_mpp_modes
110 * @nmodes: number of available mvebu_mpp_modes
111 * @gpioranges: list of pinctrl_gpio_ranges
112 * @ngpioranges: number of available pinctrl_gpio_ranges
114 * This struct describes all pinctrl related information for a specific SoC.
115 * If variant is unequal 0 it will be matched (AND) with variant of each
116 * setting and allows to distinguish between different revisions of one SoC.
118 struct mvebu_pinctrl_soc_info {
120 const struct mvebu_mpp_ctrl *controls;
121 struct mvebu_mpp_ctrl_data *control_data;
123 struct mvebu_mpp_mode *modes;
125 struct pinctrl_gpio_range *gpioranges;
129 #define MPP_FUNC_CTRL(_idl, _idh, _name, _func) \
133 .npins = _idh - _idl + 1, \
134 .pins = (unsigned[_idh - _idl + 1]) { }, \
135 .mpp_get = _func ## _get, \
136 .mpp_set = _func ## _set, \
137 .mpp_gpio_req = NULL, \
138 .mpp_gpio_dir = NULL, \
141 #define MPP_FUNC_GPIO_CTRL(_idl, _idh, _name, _func) \
145 .npins = _idh - _idl + 1, \
146 .pins = (unsigned[_idh - _idl + 1]) { }, \
147 .mpp_get = _func ## _get, \
148 .mpp_set = _func ## _set, \
149 .mpp_gpio_req = _func ## _gpio_req, \
150 .mpp_gpio_dir = _func ## _gpio_dir, \
153 #define _MPP_VAR_FUNCTION(_val, _name, _subname, _mask) \
157 .subname = _subname, \
162 #if defined(CONFIG_DEBUG_FS)
163 #define MPP_VAR_FUNCTION(_val, _name, _subname, _mask) \
164 _MPP_VAR_FUNCTION(_val, _name, _subname, _mask)
166 #define MPP_VAR_FUNCTION(_val, _name, _subname, _mask) \
167 _MPP_VAR_FUNCTION(_val, _name, NULL, _mask)
170 #define MPP_FUNCTION(_val, _name, _subname) \
171 MPP_VAR_FUNCTION(_val, _name, _subname, (u8)-1)
173 #define MPP_MODE(_id, ...) \
176 .settings = (struct mvebu_mpp_ctrl_setting[]){ \
177 __VA_ARGS__, { } }, \
180 #define MPP_GPIO_RANGE(_id, _pinbase, _gpiobase, _npins) \
182 .name = "mvebu-gpio", \
184 .pin_base = _pinbase, \
189 #define MVEBU_MPPS_PER_REG 8
190 #define MVEBU_MPP_BITS 4
191 #define MVEBU_MPP_MASK 0xf
193 static inline int default_mpp_ctrl_get(void __iomem *base, unsigned int pid,
194 unsigned long *config)
196 unsigned off = (pid / MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
197 unsigned shift = (pid % MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
199 *config = (readl(base + off) >> shift) & MVEBU_MPP_MASK;
204 static inline int default_mpp_ctrl_set(void __iomem *base, unsigned int pid,
205 unsigned long config)
207 unsigned off = (pid / MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
208 unsigned shift = (pid % MVEBU_MPPS_PER_REG) * MVEBU_MPP_BITS;
211 reg = readl(base + off) & ~(MVEBU_MPP_MASK << shift);
212 writel(reg | (config << shift), base + off);
217 int mvebu_pinctrl_probe(struct platform_device *pdev);