4 * Copyright (c) 2014,2015 AMD Corporation.
5 * Authors: Ken Xue <Ken.Xue@amd.com>
6 * Wu, Jeff <Jeff.Wu@amd.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
13 #include <linux/err.h>
14 #include <linux/bug.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/spinlock.h>
18 #include <linux/compiler.h>
19 #include <linux/types.h>
20 #include <linux/errno.h>
21 #include <linux/log2.h>
23 #include <linux/gpio.h>
24 #include <linux/slab.h>
25 #include <linux/platform_device.h>
26 #include <linux/mutex.h>
27 #include <linux/acpi.h>
28 #include <linux/seq_file.h>
29 #include <linux/interrupt.h>
30 #include <linux/list.h>
31 #include <linux/bitops.h>
32 #include <linux/pinctrl/pinconf.h>
33 #include <linux/pinctrl/pinconf-generic.h>
35 #include "pinctrl-utils.h"
36 #include "pinctrl-amd.h"
38 static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
42 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
44 spin_lock_irqsave(&gpio_dev->lock, flags);
45 pin_reg = readl(gpio_dev->base + offset * 4);
46 pin_reg &= ~BIT(OUTPUT_ENABLE_OFF);
47 writel(pin_reg, gpio_dev->base + offset * 4);
48 spin_unlock_irqrestore(&gpio_dev->lock, flags);
53 static int amd_gpio_direction_output(struct gpio_chip *gc, unsigned offset,
58 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
60 spin_lock_irqsave(&gpio_dev->lock, flags);
61 pin_reg = readl(gpio_dev->base + offset * 4);
62 pin_reg |= BIT(OUTPUT_ENABLE_OFF);
64 pin_reg |= BIT(OUTPUT_VALUE_OFF);
66 pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
67 writel(pin_reg, gpio_dev->base + offset * 4);
68 spin_unlock_irqrestore(&gpio_dev->lock, flags);
73 static int amd_gpio_get_value(struct gpio_chip *gc, unsigned offset)
77 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
79 spin_lock_irqsave(&gpio_dev->lock, flags);
80 pin_reg = readl(gpio_dev->base + offset * 4);
81 spin_unlock_irqrestore(&gpio_dev->lock, flags);
83 return !!(pin_reg & BIT(PIN_STS_OFF));
86 static void amd_gpio_set_value(struct gpio_chip *gc, unsigned offset, int value)
90 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
92 spin_lock_irqsave(&gpio_dev->lock, flags);
93 pin_reg = readl(gpio_dev->base + offset * 4);
95 pin_reg |= BIT(OUTPUT_VALUE_OFF);
97 pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
98 writel(pin_reg, gpio_dev->base + offset * 4);
99 spin_unlock_irqrestore(&gpio_dev->lock, flags);
102 static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset,
109 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
111 spin_lock_irqsave(&gpio_dev->lock, flags);
112 pin_reg = readl(gpio_dev->base + offset * 4);
115 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
116 pin_reg &= ~DB_TMR_OUT_MASK;
118 Debounce Debounce Timer Max
119 TmrLarge TmrOutUnit Unit Debounce
121 0 0 61 usec (2 RtcClk) 976 usec
122 0 1 244 usec (8 RtcClk) 3.9 msec
123 1 0 15.6 msec (512 RtcClk) 250 msec
124 1 1 62.5 msec (2048 RtcClk) 1 sec
129 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
130 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
131 } else if (debounce < 976) {
132 time = debounce / 61;
133 pin_reg |= time & DB_TMR_OUT_MASK;
134 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
135 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
136 } else if (debounce < 3900) {
137 time = debounce / 244;
138 pin_reg |= time & DB_TMR_OUT_MASK;
139 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
140 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
141 } else if (debounce < 250000) {
142 time = debounce / 15600;
143 pin_reg |= time & DB_TMR_OUT_MASK;
144 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
145 pin_reg |= BIT(DB_TMR_LARGE_OFF);
146 } else if (debounce < 1000000) {
147 time = debounce / 62500;
148 pin_reg |= time & DB_TMR_OUT_MASK;
149 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
150 pin_reg |= BIT(DB_TMR_LARGE_OFF);
152 pin_reg &= ~DB_CNTRl_MASK;
156 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
157 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
158 pin_reg &= ~DB_TMR_OUT_MASK;
159 pin_reg &= ~DB_CNTRl_MASK;
161 writel(pin_reg, gpio_dev->base + offset * 4);
162 spin_unlock_irqrestore(&gpio_dev->lock, flags);
167 #ifdef CONFIG_DEBUG_FS
168 static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc)
172 unsigned int bank, i, pin_num;
173 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
177 char *interrupt_enable;
178 char *interrupt_mask;
184 char *pull_up_enable;
185 char *pull_down_enable;
189 for (bank = 0; bank < AMD_GPIO_TOTAL_BANKS; bank++) {
190 seq_printf(s, "GPIO bank%d\t", bank);
195 pin_num = AMD_GPIO_PINS_BANK0;
199 pin_num = AMD_GPIO_PINS_BANK1 + i;
203 pin_num = AMD_GPIO_PINS_BANK2 + i;
207 for (; i < pin_num; i++) {
208 seq_printf(s, "pin%d\t", i);
209 spin_lock_irqsave(&gpio_dev->lock, flags);
210 pin_reg = readl(gpio_dev->base + i * 4);
211 spin_unlock_irqrestore(&gpio_dev->lock, flags);
213 if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) {
214 interrupt_enable = "interrupt is enabled|";
216 if (!(pin_reg & BIT(ACTIVE_LEVEL_OFF))
217 && !(pin_reg & BIT(ACTIVE_LEVEL_OFF+1)))
218 active_level = "Active low|";
219 else if (pin_reg & BIT(ACTIVE_LEVEL_OFF)
220 && !(pin_reg & BIT(ACTIVE_LEVEL_OFF+1)))
221 active_level = "Active high|";
222 else if (!(pin_reg & BIT(ACTIVE_LEVEL_OFF))
223 && pin_reg & BIT(ACTIVE_LEVEL_OFF+1))
224 active_level = "Active on both|";
226 active_level = "Unknow Active level|";
228 if (pin_reg & BIT(LEVEL_TRIG_OFF))
229 level_trig = "Level trigger|";
231 level_trig = "Edge trigger|";
235 "interrupt is disabled|";
240 if (pin_reg & BIT(INTERRUPT_MASK_OFF))
242 "interrupt is unmasked|";
245 "interrupt is masked|";
247 if (pin_reg & BIT(WAKE_CNTRL_OFF))
248 wake_cntrl0 = "enable wakeup in S0i3 state|";
250 wake_cntrl0 = "disable wakeup in S0i3 state|";
252 if (pin_reg & BIT(WAKE_CNTRL_OFF))
253 wake_cntrl1 = "enable wakeup in S3 state|";
255 wake_cntrl1 = "disable wakeup in S3 state|";
257 if (pin_reg & BIT(WAKE_CNTRL_OFF))
258 wake_cntrl2 = "enable wakeup in S4/S5 state|";
260 wake_cntrl2 = "disable wakeup in S4/S5 state|";
262 if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) {
263 pull_up_enable = "pull-up is enabled|";
264 if (pin_reg & BIT(PULL_UP_SEL_OFF))
265 pull_up_sel = "8k pull-up|";
267 pull_up_sel = "4k pull-up|";
269 pull_up_enable = "pull-up is disabled|";
273 if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF))
274 pull_down_enable = "pull-down is enabled|";
276 pull_down_enable = "Pull-down is disabled|";
278 if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) {
280 output_enable = "output is enabled|";
281 if (pin_reg & BIT(OUTPUT_VALUE_OFF))
282 output_value = "output is high|";
284 output_value = "output is low|";
286 output_enable = "output is disabled|";
289 if (pin_reg & BIT(PIN_STS_OFF))
290 pin_sts = "input is high|";
292 pin_sts = "input is low|";
295 seq_printf(s, "%s %s %s %s %s %s\n"
296 " %s %s %s %s %s %s %s 0x%x\n",
297 level_trig, active_level, interrupt_enable,
298 interrupt_mask, wake_cntrl0, wake_cntrl1,
299 wake_cntrl2, pin_sts, pull_up_sel,
300 pull_up_enable, pull_down_enable,
301 output_value, output_enable, pin_reg);
306 #define amd_gpio_dbg_show NULL
309 static void amd_gpio_irq_enable(struct irq_data *d)
313 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
314 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
316 spin_lock_irqsave(&gpio_dev->lock, flags);
317 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
318 pin_reg |= BIT(INTERRUPT_ENABLE_OFF);
319 pin_reg |= BIT(INTERRUPT_MASK_OFF);
320 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
321 spin_unlock_irqrestore(&gpio_dev->lock, flags);
324 static void amd_gpio_irq_disable(struct irq_data *d)
328 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
329 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
331 spin_lock_irqsave(&gpio_dev->lock, flags);
332 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
333 pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF);
334 pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
335 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
336 spin_unlock_irqrestore(&gpio_dev->lock, flags);
339 static void amd_gpio_irq_mask(struct irq_data *d)
343 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
344 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
346 spin_lock_irqsave(&gpio_dev->lock, flags);
347 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
348 pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
349 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
350 spin_unlock_irqrestore(&gpio_dev->lock, flags);
353 static void amd_gpio_irq_unmask(struct irq_data *d)
357 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
358 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
360 spin_lock_irqsave(&gpio_dev->lock, flags);
361 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
362 pin_reg |= BIT(INTERRUPT_MASK_OFF);
363 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
364 spin_unlock_irqrestore(&gpio_dev->lock, flags);
367 static void amd_gpio_irq_eoi(struct irq_data *d)
371 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
372 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
374 spin_lock_irqsave(&gpio_dev->lock, flags);
375 reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
377 writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG);
378 spin_unlock_irqrestore(&gpio_dev->lock, flags);
381 static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
385 unsigned long flags, irq_flags;
386 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
387 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
389 spin_lock_irqsave(&gpio_dev->lock, flags);
390 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
392 /* Ignore the settings coming from the client and
393 * read the values from the ACPI tables
394 * while setting the trigger type
397 irq_flags = irq_get_trigger_type(d->irq);
398 if (irq_flags != IRQ_TYPE_NONE)
401 switch (type & IRQ_TYPE_SENSE_MASK) {
402 case IRQ_TYPE_EDGE_RISING:
403 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
404 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
405 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
406 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
407 irq_set_handler_locked(d, handle_edge_irq);
410 case IRQ_TYPE_EDGE_FALLING:
411 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
412 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
413 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
414 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
415 irq_set_handler_locked(d, handle_edge_irq);
418 case IRQ_TYPE_EDGE_BOTH:
419 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
420 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
421 pin_reg |= BOTH_EADGE << ACTIVE_LEVEL_OFF;
422 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
423 irq_set_handler_locked(d, handle_edge_irq);
426 case IRQ_TYPE_LEVEL_HIGH:
427 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
428 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
429 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
430 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
431 pin_reg |= DB_TYPE_PRESERVE_LOW_GLITCH << DB_CNTRL_OFF;
432 irq_set_handler_locked(d, handle_level_irq);
435 case IRQ_TYPE_LEVEL_LOW:
436 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
437 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
438 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
439 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
440 pin_reg |= DB_TYPE_PRESERVE_HIGH_GLITCH << DB_CNTRL_OFF;
441 irq_set_handler_locked(d, handle_level_irq);
448 dev_err(&gpio_dev->pdev->dev, "Invalid type value\n");
452 pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF;
453 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
454 spin_unlock_irqrestore(&gpio_dev->lock, flags);
459 static void amd_irq_ack(struct irq_data *d)
462 * based on HW design,there is no need to ack HW
463 * before handle current irq. But this routine is
464 * necessary for handle_edge_irq
468 static struct irq_chip amd_gpio_irqchip = {
470 .irq_ack = amd_irq_ack,
471 .irq_enable = amd_gpio_irq_enable,
472 .irq_disable = amd_gpio_irq_disable,
473 .irq_mask = amd_gpio_irq_mask,
474 .irq_unmask = amd_gpio_irq_unmask,
475 .irq_eoi = amd_gpio_irq_eoi,
476 .irq_set_type = amd_gpio_irq_set_type,
479 static void amd_gpio_irq_handler(struct irq_desc *desc)
489 struct irq_chip *chip = irq_desc_get_chip(desc);
490 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
491 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
493 chained_irq_enter(chip, desc);
494 /*enable GPIO interrupt again*/
495 spin_lock_irqsave(&gpio_dev->lock, flags);
496 reg = readl(gpio_dev->base + WAKE_INT_STATUS_REG1);
500 reg = readl(gpio_dev->base + WAKE_INT_STATUS_REG0);
502 spin_unlock_irqrestore(&gpio_dev->lock, flags);
505 * first 46 bits indicates interrupt status.
506 * one bit represents four interrupt sources.
508 for (off = 0; off < 46 ; off++) {
509 if (reg64 & BIT(off)) {
510 for (i = 0; i < 4; i++) {
511 pin_reg = readl(gpio_dev->base +
513 if ((pin_reg & BIT(INTERRUPT_STS_OFF)) ||
514 (pin_reg & BIT(WAKE_STS_OFF))) {
515 irq = irq_find_mapping(gc->irqdomain,
517 generic_handle_irq(irq);
520 + (off * 4 + i) * 4);
528 handle_bad_irq(desc);
530 spin_lock_irqsave(&gpio_dev->lock, flags);
531 reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
533 writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG);
534 spin_unlock_irqrestore(&gpio_dev->lock, flags);
536 chained_irq_exit(chip, desc);
539 static int amd_get_groups_count(struct pinctrl_dev *pctldev)
541 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
543 return gpio_dev->ngroups;
546 static const char *amd_get_group_name(struct pinctrl_dev *pctldev,
549 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
551 return gpio_dev->groups[group].name;
554 static int amd_get_group_pins(struct pinctrl_dev *pctldev,
556 const unsigned **pins,
559 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
561 *pins = gpio_dev->groups[group].pins;
562 *num_pins = gpio_dev->groups[group].npins;
566 static const struct pinctrl_ops amd_pinctrl_ops = {
567 .get_groups_count = amd_get_groups_count,
568 .get_group_name = amd_get_group_name,
569 .get_group_pins = amd_get_group_pins,
571 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
572 .dt_free_map = pinctrl_utils_free_map,
576 static int amd_pinconf_get(struct pinctrl_dev *pctldev,
578 unsigned long *config)
583 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
584 enum pin_config_param param = pinconf_to_config_param(*config);
586 spin_lock_irqsave(&gpio_dev->lock, flags);
587 pin_reg = readl(gpio_dev->base + pin*4);
588 spin_unlock_irqrestore(&gpio_dev->lock, flags);
590 case PIN_CONFIG_INPUT_DEBOUNCE:
591 arg = pin_reg & DB_TMR_OUT_MASK;
594 case PIN_CONFIG_BIAS_PULL_DOWN:
595 arg = (pin_reg >> PULL_DOWN_ENABLE_OFF) & BIT(0);
598 case PIN_CONFIG_BIAS_PULL_UP:
599 arg = (pin_reg >> PULL_UP_SEL_OFF) & (BIT(0) | BIT(1));
602 case PIN_CONFIG_DRIVE_STRENGTH:
603 arg = (pin_reg >> DRV_STRENGTH_SEL_OFF) & DRV_STRENGTH_SEL_MASK;
607 dev_err(&gpio_dev->pdev->dev, "Invalid config param %04x\n",
612 *config = pinconf_to_config_packed(param, arg);
617 static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
618 unsigned long *configs, unsigned num_configs)
625 enum pin_config_param param;
626 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
628 spin_lock_irqsave(&gpio_dev->lock, flags);
629 for (i = 0; i < num_configs; i++) {
630 param = pinconf_to_config_param(configs[i]);
631 arg = pinconf_to_config_argument(configs[i]);
632 pin_reg = readl(gpio_dev->base + pin*4);
635 case PIN_CONFIG_INPUT_DEBOUNCE:
636 pin_reg &= ~DB_TMR_OUT_MASK;
637 pin_reg |= arg & DB_TMR_OUT_MASK;
640 case PIN_CONFIG_BIAS_PULL_DOWN:
641 pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF);
642 pin_reg |= (arg & BIT(0)) << PULL_DOWN_ENABLE_OFF;
645 case PIN_CONFIG_BIAS_PULL_UP:
646 pin_reg &= ~BIT(PULL_UP_SEL_OFF);
647 pin_reg |= (arg & BIT(0)) << PULL_UP_SEL_OFF;
648 pin_reg &= ~BIT(PULL_UP_ENABLE_OFF);
649 pin_reg |= ((arg>>1) & BIT(0)) << PULL_UP_ENABLE_OFF;
652 case PIN_CONFIG_DRIVE_STRENGTH:
653 pin_reg &= ~(DRV_STRENGTH_SEL_MASK
654 << DRV_STRENGTH_SEL_OFF);
655 pin_reg |= (arg & DRV_STRENGTH_SEL_MASK)
656 << DRV_STRENGTH_SEL_OFF;
660 dev_err(&gpio_dev->pdev->dev,
661 "Invalid config param %04x\n", param);
665 writel(pin_reg, gpio_dev->base + pin*4);
667 spin_unlock_irqrestore(&gpio_dev->lock, flags);
672 static int amd_pinconf_group_get(struct pinctrl_dev *pctldev,
674 unsigned long *config)
676 const unsigned *pins;
680 ret = amd_get_group_pins(pctldev, group, &pins, &npins);
684 if (amd_pinconf_get(pctldev, pins[0], config))
690 static int amd_pinconf_group_set(struct pinctrl_dev *pctldev,
691 unsigned group, unsigned long *configs,
692 unsigned num_configs)
694 const unsigned *pins;
698 ret = amd_get_group_pins(pctldev, group, &pins, &npins);
701 for (i = 0; i < npins; i++) {
702 if (amd_pinconf_set(pctldev, pins[i], configs, num_configs))
708 static const struct pinconf_ops amd_pinconf_ops = {
709 .pin_config_get = amd_pinconf_get,
710 .pin_config_set = amd_pinconf_set,
711 .pin_config_group_get = amd_pinconf_group_get,
712 .pin_config_group_set = amd_pinconf_group_set,
715 static struct pinctrl_desc amd_pinctrl_desc = {
717 .npins = ARRAY_SIZE(kerncz_pins),
718 .pctlops = &amd_pinctrl_ops,
719 .confops = &amd_pinconf_ops,
720 .owner = THIS_MODULE,
723 static int amd_gpio_probe(struct platform_device *pdev)
727 struct resource *res;
728 struct amd_gpio *gpio_dev;
730 gpio_dev = devm_kzalloc(&pdev->dev,
731 sizeof(struct amd_gpio), GFP_KERNEL);
735 spin_lock_init(&gpio_dev->lock);
737 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
739 dev_err(&pdev->dev, "Failed to get gpio io resource.\n");
743 gpio_dev->base = devm_ioremap_nocache(&pdev->dev, res->start,
748 irq_base = platform_get_irq(pdev, 0);
750 dev_err(&pdev->dev, "Failed to get gpio IRQ.\n");
754 gpio_dev->pdev = pdev;
755 gpio_dev->gc.direction_input = amd_gpio_direction_input;
756 gpio_dev->gc.direction_output = amd_gpio_direction_output;
757 gpio_dev->gc.get = amd_gpio_get_value;
758 gpio_dev->gc.set = amd_gpio_set_value;
759 gpio_dev->gc.set_debounce = amd_gpio_set_debounce;
760 gpio_dev->gc.dbg_show = amd_gpio_dbg_show;
762 gpio_dev->gc.base = 0;
763 gpio_dev->gc.label = pdev->name;
764 gpio_dev->gc.owner = THIS_MODULE;
765 gpio_dev->gc.parent = &pdev->dev;
766 gpio_dev->gc.ngpio = TOTAL_NUMBER_OF_PINS;
767 #if defined(CONFIG_OF_GPIO)
768 gpio_dev->gc.of_node = pdev->dev.of_node;
771 gpio_dev->groups = kerncz_groups;
772 gpio_dev->ngroups = ARRAY_SIZE(kerncz_groups);
774 amd_pinctrl_desc.name = dev_name(&pdev->dev);
775 gpio_dev->pctrl = devm_pinctrl_register(&pdev->dev, &amd_pinctrl_desc,
777 if (IS_ERR(gpio_dev->pctrl)) {
778 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
779 return PTR_ERR(gpio_dev->pctrl);
782 ret = gpiochip_add_data(&gpio_dev->gc, gpio_dev);
786 ret = gpiochip_add_pin_range(&gpio_dev->gc, dev_name(&pdev->dev),
787 0, 0, TOTAL_NUMBER_OF_PINS);
789 dev_err(&pdev->dev, "Failed to add pin range\n");
793 ret = gpiochip_irqchip_add(&gpio_dev->gc,
799 dev_err(&pdev->dev, "could not add irqchip\n");
804 gpiochip_set_chained_irqchip(&gpio_dev->gc,
807 amd_gpio_irq_handler);
809 platform_set_drvdata(pdev, gpio_dev);
811 dev_dbg(&pdev->dev, "amd gpio driver loaded\n");
815 gpiochip_remove(&gpio_dev->gc);
820 static int amd_gpio_remove(struct platform_device *pdev)
822 struct amd_gpio *gpio_dev;
824 gpio_dev = platform_get_drvdata(pdev);
826 gpiochip_remove(&gpio_dev->gc);
831 static const struct acpi_device_id amd_gpio_acpi_match[] = {
836 MODULE_DEVICE_TABLE(acpi, amd_gpio_acpi_match);
838 static struct platform_driver amd_gpio_driver = {
841 .acpi_match_table = ACPI_PTR(amd_gpio_acpi_match),
843 .probe = amd_gpio_probe,
844 .remove = amd_gpio_remove,
847 module_platform_driver(amd_gpio_driver);
849 MODULE_LICENSE("GPL v2");
850 MODULE_AUTHOR("Ken Xue <Ken.Xue@amd.com>, Jeff Wu <Jeff.Wu@amd.com>");
851 MODULE_DESCRIPTION("AMD GPIO pinctrl driver");