2 * Pinctrl GPIO driver for Intel Baytrail
3 * Copyright (c) 2012-2013, Intel Corporation.
5 * Author: Mathias Nyman <mathias.nyman@linux.intel.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/init.h>
25 #include <linux/types.h>
26 #include <linux/bitops.h>
27 #include <linux/interrupt.h>
28 #include <linux/irq.h>
29 #include <linux/gpio.h>
30 #include <linux/irqdomain.h>
31 #include <linux/acpi.h>
32 #include <linux/platform_device.h>
33 #include <linux/seq_file.h>
35 #include <linux/pm_runtime.h>
36 #include <linux/pinctrl/pinctrl.h>
38 /* memory mapped register offsets */
39 #define BYT_CONF0_REG 0x000
40 #define BYT_CONF1_REG 0x004
41 #define BYT_VAL_REG 0x008
42 #define BYT_DFT_REG 0x00c
43 #define BYT_INT_STAT_REG 0x800
45 /* BYT_CONF0_REG register bits */
46 #define BYT_TRIG_NEG BIT(26)
47 #define BYT_TRIG_POS BIT(25)
48 #define BYT_TRIG_LVL BIT(24)
49 #define BYT_PIN_MUX 0x07
51 /* BYT_VAL_REG register bits */
52 #define BYT_INPUT_EN BIT(2) /* 0: input enabled (active low)*/
53 #define BYT_OUTPUT_EN BIT(1) /* 0: output enabled (active low)*/
54 #define BYT_LEVEL BIT(0)
56 #define BYT_DIR_MASK (BIT(1) | BIT(2))
57 #define BYT_TRIG_MASK (BIT(26) | BIT(25) | BIT(24))
59 #define BYT_NGPIO_SCORE 102
60 #define BYT_NGPIO_NCORE 28
61 #define BYT_NGPIO_SUS 44
63 #define BYT_SCORE_ACPI_UID "1"
64 #define BYT_NCORE_ACPI_UID "2"
65 #define BYT_SUS_ACPI_UID "3"
68 * Baytrail gpio controller consist of three separate sub-controllers called
69 * SCORE, NCORE and SUS. The sub-controllers are identified by their acpi UID.
71 * GPIO numbering is _not_ ordered meaning that gpio # 0 in ACPI namespace does
72 * _not_ correspond to the first gpio register at controller's gpio base.
73 * There is no logic or pattern in mapping gpio numbers to registers (pads) so
74 * each sub-controller needs to have its own mapping table
77 /* score_pins[gpio_nr] = pad_nr */
79 static unsigned const score_pins[BYT_NGPIO_SCORE] = {
80 85, 89, 93, 96, 99, 102, 98, 101, 34, 37,
81 36, 38, 39, 35, 40, 84, 62, 61, 64, 59,
82 54, 56, 60, 55, 63, 57, 51, 50, 53, 47,
83 52, 49, 48, 43, 46, 41, 45, 42, 58, 44,
84 95, 105, 70, 68, 67, 66, 69, 71, 65, 72,
85 86, 90, 88, 92, 103, 77, 79, 83, 78, 81,
86 80, 82, 13, 12, 15, 14, 17, 18, 19, 16,
87 2, 1, 0, 4, 6, 7, 9, 8, 33, 32,
88 31, 30, 29, 27, 25, 28, 26, 23, 21, 20,
89 24, 22, 5, 3, 10, 11, 106, 87, 91, 104,
93 static unsigned const ncore_pins[BYT_NGPIO_NCORE] = {
94 19, 18, 17, 20, 21, 22, 24, 25, 23, 16,
95 14, 15, 12, 26, 27, 1, 4, 8, 11, 0,
96 3, 6, 10, 13, 2, 5, 9, 7,
99 static unsigned const sus_pins[BYT_NGPIO_SUS] = {
100 29, 33, 30, 31, 32, 34, 36, 35, 38, 37,
101 18, 7, 11, 20, 17, 1, 8, 10, 19, 12,
102 0, 2, 23, 39, 28, 27, 22, 21, 24, 25,
103 26, 51, 56, 54, 49, 55, 48, 57, 50, 58,
107 static struct pinctrl_gpio_range byt_ranges[] = {
109 .name = BYT_SCORE_ACPI_UID, /* match with acpi _UID in probe */
110 .npins = BYT_NGPIO_SCORE,
114 .name = BYT_NCORE_ACPI_UID,
115 .npins = BYT_NGPIO_NCORE,
119 .name = BYT_SUS_ACPI_UID,
120 .npins = BYT_NGPIO_SUS,
128 struct gpio_chip chip;
129 struct irq_domain *domain;
130 struct platform_device *pdev;
132 void __iomem *reg_base;
133 struct pinctrl_gpio_range *range;
136 #define to_byt_gpio(c) container_of(c, struct byt_gpio, chip)
138 static void __iomem *byt_gpio_reg(struct gpio_chip *chip, unsigned offset,
141 struct byt_gpio *vg = to_byt_gpio(chip);
144 if (reg == BYT_INT_STAT_REG)
145 reg_offset = (offset / 32) * 4;
147 reg_offset = vg->range->pins[offset] * 16;
149 return vg->reg_base + reg_offset + reg;
152 static bool is_special_pin(struct byt_gpio *vg, unsigned offset)
154 /* SCORE pin 92-93 */
155 if (!strcmp(vg->range->name, BYT_SCORE_ACPI_UID) &&
156 offset >= 92 && offset <= 93)
160 if (!strcmp(vg->range->name, BYT_SUS_ACPI_UID) &&
161 offset >= 11 && offset <= 21)
167 static int byt_gpio_request(struct gpio_chip *chip, unsigned offset)
169 struct byt_gpio *vg = to_byt_gpio(chip);
170 void __iomem *reg = byt_gpio_reg(chip, offset, BYT_CONF0_REG);
175 * In most cases, func pin mux 000 means GPIO function.
176 * But, some pins may have func pin mux 001 represents
177 * GPIO function. Only allow user to export pin with
178 * func pin mux preset as GPIO function by BIOS/FW.
180 value = readl(reg) & BYT_PIN_MUX;
181 special = is_special_pin(vg, offset);
182 if ((special && value != 1) || (!special && value)) {
183 dev_err(&vg->pdev->dev,
184 "pin %u cannot be used as GPIO.\n", offset);
188 pm_runtime_get(&vg->pdev->dev);
193 static void byt_gpio_free(struct gpio_chip *chip, unsigned offset)
195 struct byt_gpio *vg = to_byt_gpio(chip);
196 void __iomem *reg = byt_gpio_reg(&vg->chip, offset, BYT_CONF0_REG);
199 /* clear interrupt triggering */
201 value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL);
204 pm_runtime_put(&vg->pdev->dev);
207 static int byt_irq_type(struct irq_data *d, unsigned type)
209 struct byt_gpio *vg = irq_data_get_irq_chip_data(d);
210 u32 offset = irqd_to_hwirq(d);
213 void __iomem *reg = byt_gpio_reg(&vg->chip, offset, BYT_CONF0_REG);
215 if (offset >= vg->chip.ngpio)
218 spin_lock_irqsave(&vg->lock, flags);
221 /* For level trigges the BYT_TRIG_POS and BYT_TRIG_NEG bits
222 * are used to indicate high and low level triggering
224 value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL);
227 case IRQ_TYPE_LEVEL_HIGH:
228 value |= BYT_TRIG_LVL;
229 case IRQ_TYPE_EDGE_RISING:
230 value |= BYT_TRIG_POS;
232 case IRQ_TYPE_LEVEL_LOW:
233 value |= BYT_TRIG_LVL;
234 case IRQ_TYPE_EDGE_FALLING:
235 value |= BYT_TRIG_NEG;
237 case IRQ_TYPE_EDGE_BOTH:
238 value |= (BYT_TRIG_NEG | BYT_TRIG_POS);
243 spin_unlock_irqrestore(&vg->lock, flags);
248 static int byt_gpio_get(struct gpio_chip *chip, unsigned offset)
250 void __iomem *reg = byt_gpio_reg(chip, offset, BYT_VAL_REG);
251 return readl(reg) & BYT_LEVEL;
254 static void byt_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
256 struct byt_gpio *vg = to_byt_gpio(chip);
257 void __iomem *reg = byt_gpio_reg(chip, offset, BYT_VAL_REG);
261 spin_lock_irqsave(&vg->lock, flags);
263 old_val = readl(reg);
266 writel(old_val | BYT_LEVEL, reg);
268 writel(old_val & ~BYT_LEVEL, reg);
270 spin_unlock_irqrestore(&vg->lock, flags);
273 static int byt_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
275 struct byt_gpio *vg = to_byt_gpio(chip);
276 void __iomem *reg = byt_gpio_reg(chip, offset, BYT_VAL_REG);
280 spin_lock_irqsave(&vg->lock, flags);
282 value = readl(reg) | BYT_DIR_MASK;
283 value &= ~BYT_INPUT_EN; /* active low */
286 spin_unlock_irqrestore(&vg->lock, flags);
291 static int byt_gpio_direction_output(struct gpio_chip *chip,
292 unsigned gpio, int value)
294 struct byt_gpio *vg = to_byt_gpio(chip);
295 void __iomem *reg = byt_gpio_reg(chip, gpio, BYT_VAL_REG);
299 spin_lock_irqsave(&vg->lock, flags);
301 reg_val = readl(reg) | BYT_DIR_MASK;
302 reg_val &= ~BYT_OUTPUT_EN;
305 writel(reg_val | BYT_LEVEL, reg);
307 writel(reg_val & ~BYT_LEVEL, reg);
309 spin_unlock_irqrestore(&vg->lock, flags);
314 static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
316 struct byt_gpio *vg = to_byt_gpio(chip);
319 u32 conf0, val, offs;
321 spin_lock_irqsave(&vg->lock, flags);
323 for (i = 0; i < vg->chip.ngpio; i++) {
325 offs = vg->range->pins[i] * 16;
326 conf0 = readl(vg->reg_base + offs + BYT_CONF0_REG);
327 val = readl(vg->reg_base + offs + BYT_VAL_REG);
329 label = gpiochip_is_requested(chip, i);
331 label = "Unrequested";
334 " gpio-%-3d (%-20.20s) %s %s %s pad-%-3d offset:0x%03x mux:%d %s%s%s\n",
337 val & BYT_INPUT_EN ? " " : "in",
338 val & BYT_OUTPUT_EN ? " " : "out",
339 val & BYT_LEVEL ? "hi" : "lo",
340 vg->range->pins[i], offs,
342 conf0 & BYT_TRIG_NEG ? " fall" : "",
343 conf0 & BYT_TRIG_POS ? " rise" : "",
344 conf0 & BYT_TRIG_LVL ? " level" : "");
346 spin_unlock_irqrestore(&vg->lock, flags);
349 static int byt_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
351 struct byt_gpio *vg = to_byt_gpio(chip);
352 return irq_create_mapping(vg->domain, offset);
355 static void byt_gpio_irq_handler(unsigned irq, struct irq_desc *desc)
357 struct irq_data *data = irq_desc_get_irq_data(desc);
358 struct byt_gpio *vg = irq_data_get_irq_handler_data(data);
359 struct irq_chip *chip = irq_data_get_irq_chip(data);
366 /* check from GPIO controller which pin triggered the interrupt */
367 for (base = 0; base < vg->chip.ngpio; base += 32) {
369 reg = byt_gpio_reg(&vg->chip, base, BYT_INT_STAT_REG);
371 while ((pending = readl(reg))) {
372 pin = __ffs(pending);
374 /* Clear before handling so we can't lose an edge */
377 virq = irq_find_mapping(vg->domain, base + pin);
378 generic_handle_irq(virq);
380 /* In case bios or user sets triggering incorretly a pin
381 * might remain in "interrupt triggered" state.
383 if (looplimit++ > 32) {
384 dev_err(&vg->pdev->dev,
385 "Gpio %d interrupt flood, disabling\n",
388 reg = byt_gpio_reg(&vg->chip, base + pin,
391 mask &= ~(BYT_TRIG_NEG | BYT_TRIG_POS |
394 mask = readl(reg); /* flush */
402 static void byt_irq_unmask(struct irq_data *d)
406 static void byt_irq_mask(struct irq_data *d)
410 static int byt_irq_reqres(struct irq_data *d)
412 struct byt_gpio *vg = irq_data_get_irq_chip_data(d);
414 if (gpio_lock_as_irq(&vg->chip, irqd_to_hwirq(d))) {
415 dev_err(vg->chip.dev,
416 "unable to lock HW IRQ %lu for IRQ\n",
423 static void byt_irq_relres(struct irq_data *d)
425 struct byt_gpio *vg = irq_data_get_irq_chip_data(d);
427 gpio_unlock_as_irq(&vg->chip, irqd_to_hwirq(d));
430 static struct irq_chip byt_irqchip = {
432 .irq_mask = byt_irq_mask,
433 .irq_unmask = byt_irq_unmask,
434 .irq_set_type = byt_irq_type,
435 .irq_request_resources = byt_irq_reqres,
436 .irq_release_resources = byt_irq_relres,
439 static void byt_gpio_irq_init_hw(struct byt_gpio *vg)
444 /* clear interrupt status trigger registers */
445 for (base = 0; base < vg->chip.ngpio; base += 32) {
446 reg = byt_gpio_reg(&vg->chip, base, BYT_INT_STAT_REG);
447 writel(0xffffffff, reg);
448 /* make sure trigger bits are cleared, if not then a pin
449 might be misconfigured in bios */
452 dev_err(&vg->pdev->dev,
453 "GPIO interrupt error, pins misconfigured\n");
457 static int byt_gpio_irq_map(struct irq_domain *d, unsigned int virq,
460 struct byt_gpio *vg = d->host_data;
462 irq_set_chip_and_handler_name(virq, &byt_irqchip, handle_simple_irq,
464 irq_set_chip_data(virq, vg);
465 irq_set_irq_type(virq, IRQ_TYPE_NONE);
470 static const struct irq_domain_ops byt_gpio_irq_ops = {
471 .map = byt_gpio_irq_map,
474 static int byt_gpio_probe(struct platform_device *pdev)
477 struct gpio_chip *gc;
478 struct resource *mem_rc, *irq_rc;
479 struct device *dev = &pdev->dev;
480 struct acpi_device *acpi_dev;
481 struct pinctrl_gpio_range *range;
482 acpi_handle handle = ACPI_HANDLE(dev);
486 if (acpi_bus_get_device(handle, &acpi_dev))
489 vg = devm_kzalloc(dev, sizeof(struct byt_gpio), GFP_KERNEL);
491 dev_err(&pdev->dev, "can't allocate byt_gpio chip data\n");
495 for (range = byt_ranges; range->name; range++) {
496 if (!strcmp(acpi_dev->pnp.unique_id, range->name)) {
497 vg->chip.ngpio = range->npins;
503 if (!vg->chip.ngpio || !vg->range)
507 platform_set_drvdata(pdev, vg);
509 mem_rc = platform_get_resource(pdev, IORESOURCE_MEM, 0);
510 vg->reg_base = devm_ioremap_resource(dev, mem_rc);
511 if (IS_ERR(vg->reg_base))
512 return PTR_ERR(vg->reg_base);
514 spin_lock_init(&vg->lock);
517 gc->label = dev_name(&pdev->dev);
518 gc->owner = THIS_MODULE;
519 gc->request = byt_gpio_request;
520 gc->free = byt_gpio_free;
521 gc->direction_input = byt_gpio_direction_input;
522 gc->direction_output = byt_gpio_direction_output;
523 gc->get = byt_gpio_get;
524 gc->set = byt_gpio_set;
525 gc->dbg_show = byt_gpio_dbg_show;
527 gc->can_sleep = false;
530 ret = gpiochip_add(gc);
532 dev_err(&pdev->dev, "failed adding byt-gpio chip\n");
536 /* set up interrupts */
537 irq_rc = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
538 if (irq_rc && irq_rc->start) {
539 hwirq = irq_rc->start;
540 gc->to_irq = byt_gpio_to_irq;
542 vg->domain = irq_domain_add_linear(NULL, gc->ngpio,
543 &byt_gpio_irq_ops, vg);
547 byt_gpio_irq_init_hw(vg);
549 irq_set_handler_data(hwirq, vg);
550 irq_set_chained_handler(hwirq, byt_gpio_irq_handler);
553 pm_runtime_enable(dev);
558 static int byt_gpio_runtime_suspend(struct device *dev)
563 static int byt_gpio_runtime_resume(struct device *dev)
568 static const struct dev_pm_ops byt_gpio_pm_ops = {
569 .runtime_suspend = byt_gpio_runtime_suspend,
570 .runtime_resume = byt_gpio_runtime_resume,
573 static const struct acpi_device_id byt_gpio_acpi_match[] = {
577 MODULE_DEVICE_TABLE(acpi, byt_gpio_acpi_match);
579 static int byt_gpio_remove(struct platform_device *pdev)
581 struct byt_gpio *vg = platform_get_drvdata(pdev);
584 pm_runtime_disable(&pdev->dev);
585 err = gpiochip_remove(&vg->chip);
587 dev_warn(&pdev->dev, "failed to remove gpio_chip.\n");
592 static struct platform_driver byt_gpio_driver = {
593 .probe = byt_gpio_probe,
594 .remove = byt_gpio_remove,
597 .owner = THIS_MODULE,
598 .pm = &byt_gpio_pm_ops,
599 .acpi_match_table = ACPI_PTR(byt_gpio_acpi_match),
603 static int __init byt_gpio_init(void)
605 return platform_driver_register(&byt_gpio_driver);
608 subsys_initcall(byt_gpio_init);