2 * Pinctrl GPIO driver for Intel Baytrail
3 * Copyright (c) 2012-2013, Intel Corporation.
5 * Author: Mathias Nyman <mathias.nyman@linux.intel.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/init.h>
25 #include <linux/types.h>
26 #include <linux/bitops.h>
27 #include <linux/interrupt.h>
28 #include <linux/irq.h>
29 #include <linux/gpio.h>
30 #include <linux/irqdomain.h>
31 #include <linux/acpi.h>
32 #include <linux/acpi_gpio.h>
33 #include <linux/platform_device.h>
34 #include <linux/seq_file.h>
36 #include <linux/pm_runtime.h>
37 #include <linux/pinctrl/pinctrl.h>
39 /* memory mapped register offsets */
40 #define BYT_CONF0_REG 0x000
41 #define BYT_CONF1_REG 0x004
42 #define BYT_VAL_REG 0x008
43 #define BYT_DFT_REG 0x00c
44 #define BYT_INT_STAT_REG 0x800
46 /* BYT_CONF0_REG register bits */
47 #define BYT_TRIG_NEG BIT(26)
48 #define BYT_TRIG_POS BIT(25)
49 #define BYT_TRIG_LVL BIT(24)
50 #define BYT_PIN_MUX 0x07
52 /* BYT_VAL_REG register bits */
53 #define BYT_INPUT_EN BIT(2) /* 0: input enabled (active low)*/
54 #define BYT_OUTPUT_EN BIT(1) /* 0: output enabled (active low)*/
55 #define BYT_LEVEL BIT(0)
57 #define BYT_DIR_MASK (BIT(1) | BIT(2))
58 #define BYT_TRIG_MASK (BIT(26) | BIT(25) | BIT(24))
60 #define BYT_NGPIO_SCORE 102
61 #define BYT_NGPIO_NCORE 28
62 #define BYT_NGPIO_SUS 44
65 * Baytrail gpio controller consist of three separate sub-controllers called
66 * SCORE, NCORE and SUS. The sub-controllers are identified by their acpi UID.
68 * GPIO numbering is _not_ ordered meaning that gpio # 0 in ACPI namespace does
69 * _not_ correspond to the first gpio register at controller's gpio base.
70 * There is no logic or pattern in mapping gpio numbers to registers (pads) so
71 * each sub-controller needs to have its own mapping table
74 /* score_pins[gpio_nr] = pad_nr */
76 static unsigned const score_pins[BYT_NGPIO_SCORE] = {
77 85, 89, 93, 96, 99, 102, 98, 101, 34, 37,
78 36, 38, 39, 35, 40, 84, 62, 61, 64, 59,
79 54, 56, 60, 55, 63, 57, 51, 50, 53, 47,
80 52, 49, 48, 43, 46, 41, 45, 42, 58, 44,
81 95, 105, 70, 68, 67, 66, 69, 71, 65, 72,
82 86, 90, 88, 92, 103, 77, 79, 83, 78, 81,
83 80, 82, 13, 12, 15, 14, 17, 18, 19, 16,
84 2, 1, 0, 4, 6, 7, 9, 8, 33, 32,
85 31, 30, 29, 27, 25, 28, 26, 23, 21, 20,
86 24, 22, 5, 3, 10, 11, 106, 87, 91, 104,
90 static unsigned const ncore_pins[BYT_NGPIO_NCORE] = {
91 19, 18, 17, 20, 21, 22, 24, 25, 23, 16,
92 14, 15, 12, 26, 27, 1, 4, 8, 11, 0,
93 3, 6, 10, 13, 2, 5, 9, 7,
96 static unsigned const sus_pins[BYT_NGPIO_SUS] = {
97 29, 33, 30, 31, 32, 34, 36, 35, 38, 37,
98 18, 7, 11, 20, 17, 1, 8, 10, 19, 12,
99 0, 2, 23, 39, 28, 27, 22, 21, 24, 25,
100 26, 51, 56, 54, 49, 55, 48, 57, 50, 58,
104 static struct pinctrl_gpio_range byt_ranges[] = {
106 .name = "1", /* match with acpi _UID in probe */
107 .npins = BYT_NGPIO_SCORE,
112 .npins = BYT_NGPIO_NCORE,
117 .npins = BYT_NGPIO_SUS,
125 struct gpio_chip chip;
126 struct irq_domain *domain;
127 struct platform_device *pdev;
129 void __iomem *reg_base;
130 struct pinctrl_gpio_range *range;
133 static void __iomem *byt_gpio_reg(struct gpio_chip *chip, unsigned offset,
136 struct byt_gpio *vg = container_of(chip, struct byt_gpio, chip);
139 if (reg == BYT_INT_STAT_REG)
140 reg_offset = (offset / 32) * 4;
142 reg_offset = vg->range->pins[offset] * 16;
144 return vg->reg_base + reg_offset + reg;
147 static int byt_gpio_request(struct gpio_chip *chip, unsigned offset)
149 struct byt_gpio *vg = container_of(chip, struct byt_gpio, chip);
151 pm_runtime_get(&vg->pdev->dev);
156 static void byt_gpio_free(struct gpio_chip *chip, unsigned offset)
158 struct byt_gpio *vg = container_of(chip, struct byt_gpio, chip);
159 void __iomem *reg = byt_gpio_reg(&vg->chip, offset, BYT_CONF0_REG);
162 /* clear interrupt triggering */
164 value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL);
167 pm_runtime_put(&vg->pdev->dev);
170 static int byt_irq_type(struct irq_data *d, unsigned type)
172 struct byt_gpio *vg = irq_data_get_irq_chip_data(d);
173 u32 offset = irqd_to_hwirq(d);
176 void __iomem *reg = byt_gpio_reg(&vg->chip, offset, BYT_CONF0_REG);
178 if (offset >= vg->chip.ngpio)
181 spin_lock_irqsave(&vg->lock, flags);
184 /* For level trigges the BYT_TRIG_POS and BYT_TRIG_NEG bits
185 * are used to indicate high and low level triggering
187 value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL);
190 case IRQ_TYPE_LEVEL_HIGH:
191 value |= BYT_TRIG_LVL;
192 case IRQ_TYPE_EDGE_RISING:
193 value |= BYT_TRIG_POS;
195 case IRQ_TYPE_LEVEL_LOW:
196 value |= BYT_TRIG_LVL;
197 case IRQ_TYPE_EDGE_FALLING:
198 value |= BYT_TRIG_NEG;
200 case IRQ_TYPE_EDGE_BOTH:
201 value |= (BYT_TRIG_NEG | BYT_TRIG_POS);
206 spin_unlock_irqrestore(&vg->lock, flags);
211 static int byt_gpio_get(struct gpio_chip *chip, unsigned offset)
213 void __iomem *reg = byt_gpio_reg(chip, offset, BYT_VAL_REG);
214 return readl(reg) & BYT_LEVEL;
217 static void byt_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
219 struct byt_gpio *vg = container_of(chip, struct byt_gpio, chip);
220 void __iomem *reg = byt_gpio_reg(chip, offset, BYT_VAL_REG);
224 spin_lock_irqsave(&vg->lock, flags);
226 old_val = readl(reg);
229 writel(old_val | BYT_LEVEL, reg);
231 writel(old_val & ~BYT_LEVEL, reg);
233 spin_unlock_irqrestore(&vg->lock, flags);
236 static int byt_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
238 struct byt_gpio *vg = container_of(chip, struct byt_gpio, chip);
239 void __iomem *reg = byt_gpio_reg(chip, offset, BYT_VAL_REG);
243 spin_lock_irqsave(&vg->lock, flags);
245 value = readl(reg) | BYT_DIR_MASK;
246 value = value & (~BYT_INPUT_EN); /* active low */
249 spin_unlock_irqrestore(&vg->lock, flags);
254 static int byt_gpio_direction_output(struct gpio_chip *chip,
255 unsigned gpio, int value)
257 struct byt_gpio *vg = container_of(chip, struct byt_gpio, chip);
258 void __iomem *reg = byt_gpio_reg(chip, gpio, BYT_VAL_REG);
262 spin_lock_irqsave(&vg->lock, flags);
264 reg_val = readl(reg) | (BYT_DIR_MASK | !!value);
265 reg_val &= ~(BYT_OUTPUT_EN | !value);
266 writel(reg_val, reg);
268 spin_unlock_irqrestore(&vg->lock, flags);
273 static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
275 struct byt_gpio *vg = container_of(chip, struct byt_gpio, chip);
278 u32 conf0, val, offs;
280 spin_lock_irqsave(&vg->lock, flags);
282 for (i = 0; i < vg->chip.ngpio; i++) {
283 offs = vg->range->pins[i] * 16;
284 conf0 = readl(vg->reg_base + offs + BYT_CONF0_REG);
285 val = readl(vg->reg_base + offs + BYT_VAL_REG);
288 " gpio-%-3d %s %s %s pad-%-3d offset:0x%03x mux:%d %s%s%s\n",
290 val & BYT_INPUT_EN ? " " : "in",
291 val & BYT_OUTPUT_EN ? " " : "out",
292 val & BYT_LEVEL ? "hi" : "lo",
293 vg->range->pins[i], offs,
295 conf0 & BYT_TRIG_NEG ? " fall" : "",
296 conf0 & BYT_TRIG_POS ? " rise" : "",
297 conf0 & BYT_TRIG_LVL ? " level" : "");
299 spin_unlock_irqrestore(&vg->lock, flags);
302 static int byt_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
304 struct byt_gpio *vg = container_of(chip, struct byt_gpio, chip);
305 return irq_create_mapping(vg->domain, offset);
308 static void byt_gpio_irq_handler(unsigned irq, struct irq_desc *desc)
310 struct irq_data *data = irq_desc_get_irq_data(desc);
311 struct byt_gpio *vg = irq_data_get_irq_handler_data(data);
312 struct irq_chip *chip = irq_data_get_irq_chip(data);
319 /* check from GPIO controller which pin triggered the interrupt */
320 for (base = 0; base < vg->chip.ngpio; base += 32) {
322 reg = byt_gpio_reg(&vg->chip, base, BYT_INT_STAT_REG);
324 while ((pending = readl(reg))) {
325 pin = __ffs(pending);
327 /* Clear before handling so we can't lose an edge */
330 virq = irq_find_mapping(vg->domain, base + pin);
331 generic_handle_irq(virq);
333 /* In case bios or user sets triggering incorretly a pin
334 * might remain in "interrupt triggered" state.
336 if (looplimit++ > 32) {
337 dev_err(&vg->pdev->dev,
338 "Gpio %d interrupt flood, disabling\n",
341 reg = byt_gpio_reg(&vg->chip, base + pin,
344 mask &= ~(BYT_TRIG_NEG | BYT_TRIG_POS |
347 mask = readl(reg); /* flush */
355 static void byt_irq_unmask(struct irq_data *d)
359 static void byt_irq_mask(struct irq_data *d)
363 static struct irq_chip byt_irqchip = {
365 .irq_mask = byt_irq_mask,
366 .irq_unmask = byt_irq_unmask,
367 .irq_set_type = byt_irq_type,
370 static void byt_gpio_irq_init_hw(struct byt_gpio *vg)
375 /* clear interrupt status trigger registers */
376 for (base = 0; base < vg->chip.ngpio; base += 32) {
377 reg = byt_gpio_reg(&vg->chip, base, BYT_INT_STAT_REG);
378 writel(0xffffffff, reg);
379 /* make sure trigger bits are cleared, if not then a pin
380 might be misconfigured in bios */
383 dev_err(&vg->pdev->dev,
384 "GPIO interrupt error, pins misconfigured\n");
388 static int byt_gpio_irq_map(struct irq_domain *d, unsigned int virq,
391 struct byt_gpio *vg = d->host_data;
393 irq_set_chip_and_handler_name(virq, &byt_irqchip, handle_simple_irq,
395 irq_set_chip_data(virq, vg);
396 irq_set_irq_type(virq, IRQ_TYPE_NONE);
401 static const struct irq_domain_ops byt_gpio_irq_ops = {
402 .map = byt_gpio_irq_map,
405 static int byt_gpio_probe(struct platform_device *pdev)
408 struct gpio_chip *gc;
409 struct resource *mem_rc, *irq_rc;
410 struct device *dev = &pdev->dev;
411 struct acpi_device *acpi_dev;
412 struct pinctrl_gpio_range *range;
413 acpi_handle handle = ACPI_HANDLE(dev);
417 if (acpi_bus_get_device(handle, &acpi_dev))
420 vg = devm_kzalloc(dev, sizeof(struct byt_gpio), GFP_KERNEL);
422 dev_err(&pdev->dev, "can't allocate byt_gpio chip data\n");
426 for (range = byt_ranges; range->name; range++) {
427 if (!strcmp(acpi_dev->pnp.unique_id, range->name)) {
428 vg->chip.ngpio = range->npins;
434 if (!vg->chip.ngpio || !vg->range)
438 platform_set_drvdata(pdev, vg);
440 mem_rc = platform_get_resource(pdev, IORESOURCE_MEM, 0);
441 vg->reg_base = devm_ioremap_resource(dev, mem_rc);
442 if (IS_ERR(vg->reg_base))
443 return PTR_ERR(vg->reg_base);
445 spin_lock_init(&vg->lock);
448 gc->label = dev_name(&pdev->dev);
449 gc->owner = THIS_MODULE;
450 gc->request = byt_gpio_request;
451 gc->free = byt_gpio_free;
452 gc->direction_input = byt_gpio_direction_input;
453 gc->direction_output = byt_gpio_direction_output;
454 gc->get = byt_gpio_get;
455 gc->set = byt_gpio_set;
456 gc->dbg_show = byt_gpio_dbg_show;
461 ret = gpiochip_add(gc);
463 dev_err(&pdev->dev, "failed adding byt-gpio chip\n");
467 /* set up interrupts */
468 irq_rc = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
469 if (irq_rc && irq_rc->start) {
470 hwirq = irq_rc->start;
471 gc->to_irq = byt_gpio_to_irq;
473 vg->domain = irq_domain_add_linear(NULL, gc->ngpio,
474 &byt_gpio_irq_ops, vg);
478 byt_gpio_irq_init_hw(vg);
480 irq_set_handler_data(hwirq, vg);
481 irq_set_chained_handler(hwirq, byt_gpio_irq_handler);
483 /* Register interrupt handlers for gpio signaled acpi events */
484 acpi_gpiochip_request_interrupts(gc);
487 pm_runtime_enable(dev);
492 static int byt_gpio_runtime_suspend(struct device *dev)
497 static int byt_gpio_runtime_resume(struct device *dev)
502 static const struct dev_pm_ops byt_gpio_pm_ops = {
503 .runtime_suspend = byt_gpio_runtime_suspend,
504 .runtime_resume = byt_gpio_runtime_resume,
507 static const struct acpi_device_id byt_gpio_acpi_match[] = {
511 MODULE_DEVICE_TABLE(acpi, byt_gpio_acpi_match);
513 static int byt_gpio_remove(struct platform_device *pdev)
515 struct byt_gpio *vg = platform_get_drvdata(pdev);
518 pm_runtime_disable(&pdev->dev);
519 err = gpiochip_remove(&vg->chip);
521 dev_warn(&pdev->dev, "failed to remove gpio_chip.\n");
526 static struct platform_driver byt_gpio_driver = {
527 .probe = byt_gpio_probe,
528 .remove = byt_gpio_remove,
531 .owner = THIS_MODULE,
532 .pm = &byt_gpio_pm_ops,
533 .acpi_match_table = ACPI_PTR(byt_gpio_acpi_match),
537 static int __init byt_gpio_init(void)
539 return platform_driver_register(&byt_gpio_driver);
542 subsys_initcall(byt_gpio_init);