drivers/pinctrl/pinctrl-exynos.c

   1 /*
   2  * Exynos specific support for Samsung pinctrl/gpiolib driver with eint support.
   3  *
   4  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  * Copyright (c) 2012 Linaro Ltd
   7  *              http://www.linaro.org
   8  *
   9  * Author: Thomas Abraham <thomas.ab@samsung.com>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * This file contains the Samsung Exynos specific information required by the
  17  * the Samsung pinctrl/gpiolib driver. It also includes the implementation of
  18  * external gpio and wakeup interrupt support.
  19  */
  20
  21 #include <linux/module.h>
  22 #include <linux/device.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/irqdomain.h>
  25 #include <linux/irq.h>
  26 #include <linux/irqchip/chained_irq.h>
  27 #include <linux/of_irq.h>
  28 #include <linux/io.h>
  29 #include <linux/slab.h>
  30 #include <linux/spinlock.h>
  31 #include <linux/err.h>
  32
  33 #include "pinctrl-samsung.h"
  34 #include "pinctrl-exynos.h"
  35
  36
  37 static struct samsung_pin_bank_type bank_type_off = {
  38         .fld_width = { 4, 1, 2, 2, 2, 2, },
  39         .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
  40 };
  41
  42 static struct samsung_pin_bank_type bank_type_alive = {
  43         .fld_width = { 4, 1, 2, 2, },
  44         .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
  45 };
  46
  47 /* list of external wakeup controllers supported */
  48 static const struct of_device_id exynos_wkup_irq_ids[] = {
  49         { .compatible = "samsung,exynos4210-wakeup-eint", },
  50         { }
  51 };
  52
  53 static void exynos_gpio_irq_mask(struct irq_data *irqd)
  54 {
  55         struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
  56         struct samsung_pinctrl_drv_data *d = bank->drvdata;
  57         unsigned long reg_mask = d->ctrl->geint_mask + bank->eint_offset;
  58         unsigned long mask;
  59         unsigned long flags;
  60
  61         spin_lock_irqsave(&bank->slock, flags);
  62
  63         mask = readl(d->virt_base + reg_mask);
  64         mask |= 1 << irqd->hwirq;
  65         writel(mask, d->virt_base + reg_mask);
  66
  67         spin_unlock_irqrestore(&bank->slock, flags);
  68 }
  69
  70 static void exynos_gpio_irq_ack(struct irq_data *irqd)
  71 {
  72         struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
  73         struct samsung_pinctrl_drv_data *d = bank->drvdata;
  74         unsigned long reg_pend = d->ctrl->geint_pend + bank->eint_offset;
  75
  76         writel(1 << irqd->hwirq, d->virt_base + reg_pend);
  77 }
  78
  79 static void exynos_gpio_irq_unmask(struct irq_data *irqd)
  80 {
  81         struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
  82         struct samsung_pinctrl_drv_data *d = bank->drvdata;
  83         unsigned long reg_mask = d->ctrl->geint_mask + bank->eint_offset;
  84         unsigned long mask;
  85         unsigned long flags;
  86
  87         /*
  88          * Ack level interrupts right before unmask
  89          *
  90          * If we don't do this we'll get a double-interrupt.  Level triggered
  91          * interrupts must not fire an interrupt if the level is not
  92          * _currently_ active, even if it was active while the interrupt was
  93          * masked.
  94          */
  95         if (irqd_get_trigger_type(irqd) & IRQ_TYPE_LEVEL_MASK)
  96                 exynos_gpio_irq_ack(irqd);
  97
  98         spin_lock_irqsave(&bank->slock, flags);
  99
 100         mask = readl(d->virt_base + reg_mask);
 101         mask &= ~(1 << irqd->hwirq);
 102         writel(mask, d->virt_base + reg_mask);
 103
 104         spin_unlock_irqrestore(&bank->slock, flags);
 105 }
 106
 107 static int exynos_gpio_irq_set_type(struct irq_data *irqd, unsigned int type)
 108 {
 109         struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
 110         struct samsung_pin_bank_type *bank_type = bank->type;
 111         struct samsung_pinctrl_drv_data *d = bank->drvdata;
 112         struct samsung_pin_ctrl *ctrl = d->ctrl;
 113         unsigned int pin = irqd->hwirq;
 114         unsigned int shift = EXYNOS_EINT_CON_LEN * pin;
 115         unsigned int con, trig_type;
 116         unsigned long reg_con = ctrl->geint_con + bank->eint_offset;
 117         unsigned long flags;
 118         unsigned int mask;
 119
 120         switch (type) {
 121         case IRQ_TYPE_EDGE_RISING:
 122                 trig_type = EXYNOS_EINT_EDGE_RISING;
 123                 break;
 124         case IRQ_TYPE_EDGE_FALLING:
 125                 trig_type = EXYNOS_EINT_EDGE_FALLING;
 126                 break;
 127         case IRQ_TYPE_EDGE_BOTH:
 128                 trig_type = EXYNOS_EINT_EDGE_BOTH;
 129                 break;
 130         case IRQ_TYPE_LEVEL_HIGH:
 131                 trig_type = EXYNOS_EINT_LEVEL_HIGH;
 132                 break;
 133         case IRQ_TYPE_LEVEL_LOW:
 134                 trig_type = EXYNOS_EINT_LEVEL_LOW;
 135                 break;
 136         default:
 137                 pr_err("unsupported external interrupt type\n");
 138                 return -EINVAL;
 139         }
 140
 141         if (type & IRQ_TYPE_EDGE_BOTH)
 142                 __irq_set_handler_locked(irqd->irq, handle_edge_irq);
 143         else
 144                 __irq_set_handler_locked(irqd->irq, handle_level_irq);
 145
 146         con = readl(d->virt_base + reg_con);
 147         con &= ~(EXYNOS_EINT_CON_MASK << shift);
 148         con |= trig_type << shift;
 149         writel(con, d->virt_base + reg_con);
 150
 151         reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC];
 152         shift = pin * bank_type->fld_width[PINCFG_TYPE_FUNC];
 153         mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;
 154
 155         spin_lock_irqsave(&bank->slock, flags);
 156
 157         con = readl(d->virt_base + reg_con);
 158         con &= ~(mask << shift);
 159         con |= EXYNOS_EINT_FUNC << shift;
 160         writel(con, d->virt_base + reg_con);
 161
 162         spin_unlock_irqrestore(&bank->slock, flags);
 163
 164         return 0;
 165 }
 166
 167 /*
 168  * irq_chip for gpio interrupts.
 169  */
 170 static struct irq_chip exynos_gpio_irq_chip = {
 171         .name           = "exynos_gpio_irq_chip",
 172         .irq_unmask     = exynos_gpio_irq_unmask,
 173         .irq_mask       = exynos_gpio_irq_mask,
 174         .irq_ack                = exynos_gpio_irq_ack,
 175         .irq_set_type   = exynos_gpio_irq_set_type,
 176 };
 177
 178 static int exynos_gpio_irq_map(struct irq_domain *h, unsigned int virq,
 179                                         irq_hw_number_t hw)
 180 {
 181         struct samsung_pin_bank *b = h->host_data;
 182
 183         irq_set_chip_data(virq, b);
 184         irq_set_chip_and_handler(virq, &exynos_gpio_irq_chip,
 185                                         handle_level_irq);
 186         set_irq_flags(virq, IRQF_VALID);
 187         return 0;
 188 }
 189
 190 /*
 191  * irq domain callbacks for external gpio interrupt controller.
 192  */
 193 static const struct irq_domain_ops exynos_gpio_irqd_ops = {
 194         .map    = exynos_gpio_irq_map,
 195         .xlate  = irq_domain_xlate_twocell,
 196 };
 197
 198 static irqreturn_t exynos_eint_gpio_irq(int irq, void *data)
 199 {
 200         struct samsung_pinctrl_drv_data *d = data;
 201         struct samsung_pin_ctrl *ctrl = d->ctrl;
 202         struct samsung_pin_bank *bank = ctrl->pin_banks;
 203         unsigned int svc, group, pin, virq;
 204
 205         svc = readl(d->virt_base + ctrl->svc);
 206         group = EXYNOS_SVC_GROUP(svc);
 207         pin = svc & EXYNOS_SVC_NUM_MASK;
 208
 209         if (!group)
 210                 return IRQ_HANDLED;
 211         bank += (group - 1);
 212
 213         virq = irq_linear_revmap(bank->irq_domain, pin);
 214         if (!virq)
 215                 return IRQ_NONE;
 216         generic_handle_irq(virq);
 217         return IRQ_HANDLED;
 218 }
 219
 220 struct exynos_eint_gpio_save {
 221         u32 eint_con;
 222         u32 eint_fltcon0;
 223         u32 eint_fltcon1;
 224 };
 225
 226 /*
 227  * exynos_eint_gpio_init() - setup handling of external gpio interrupts.
 228  * @d: driver data of samsung pinctrl driver.
 229  */
 230 static int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d)
 231 {
 232         struct samsung_pin_bank *bank;
 233         struct device *dev = d->dev;
 234         int ret;
 235         int i;
 236
 237         if (!d->irq) {
 238                 dev_err(dev, "irq number not available\n");
 239                 return -EINVAL;
 240         }
 241
 242         ret = devm_request_irq(dev, d->irq, exynos_eint_gpio_irq,
 243                                         0, dev_name(dev), d);
 244         if (ret) {
 245                 dev_err(dev, "irq request failed\n");
 246                 return -ENXIO;
 247         }
 248
 249         bank = d->ctrl->pin_banks;
 250         for (i = 0; i < d->ctrl->nr_banks; ++i, ++bank) {
 251                 if (bank->eint_type != EINT_TYPE_GPIO)
 252                         continue;
 253                 bank->irq_domain = irq_domain_add_linear(bank->of_node,
 254                                 bank->nr_pins, &exynos_gpio_irqd_ops, bank);
 255                 if (!bank->irq_domain) {
 256                         dev_err(dev, "gpio irq domain add failed\n");
 257                         ret = -ENXIO;
 258                         goto err_domains;
 259                 }
 260
 261                 bank->soc_priv = devm_kzalloc(d->dev,
 262                         sizeof(struct exynos_eint_gpio_save), GFP_KERNEL);
 263                 if (!bank->soc_priv) {
 264                         irq_domain_remove(bank->irq_domain);
 265                         ret = -ENOMEM;
 266                         goto err_domains;
 267                 }
 268         }
 269
 270         return 0;
 271
 272 err_domains:
 273         for (--i, --bank; i >= 0; --i, --bank) {
 274                 if (bank->eint_type != EINT_TYPE_GPIO)
 275                         continue;
 276                 irq_domain_remove(bank->irq_domain);
 277         }
 278
 279         return ret;
 280 }
 281
 282 static void exynos_wkup_irq_mask(struct irq_data *irqd)
 283 {
 284         struct samsung_pin_bank *b = irq_data_get_irq_chip_data(irqd);
 285         struct samsung_pinctrl_drv_data *d = b->drvdata;
 286         unsigned long reg_mask = d->ctrl->weint_mask + b->eint_offset;
 287         unsigned long mask;
 288         unsigned long flags;
 289
 290         spin_lock_irqsave(&b->slock, flags);
 291
 292         mask = readl(d->virt_base + reg_mask);
 293         mask |= 1 << irqd->hwirq;
 294         writel(mask, d->virt_base + reg_mask);
 295
 296         spin_unlock_irqrestore(&b->slock, flags);
 297 }
 298
 299 static void exynos_wkup_irq_ack(struct irq_data *irqd)
 300 {
 301         struct samsung_pin_bank *b = irq_data_get_irq_chip_data(irqd);
 302         struct samsung_pinctrl_drv_data *d = b->drvdata;
 303         unsigned long pend = d->ctrl->weint_pend + b->eint_offset;
 304
 305         writel(1 << irqd->hwirq, d->virt_base + pend);
 306 }
 307
 308 static void exynos_wkup_irq_unmask(struct irq_data *irqd)
 309 {
 310         struct samsung_pin_bank *b = irq_data_get_irq_chip_data(irqd);
 311         struct samsung_pinctrl_drv_data *d = b->drvdata;
 312         unsigned long reg_mask = d->ctrl->weint_mask + b->eint_offset;
 313         unsigned long mask;
 314         unsigned long flags;
 315
 316         /*
 317          * Ack level interrupts right before unmask
 318          *
 319          * If we don't do this we'll get a double-interrupt.  Level triggered
 320          * interrupts must not fire an interrupt if the level is not
 321          * _currently_ active, even if it was active while the interrupt was
 322          * masked.
 323          */
 324         if (irqd_get_trigger_type(irqd) & IRQ_TYPE_LEVEL_MASK)
 325                 exynos_wkup_irq_ack(irqd);
 326
 327         spin_lock_irqsave(&b->slock, flags);
 328
 329         mask = readl(d->virt_base + reg_mask);
 330         mask &= ~(1 << irqd->hwirq);
 331         writel(mask, d->virt_base + reg_mask);
 332
 333         spin_unlock_irqrestore(&b->slock, flags);
 334 }
 335
 336 static int exynos_wkup_irq_set_type(struct irq_data *irqd, unsigned int type)
 337 {
 338         struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
 339         struct samsung_pin_bank_type *bank_type = bank->type;
 340         struct samsung_pinctrl_drv_data *d = bank->drvdata;
 341         unsigned int pin = irqd->hwirq;
 342         unsigned long reg_con = d->ctrl->weint_con + bank->eint_offset;
 343         unsigned long shift = EXYNOS_EINT_CON_LEN * pin;
 344         unsigned long con, trig_type;
 345         unsigned long flags;
 346         unsigned int mask;
 347
 348         switch (type) {
 349         case IRQ_TYPE_EDGE_RISING:
 350                 trig_type = EXYNOS_EINT_EDGE_RISING;
 351                 break;
 352         case IRQ_TYPE_EDGE_FALLING:
 353                 trig_type = EXYNOS_EINT_EDGE_FALLING;
 354                 break;
 355         case IRQ_TYPE_EDGE_BOTH:
 356                 trig_type = EXYNOS_EINT_EDGE_BOTH;
 357                 break;
 358         case IRQ_TYPE_LEVEL_HIGH:
 359                 trig_type = EXYNOS_EINT_LEVEL_HIGH;
 360                 break;
 361         case IRQ_TYPE_LEVEL_LOW:
 362                 trig_type = EXYNOS_EINT_LEVEL_LOW;
 363                 break;
 364         default:
 365                 pr_err("unsupported external interrupt type\n");
 366                 return -EINVAL;
 367         }
 368
 369         if (type & IRQ_TYPE_EDGE_BOTH)
 370                 __irq_set_handler_locked(irqd->irq, handle_edge_irq);
 371         else
 372                 __irq_set_handler_locked(irqd->irq, handle_level_irq);
 373
 374         con = readl(d->virt_base + reg_con);
 375         con &= ~(EXYNOS_EINT_CON_MASK << shift);
 376         con |= trig_type << shift;
 377         writel(con, d->virt_base + reg_con);
 378
 379         reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC];
 380         shift = pin * bank_type->fld_width[PINCFG_TYPE_FUNC];
 381         mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;
 382
 383         spin_lock_irqsave(&bank->slock, flags);
 384
 385         con = readl(d->virt_base + reg_con);
 386         con &= ~(mask << shift);
 387         con |= EXYNOS_EINT_FUNC << shift;
 388         writel(con, d->virt_base + reg_con);
 389
 390         spin_unlock_irqrestore(&bank->slock, flags);
 391
 392         return 0;
 393 }
 394
 395 static u32 exynos_eint_wake_mask = 0xffffffff;
 396
 397 u32 exynos_get_eint_wake_mask(void)
 398 {
 399         return exynos_eint_wake_mask;
 400 }
 401
 402 static int exynos_wkup_irq_set_wake(struct irq_data *irqd, unsigned int on)
 403 {
 404         struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
 405         unsigned long bit = 1UL << (2 * bank->eint_offset + irqd->hwirq);
 406
 407         pr_info("wake %s for irq %d\n", on ? "enabled" : "disabled", irqd->irq);
 408
 409         if (!on)
 410                 exynos_eint_wake_mask |= bit;
 411         else
 412                 exynos_eint_wake_mask &= ~bit;
 413
 414         return 0;
 415 }
 416
 417 /*
 418  * irq_chip for wakeup interrupts
 419  */
 420 static struct irq_chip exynos_wkup_irq_chip = {
 421         .name   = "exynos_wkup_irq_chip",
 422         .irq_unmask     = exynos_wkup_irq_unmask,
 423         .irq_mask       = exynos_wkup_irq_mask,
 424         .irq_ack        = exynos_wkup_irq_ack,
 425         .irq_set_type   = exynos_wkup_irq_set_type,
 426         .irq_set_wake   = exynos_wkup_irq_set_wake,
 427 };
 428
 429 /* interrupt handler for wakeup interrupts 0..15 */
 430 static void exynos_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
 431 {
 432         struct exynos_weint_data *eintd = irq_get_handler_data(irq);
 433         struct samsung_pin_bank *bank = eintd->bank;
 434         struct irq_chip *chip = irq_get_chip(irq);
 435         int eint_irq;
 436
 437         chained_irq_enter(chip, desc);
 438         chip->irq_mask(&desc->irq_data);
 439
 440         if (chip->irq_ack)
 441                 chip->irq_ack(&desc->irq_data);
 442
 443         eint_irq = irq_linear_revmap(bank->irq_domain, eintd->irq);
 444         generic_handle_irq(eint_irq);
 445         chip->irq_unmask(&desc->irq_data);
 446         chained_irq_exit(chip, desc);
 447 }
 448
 449 static inline void exynos_irq_demux_eint(unsigned long pend,
 450                                                 struct irq_domain *domain)
 451 {
 452         unsigned int irq;
 453
 454         while (pend) {
 455                 irq = fls(pend) - 1;
 456                 generic_handle_irq(irq_find_mapping(domain, irq));
 457                 pend &= ~(1 << irq);
 458         }
 459 }
 460
 461 /* interrupt handler for wakeup interrupt 16 */
 462 static void exynos_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
 463 {
 464         struct irq_chip *chip = irq_get_chip(irq);
 465         struct exynos_muxed_weint_data *eintd = irq_get_handler_data(irq);
 466         struct samsung_pinctrl_drv_data *d = eintd->banks[0]->drvdata;
 467         struct samsung_pin_ctrl *ctrl = d->ctrl;
 468         unsigned long pend;
 469         unsigned long mask;
 470         int i;
 471
 472         chained_irq_enter(chip, desc);
 473
 474         for (i = 0; i < eintd->nr_banks; ++i) {
 475                 struct samsung_pin_bank *b = eintd->banks[i];
 476                 pend = readl(d->virt_base + ctrl->weint_pend + b->eint_offset);
 477                 mask = readl(d->virt_base + ctrl->weint_mask + b->eint_offset);
 478                 exynos_irq_demux_eint(pend & ~mask, b->irq_domain);
 479         }
 480
 481         chained_irq_exit(chip, desc);
 482 }
 483
 484 static int exynos_wkup_irq_map(struct irq_domain *h, unsigned int virq,
 485                                         irq_hw_number_t hw)
 486 {
 487         irq_set_chip_and_handler(virq, &exynos_wkup_irq_chip, handle_level_irq);
 488         irq_set_chip_data(virq, h->host_data);
 489         set_irq_flags(virq, IRQF_VALID);
 490         return 0;
 491 }
 492
 493 /*
 494  * irq domain callbacks for external wakeup interrupt controller.
 495  */
 496 static const struct irq_domain_ops exynos_wkup_irqd_ops = {
 497         .map    = exynos_wkup_irq_map,
 498         .xlate  = irq_domain_xlate_twocell,
 499 };
 500
 501 /*
 502  * exynos_eint_wkup_init() - setup handling of external wakeup interrupts.
 503  * @d: driver data of samsung pinctrl driver.
 504  */
 505 static int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d)
 506 {
 507         struct device *dev = d->dev;
 508         struct device_node *wkup_np = NULL;
 509         struct device_node *np;
 510         struct samsung_pin_bank *bank;
 511         struct exynos_weint_data *weint_data;
 512         struct exynos_muxed_weint_data *muxed_data;
 513         unsigned int muxed_banks = 0;
 514         unsigned int i;
 515         int idx, irq;
 516
 517         for_each_child_of_node(dev->of_node, np) {
 518                 if (of_match_node(exynos_wkup_irq_ids, np)) {
 519                         wkup_np = np;
 520                         break;
 521                 }
 522         }
 523         if (!wkup_np)
 524                 return -ENODEV;
 525
 526         bank = d->ctrl->pin_banks;
 527         for (i = 0; i < d->ctrl->nr_banks; ++i, ++bank) {
 528                 if (bank->eint_type != EINT_TYPE_WKUP)
 529                         continue;
 530
 531                 bank->irq_domain = irq_domain_add_linear(bank->of_node,
 532                                 bank->nr_pins, &exynos_wkup_irqd_ops, bank);
 533                 if (!bank->irq_domain) {
 534                         dev_err(dev, "wkup irq domain add failed\n");
 535                         return -ENXIO;
 536                 }
 537
 538                 if (!of_find_property(bank->of_node, "interrupts", NULL)) {
 539                         bank->eint_type = EINT_TYPE_WKUP_MUX;
 540                         ++muxed_banks;
 541                         continue;
 542                 }
 543
 544                 weint_data = devm_kzalloc(dev, bank->nr_pins
 545                                         * sizeof(*weint_data), GFP_KERNEL);
 546                 if (!weint_data) {
 547                         dev_err(dev, "could not allocate memory for weint_data\n");
 548                         return -ENOMEM;
 549                 }
 550
 551                 for (idx = 0; idx < bank->nr_pins; ++idx) {
 552                         irq = irq_of_parse_and_map(bank->of_node, idx);
 553                         if (!irq) {
 554                                 dev_err(dev, "irq number for eint-%s-%d not found\n",
 555                                                         bank->name, idx);
 556                                 continue;
 557                         }
 558                         weint_data[idx].irq = idx;
 559                         weint_data[idx].bank = bank;
 560                         irq_set_handler_data(irq, &weint_data[idx]);
 561                         irq_set_chained_handler(irq, exynos_irq_eint0_15);
 562                 }
 563         }
 564
 565         if (!muxed_banks)
 566                 return 0;
 567
 568         irq = irq_of_parse_and_map(wkup_np, 0);
 569         if (!irq) {
 570                 dev_err(dev, "irq number for muxed EINTs not found\n");
 571                 return 0;
 572         }
 573
 574         muxed_data = devm_kzalloc(dev, sizeof(*muxed_data)
 575                 + muxed_banks*sizeof(struct samsung_pin_bank *), GFP_KERNEL);
 576         if (!muxed_data) {
 577                 dev_err(dev, "could not allocate memory for muxed_data\n");
 578                 return -ENOMEM;
 579         }
 580
 581         irq_set_chained_handler(irq, exynos_irq_demux_eint16_31);
 582         irq_set_handler_data(irq, muxed_data);
 583
 584         bank = d->ctrl->pin_banks;
 585         idx = 0;
 586         for (i = 0; i < d->ctrl->nr_banks; ++i, ++bank) {
 587                 if (bank->eint_type != EINT_TYPE_WKUP_MUX)
 588                         continue;
 589
 590                 muxed_data->banks[idx++] = bank;
 591         }
 592         muxed_data->nr_banks = muxed_banks;
 593
 594         return 0;
 595 }
 596
 597 static void exynos_pinctrl_suspend_bank(
 598                                 struct samsung_pinctrl_drv_data *drvdata,
 599                                 struct samsung_pin_bank *bank)
 600 {
 601         struct exynos_eint_gpio_save *save = bank->soc_priv;
 602         void __iomem *regs = drvdata->virt_base;
 603
 604         save->eint_con = readl(regs + EXYNOS_GPIO_ECON_OFFSET
 605                                                 + bank->eint_offset);
 606         save->eint_fltcon0 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
 607                                                 + 2 * bank->eint_offset);
 608         save->eint_fltcon1 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
 609                                                 + 2 * bank->eint_offset + 4);
 610
 611         pr_debug("%s: save     con %#010x\n", bank->name, save->eint_con);
 612         pr_debug("%s: save fltcon0 %#010x\n", bank->name, save->eint_fltcon0);
 613         pr_debug("%s: save fltcon1 %#010x\n", bank->name, save->eint_fltcon1);
 614 }
 615
 616 static void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata)
 617 {
 618         struct samsung_pin_ctrl *ctrl = drvdata->ctrl;
 619         struct samsung_pin_bank *bank = ctrl->pin_banks;
 620         int i;
 621
 622         for (i = 0; i < ctrl->nr_banks; ++i, ++bank)
 623                 if (bank->eint_type == EINT_TYPE_GPIO)
 624                         exynos_pinctrl_suspend_bank(drvdata, bank);
 625 }
 626
 627 static void exynos_pinctrl_resume_bank(
 628                                 struct samsung_pinctrl_drv_data *drvdata,
 629                                 struct samsung_pin_bank *bank)
 630 {
 631         struct exynos_eint_gpio_save *save = bank->soc_priv;
 632         void __iomem *regs = drvdata->virt_base;
 633
 634         pr_debug("%s:     con %#010x => %#010x\n", bank->name,
 635                         readl(regs + EXYNOS_GPIO_ECON_OFFSET
 636                         + bank->eint_offset), save->eint_con);
 637         pr_debug("%s: fltcon0 %#010x => %#010x\n", bank->name,
 638                         readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
 639                         + 2 * bank->eint_offset), save->eint_fltcon0);
 640         pr_debug("%s: fltcon1 %#010x => %#010x\n", bank->name,
 641                         readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
 642                         + 2 * bank->eint_offset + 4), save->eint_fltcon1);
 643
 644         writel(save->eint_con, regs + EXYNOS_GPIO_ECON_OFFSET
 645                                                 + bank->eint_offset);
 646         writel(save->eint_fltcon0, regs + EXYNOS_GPIO_EFLTCON_OFFSET
 647                                                 + 2 * bank->eint_offset);
 648         writel(save->eint_fltcon1, regs + EXYNOS_GPIO_EFLTCON_OFFSET
 649                                                 + 2 * bank->eint_offset + 4);
 650 }
 651
 652 static void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata)
 653 {
 654         struct samsung_pin_ctrl *ctrl = drvdata->ctrl;
 655         struct samsung_pin_bank *bank = ctrl->pin_banks;
 656         int i;
 657
 658         for (i = 0; i < ctrl->nr_banks; ++i, ++bank)
 659                 if (bank->eint_type == EINT_TYPE_GPIO)
 660                         exynos_pinctrl_resume_bank(drvdata, bank);
 661 }
 662
 663 /* pin banks of s5pv210 pin-controller */
 664 static struct samsung_pin_bank s5pv210_pin_bank[] = {
 665         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
 666         EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpa1", 0x04),
 667         EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
 668         EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
 669         EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
 670         EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14),
 671         EXYNOS_PIN_BANK_EINTG(6, 0x0c0, "gpd1", 0x18),
 672         EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpe0", 0x1c),
 673         EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpe1", 0x20),
 674         EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpf0", 0x24),
 675         EXYNOS_PIN_BANK_EINTG(8, 0x140, "gpf1", 0x28),
 676         EXYNOS_PIN_BANK_EINTG(8, 0x160, "gpf2", 0x2c),
 677         EXYNOS_PIN_BANK_EINTG(6, 0x180, "gpf3", 0x30),
 678         EXYNOS_PIN_BANK_EINTG(7, 0x1a0, "gpg0", 0x34),
 679         EXYNOS_PIN_BANK_EINTG(7, 0x1c0, "gpg1", 0x38),
 680         EXYNOS_PIN_BANK_EINTG(7, 0x1e0, "gpg2", 0x3c),
 681         EXYNOS_PIN_BANK_EINTG(7, 0x200, "gpg3", 0x40),
 682         EXYNOS_PIN_BANK_EINTN(7, 0x220, "gpi"),
 683         EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpj0", 0x44),
 684         EXYNOS_PIN_BANK_EINTG(6, 0x260, "gpj1", 0x48),
 685         EXYNOS_PIN_BANK_EINTG(8, 0x280, "gpj2", 0x4c),
 686         EXYNOS_PIN_BANK_EINTG(8, 0x2a0, "gpj3", 0x50),
 687         EXYNOS_PIN_BANK_EINTG(5, 0x2c0, "gpj4", 0x54),
 688         EXYNOS_PIN_BANK_EINTN(8, 0x2e0, "mp01"),
 689         EXYNOS_PIN_BANK_EINTN(4, 0x300, "mp02"),
 690         EXYNOS_PIN_BANK_EINTN(8, 0x320, "mp03"),
 691         EXYNOS_PIN_BANK_EINTN(8, 0x340, "mp04"),
 692         EXYNOS_PIN_BANK_EINTN(8, 0x360, "mp05"),
 693         EXYNOS_PIN_BANK_EINTN(8, 0x380, "mp06"),
 694         EXYNOS_PIN_BANK_EINTN(8, 0x3a0, "mp07"),
 695         EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gph0", 0x00),
 696         EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gph1", 0x04),
 697         EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gph2", 0x08),
 698         EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gph3", 0x0c),
 699 };
 700
 701 struct samsung_pin_ctrl s5pv210_pin_ctrl[] = {
 702         {
 703                 /* pin-controller instance 0 data */
 704                 .pin_banks      = s5pv210_pin_bank,
 705                 .nr_banks       = ARRAY_SIZE(s5pv210_pin_bank),
 706                 .geint_con      = EXYNOS_GPIO_ECON_OFFSET,
 707                 .geint_mask     = EXYNOS_GPIO_EMASK_OFFSET,
 708                 .geint_pend     = EXYNOS_GPIO_EPEND_OFFSET,
 709                 .weint_con      = EXYNOS_WKUP_ECON_OFFSET,
 710                 .weint_mask     = EXYNOS_WKUP_EMASK_OFFSET,
 711                 .weint_pend     = EXYNOS_WKUP_EPEND_OFFSET,
 712                 .svc            = EXYNOS_SVC_OFFSET,
 713                 .eint_gpio_init = exynos_eint_gpio_init,
 714                 .eint_wkup_init = exynos_eint_wkup_init,
 715                 .suspend        = exynos_pinctrl_suspend,
 716                 .resume         = exynos_pinctrl_resume,
 717                 .label          = "s5pv210-gpio-ctrl0",
 718         },
 719 };
 720
 721 /* pin banks of exynos4210 pin-controller 0 */
 722 static struct samsung_pin_bank exynos4210_pin_banks0[] = {
 723         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
 724         EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
 725         EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
 726         EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
 727         EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
 728         EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14),
 729         EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18),
 730         EXYNOS_PIN_BANK_EINTG(5, 0x0E0, "gpe0", 0x1c),
 731         EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpe1", 0x20),
 732         EXYNOS_PIN_BANK_EINTG(6, 0x120, "gpe2", 0x24),
 733         EXYNOS_PIN_BANK_EINTG(8, 0x140, "gpe3", 0x28),
 734         EXYNOS_PIN_BANK_EINTG(8, 0x160, "gpe4", 0x2c),
 735         EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30),
 736         EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34),
 737         EXYNOS_PIN_BANK_EINTG(8, 0x1C0, "gpf2", 0x38),
 738         EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf3", 0x3c),
 739 };
 740
 741 /* pin banks of exynos4210 pin-controller 1 */
 742 static struct samsung_pin_bank exynos4210_pin_banks1[] = {
 743         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpj0", 0x00),
 744         EXYNOS_PIN_BANK_EINTG(5, 0x020, "gpj1", 0x04),
 745         EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08),
 746         EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c),
 747         EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10),
 748         EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14),
 749         EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpl0", 0x18),
 750         EXYNOS_PIN_BANK_EINTG(3, 0x0E0, "gpl1", 0x1c),
 751         EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpl2", 0x20),
 752         EXYNOS_PIN_BANK_EINTN(6, 0x120, "gpy0"),
 753         EXYNOS_PIN_BANK_EINTN(4, 0x140, "gpy1"),
 754         EXYNOS_PIN_BANK_EINTN(6, 0x160, "gpy2"),
 755         EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy3"),
 756         EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "gpy4"),
 757         EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "gpy5"),
 758         EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "gpy6"),
 759         EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
 760         EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
 761         EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
 762         EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
 763 };
 764
 765 /* pin banks of exynos4210 pin-controller 2 */
 766 static struct samsung_pin_bank exynos4210_pin_banks2[] = {
 767         EXYNOS_PIN_BANK_EINTN(7, 0x000, "gpz"),
 768 };
 769
 770 /*
 771  * Samsung pinctrl driver data for Exynos4210 SoC. Exynos4210 SoC includes
 772  * three gpio/pin-mux/pinconfig controllers.
 773  */
 774 struct samsung_pin_ctrl exynos4210_pin_ctrl[] = {
 775         {
 776                 /* pin-controller instance 0 data */
 777                 .pin_banks      = exynos4210_pin_banks0,
 778                 .nr_banks       = ARRAY_SIZE(exynos4210_pin_banks0),
 779                 .geint_con      = EXYNOS_GPIO_ECON_OFFSET,
 780                 .geint_mask     = EXYNOS_GPIO_EMASK_OFFSET,
 781                 .geint_pend     = EXYNOS_GPIO_EPEND_OFFSET,
 782                 .svc            = EXYNOS_SVC_OFFSET,
 783                 .eint_gpio_init = exynos_eint_gpio_init,
 784                 .suspend        = exynos_pinctrl_suspend,
 785                 .resume         = exynos_pinctrl_resume,
 786                 .label          = "exynos4210-gpio-ctrl0",
 787         }, {
 788                 /* pin-controller instance 1 data */
 789                 .pin_banks      = exynos4210_pin_banks1,
 790                 .nr_banks       = ARRAY_SIZE(exynos4210_pin_banks1),
 791                 .geint_con      = EXYNOS_GPIO_ECON_OFFSET,
 792                 .geint_mask     = EXYNOS_GPIO_EMASK_OFFSET,
 793                 .geint_pend     = EXYNOS_GPIO_EPEND_OFFSET,
 794                 .weint_con      = EXYNOS_WKUP_ECON_OFFSET,
 795                 .weint_mask     = EXYNOS_WKUP_EMASK_OFFSET,
 796                 .weint_pend     = EXYNOS_WKUP_EPEND_OFFSET,
 797                 .svc            = EXYNOS_SVC_OFFSET,
 798                 .eint_gpio_init = exynos_eint_gpio_init,
 799                 .eint_wkup_init = exynos_eint_wkup_init,
 800                 .suspend        = exynos_pinctrl_suspend,
 801                 .resume         = exynos_pinctrl_resume,
 802                 .label          = "exynos4210-gpio-ctrl1",
 803         }, {
 804                 /* pin-controller instance 2 data */
 805                 .pin_banks      = exynos4210_pin_banks2,
 806                 .nr_banks       = ARRAY_SIZE(exynos4210_pin_banks2),
 807                 .label          = "exynos4210-gpio-ctrl2",
 808         },
 809 };
 810
 811 /* pin banks of exynos4x12 pin-controller 0 */
 812 static struct samsung_pin_bank exynos4x12_pin_banks0[] = {
 813         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
 814         EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
 815         EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
 816         EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
 817         EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
 818         EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14),
 819         EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18),
 820         EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30),
 821         EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34),
 822         EXYNOS_PIN_BANK_EINTG(8, 0x1C0, "gpf2", 0x38),
 823         EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf3", 0x3c),
 824         EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpj0", 0x40),
 825         EXYNOS_PIN_BANK_EINTG(5, 0x260, "gpj1", 0x44),
 826 };
 827
 828 /* pin banks of exynos4x12 pin-controller 1 */
 829 static struct samsung_pin_bank exynos4x12_pin_banks1[] = {
 830         EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08),
 831         EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c),
 832         EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10),
 833         EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14),
 834         EXYNOS_PIN_BANK_EINTG(7, 0x0C0, "gpl0", 0x18),
 835         EXYNOS_PIN_BANK_EINTG(2, 0x0E0, "gpl1", 0x1c),
 836         EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpl2", 0x20),
 837         EXYNOS_PIN_BANK_EINTG(8, 0x260, "gpm0", 0x24),
 838         EXYNOS_PIN_BANK_EINTG(7, 0x280, "gpm1", 0x28),
 839         EXYNOS_PIN_BANK_EINTG(5, 0x2A0, "gpm2", 0x2c),
 840         EXYNOS_PIN_BANK_EINTG(8, 0x2C0, "gpm3", 0x30),
 841         EXYNOS_PIN_BANK_EINTG(8, 0x2E0, "gpm4", 0x34),
 842         EXYNOS_PIN_BANK_EINTN(6, 0x120, "gpy0"),
 843         EXYNOS_PIN_BANK_EINTN(4, 0x140, "gpy1"),
 844         EXYNOS_PIN_BANK_EINTN(6, 0x160, "gpy2"),
 845         EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy3"),
 846         EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "gpy4"),
 847         EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "gpy5"),
 848         EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "gpy6"),
 849         EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
 850         EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
 851         EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
 852         EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
 853 };
 854
 855 /* pin banks of exynos4x12 pin-controller 2 */
 856 static struct samsung_pin_bank exynos4x12_pin_banks2[] = {
 857         EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
 858 };
 859
 860 /* pin banks of exynos4x12 pin-controller 3 */
 861 static struct samsung_pin_bank exynos4x12_pin_banks3[] = {
 862         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00),
 863         EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04),
 864         EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpv2", 0x08),
 865         EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv3", 0x0c),
 866         EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpv4", 0x10),
 867 };
 868
 869 /*
 870  * Samsung pinctrl driver data for Exynos4x12 SoC. Exynos4x12 SoC includes
 871  * four gpio/pin-mux/pinconfig controllers.
 872  */
 873 struct samsung_pin_ctrl exynos4x12_pin_ctrl[] = {
 874         {
 875                 /* pin-controller instance 0 data */
 876                 .pin_banks      = exynos4x12_pin_banks0,
 877                 .nr_banks       = ARRAY_SIZE(exynos4x12_pin_banks0),
 878                 .geint_con      = EXYNOS_GPIO_ECON_OFFSET,
 879                 .geint_mask     = EXYNOS_GPIO_EMASK_OFFSET,
 880                 .geint_pend     = EXYNOS_GPIO_EPEND_OFFSET,
 881                 .svc            = EXYNOS_SVC_OFFSET,
 882                 .eint_gpio_init = exynos_eint_gpio_init,
 883                 .suspend        = exynos_pinctrl_suspend,
 884                 .resume         = exynos_pinctrl_resume,
 885                 .label          = "exynos4x12-gpio-ctrl0",
 886         }, {
 887                 /* pin-controller instance 1 data */
 888                 .pin_banks      = exynos4x12_pin_banks1,
 889                 .nr_banks       = ARRAY_SIZE(exynos4x12_pin_banks1),
 890                 .geint_con      = EXYNOS_GPIO_ECON_OFFSET,
 891                 .geint_mask     = EXYNOS_GPIO_EMASK_OFFSET,
 892                 .geint_pend     = EXYNOS_GPIO_EPEND_OFFSET,
 893                 .weint_con      = EXYNOS_WKUP_ECON_OFFSET,
 894                 .weint_mask     = EXYNOS_WKUP_EMASK_OFFSET,
 895                 .weint_pend     = EXYNOS_WKUP_EPEND_OFFSET,
 896                 .svc            = EXYNOS_SVC_OFFSET,
 897                 .eint_gpio_init = exynos_eint_gpio_init,
 898                 .eint_wkup_init = exynos_eint_wkup_init,
 899                 .suspend        = exynos_pinctrl_suspend,
 900                 .resume         = exynos_pinctrl_resume,
 901                 .label          = "exynos4x12-gpio-ctrl1",
 902         }, {
 903                 /* pin-controller instance 2 data */
 904                 .pin_banks      = exynos4x12_pin_banks2,
 905                 .nr_banks       = ARRAY_SIZE(exynos4x12_pin_banks2),
 906                 .geint_con      = EXYNOS_GPIO_ECON_OFFSET,
 907                 .geint_mask     = EXYNOS_GPIO_EMASK_OFFSET,
 908                 .geint_pend     = EXYNOS_GPIO_EPEND_OFFSET,
 909                 .svc            = EXYNOS_SVC_OFFSET,
 910                 .eint_gpio_init = exynos_eint_gpio_init,
 911                 .suspend        = exynos_pinctrl_suspend,
 912                 .resume         = exynos_pinctrl_resume,
 913                 .label          = "exynos4x12-gpio-ctrl2",
 914         }, {
 915                 /* pin-controller instance 3 data */
 916                 .pin_banks      = exynos4x12_pin_banks3,
 917                 .nr_banks       = ARRAY_SIZE(exynos4x12_pin_banks3),
 918                 .geint_con      = EXYNOS_GPIO_ECON_OFFSET,
 919                 .geint_mask     = EXYNOS_GPIO_EMASK_OFFSET,
 920                 .geint_pend     = EXYNOS_GPIO_EPEND_OFFSET,
 921                 .svc            = EXYNOS_SVC_OFFSET,
 922                 .eint_gpio_init = exynos_eint_gpio_init,
 923                 .suspend        = exynos_pinctrl_suspend,
 924                 .resume         = exynos_pinctrl_resume,
 925                 .label          = "exynos4x12-gpio-ctrl3",
 926         },
 927 };
 928
 929 /* pin banks of exynos5250 pin-controller 0 */
 930 static struct samsung_pin_bank exynos5250_pin_banks0[] = {
 931         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
 932         EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
 933         EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
 934         EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),
 935         EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10),
 936         EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14),
 937         EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpb3", 0x18),
 938         EXYNOS_PIN_BANK_EINTG(7, 0x0E0, "gpc0", 0x1c),
 939         EXYNOS_PIN_BANK_EINTG(4, 0x100, "gpc1", 0x20),
 940         EXYNOS_PIN_BANK_EINTG(7, 0x120, "gpc2", 0x24),
 941         EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpc3", 0x28),
 942         EXYNOS_PIN_BANK_EINTG(4, 0x160, "gpd0", 0x2c),
 943         EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpd1", 0x30),
 944         EXYNOS_PIN_BANK_EINTG(7, 0x2E0, "gpc4", 0x34),
 945         EXYNOS_PIN_BANK_EINTN(6, 0x1A0, "gpy0"),
 946         EXYNOS_PIN_BANK_EINTN(4, 0x1C0, "gpy1"),
 947         EXYNOS_PIN_BANK_EINTN(6, 0x1E0, "gpy2"),
 948         EXYNOS_PIN_BANK_EINTN(8, 0x200, "gpy3"),
 949         EXYNOS_PIN_BANK_EINTN(8, 0x220, "gpy4"),
 950         EXYNOS_PIN_BANK_EINTN(8, 0x240, "gpy5"),
 951         EXYNOS_PIN_BANK_EINTN(8, 0x260, "gpy6"),
 952         EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
 953         EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
 954         EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
 955         EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
 956 };
 957
 958 /* pin banks of exynos5250 pin-controller 1 */
 959 static struct samsung_pin_bank exynos5250_pin_banks1[] = {
 960         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00),
 961         EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04),
 962         EXYNOS_PIN_BANK_EINTG(4, 0x040, "gpf0", 0x08),
 963         EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpf1", 0x0c),
 964         EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10),
 965         EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14),
 966         EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpg2", 0x18),
 967         EXYNOS_PIN_BANK_EINTG(4, 0x0E0, "gph0", 0x1c),
 968         EXYNOS_PIN_BANK_EINTG(8, 0x100, "gph1", 0x20),
 969 };
 970
 971 /* pin banks of exynos5250 pin-controller 2 */
 972 static struct samsung_pin_bank exynos5250_pin_banks2[] = {
 973         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00),
 974         EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04),
 975         EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv2", 0x08),
 976         EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpv3", 0x0c),
 977         EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpv4", 0x10),
 978 };
 979
 980 /* pin banks of exynos5250 pin-controller 3 */
 981 static struct samsung_pin_bank exynos5250_pin_banks3[] = {
 982         EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
 983 };
 984
 985 /*
 986  * Samsung pinctrl driver data for Exynos5250 SoC. Exynos5250 SoC includes
 987  * four gpio/pin-mux/pinconfig controllers.
 988  */
 989 struct samsung_pin_ctrl exynos5250_pin_ctrl[] = {
 990         {
 991                 /* pin-controller instance 0 data */
 992                 .pin_banks      = exynos5250_pin_banks0,
 993                 .nr_banks       = ARRAY_SIZE(exynos5250_pin_banks0),
 994                 .geint_con      = EXYNOS_GPIO_ECON_OFFSET,
 995                 .geint_mask     = EXYNOS_GPIO_EMASK_OFFSET,
 996                 .geint_pend     = EXYNOS_GPIO_EPEND_OFFSET,
 997                 .weint_con      = EXYNOS_WKUP_ECON_OFFSET,
 998                 .weint_mask     = EXYNOS_WKUP_EMASK_OFFSET,
 999                 .weint_pend     = EXYNOS_WKUP_EPEND_OFFSET,
1000                 .svc            = EXYNOS_SVC_OFFSET,
1001                 .eint_gpio_init = exynos_eint_gpio_init,
1002                 .eint_wkup_init = exynos_eint_wkup_init,
1003                 .suspend        = exynos_pinctrl_suspend,
1004                 .resume         = exynos_pinctrl_resume,
1005                 .label          = "exynos5250-gpio-ctrl0",
1006         }, {
1007                 /* pin-controller instance 1 data */
1008                 .pin_banks      = exynos5250_pin_banks1,
1009                 .nr_banks       = ARRAY_SIZE(exynos5250_pin_banks1),
1010                 .geint_con      = EXYNOS_GPIO_ECON_OFFSET,
1011                 .geint_mask     = EXYNOS_GPIO_EMASK_OFFSET,
1012                 .geint_pend     = EXYNOS_GPIO_EPEND_OFFSET,
1013                 .svc            = EXYNOS_SVC_OFFSET,
1014                 .eint_gpio_init = exynos_eint_gpio_init,
1015                 .suspend        = exynos_pinctrl_suspend,
1016                 .resume         = exynos_pinctrl_resume,
1017                 .label          = "exynos5250-gpio-ctrl1",
1018         }, {
1019                 /* pin-controller instance 2 data */
1020                 .pin_banks      = exynos5250_pin_banks2,
1021                 .nr_banks       = ARRAY_SIZE(exynos5250_pin_banks2),
1022                 .geint_con      = EXYNOS_GPIO_ECON_OFFSET,
1023                 .geint_mask     = EXYNOS_GPIO_EMASK_OFFSET,
1024                 .geint_pend     = EXYNOS_GPIO_EPEND_OFFSET,
1025                 .svc            = EXYNOS_SVC_OFFSET,
1026                 .eint_gpio_init = exynos_eint_gpio_init,
1027                 .suspend        = exynos_pinctrl_suspend,
1028                 .resume         = exynos_pinctrl_resume,
1029                 .label          = "exynos5250-gpio-ctrl2",
1030         }, {
1031                 /* pin-controller instance 3 data */
1032                 .pin_banks      = exynos5250_pin_banks3,
1033                 .nr_banks       = ARRAY_SIZE(exynos5250_pin_banks3),
1034                 .geint_con      = EXYNOS_GPIO_ECON_OFFSET,
1035                 .geint_mask     = EXYNOS_GPIO_EMASK_OFFSET,
1036                 .geint_pend     = EXYNOS_GPIO_EPEND_OFFSET,
1037                 .svc            = EXYNOS_SVC_OFFSET,
1038                 .eint_gpio_init = exynos_eint_gpio_init,
1039                 .suspend        = exynos_pinctrl_suspend,
1040                 .resume         = exynos_pinctrl_resume,
1041                 .label          = "exynos5250-gpio-ctrl3",
1042         },
1043 };
1044
1045 /* pin banks of exynos5420 pin-controller 0 */
1046 static struct samsung_pin_bank exynos5420_pin_banks0[] = {
1047         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpy7", 0x00),
1048         EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
1049         EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
1050         EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
1051         EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
1052 };
1053
1054 /* pin banks of exynos5420 pin-controller 1 */
1055 static struct samsung_pin_bank exynos5420_pin_banks1[] = {
1056         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpc0", 0x00),
1057         EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpc1", 0x04),
1058         EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08),
1059         EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpc3", 0x0c),
1060         EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpc4", 0x10),
1061         EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpd1", 0x14),
1062         EXYNOS_PIN_BANK_EINTN(6, 0x0C0, "gpy0"),
1063         EXYNOS_PIN_BANK_EINTN(4, 0x0E0, "gpy1"),
1064         EXYNOS_PIN_BANK_EINTN(6, 0x100, "gpy2"),
1065         EXYNOS_PIN_BANK_EINTN(8, 0x120, "gpy3"),
1066         EXYNOS_PIN_BANK_EINTN(8, 0x140, "gpy4"),
1067         EXYNOS_PIN_BANK_EINTN(8, 0x160, "gpy5"),
1068         EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy6"),
1069 };
1070
1071 /* pin banks of exynos5420 pin-controller 2 */
1072 static struct samsung_pin_bank exynos5420_pin_banks2[] = {
1073         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00),
1074         EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04),
1075         EXYNOS_PIN_BANK_EINTG(6, 0x040, "gpf0", 0x08),
1076         EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpf1", 0x0c),
1077         EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10),
1078         EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14),
1079         EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpg2", 0x18),
1080         EXYNOS_PIN_BANK_EINTG(4, 0x0E0, "gpj4", 0x1c),
1081 };
1082
1083 /* pin banks of exynos5420 pin-controller 3 */
1084 static struct samsung_pin_bank exynos5420_pin_banks3[] = {
1085         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
1086         EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
1087         EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
1088         EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),
1089         EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10),
1090         EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14),
1091         EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpb3", 0x18),
1092         EXYNOS_PIN_BANK_EINTG(2, 0x0E0, "gpb4", 0x1c),
1093         EXYNOS_PIN_BANK_EINTG(8, 0x100, "gph0", 0x20),
1094 };
1095
1096 /* pin banks of exynos5420 pin-controller 4 */
1097 static struct samsung_pin_bank exynos5420_pin_banks4[] = {
1098         EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
1099 };
1100
1101 /*
1102  * Samsung pinctrl driver data for Exynos5420 SoC. Exynos5420 SoC includes
1103  * four gpio/pin-mux/pinconfig controllers.
1104  */
1105 struct samsung_pin_ctrl exynos5420_pin_ctrl[] = {
1106         {
1107                 /* pin-controller instance 0 data */
1108                 .pin_banks      = exynos5420_pin_banks0,
1109                 .nr_banks       = ARRAY_SIZE(exynos5420_pin_banks0),
1110                 .geint_con      = EXYNOS_GPIO_ECON_OFFSET,
1111                 .geint_mask     = EXYNOS_GPIO_EMASK_OFFSET,
1112                 .geint_pend     = EXYNOS_GPIO_EPEND_OFFSET,
1113                 .weint_con      = EXYNOS_WKUP_ECON_OFFSET,
1114                 .weint_mask     = EXYNOS_WKUP_EMASK_OFFSET,
1115                 .weint_pend     = EXYNOS_WKUP_EPEND_OFFSET,
1116                 .svc            = EXYNOS_SVC_OFFSET,
1117                 .eint_gpio_init = exynos_eint_gpio_init,
1118                 .eint_wkup_init = exynos_eint_wkup_init,
1119                 .label          = "exynos5420-gpio-ctrl0",
1120         }, {
1121                 /* pin-controller instance 1 data */
1122                 .pin_banks      = exynos5420_pin_banks1,
1123                 .nr_banks       = ARRAY_SIZE(exynos5420_pin_banks1),
1124                 .geint_con      = EXYNOS_GPIO_ECON_OFFSET,
1125                 .geint_mask     = EXYNOS_GPIO_EMASK_OFFSET,
1126                 .geint_pend     = EXYNOS_GPIO_EPEND_OFFSET,
1127                 .svc            = EXYNOS_SVC_OFFSET,
1128                 .eint_gpio_init = exynos_eint_gpio_init,
1129                 .label          = "exynos5420-gpio-ctrl1",
1130         }, {
1131                 /* pin-controller instance 2 data */
1132                 .pin_banks      = exynos5420_pin_banks2,
1133                 .nr_banks       = ARRAY_SIZE(exynos5420_pin_banks2),
1134                 .geint_con      = EXYNOS_GPIO_ECON_OFFSET,
1135                 .geint_mask     = EXYNOS_GPIO_EMASK_OFFSET,
1136                 .geint_pend     = EXYNOS_GPIO_EPEND_OFFSET,
1137                 .svc            = EXYNOS_SVC_OFFSET,
1138                 .eint_gpio_init = exynos_eint_gpio_init,
1139                 .label          = "exynos5420-gpio-ctrl2",
1140         }, {
1141                 /* pin-controller instance 3 data */
1142                 .pin_banks      = exynos5420_pin_banks3,
1143                 .nr_banks       = ARRAY_SIZE(exynos5420_pin_banks3),
1144                 .geint_con      = EXYNOS_GPIO_ECON_OFFSET,
1145                 .geint_mask     = EXYNOS_GPIO_EMASK_OFFSET,
1146                 .geint_pend     = EXYNOS_GPIO_EPEND_OFFSET,
1147                 .svc            = EXYNOS_SVC_OFFSET,
1148                 .eint_gpio_init = exynos_eint_gpio_init,
1149                 .label          = "exynos5420-gpio-ctrl3",
1150         }, {
1151                 /* pin-controller instance 4 data */
1152                 .pin_banks      = exynos5420_pin_banks4,
1153                 .nr_banks       = ARRAY_SIZE(exynos5420_pin_banks4),
1154                 .geint_con      = EXYNOS_GPIO_ECON_OFFSET,
1155                 .geint_mask     = EXYNOS_GPIO_EMASK_OFFSET,
1156                 .geint_pend     = EXYNOS_GPIO_EPEND_OFFSET,
1157                 .svc            = EXYNOS_SVC_OFFSET,
1158                 .eint_gpio_init = exynos_eint_gpio_init,
1159                 .label          = "exynos5420-gpio-ctrl4",
1160         },
1161 };