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[karo-tx-linux.git] / drivers / pinctrl / pinctrl-imx50.c
1 /*
2  * imx50 pinctrl driver based on imx pinmux core
3  *
4  * Copyright (C) 2013 Greg Ungerer <gerg@uclinux.org>
5  * Copyright (C) 2012 Freescale Semiconductor, Inc.
6  * Copyright (C) 2012 Linaro, Inc.
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  */
13
14 #include <linux/err.h>
15 #include <linux/init.h>
16 #include <linux/io.h>
17 #include <linux/module.h>
18 #include <linux/of.h>
19 #include <linux/of_device.h>
20 #include <linux/pinctrl/pinctrl.h>
21
22 #include "pinctrl-imx.h"
23
24 enum imx50_pads {
25         MX50_PAD_RESERVE0 = 0,
26         MX50_PAD_RESERVE1 = 1,
27         MX50_PAD_RESERVE2 = 2,
28         MX50_PAD_RESERVE3 = 3,
29         MX50_PAD_RESERVE4 = 4,
30         MX50_PAD_RESERVE5 = 5,
31         MX50_PAD_RESERVE6 = 6,
32         MX50_PAD_RESERVE7 = 7,
33         MX50_PAD_KEY_COL0 = 8,
34         MX50_PAD_KEY_ROW0 = 9,
35         MX50_PAD_KEY_COL1 = 10,
36         MX50_PAD_KEY_ROW1 = 11,
37         MX50_PAD_KEY_COL2 = 12,
38         MX50_PAD_KEY_ROW2 = 13,
39         MX50_PAD_KEY_COL3 = 14,
40         MX50_PAD_KEY_ROW3 = 15,
41         MX50_PAD_I2C1_SCL = 16,
42         MX50_PAD_I2C1_SDA = 17,
43         MX50_PAD_I2C2_SCL = 18,
44         MX50_PAD_I2C2_SDA = 19,
45         MX50_PAD_I2C3_SCL = 20,
46         MX50_PAD_I2C3_SDA = 21,
47         MX50_PAD_PWM1 = 22,
48         MX50_PAD_PWM2 = 23,
49         MX50_PAD_0WIRE = 24,
50         MX50_PAD_EPITO = 25,
51         MX50_PAD_WDOG = 26,
52         MX50_PAD_SSI_TXFS = 27,
53         MX50_PAD_SSI_TXC = 28,
54         MX50_PAD_SSI_TXD = 29,
55         MX50_PAD_SSI_RXD = 30,
56         MX50_PAD_SSI_RXF = 31,
57         MX50_PAD_SSI_RXC = 32,
58         MX50_PAD_UART1_TXD = 33,
59         MX50_PAD_UART1_RXD = 34,
60         MX50_PAD_UART1_CTS = 35,
61         MX50_PAD_UART1_RTS = 36,
62         MX50_PAD_UART2_TXD = 37,
63         MX50_PAD_UART2_RXD = 38,
64         MX50_PAD_UART2_CTS = 39,
65         MX50_PAD_UART2_RTS = 40,
66         MX50_PAD_UART3_TXD = 41,
67         MX50_PAD_UART3_RXD = 42,
68         MX50_PAD_UART4_TXD = 43,
69         MX50_PAD_UART4_RXD = 44,
70         MX50_PAD_CSPI_CLK = 45,
71         MX50_PAD_CSPI_MOSI = 46,
72         MX50_PAD_CSPI_MISO = 47,
73         MX50_PAD_CSPI_SS0 = 48,
74         MX50_PAD_ECSPI1_CLK = 49,
75         MX50_PAD_ECSPI1_MOSI = 50,
76         MX50_PAD_ECSPI1_MISO = 51,
77         MX50_PAD_ECSPI1_SS0 = 52,
78         MX50_PAD_ECSPI2_CLK = 53,
79         MX50_PAD_ECSPI2_MOSI = 54,
80         MX50_PAD_ECSPI2_MISO = 55,
81         MX50_PAD_ECSPI2_SS0 = 56,
82         MX50_PAD_SD1_CLK = 57,
83         MX50_PAD_SD1_CMD = 58,
84         MX50_PAD_SD1_D0 = 59,
85         MX50_PAD_SD1_D1 = 60,
86         MX50_PAD_SD1_D2 = 61,
87         MX50_PAD_SD1_D3 = 62,
88         MX50_PAD_SD2_CLK = 63,
89         MX50_PAD_SD2_CMD = 64,
90         MX50_PAD_SD2_D0 = 65,
91         MX50_PAD_SD2_D1 = 66,
92         MX50_PAD_SD2_D2 = 67,
93         MX50_PAD_SD2_D3 = 68,
94         MX50_PAD_SD2_D4 = 69,
95         MX50_PAD_SD2_D5 = 70,
96         MX50_PAD_SD2_D6 = 71,
97         MX50_PAD_SD2_D7 = 72,
98         MX50_PAD_SD2_WP = 73,
99         MX50_PAD_SD2_CD = 74,
100         MX50_PAD_DISP_D0 = 75,
101         MX50_PAD_DISP_D1 = 76,
102         MX50_PAD_DISP_D2 = 77,
103         MX50_PAD_DISP_D3 = 78,
104         MX50_PAD_DISP_D4 = 79,
105         MX50_PAD_DISP_D5 = 80,
106         MX50_PAD_DISP_D6 = 81,
107         MX50_PAD_DISP_D7 = 82,
108         MX50_PAD_DISP_WR = 83,
109         MX50_PAD_DISP_RD = 84,
110         MX50_PAD_DISP_RS = 85,
111         MX50_PAD_DISP_CS = 86,
112         MX50_PAD_DISP_BUSY = 87,
113         MX50_PAD_DISP_RESET = 88,
114         MX50_PAD_SD3_CLK = 89,
115         MX50_PAD_SD3_CMD = 90,
116         MX50_PAD_SD3_D0 = 91,
117         MX50_PAD_SD3_D1 = 92,
118         MX50_PAD_SD3_D2 = 93,
119         MX50_PAD_SD3_D3 = 94,
120         MX50_PAD_SD3_D4 = 95,
121         MX50_PAD_SD3_D5 = 96,
122         MX50_PAD_SD3_D6 = 97,
123         MX50_PAD_SD3_D7 = 98,
124         MX50_PAD_SD3_WP = 99,
125         MX50_PAD_DISP_D8 = 100,
126         MX50_PAD_DISP_D9 = 101,
127         MX50_PAD_DISP_D10 = 102,
128         MX50_PAD_DISP_D11 = 103,
129         MX50_PAD_DISP_D12 = 104,
130         MX50_PAD_DISP_D13 = 105,
131         MX50_PAD_DISP_D14 = 106,
132         MX50_PAD_DISP_D15 = 107,
133         MX50_PAD_EPDC_D0 = 108,
134         MX50_PAD_EPDC_D1 = 109,
135         MX50_PAD_EPDC_D2 = 110,
136         MX50_PAD_EPDC_D3 = 111,
137         MX50_PAD_EPDC_D4 = 112,
138         MX50_PAD_EPDC_D5 = 113,
139         MX50_PAD_EPDC_D6 = 114,
140         MX50_PAD_EPDC_D7 = 115,
141         MX50_PAD_EPDC_D8 = 116,
142         MX50_PAD_EPDC_D9 = 117,
143         MX50_PAD_EPDC_D10 = 118,
144         MX50_PAD_EPDC_D11 = 119,
145         MX50_PAD_EPDC_D12 = 120,
146         MX50_PAD_EPDC_D13 = 121,
147         MX50_PAD_EPDC_D14 = 122,
148         MX50_PAD_EPDC_D15 = 123,
149         MX50_PAD_EPDC_GDCLK = 124,
150         MX50_PAD_EPDC_GDSP = 125,
151         MX50_PAD_EPDC_GDOE = 126,
152         MX50_PAD_EPDC_GDRL = 127,
153         MX50_PAD_EPDC_SDCLK = 128,
154         MX50_PAD_EPDC_SDOEZ = 129,
155         MX50_PAD_EPDC_SDOED = 130,
156         MX50_PAD_EPDC_SDOE = 131,
157         MX50_PAD_EPDC_SDLE = 132,
158         MX50_PAD_EPDC_SDCLKN = 133,
159         MX50_PAD_EPDC_SDSHR = 134,
160         MX50_PAD_EPDC_PWRCOM = 135,
161         MX50_PAD_EPDC_PWRSTAT = 136,
162         MX50_PAD_EPDC_PWRCTRL0 = 137,
163         MX50_PAD_EPDC_PWRCTRL1 = 138,
164         MX50_PAD_EPDC_PWRCTRL2 = 139,
165         MX50_PAD_EPDC_PWRCTRL3 = 140,
166         MX50_PAD_EPDC_VCOM0 = 141,
167         MX50_PAD_EPDC_VCOM1 = 142,
168         MX50_PAD_EPDC_BDR0 = 143,
169         MX50_PAD_EPDC_BDR1 = 144,
170         MX50_PAD_EPDC_SDCE0 = 145,
171         MX50_PAD_EPDC_SDCE1 = 146,
172         MX50_PAD_EPDC_SDCE2 = 147,
173         MX50_PAD_EPDC_SDCE3 = 148,
174         MX50_PAD_EPDC_SDCE4 = 149,
175         MX50_PAD_EPDC_SDCE5 = 150,
176         MX50_PAD_EIM_DA0 = 151,
177         MX50_PAD_EIM_DA1 = 152,
178         MX50_PAD_EIM_DA2 = 153,
179         MX50_PAD_EIM_DA3 = 154,
180         MX50_PAD_EIM_DA4 = 155,
181         MX50_PAD_EIM_DA5 = 156,
182         MX50_PAD_EIM_DA6 = 157,
183         MX50_PAD_EIM_DA7 = 158,
184         MX50_PAD_EIM_DA8 = 159,
185         MX50_PAD_EIM_DA9 = 160,
186         MX50_PAD_EIM_DA10 = 161,
187         MX50_PAD_EIM_DA11 = 162,
188         MX50_PAD_EIM_DA12 = 163,
189         MX50_PAD_EIM_DA13 = 164,
190         MX50_PAD_EIM_DA14 = 165,
191         MX50_PAD_EIM_DA15 = 166,
192         MX50_PAD_EIM_CS2 = 167,
193         MX50_PAD_EIM_CS1 = 168,
194         MX50_PAD_EIM_CS0 = 169,
195         MX50_PAD_EIM_EB0 = 170,
196         MX50_PAD_EIM_EB1 = 171,
197         MX50_PAD_EIM_WAIT = 172,
198         MX50_PAD_EIM_BCLK = 173,
199         MX50_PAD_EIM_RDY = 174,
200         MX50_PAD_EIM_OE = 175,
201         MX50_PAD_EIM_RW = 176,
202         MX50_PAD_EIM_LBA = 177,
203         MX50_PAD_EIM_CRE = 178,
204 };
205
206 /* Pad names for the pinmux subsystem */
207 static const struct pinctrl_pin_desc imx50_pinctrl_pads[] = {
208         IMX_PINCTRL_PIN(MX50_PAD_RESERVE0),
209         IMX_PINCTRL_PIN(MX50_PAD_RESERVE1),
210         IMX_PINCTRL_PIN(MX50_PAD_RESERVE2),
211         IMX_PINCTRL_PIN(MX50_PAD_RESERVE3),
212         IMX_PINCTRL_PIN(MX50_PAD_RESERVE4),
213         IMX_PINCTRL_PIN(MX50_PAD_RESERVE5),
214         IMX_PINCTRL_PIN(MX50_PAD_RESERVE6),
215         IMX_PINCTRL_PIN(MX50_PAD_RESERVE7),
216         IMX_PINCTRL_PIN(MX50_PAD_KEY_COL0),
217         IMX_PINCTRL_PIN(MX50_PAD_KEY_ROW0),
218         IMX_PINCTRL_PIN(MX50_PAD_KEY_COL1),
219         IMX_PINCTRL_PIN(MX50_PAD_KEY_ROW1),
220         IMX_PINCTRL_PIN(MX50_PAD_KEY_COL2),
221         IMX_PINCTRL_PIN(MX50_PAD_KEY_ROW2),
222         IMX_PINCTRL_PIN(MX50_PAD_KEY_COL3),
223         IMX_PINCTRL_PIN(MX50_PAD_KEY_ROW3),
224         IMX_PINCTRL_PIN(MX50_PAD_I2C1_SCL),
225         IMX_PINCTRL_PIN(MX50_PAD_I2C1_SDA),
226         IMX_PINCTRL_PIN(MX50_PAD_I2C2_SCL),
227         IMX_PINCTRL_PIN(MX50_PAD_I2C2_SDA),
228         IMX_PINCTRL_PIN(MX50_PAD_I2C3_SCL),
229         IMX_PINCTRL_PIN(MX50_PAD_I2C3_SDA),
230         IMX_PINCTRL_PIN(MX50_PAD_PWM1),
231         IMX_PINCTRL_PIN(MX50_PAD_PWM2),
232         IMX_PINCTRL_PIN(MX50_PAD_0WIRE),
233         IMX_PINCTRL_PIN(MX50_PAD_EPITO),
234         IMX_PINCTRL_PIN(MX50_PAD_WDOG),
235         IMX_PINCTRL_PIN(MX50_PAD_SSI_TXFS),
236         IMX_PINCTRL_PIN(MX50_PAD_SSI_TXC),
237         IMX_PINCTRL_PIN(MX50_PAD_SSI_TXD),
238         IMX_PINCTRL_PIN(MX50_PAD_SSI_RXD),
239         IMX_PINCTRL_PIN(MX50_PAD_SSI_RXF),
240         IMX_PINCTRL_PIN(MX50_PAD_SSI_RXC),
241         IMX_PINCTRL_PIN(MX50_PAD_UART1_TXD),
242         IMX_PINCTRL_PIN(MX50_PAD_UART1_RXD),
243         IMX_PINCTRL_PIN(MX50_PAD_UART1_CTS),
244         IMX_PINCTRL_PIN(MX50_PAD_UART1_RTS),
245         IMX_PINCTRL_PIN(MX50_PAD_UART2_TXD),
246         IMX_PINCTRL_PIN(MX50_PAD_UART2_RXD),
247         IMX_PINCTRL_PIN(MX50_PAD_UART2_CTS),
248         IMX_PINCTRL_PIN(MX50_PAD_UART2_RTS),
249         IMX_PINCTRL_PIN(MX50_PAD_UART3_TXD),
250         IMX_PINCTRL_PIN(MX50_PAD_UART3_RXD),
251         IMX_PINCTRL_PIN(MX50_PAD_UART4_TXD),
252         IMX_PINCTRL_PIN(MX50_PAD_UART4_RXD),
253         IMX_PINCTRL_PIN(MX50_PAD_CSPI_CLK),
254         IMX_PINCTRL_PIN(MX50_PAD_CSPI_MOSI),
255         IMX_PINCTRL_PIN(MX50_PAD_CSPI_MISO),
256         IMX_PINCTRL_PIN(MX50_PAD_CSPI_SS0),
257         IMX_PINCTRL_PIN(MX50_PAD_ECSPI1_CLK),
258         IMX_PINCTRL_PIN(MX50_PAD_ECSPI1_MOSI),
259         IMX_PINCTRL_PIN(MX50_PAD_ECSPI1_MISO),
260         IMX_PINCTRL_PIN(MX50_PAD_ECSPI1_SS0),
261         IMX_PINCTRL_PIN(MX50_PAD_ECSPI2_CLK),
262         IMX_PINCTRL_PIN(MX50_PAD_ECSPI2_MOSI),
263         IMX_PINCTRL_PIN(MX50_PAD_ECSPI2_MISO),
264         IMX_PINCTRL_PIN(MX50_PAD_ECSPI2_SS0),
265         IMX_PINCTRL_PIN(MX50_PAD_SD1_CLK),
266         IMX_PINCTRL_PIN(MX50_PAD_SD1_CMD),
267         IMX_PINCTRL_PIN(MX50_PAD_SD1_D0),
268         IMX_PINCTRL_PIN(MX50_PAD_SD1_D1),
269         IMX_PINCTRL_PIN(MX50_PAD_SD1_D2),
270         IMX_PINCTRL_PIN(MX50_PAD_SD1_D3),
271         IMX_PINCTRL_PIN(MX50_PAD_SD2_CLK),
272         IMX_PINCTRL_PIN(MX50_PAD_SD2_CMD),
273         IMX_PINCTRL_PIN(MX50_PAD_SD2_D0),
274         IMX_PINCTRL_PIN(MX50_PAD_SD2_D1),
275         IMX_PINCTRL_PIN(MX50_PAD_SD2_D2),
276         IMX_PINCTRL_PIN(MX50_PAD_SD2_D3),
277         IMX_PINCTRL_PIN(MX50_PAD_SD2_D4),
278         IMX_PINCTRL_PIN(MX50_PAD_SD2_D5),
279         IMX_PINCTRL_PIN(MX50_PAD_SD2_D6),
280         IMX_PINCTRL_PIN(MX50_PAD_SD2_D7),
281         IMX_PINCTRL_PIN(MX50_PAD_SD2_WP),
282         IMX_PINCTRL_PIN(MX50_PAD_SD2_CD),
283         IMX_PINCTRL_PIN(MX50_PAD_DISP_D0),
284         IMX_PINCTRL_PIN(MX50_PAD_DISP_D1),
285         IMX_PINCTRL_PIN(MX50_PAD_DISP_D2),
286         IMX_PINCTRL_PIN(MX50_PAD_DISP_D3),
287         IMX_PINCTRL_PIN(MX50_PAD_DISP_D4),
288         IMX_PINCTRL_PIN(MX50_PAD_DISP_D5),
289         IMX_PINCTRL_PIN(MX50_PAD_DISP_D6),
290         IMX_PINCTRL_PIN(MX50_PAD_DISP_D7),
291         IMX_PINCTRL_PIN(MX50_PAD_DISP_WR),
292         IMX_PINCTRL_PIN(MX50_PAD_DISP_RD),
293         IMX_PINCTRL_PIN(MX50_PAD_DISP_RS),
294         IMX_PINCTRL_PIN(MX50_PAD_DISP_CS),
295         IMX_PINCTRL_PIN(MX50_PAD_DISP_BUSY),
296         IMX_PINCTRL_PIN(MX50_PAD_DISP_RESET),
297         IMX_PINCTRL_PIN(MX50_PAD_SD3_CLK),
298         IMX_PINCTRL_PIN(MX50_PAD_SD3_CMD),
299         IMX_PINCTRL_PIN(MX50_PAD_SD3_D0),
300         IMX_PINCTRL_PIN(MX50_PAD_SD3_D1),
301         IMX_PINCTRL_PIN(MX50_PAD_SD3_D2),
302         IMX_PINCTRL_PIN(MX50_PAD_SD3_D3),
303         IMX_PINCTRL_PIN(MX50_PAD_SD3_D4),
304         IMX_PINCTRL_PIN(MX50_PAD_SD3_D5),
305         IMX_PINCTRL_PIN(MX50_PAD_SD3_D6),
306         IMX_PINCTRL_PIN(MX50_PAD_SD3_D7),
307         IMX_PINCTRL_PIN(MX50_PAD_SD3_WP),
308         IMX_PINCTRL_PIN(MX50_PAD_DISP_D8),
309         IMX_PINCTRL_PIN(MX50_PAD_DISP_D9),
310         IMX_PINCTRL_PIN(MX50_PAD_DISP_D10),
311         IMX_PINCTRL_PIN(MX50_PAD_DISP_D11),
312         IMX_PINCTRL_PIN(MX50_PAD_DISP_D12),
313         IMX_PINCTRL_PIN(MX50_PAD_DISP_D13),
314         IMX_PINCTRL_PIN(MX50_PAD_DISP_D14),
315         IMX_PINCTRL_PIN(MX50_PAD_DISP_D15),
316         IMX_PINCTRL_PIN(MX50_PAD_EPDC_D0),
317         IMX_PINCTRL_PIN(MX50_PAD_EPDC_D1),
318         IMX_PINCTRL_PIN(MX50_PAD_EPDC_D2),
319         IMX_PINCTRL_PIN(MX50_PAD_EPDC_D3),
320         IMX_PINCTRL_PIN(MX50_PAD_EPDC_D4),
321         IMX_PINCTRL_PIN(MX50_PAD_EPDC_D5),
322         IMX_PINCTRL_PIN(MX50_PAD_EPDC_D6),
323         IMX_PINCTRL_PIN(MX50_PAD_EPDC_D7),
324         IMX_PINCTRL_PIN(MX50_PAD_EPDC_D8),
325         IMX_PINCTRL_PIN(MX50_PAD_EPDC_D9),
326         IMX_PINCTRL_PIN(MX50_PAD_EPDC_D10),
327         IMX_PINCTRL_PIN(MX50_PAD_EPDC_D11),
328         IMX_PINCTRL_PIN(MX50_PAD_EPDC_D12),
329         IMX_PINCTRL_PIN(MX50_PAD_EPDC_D13),
330         IMX_PINCTRL_PIN(MX50_PAD_EPDC_D14),
331         IMX_PINCTRL_PIN(MX50_PAD_EPDC_D15),
332         IMX_PINCTRL_PIN(MX50_PAD_EPDC_GDCLK),
333         IMX_PINCTRL_PIN(MX50_PAD_EPDC_GDSP),
334         IMX_PINCTRL_PIN(MX50_PAD_EPDC_GDOE),
335         IMX_PINCTRL_PIN(MX50_PAD_EPDC_GDRL),
336         IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCLK),
337         IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDOEZ),
338         IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDOED),
339         IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDOE),
340         IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDLE),
341         IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCLKN),
342         IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDSHR),
343         IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRCOM),
344         IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRSTAT),
345         IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRCTRL0),
346         IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRCTRL1),
347         IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRCTRL2),
348         IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRCTRL3),
349         IMX_PINCTRL_PIN(MX50_PAD_EPDC_VCOM0),
350         IMX_PINCTRL_PIN(MX50_PAD_EPDC_VCOM1),
351         IMX_PINCTRL_PIN(MX50_PAD_EPDC_BDR0),
352         IMX_PINCTRL_PIN(MX50_PAD_EPDC_BDR1),
353         IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE0),
354         IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE1),
355         IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE2),
356         IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE3),
357         IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE4),
358         IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE5),
359         IMX_PINCTRL_PIN(MX50_PAD_EIM_DA0),
360         IMX_PINCTRL_PIN(MX50_PAD_EIM_DA1),
361         IMX_PINCTRL_PIN(MX50_PAD_EIM_DA2),
362         IMX_PINCTRL_PIN(MX50_PAD_EIM_DA3),
363         IMX_PINCTRL_PIN(MX50_PAD_EIM_DA4),
364         IMX_PINCTRL_PIN(MX50_PAD_EIM_DA5),
365         IMX_PINCTRL_PIN(MX50_PAD_EIM_DA6),
366         IMX_PINCTRL_PIN(MX50_PAD_EIM_DA7),
367         IMX_PINCTRL_PIN(MX50_PAD_EIM_DA8),
368         IMX_PINCTRL_PIN(MX50_PAD_EIM_DA9),
369         IMX_PINCTRL_PIN(MX50_PAD_EIM_DA10),
370         IMX_PINCTRL_PIN(MX50_PAD_EIM_DA11),
371         IMX_PINCTRL_PIN(MX50_PAD_EIM_DA12),
372         IMX_PINCTRL_PIN(MX50_PAD_EIM_DA13),
373         IMX_PINCTRL_PIN(MX50_PAD_EIM_DA14),
374         IMX_PINCTRL_PIN(MX50_PAD_EIM_DA15),
375         IMX_PINCTRL_PIN(MX50_PAD_EIM_CS2),
376         IMX_PINCTRL_PIN(MX50_PAD_EIM_CS1),
377         IMX_PINCTRL_PIN(MX50_PAD_EIM_CS0),
378         IMX_PINCTRL_PIN(MX50_PAD_EIM_EB0),
379         IMX_PINCTRL_PIN(MX50_PAD_EIM_EB1),
380         IMX_PINCTRL_PIN(MX50_PAD_EIM_WAIT),
381         IMX_PINCTRL_PIN(MX50_PAD_EIM_BCLK),
382         IMX_PINCTRL_PIN(MX50_PAD_EIM_RDY),
383         IMX_PINCTRL_PIN(MX50_PAD_EIM_OE),
384         IMX_PINCTRL_PIN(MX50_PAD_EIM_RW),
385         IMX_PINCTRL_PIN(MX50_PAD_EIM_LBA),
386         IMX_PINCTRL_PIN(MX50_PAD_EIM_CRE),
387 };
388
389 static struct imx_pinctrl_soc_info imx50_pinctrl_info = {
390         .pins = imx50_pinctrl_pads,
391         .npins = ARRAY_SIZE(imx50_pinctrl_pads),
392 };
393
394 static struct of_device_id imx50_pinctrl_of_match[] = {
395         { .compatible = "fsl,imx50-iomuxc", },
396         { /* sentinel */ }
397 };
398
399 static int imx50_pinctrl_probe(struct platform_device *pdev)
400 {
401         return imx_pinctrl_probe(pdev, &imx50_pinctrl_info);
402 }
403
404 static struct platform_driver imx50_pinctrl_driver = {
405         .driver = {
406                 .name = "imx50-pinctrl",
407                 .owner = THIS_MODULE,
408                 .of_match_table = of_match_ptr(imx50_pinctrl_of_match),
409         },
410         .probe = imx50_pinctrl_probe,
411         .remove = imx_pinctrl_remove,
412 };
413
414 static int __init imx50_pinctrl_init(void)
415 {
416         return platform_driver_register(&imx50_pinctrl_driver);
417 }
418 arch_initcall(imx50_pinctrl_init);
419
420 static void __exit imx50_pinctrl_exit(void)
421 {
422         platform_driver_unregister(&imx50_pinctrl_driver);
423 }
424 module_exit(imx50_pinctrl_exit);
425 MODULE_DESCRIPTION("Freescale IMX50 pinctrl driver");
426 MODULE_LICENSE("GPL v2");