2 * Copyright (c) 2013, Sony Mobile Communications AB.
3 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 and
7 * only version 2 as published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
15 #include <linux/err.h>
16 #include <linux/irqdomain.h>
18 #include <linux/module.h>
20 #include <linux/platform_device.h>
21 #include <linux/pinctrl/machine.h>
22 #include <linux/pinctrl/pinctrl.h>
23 #include <linux/pinctrl/pinmux.h>
24 #include <linux/pinctrl/pinconf.h>
25 #include <linux/pinctrl/pinconf-generic.h>
26 #include <linux/slab.h>
27 #include <linux/gpio.h>
28 #include <linux/interrupt.h>
29 #include <linux/irq.h>
30 #include <linux/irqchip/chained_irq.h>
31 #include <linux/spinlock.h>
35 #include "pinctrl-msm.h"
36 #include "pinctrl-utils.h"
38 #define MAX_NR_GPIO 300
41 * struct msm_pinctrl - state for a pinctrl-msm device
42 * @dev: device handle.
43 * @pctrl: pinctrl handle.
44 * @domain: irqdomain handle.
45 * @chip: gpiochip handle.
46 * @irq: parent irq for the TLMM irq_chip.
47 * @lock: Spinlock to protect register resources as well
48 * as msm_pinctrl data structures.
49 * @enabled_irqs: Bitmap of currently enabled irqs.
50 * @dual_edge_irqs: Bitmap of irqs that need sw emulated dual edge
52 * @soc; Reference to soc_data of platform specific data.
53 * @regs: Base address for the TLMM register map.
57 struct pinctrl_dev *pctrl;
58 struct irq_domain *domain;
59 struct gpio_chip chip;
64 DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO);
65 DECLARE_BITMAP(enabled_irqs, MAX_NR_GPIO);
67 const struct msm_pinctrl_soc_data *soc;
71 static int msm_get_groups_count(struct pinctrl_dev *pctldev)
73 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
75 return pctrl->soc->ngroups;
78 static const char *msm_get_group_name(struct pinctrl_dev *pctldev,
81 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
83 return pctrl->soc->groups[group].name;
86 static int msm_get_group_pins(struct pinctrl_dev *pctldev,
88 const unsigned **pins,
91 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
93 *pins = pctrl->soc->groups[group].pins;
94 *num_pins = pctrl->soc->groups[group].npins;
98 static const struct pinctrl_ops msm_pinctrl_ops = {
99 .get_groups_count = msm_get_groups_count,
100 .get_group_name = msm_get_group_name,
101 .get_group_pins = msm_get_group_pins,
102 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
103 .dt_free_map = pinctrl_utils_dt_free_map,
106 static int msm_get_functions_count(struct pinctrl_dev *pctldev)
108 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
110 return pctrl->soc->nfunctions;
113 static const char *msm_get_function_name(struct pinctrl_dev *pctldev,
116 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
118 return pctrl->soc->functions[function].name;
121 static int msm_get_function_groups(struct pinctrl_dev *pctldev,
123 const char * const **groups,
124 unsigned * const num_groups)
126 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
128 *groups = pctrl->soc->functions[function].groups;
129 *num_groups = pctrl->soc->functions[function].ngroups;
133 static int msm_pinmux_enable(struct pinctrl_dev *pctldev,
137 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
138 const struct msm_pingroup *g;
143 g = &pctrl->soc->groups[group];
145 if (WARN_ON(g->mux_bit < 0))
148 for (i = 0; i < ARRAY_SIZE(g->funcs); i++) {
149 if (g->funcs[i] == function)
153 if (WARN_ON(i == ARRAY_SIZE(g->funcs)))
156 spin_lock_irqsave(&pctrl->lock, flags);
158 val = readl(pctrl->regs + g->ctl_reg);
159 val &= ~(0x7 << g->mux_bit);
160 val |= i << g->mux_bit;
161 writel(val, pctrl->regs + g->ctl_reg);
163 spin_unlock_irqrestore(&pctrl->lock, flags);
168 static void msm_pinmux_disable(struct pinctrl_dev *pctldev,
172 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
173 const struct msm_pingroup *g;
177 g = &pctrl->soc->groups[group];
179 if (WARN_ON(g->mux_bit < 0))
182 spin_lock_irqsave(&pctrl->lock, flags);
184 /* Clear the mux bits to select gpio mode */
185 val = readl(pctrl->regs + g->ctl_reg);
186 val &= ~(0x7 << g->mux_bit);
187 writel(val, pctrl->regs + g->ctl_reg);
189 spin_unlock_irqrestore(&pctrl->lock, flags);
192 static const struct pinmux_ops msm_pinmux_ops = {
193 .get_functions_count = msm_get_functions_count,
194 .get_function_name = msm_get_function_name,
195 .get_function_groups = msm_get_function_groups,
196 .enable = msm_pinmux_enable,
197 .disable = msm_pinmux_disable,
200 static int msm_config_reg(struct msm_pinctrl *pctrl,
201 const struct msm_pingroup *g,
207 case PIN_CONFIG_BIAS_DISABLE:
208 case PIN_CONFIG_BIAS_PULL_DOWN:
209 case PIN_CONFIG_BIAS_PULL_UP:
213 case PIN_CONFIG_DRIVE_STRENGTH:
217 case PIN_CONFIG_OUTPUT:
222 dev_err(pctrl->dev, "Invalid config param %04x\n", param);
229 static int msm_config_get(struct pinctrl_dev *pctldev,
231 unsigned long *config)
233 dev_err(pctldev->dev, "pin_config_set op not supported\n");
237 static int msm_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
238 unsigned long *configs, unsigned num_configs)
240 dev_err(pctldev->dev, "pin_config_set op not supported\n");
244 #define MSM_NO_PULL 0
245 #define MSM_PULL_DOWN 1
246 #define MSM_PULL_UP 3
248 static unsigned msm_regval_to_drive(u32 val)
250 return (val + 1) * 2;
253 static int msm_config_group_get(struct pinctrl_dev *pctldev,
255 unsigned long *config)
257 const struct msm_pingroup *g;
258 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
259 unsigned param = pinconf_to_config_param(*config);
266 g = &pctrl->soc->groups[group];
268 ret = msm_config_reg(pctrl, g, param, &mask, &bit);
272 val = readl(pctrl->regs + g->ctl_reg);
273 arg = (val >> bit) & mask;
275 /* Convert register value to pinconf value */
277 case PIN_CONFIG_BIAS_DISABLE:
278 arg = arg == MSM_NO_PULL;
280 case PIN_CONFIG_BIAS_PULL_DOWN:
281 arg = arg == MSM_PULL_DOWN;
283 case PIN_CONFIG_BIAS_PULL_UP:
284 arg = arg == MSM_PULL_UP;
286 case PIN_CONFIG_DRIVE_STRENGTH:
287 arg = msm_regval_to_drive(arg);
289 case PIN_CONFIG_OUTPUT:
290 /* Pin is not output */
294 val = readl(pctrl->regs + g->io_reg);
295 arg = !!(val & BIT(g->in_bit));
298 dev_err(pctrl->dev, "Unsupported config parameter: %x\n",
303 *config = pinconf_to_config_packed(param, arg);
308 static int msm_config_group_set(struct pinctrl_dev *pctldev,
310 unsigned long *configs,
311 unsigned num_configs)
313 const struct msm_pingroup *g;
314 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
324 g = &pctrl->soc->groups[group];
326 for (i = 0; i < num_configs; i++) {
327 param = pinconf_to_config_param(configs[i]);
328 arg = pinconf_to_config_argument(configs[i]);
330 ret = msm_config_reg(pctrl, g, param, &mask, &bit);
334 /* Convert pinconf values to register values */
336 case PIN_CONFIG_BIAS_DISABLE:
339 case PIN_CONFIG_BIAS_PULL_DOWN:
342 case PIN_CONFIG_BIAS_PULL_UP:
345 case PIN_CONFIG_DRIVE_STRENGTH:
346 /* Check for invalid values */
347 if (arg > 16 || arg < 2 || (arg % 2) != 0)
352 case PIN_CONFIG_OUTPUT:
353 /* set output value */
354 spin_lock_irqsave(&pctrl->lock, flags);
355 val = readl(pctrl->regs + g->io_reg);
357 val |= BIT(g->out_bit);
359 val &= ~BIT(g->out_bit);
360 writel(val, pctrl->regs + g->io_reg);
361 spin_unlock_irqrestore(&pctrl->lock, flags);
367 dev_err(pctrl->dev, "Unsupported config parameter: %x\n",
372 /* Range-check user-supplied value */
374 dev_err(pctrl->dev, "config %x: %x is invalid\n", param, arg);
378 spin_lock_irqsave(&pctrl->lock, flags);
379 val = readl(pctrl->regs + g->ctl_reg);
380 val &= ~(mask << bit);
382 writel(val, pctrl->regs + g->ctl_reg);
383 spin_unlock_irqrestore(&pctrl->lock, flags);
389 static const struct pinconf_ops msm_pinconf_ops = {
390 .pin_config_get = msm_config_get,
391 .pin_config_set = msm_config_set,
392 .pin_config_group_get = msm_config_group_get,
393 .pin_config_group_set = msm_config_group_set,
396 static struct pinctrl_desc msm_pinctrl_desc = {
397 .pctlops = &msm_pinctrl_ops,
398 .pmxops = &msm_pinmux_ops,
399 .confops = &msm_pinconf_ops,
400 .owner = THIS_MODULE,
403 static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
405 const struct msm_pingroup *g;
406 struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip);
410 g = &pctrl->soc->groups[offset];
412 spin_lock_irqsave(&pctrl->lock, flags);
414 val = readl(pctrl->regs + g->ctl_reg);
415 val &= ~BIT(g->oe_bit);
416 writel(val, pctrl->regs + g->ctl_reg);
418 spin_unlock_irqrestore(&pctrl->lock, flags);
423 static int msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value)
425 const struct msm_pingroup *g;
426 struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip);
430 g = &pctrl->soc->groups[offset];
432 spin_lock_irqsave(&pctrl->lock, flags);
434 val = readl(pctrl->regs + g->io_reg);
436 val |= BIT(g->out_bit);
438 val &= ~BIT(g->out_bit);
439 writel(val, pctrl->regs + g->io_reg);
441 val = readl(pctrl->regs + g->ctl_reg);
442 val |= BIT(g->oe_bit);
443 writel(val, pctrl->regs + g->ctl_reg);
445 spin_unlock_irqrestore(&pctrl->lock, flags);
450 static int msm_gpio_get(struct gpio_chip *chip, unsigned offset)
452 const struct msm_pingroup *g;
453 struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip);
456 g = &pctrl->soc->groups[offset];
458 val = readl(pctrl->regs + g->io_reg);
459 return !!(val & BIT(g->in_bit));
462 static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
464 const struct msm_pingroup *g;
465 struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip);
469 g = &pctrl->soc->groups[offset];
471 spin_lock_irqsave(&pctrl->lock, flags);
473 val = readl(pctrl->regs + g->io_reg);
475 val |= BIT(g->out_bit);
477 val &= ~BIT(g->out_bit);
478 writel(val, pctrl->regs + g->io_reg);
480 spin_unlock_irqrestore(&pctrl->lock, flags);
483 static int msm_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
485 struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip);
487 return irq_find_mapping(pctrl->domain, offset);
490 static int msm_gpio_request(struct gpio_chip *chip, unsigned offset)
492 int gpio = chip->base + offset;
493 return pinctrl_request_gpio(gpio);
496 static void msm_gpio_free(struct gpio_chip *chip, unsigned offset)
498 int gpio = chip->base + offset;
499 return pinctrl_free_gpio(gpio);
502 #ifdef CONFIG_DEBUG_FS
503 #include <linux/seq_file.h>
505 static void msm_gpio_dbg_show_one(struct seq_file *s,
506 struct pinctrl_dev *pctldev,
507 struct gpio_chip *chip,
511 const struct msm_pingroup *g;
512 struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip);
519 static const char * const pulls[] = {
526 g = &pctrl->soc->groups[offset];
527 ctl_reg = readl(pctrl->regs + g->ctl_reg);
529 is_out = !!(ctl_reg & BIT(g->oe_bit));
530 func = (ctl_reg >> g->mux_bit) & 7;
531 drive = (ctl_reg >> g->drv_bit) & 7;
532 pull = (ctl_reg >> g->pull_bit) & 3;
534 seq_printf(s, " %-8s: %-3s %d", g->name, is_out ? "out" : "in", func);
535 seq_printf(s, " %dmA", msm_regval_to_drive(drive));
536 seq_printf(s, " %s", pulls[pull]);
539 static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
541 unsigned gpio = chip->base;
544 for (i = 0; i < chip->ngpio; i++, gpio++) {
545 msm_gpio_dbg_show_one(s, NULL, chip, i, gpio);
551 #define msm_gpio_dbg_show NULL
554 static struct gpio_chip msm_gpio_template = {
555 .direction_input = msm_gpio_direction_input,
556 .direction_output = msm_gpio_direction_output,
559 .to_irq = msm_gpio_to_irq,
560 .request = msm_gpio_request,
561 .free = msm_gpio_free,
562 .dbg_show = msm_gpio_dbg_show,
565 /* For dual-edge interrupts in software, since some hardware has no
568 * At appropriate moments, this function may be called to flip the polarity
569 * settings of both-edge irq lines to try and catch the next edge.
571 * The attempt is considered successful if:
572 * - the status bit goes high, indicating that an edge was caught, or
573 * - the input value of the gpio doesn't change during the attempt.
574 * If the value changes twice during the process, that would cause the first
575 * test to fail but would force the second, as two opposite
576 * transitions would cause a detection no matter the polarity setting.
578 * The do-loop tries to sledge-hammer closed the timing hole between
579 * the initial value-read and the polarity-write - if the line value changes
580 * during that window, an interrupt is lost, the new polarity setting is
581 * incorrect, and the first success test will fail, causing a retry.
583 * Algorithm comes from Google's msmgpio driver.
585 static void msm_gpio_update_dual_edge_pos(struct msm_pinctrl *pctrl,
586 const struct msm_pingroup *g,
589 int loop_limit = 100;
590 unsigned val, val2, intstat;
594 val = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit);
596 pol = readl(pctrl->regs + g->intr_cfg_reg);
597 pol ^= BIT(g->intr_polarity_bit);
598 writel(pol, pctrl->regs + g->intr_cfg_reg);
600 val2 = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit);
601 intstat = readl(pctrl->regs + g->intr_status_reg);
602 if (intstat || (val == val2))
604 } while (loop_limit-- > 0);
605 dev_err(pctrl->dev, "dual-edge irq failed to stabilize, %#08x != %#08x\n",
609 static void msm_gpio_irq_mask(struct irq_data *d)
611 const struct msm_pingroup *g;
612 struct msm_pinctrl *pctrl;
616 pctrl = irq_data_get_irq_chip_data(d);
617 g = &pctrl->soc->groups[d->hwirq];
619 spin_lock_irqsave(&pctrl->lock, flags);
621 val = readl(pctrl->regs + g->intr_cfg_reg);
622 val &= ~BIT(g->intr_enable_bit);
623 writel(val, pctrl->regs + g->intr_cfg_reg);
625 clear_bit(d->hwirq, pctrl->enabled_irqs);
627 spin_unlock_irqrestore(&pctrl->lock, flags);
630 static void msm_gpio_irq_unmask(struct irq_data *d)
632 const struct msm_pingroup *g;
633 struct msm_pinctrl *pctrl;
637 pctrl = irq_data_get_irq_chip_data(d);
638 g = &pctrl->soc->groups[d->hwirq];
640 spin_lock_irqsave(&pctrl->lock, flags);
642 val = readl(pctrl->regs + g->intr_status_reg);
643 val &= ~BIT(g->intr_status_bit);
644 writel(val, pctrl->regs + g->intr_status_reg);
646 val = readl(pctrl->regs + g->intr_cfg_reg);
647 val |= BIT(g->intr_enable_bit);
648 writel(val, pctrl->regs + g->intr_cfg_reg);
650 set_bit(d->hwirq, pctrl->enabled_irqs);
652 spin_unlock_irqrestore(&pctrl->lock, flags);
655 static void msm_gpio_irq_ack(struct irq_data *d)
657 const struct msm_pingroup *g;
658 struct msm_pinctrl *pctrl;
662 pctrl = irq_data_get_irq_chip_data(d);
663 g = &pctrl->soc->groups[d->hwirq];
665 spin_lock_irqsave(&pctrl->lock, flags);
667 val = readl(pctrl->regs + g->intr_status_reg);
668 val &= ~BIT(g->intr_status_bit);
669 writel(val, pctrl->regs + g->intr_status_reg);
671 if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
672 msm_gpio_update_dual_edge_pos(pctrl, g, d);
674 spin_unlock_irqrestore(&pctrl->lock, flags);
677 #define INTR_TARGET_PROC_APPS 4
679 static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type)
681 const struct msm_pingroup *g;
682 struct msm_pinctrl *pctrl;
686 pctrl = irq_data_get_irq_chip_data(d);
687 g = &pctrl->soc->groups[d->hwirq];
689 spin_lock_irqsave(&pctrl->lock, flags);
692 * For hw without possibility of detecting both edges
694 if (g->intr_detection_width == 1 && type == IRQ_TYPE_EDGE_BOTH)
695 set_bit(d->hwirq, pctrl->dual_edge_irqs);
697 clear_bit(d->hwirq, pctrl->dual_edge_irqs);
699 /* Route interrupts to application cpu */
700 val = readl(pctrl->regs + g->intr_target_reg);
701 val &= ~(7 << g->intr_target_bit);
702 val |= INTR_TARGET_PROC_APPS << g->intr_target_bit;
703 writel(val, pctrl->regs + g->intr_target_reg);
705 /* Update configuration for gpio.
706 * RAW_STATUS_EN is left on for all gpio irqs. Due to the
707 * internal circuitry of TLMM, toggling the RAW_STATUS
708 * could cause the INTR_STATUS to be set for EDGE interrupts.
710 val = readl(pctrl->regs + g->intr_cfg_reg);
711 val |= BIT(g->intr_raw_status_bit);
712 if (g->intr_detection_width == 2) {
713 val &= ~(3 << g->intr_detection_bit);
714 val &= ~(1 << g->intr_polarity_bit);
716 case IRQ_TYPE_EDGE_RISING:
717 val |= 1 << g->intr_detection_bit;
718 val |= BIT(g->intr_polarity_bit);
720 case IRQ_TYPE_EDGE_FALLING:
721 val |= 2 << g->intr_detection_bit;
722 val |= BIT(g->intr_polarity_bit);
724 case IRQ_TYPE_EDGE_BOTH:
725 val |= 3 << g->intr_detection_bit;
726 val |= BIT(g->intr_polarity_bit);
728 case IRQ_TYPE_LEVEL_LOW:
730 case IRQ_TYPE_LEVEL_HIGH:
731 val |= BIT(g->intr_polarity_bit);
734 } else if (g->intr_detection_width == 1) {
735 val &= ~(1 << g->intr_detection_bit);
736 val &= ~(1 << g->intr_polarity_bit);
738 case IRQ_TYPE_EDGE_RISING:
739 val |= BIT(g->intr_detection_bit);
740 val |= BIT(g->intr_polarity_bit);
742 case IRQ_TYPE_EDGE_FALLING:
743 val |= BIT(g->intr_detection_bit);
745 case IRQ_TYPE_EDGE_BOTH:
746 val |= BIT(g->intr_detection_bit);
748 case IRQ_TYPE_LEVEL_LOW:
750 case IRQ_TYPE_LEVEL_HIGH:
751 val |= BIT(g->intr_polarity_bit);
757 writel(val, pctrl->regs + g->intr_cfg_reg);
759 if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
760 msm_gpio_update_dual_edge_pos(pctrl, g, d);
762 spin_unlock_irqrestore(&pctrl->lock, flags);
764 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
765 __irq_set_handler_locked(d->irq, handle_level_irq);
766 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
767 __irq_set_handler_locked(d->irq, handle_edge_irq);
772 static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
774 struct msm_pinctrl *pctrl;
777 pctrl = irq_data_get_irq_chip_data(d);
779 spin_lock_irqsave(&pctrl->lock, flags);
781 irq_set_irq_wake(pctrl->irq, on);
783 spin_unlock_irqrestore(&pctrl->lock, flags);
788 static int msm_gpio_irq_reqres(struct irq_data *d)
790 struct msm_pinctrl *pctrl = irq_data_get_irq_chip_data(d);
792 if (gpio_lock_as_irq(&pctrl->chip, d->hwirq)) {
793 dev_err(pctrl->dev, "unable to lock HW IRQ %lu for IRQ\n",
800 static void msm_gpio_irq_relres(struct irq_data *d)
802 struct msm_pinctrl *pctrl = irq_data_get_irq_chip_data(d);
804 gpio_unlock_as_irq(&pctrl->chip, d->hwirq);
807 static struct irq_chip msm_gpio_irq_chip = {
809 .irq_mask = msm_gpio_irq_mask,
810 .irq_unmask = msm_gpio_irq_unmask,
811 .irq_ack = msm_gpio_irq_ack,
812 .irq_set_type = msm_gpio_irq_set_type,
813 .irq_set_wake = msm_gpio_irq_set_wake,
814 .irq_request_resources = msm_gpio_irq_reqres,
815 .irq_release_resources = msm_gpio_irq_relres,
818 static void msm_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
820 const struct msm_pingroup *g;
821 struct msm_pinctrl *pctrl = irq_desc_get_handler_data(desc);
822 struct irq_chip *chip = irq_get_chip(irq);
828 chained_irq_enter(chip, desc);
831 * Each pin has it's own IRQ status register, so use
832 * enabled_irq bitmap to limit the number of reads.
834 for_each_set_bit(i, pctrl->enabled_irqs, pctrl->chip.ngpio) {
835 g = &pctrl->soc->groups[i];
836 val = readl(pctrl->regs + g->intr_status_reg);
837 if (val & BIT(g->intr_status_bit)) {
838 irq_pin = irq_find_mapping(pctrl->domain, i);
839 generic_handle_irq(irq_pin);
844 /* No interrupts were flagged */
846 handle_bad_irq(irq, desc);
848 chained_irq_exit(chip, desc);
852 * This lock class tells lockdep that GPIO irqs are in a different
853 * category than their parents, so it won't report false recursion.
855 static struct lock_class_key gpio_lock_class;
857 static int msm_gpio_init(struct msm_pinctrl *pctrl)
859 struct gpio_chip *chip;
864 unsigned ngpio = pctrl->soc->ngpios;
866 if (WARN_ON(ngpio > MAX_NR_GPIO))
872 chip->label = dev_name(pctrl->dev);
873 chip->dev = pctrl->dev;
874 chip->owner = THIS_MODULE;
875 chip->of_node = pctrl->dev->of_node;
877 ret = gpiochip_add(&pctrl->chip);
879 dev_err(pctrl->dev, "Failed register gpiochip\n");
883 ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), 0, 0, chip->ngpio);
885 dev_err(pctrl->dev, "Failed to add pin range\n");
889 pctrl->domain = irq_domain_add_linear(pctrl->dev->of_node, chip->ngpio,
890 &irq_domain_simple_ops, NULL);
891 if (!pctrl->domain) {
892 dev_err(pctrl->dev, "Failed to register irq domain\n");
893 r = gpiochip_remove(&pctrl->chip);
897 for (i = 0; i < chip->ngpio; i++) {
898 irq = irq_create_mapping(pctrl->domain, i);
899 irq_set_lockdep_class(irq, &gpio_lock_class);
900 irq_set_chip_and_handler(irq, &msm_gpio_irq_chip, handle_edge_irq);
901 irq_set_chip_data(irq, pctrl);
904 irq_set_handler_data(pctrl->irq, pctrl);
905 irq_set_chained_handler(pctrl->irq, msm_gpio_irq_handler);
910 int msm_pinctrl_probe(struct platform_device *pdev,
911 const struct msm_pinctrl_soc_data *soc_data)
913 struct msm_pinctrl *pctrl;
914 struct resource *res;
917 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
919 dev_err(&pdev->dev, "Can't allocate msm_pinctrl\n");
922 pctrl->dev = &pdev->dev;
923 pctrl->soc = soc_data;
924 pctrl->chip = msm_gpio_template;
926 spin_lock_init(&pctrl->lock);
928 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
929 pctrl->regs = devm_ioremap_resource(&pdev->dev, res);
930 if (IS_ERR(pctrl->regs))
931 return PTR_ERR(pctrl->regs);
933 pctrl->irq = platform_get_irq(pdev, 0);
934 if (pctrl->irq < 0) {
935 dev_err(&pdev->dev, "No interrupt defined for msmgpio\n");
939 msm_pinctrl_desc.name = dev_name(&pdev->dev);
940 msm_pinctrl_desc.pins = pctrl->soc->pins;
941 msm_pinctrl_desc.npins = pctrl->soc->npins;
942 pctrl->pctrl = pinctrl_register(&msm_pinctrl_desc, &pdev->dev, pctrl);
944 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
948 ret = msm_gpio_init(pctrl);
950 pinctrl_unregister(pctrl->pctrl);
954 platform_set_drvdata(pdev, pctrl);
956 dev_dbg(&pdev->dev, "Probed Qualcomm pinctrl driver\n");
960 EXPORT_SYMBOL(msm_pinctrl_probe);
962 int msm_pinctrl_remove(struct platform_device *pdev)
964 struct msm_pinctrl *pctrl = platform_get_drvdata(pdev);
967 ret = gpiochip_remove(&pctrl->chip);
969 dev_err(&pdev->dev, "Failed to remove gpiochip\n");
973 irq_set_chained_handler(pctrl->irq, NULL);
974 irq_domain_remove(pctrl->domain);
975 pinctrl_unregister(pctrl->pctrl);
979 EXPORT_SYMBOL(msm_pinctrl_remove);