2 * Generic GPIO driver for logic cells found in the Nomadik SoC
4 * Copyright (C) 2008,2009 STMicroelectronics
5 * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it>
6 * Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com>
7 * Copyright (C) 2011 Linus Walleij <linus.walleij@linaro.org>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/init.h>
16 #include <linux/device.h>
17 #include <linux/platform_device.h>
19 #include <linux/clk.h>
20 #include <linux/err.h>
21 #include <linux/gpio.h>
22 #include <linux/spinlock.h>
23 #include <linux/interrupt.h>
24 #include <linux/irq.h>
25 #include <linux/irqdomain.h>
26 #include <linux/slab.h>
27 #include <linux/of_device.h>
28 #include <linux/pinctrl/pinctrl.h>
29 #include <linux/pinctrl/pinmux.h>
30 #include <linux/pinctrl/pinconf.h>
31 /* Since we request GPIOs from ourself */
32 #include <linux/pinctrl/consumer.h>
34 #include <asm/mach/irq.h>
36 #include <plat/pincfg.h>
37 #include <plat/gpio-nomadik.h>
39 #include "pinctrl-nomadik.h"
42 * The GPIO module in the Nomadik family of Systems-on-Chip is an
43 * AMBA device, managing 32 pins and alternate functions. The logic block
44 * is currently used in the Nomadik and ux500.
46 * Symbols in this file are called "nmk_gpio" for "nomadik gpio"
49 #define NMK_GPIO_PER_CHIP 32
51 struct nmk_gpio_chip {
52 struct gpio_chip chip;
53 struct irq_domain *domain;
57 unsigned int parent_irq;
58 int secondary_parent_irq;
59 u32 (*get_secondary_status)(unsigned int bank);
60 void (*set_ioforce)(bool enable);
63 /* Keep track of configured edges */
77 struct pinctrl_dev *pctl;
78 const struct nmk_pinctrl_soc_data *soc;
81 static struct nmk_gpio_chip *
82 nmk_gpio_chips[DIV_ROUND_UP(ARCH_NR_GPIOS, NMK_GPIO_PER_CHIP)];
84 static DEFINE_SPINLOCK(nmk_gpio_slpm_lock);
86 #define NUM_BANKS ARRAY_SIZE(nmk_gpio_chips)
88 static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip,
89 unsigned offset, int gpio_mode)
91 u32 bit = 1 << offset;
94 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~bit;
95 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~bit;
96 if (gpio_mode & NMK_GPIO_ALT_A)
98 if (gpio_mode & NMK_GPIO_ALT_B)
100 writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA);
101 writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB);
104 static void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip,
105 unsigned offset, enum nmk_gpio_slpm mode)
107 u32 bit = 1 << offset;
110 slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC);
111 if (mode == NMK_GPIO_SLPM_NOCHANGE)
115 writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC);
118 static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip,
119 unsigned offset, enum nmk_gpio_pull pull)
121 u32 bit = 1 << offset;
124 pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS);
125 if (pull == NMK_GPIO_PULL_NONE) {
127 nmk_chip->pull_up &= ~bit;
132 writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS);
134 if (pull == NMK_GPIO_PULL_UP) {
135 nmk_chip->pull_up |= bit;
136 writel(bit, nmk_chip->addr + NMK_GPIO_DATS);
137 } else if (pull == NMK_GPIO_PULL_DOWN) {
138 nmk_chip->pull_up &= ~bit;
139 writel(bit, nmk_chip->addr + NMK_GPIO_DATC);
143 static void __nmk_gpio_set_lowemi(struct nmk_gpio_chip *nmk_chip,
144 unsigned offset, bool lowemi)
146 u32 bit = BIT(offset);
147 bool enabled = nmk_chip->lowemi & bit;
149 if (lowemi == enabled)
153 nmk_chip->lowemi |= bit;
155 nmk_chip->lowemi &= ~bit;
157 writel_relaxed(nmk_chip->lowemi,
158 nmk_chip->addr + NMK_GPIO_LOWEMI);
161 static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip,
164 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC);
167 static void __nmk_gpio_set_output(struct nmk_gpio_chip *nmk_chip,
168 unsigned offset, int val)
171 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATS);
173 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATC);
176 static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip,
177 unsigned offset, int val)
179 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRS);
180 __nmk_gpio_set_output(nmk_chip, offset, val);
183 static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip,
184 unsigned offset, int gpio_mode,
187 u32 rwimsc = nmk_chip->rwimsc;
188 u32 fwimsc = nmk_chip->fwimsc;
190 if (glitch && nmk_chip->set_ioforce) {
191 u32 bit = BIT(offset);
193 /* Prevent spurious wakeups */
194 writel(rwimsc & ~bit, nmk_chip->addr + NMK_GPIO_RWIMSC);
195 writel(fwimsc & ~bit, nmk_chip->addr + NMK_GPIO_FWIMSC);
197 nmk_chip->set_ioforce(true);
200 __nmk_gpio_set_mode(nmk_chip, offset, gpio_mode);
202 if (glitch && nmk_chip->set_ioforce) {
203 nmk_chip->set_ioforce(false);
205 writel(rwimsc, nmk_chip->addr + NMK_GPIO_RWIMSC);
206 writel(fwimsc, nmk_chip->addr + NMK_GPIO_FWIMSC);
211 nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip *nmk_chip, unsigned offset)
213 u32 falling = nmk_chip->fimsc & BIT(offset);
214 u32 rising = nmk_chip->rimsc & BIT(offset);
215 int gpio = nmk_chip->chip.base + offset;
216 int irq = NOMADIK_GPIO_TO_IRQ(gpio);
217 struct irq_data *d = irq_get_irq_data(irq);
219 if (!rising && !falling)
222 if (!d || !irqd_irq_disabled(d))
226 nmk_chip->rimsc &= ~BIT(offset);
227 writel_relaxed(nmk_chip->rimsc,
228 nmk_chip->addr + NMK_GPIO_RIMSC);
232 nmk_chip->fimsc &= ~BIT(offset);
233 writel_relaxed(nmk_chip->fimsc,
234 nmk_chip->addr + NMK_GPIO_FIMSC);
237 dev_dbg(nmk_chip->chip.dev, "%d: clearing interrupt mask\n", gpio);
240 static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset,
241 pin_cfg_t cfg, bool sleep, unsigned int *slpmregs)
243 static const char *afnames[] = {
244 [NMK_GPIO_ALT_GPIO] = "GPIO",
245 [NMK_GPIO_ALT_A] = "A",
246 [NMK_GPIO_ALT_B] = "B",
247 [NMK_GPIO_ALT_C] = "C"
249 static const char *pullnames[] = {
250 [NMK_GPIO_PULL_NONE] = "none",
251 [NMK_GPIO_PULL_UP] = "up",
252 [NMK_GPIO_PULL_DOWN] = "down",
253 [3] /* illegal */ = "??"
255 static const char *slpmnames[] = {
256 [NMK_GPIO_SLPM_INPUT] = "input/wakeup",
257 [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup",
260 int pin = PIN_NUM(cfg);
261 int pull = PIN_PULL(cfg);
262 int af = PIN_ALT(cfg);
263 int slpm = PIN_SLPM(cfg);
264 int output = PIN_DIR(cfg);
265 int val = PIN_VAL(cfg);
266 bool glitch = af == NMK_GPIO_ALT_C;
268 dev_dbg(nmk_chip->chip.dev, "pin %d [%#lx]: af %s, pull %s, slpm %s (%s%s)\n",
269 pin, cfg, afnames[af], pullnames[pull], slpmnames[slpm],
270 output ? "output " : "input",
271 output ? (val ? "high" : "low") : "");
274 int slpm_pull = PIN_SLPM_PULL(cfg);
275 int slpm_output = PIN_SLPM_DIR(cfg);
276 int slpm_val = PIN_SLPM_VAL(cfg);
278 af = NMK_GPIO_ALT_GPIO;
281 * The SLPM_* values are normal values + 1 to allow zero to
282 * mean "same as normal".
285 pull = slpm_pull - 1;
287 output = slpm_output - 1;
291 dev_dbg(nmk_chip->chip.dev, "pin %d: sleep pull %s, dir %s, val %s\n",
293 slpm_pull ? pullnames[pull] : "same",
294 slpm_output ? (output ? "output" : "input") : "same",
295 slpm_val ? (val ? "high" : "low") : "same");
299 __nmk_gpio_make_output(nmk_chip, offset, val);
301 __nmk_gpio_make_input(nmk_chip, offset);
302 __nmk_gpio_set_pull(nmk_chip, offset, pull);
305 __nmk_gpio_set_lowemi(nmk_chip, offset, PIN_LOWEMI(cfg));
308 * If the pin is switching to altfunc, and there was an interrupt
309 * installed on it which has been lazy disabled, actually mask the
310 * interrupt to prevent spurious interrupts that would occur while the
311 * pin is under control of the peripheral. Only SKE does this.
313 if (af != NMK_GPIO_ALT_GPIO)
314 nmk_gpio_disable_lazy_irq(nmk_chip, offset);
317 * If we've backed up the SLPM registers (glitch workaround), modify
318 * the backups since they will be restored.
321 if (slpm == NMK_GPIO_SLPM_NOCHANGE)
322 slpmregs[nmk_chip->bank] |= BIT(offset);
324 slpmregs[nmk_chip->bank] &= ~BIT(offset);
326 __nmk_gpio_set_slpm(nmk_chip, offset, slpm);
328 __nmk_gpio_set_mode_safe(nmk_chip, offset, af, glitch);
332 * Safe sequence used to switch IOs between GPIO and Alternate-C mode:
333 * - Save SLPM registers
334 * - Set SLPM=0 for the IOs you want to switch and others to 1
335 * - Configure the GPIO registers for the IOs that are being switched
337 * - Modify the AFLSA/B registers for the IOs that are being switched
339 * - Restore SLPM registers
340 * - Any spurious wake up event during switch sequence to be ignored and
343 static void nmk_gpio_glitch_slpm_init(unsigned int *slpm)
347 for (i = 0; i < NUM_BANKS; i++) {
348 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
349 unsigned int temp = slpm[i];
354 clk_enable(chip->clk);
356 slpm[i] = readl(chip->addr + NMK_GPIO_SLPC);
357 writel(temp, chip->addr + NMK_GPIO_SLPC);
361 static void nmk_gpio_glitch_slpm_restore(unsigned int *slpm)
365 for (i = 0; i < NUM_BANKS; i++) {
366 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
371 writel(slpm[i], chip->addr + NMK_GPIO_SLPC);
373 clk_disable(chip->clk);
377 static int __nmk_config_pins(pin_cfg_t *cfgs, int num, bool sleep)
379 static unsigned int slpm[NUM_BANKS];
385 for (i = 0; i < num; i++) {
386 if (PIN_ALT(cfgs[i]) == NMK_GPIO_ALT_C) {
392 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
395 memset(slpm, 0xff, sizeof(slpm));
397 for (i = 0; i < num; i++) {
398 int pin = PIN_NUM(cfgs[i]);
399 int offset = pin % NMK_GPIO_PER_CHIP;
401 if (PIN_ALT(cfgs[i]) == NMK_GPIO_ALT_C)
402 slpm[pin / NMK_GPIO_PER_CHIP] &= ~BIT(offset);
405 nmk_gpio_glitch_slpm_init(slpm);
408 for (i = 0; i < num; i++) {
409 struct nmk_gpio_chip *nmk_chip;
410 int pin = PIN_NUM(cfgs[i]);
412 nmk_chip = nmk_gpio_chips[pin / NMK_GPIO_PER_CHIP];
418 clk_enable(nmk_chip->clk);
419 spin_lock(&nmk_chip->lock);
420 __nmk_config_pin(nmk_chip, pin % NMK_GPIO_PER_CHIP,
421 cfgs[i], sleep, glitch ? slpm : NULL);
422 spin_unlock(&nmk_chip->lock);
423 clk_disable(nmk_chip->clk);
427 nmk_gpio_glitch_slpm_restore(slpm);
429 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
435 * nmk_config_pin - configure a pin's mux attributes
436 * @cfg: pin confguration
437 * @sleep: Non-zero to apply the sleep mode configuration
438 * Configures a pin's mode (alternate function or GPIO), its pull up status,
439 * and its sleep mode based on the specified configuration. The @cfg is
440 * usually one of the SoC specific macros defined in mach/<soc>-pins.h. These
441 * are constructed using, and can be further enhanced with, the macros in
444 * If a pin's mode is set to GPIO, it is configured as an input to avoid
445 * side-effects. The gpio can be manipulated later using standard GPIO API
448 int nmk_config_pin(pin_cfg_t cfg, bool sleep)
450 return __nmk_config_pins(&cfg, 1, sleep);
452 EXPORT_SYMBOL(nmk_config_pin);
455 * nmk_config_pins - configure several pins at once
456 * @cfgs: array of pin configurations
457 * @num: number of elments in the array
459 * Configures several pins using nmk_config_pin(). Refer to that function for
460 * further information.
462 int nmk_config_pins(pin_cfg_t *cfgs, int num)
464 return __nmk_config_pins(cfgs, num, false);
466 EXPORT_SYMBOL(nmk_config_pins);
468 int nmk_config_pins_sleep(pin_cfg_t *cfgs, int num)
470 return __nmk_config_pins(cfgs, num, true);
472 EXPORT_SYMBOL(nmk_config_pins_sleep);
475 * nmk_gpio_set_slpm() - configure the sleep mode of a pin
477 * @mode: NMK_GPIO_SLPM_INPUT or NMK_GPIO_SLPM_NOCHANGE,
479 * This register is actually in the pinmux layer, not the GPIO block itself.
480 * The GPIO1B_SLPM register defines the GPIO mode when SLEEP/DEEP-SLEEP
481 * mode is entered (i.e. when signal IOFORCE is HIGH by the platform code).
482 * Each GPIO can be configured to be forced into GPIO mode when IOFORCE is
483 * HIGH, overriding the normal setting defined by GPIO_AFSELx registers.
484 * When IOFORCE returns LOW (by software, after SLEEP/DEEP-SLEEP exit),
485 * the GPIOs return to the normal setting defined by GPIO_AFSELx registers.
487 * If @mode is NMK_GPIO_SLPM_INPUT, the corresponding GPIO is switched to GPIO
488 * mode when signal IOFORCE is HIGH (i.e. when SLEEP/DEEP-SLEEP mode is
489 * entered) regardless of the altfunction selected. Also wake-up detection is
492 * If @mode is NMK_GPIO_SLPM_NOCHANGE, the corresponding GPIO remains
493 * controlled by NMK_GPIO_DATC, NMK_GPIO_DATS, NMK_GPIO_DIR, NMK_GPIO_PDIS
494 * (for altfunction GPIO) or respective on-chip peripherals (for other
495 * altfuncs) when IOFORCE is HIGH. Also wake-up detection DISABLED.
497 * Note that enable_irq_wake() will automatically enable wakeup detection.
499 int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode)
501 struct nmk_gpio_chip *nmk_chip;
504 nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP];
508 clk_enable(nmk_chip->clk);
509 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
510 spin_lock(&nmk_chip->lock);
512 __nmk_gpio_set_slpm(nmk_chip, gpio % NMK_GPIO_PER_CHIP, mode);
514 spin_unlock(&nmk_chip->lock);
515 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
516 clk_disable(nmk_chip->clk);
522 * nmk_gpio_set_pull() - enable/disable pull up/down on a gpio
524 * @pull: one of NMK_GPIO_PULL_DOWN, NMK_GPIO_PULL_UP, and NMK_GPIO_PULL_NONE
526 * Enables/disables pull up/down on a specified pin. This only takes effect if
527 * the pin is configured as an input (either explicitly or by the alternate
530 * NOTE: If enabling the pull up/down, the caller must ensure that the GPIO is
531 * configured as an input. Otherwise, due to the way the controller registers
532 * work, this function will change the value output on the pin.
534 int nmk_gpio_set_pull(int gpio, enum nmk_gpio_pull pull)
536 struct nmk_gpio_chip *nmk_chip;
539 nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP];
543 clk_enable(nmk_chip->clk);
544 spin_lock_irqsave(&nmk_chip->lock, flags);
545 __nmk_gpio_set_pull(nmk_chip, gpio % NMK_GPIO_PER_CHIP, pull);
546 spin_unlock_irqrestore(&nmk_chip->lock, flags);
547 clk_disable(nmk_chip->clk);
554 * nmk_gpio_set_mode() - set the mux mode of a gpio pin
556 * @gpio_mode: one of NMK_GPIO_ALT_GPIO, NMK_GPIO_ALT_A,
557 * NMK_GPIO_ALT_B, and NMK_GPIO_ALT_C
559 * Sets the mode of the specified pin to one of the alternate functions or
562 int nmk_gpio_set_mode(int gpio, int gpio_mode)
564 struct nmk_gpio_chip *nmk_chip;
567 nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP];
571 clk_enable(nmk_chip->clk);
572 spin_lock_irqsave(&nmk_chip->lock, flags);
573 __nmk_gpio_set_mode(nmk_chip, gpio % NMK_GPIO_PER_CHIP, gpio_mode);
574 spin_unlock_irqrestore(&nmk_chip->lock, flags);
575 clk_disable(nmk_chip->clk);
579 EXPORT_SYMBOL(nmk_gpio_set_mode);
581 int nmk_gpio_get_mode(int gpio)
583 struct nmk_gpio_chip *nmk_chip;
584 u32 afunc, bfunc, bit;
586 nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP];
590 bit = 1 << (gpio % NMK_GPIO_PER_CHIP);
592 clk_enable(nmk_chip->clk);
594 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & bit;
595 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & bit;
597 clk_disable(nmk_chip->clk);
599 return (afunc ? NMK_GPIO_ALT_A : 0) | (bfunc ? NMK_GPIO_ALT_B : 0);
601 EXPORT_SYMBOL(nmk_gpio_get_mode);
605 static inline int nmk_gpio_get_bitmask(int gpio)
607 return 1 << (gpio % NMK_GPIO_PER_CHIP);
610 static void nmk_gpio_irq_ack(struct irq_data *d)
612 struct nmk_gpio_chip *nmk_chip;
614 nmk_chip = irq_data_get_irq_chip_data(d);
618 clk_enable(nmk_chip->clk);
619 writel(nmk_gpio_get_bitmask(d->hwirq), nmk_chip->addr + NMK_GPIO_IC);
620 clk_disable(nmk_chip->clk);
623 enum nmk_gpio_irq_type {
628 static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip,
629 int gpio, enum nmk_gpio_irq_type which,
632 u32 bitmask = nmk_gpio_get_bitmask(gpio);
638 if (which == NORMAL) {
639 rimscreg = NMK_GPIO_RIMSC;
640 fimscreg = NMK_GPIO_FIMSC;
641 rimscval = &nmk_chip->rimsc;
642 fimscval = &nmk_chip->fimsc;
644 rimscreg = NMK_GPIO_RWIMSC;
645 fimscreg = NMK_GPIO_FWIMSC;
646 rimscval = &nmk_chip->rwimsc;
647 fimscval = &nmk_chip->fwimsc;
650 /* we must individually set/clear the two edges */
651 if (nmk_chip->edge_rising & bitmask) {
653 *rimscval |= bitmask;
655 *rimscval &= ~bitmask;
656 writel(*rimscval, nmk_chip->addr + rimscreg);
658 if (nmk_chip->edge_falling & bitmask) {
660 *fimscval |= bitmask;
662 *fimscval &= ~bitmask;
663 writel(*fimscval, nmk_chip->addr + fimscreg);
667 static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip,
671 * Ensure WAKEUP_ENABLE is on. No need to disable it if wakeup is
672 * disabled, since setting SLPM to 1 increases power consumption, and
673 * wakeup is anyhow controlled by the RIMSC and FIMSC registers.
675 if (nmk_chip->sleepmode && on) {
676 __nmk_gpio_set_slpm(nmk_chip, gpio % NMK_GPIO_PER_CHIP,
677 NMK_GPIO_SLPM_WAKEUP_ENABLE);
680 __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, on);
683 static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable)
685 struct nmk_gpio_chip *nmk_chip;
689 nmk_chip = irq_data_get_irq_chip_data(d);
690 bitmask = nmk_gpio_get_bitmask(d->hwirq);
694 clk_enable(nmk_chip->clk);
695 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
696 spin_lock(&nmk_chip->lock);
698 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, enable);
700 if (!(nmk_chip->real_wake & bitmask))
701 __nmk_gpio_set_wake(nmk_chip, d->hwirq, enable);
703 spin_unlock(&nmk_chip->lock);
704 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
705 clk_disable(nmk_chip->clk);
710 static void nmk_gpio_irq_mask(struct irq_data *d)
712 nmk_gpio_irq_maskunmask(d, false);
715 static void nmk_gpio_irq_unmask(struct irq_data *d)
717 nmk_gpio_irq_maskunmask(d, true);
720 static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
722 struct nmk_gpio_chip *nmk_chip;
726 nmk_chip = irq_data_get_irq_chip_data(d);
729 bitmask = nmk_gpio_get_bitmask(d->hwirq);
731 clk_enable(nmk_chip->clk);
732 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
733 spin_lock(&nmk_chip->lock);
735 if (irqd_irq_disabled(d))
736 __nmk_gpio_set_wake(nmk_chip, d->hwirq, on);
739 nmk_chip->real_wake |= bitmask;
741 nmk_chip->real_wake &= ~bitmask;
743 spin_unlock(&nmk_chip->lock);
744 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
745 clk_disable(nmk_chip->clk);
750 static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type)
752 bool enabled = !irqd_irq_disabled(d);
753 bool wake = irqd_is_wakeup_set(d);
754 struct nmk_gpio_chip *nmk_chip;
758 nmk_chip = irq_data_get_irq_chip_data(d);
759 bitmask = nmk_gpio_get_bitmask(d->hwirq);
762 if (type & IRQ_TYPE_LEVEL_HIGH)
764 if (type & IRQ_TYPE_LEVEL_LOW)
767 clk_enable(nmk_chip->clk);
768 spin_lock_irqsave(&nmk_chip->lock, flags);
771 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, false);
774 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, false);
776 nmk_chip->edge_rising &= ~bitmask;
777 if (type & IRQ_TYPE_EDGE_RISING)
778 nmk_chip->edge_rising |= bitmask;
780 nmk_chip->edge_falling &= ~bitmask;
781 if (type & IRQ_TYPE_EDGE_FALLING)
782 nmk_chip->edge_falling |= bitmask;
785 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, true);
788 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, true);
790 spin_unlock_irqrestore(&nmk_chip->lock, flags);
791 clk_disable(nmk_chip->clk);
796 static unsigned int nmk_gpio_irq_startup(struct irq_data *d)
798 struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d);
800 clk_enable(nmk_chip->clk);
801 nmk_gpio_irq_unmask(d);
805 static void nmk_gpio_irq_shutdown(struct irq_data *d)
807 struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d);
809 nmk_gpio_irq_mask(d);
810 clk_disable(nmk_chip->clk);
813 static struct irq_chip nmk_gpio_irq_chip = {
814 .name = "Nomadik-GPIO",
815 .irq_ack = nmk_gpio_irq_ack,
816 .irq_mask = nmk_gpio_irq_mask,
817 .irq_unmask = nmk_gpio_irq_unmask,
818 .irq_set_type = nmk_gpio_irq_set_type,
819 .irq_set_wake = nmk_gpio_irq_set_wake,
820 .irq_startup = nmk_gpio_irq_startup,
821 .irq_shutdown = nmk_gpio_irq_shutdown,
822 .flags = IRQCHIP_MASK_ON_SUSPEND,
825 static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc,
828 struct nmk_gpio_chip *nmk_chip;
829 struct irq_chip *host_chip = irq_get_chip(irq);
831 chained_irq_enter(host_chip, desc);
833 nmk_chip = irq_get_handler_data(irq);
835 int bit = __ffs(status);
837 generic_handle_irq(irq_find_mapping(nmk_chip->domain, bit));
841 chained_irq_exit(host_chip, desc);
844 static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
846 struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq);
849 clk_enable(nmk_chip->clk);
850 status = readl(nmk_chip->addr + NMK_GPIO_IS);
851 clk_disable(nmk_chip->clk);
853 __nmk_gpio_irq_handler(irq, desc, status);
856 static void nmk_gpio_secondary_irq_handler(unsigned int irq,
857 struct irq_desc *desc)
859 struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq);
860 u32 status = nmk_chip->get_secondary_status(nmk_chip->bank);
862 __nmk_gpio_irq_handler(irq, desc, status);
865 static int nmk_gpio_init_irq(struct nmk_gpio_chip *nmk_chip)
867 irq_set_chained_handler(nmk_chip->parent_irq, nmk_gpio_irq_handler);
868 irq_set_handler_data(nmk_chip->parent_irq, nmk_chip);
870 if (nmk_chip->secondary_parent_irq >= 0) {
871 irq_set_chained_handler(nmk_chip->secondary_parent_irq,
872 nmk_gpio_secondary_irq_handler);
873 irq_set_handler_data(nmk_chip->secondary_parent_irq, nmk_chip);
881 static int nmk_gpio_request(struct gpio_chip *chip, unsigned offset)
884 * Map back to global GPIO space and request muxing, the direction
885 * parameter does not matter for this controller.
887 int gpio = chip->base + offset;
889 return pinctrl_request_gpio(gpio);
892 static void nmk_gpio_free(struct gpio_chip *chip, unsigned offset)
894 int gpio = chip->base + offset;
896 pinctrl_free_gpio(gpio);
899 static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset)
901 struct nmk_gpio_chip *nmk_chip =
902 container_of(chip, struct nmk_gpio_chip, chip);
904 clk_enable(nmk_chip->clk);
906 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC);
908 clk_disable(nmk_chip->clk);
913 static int nmk_gpio_get_input(struct gpio_chip *chip, unsigned offset)
915 struct nmk_gpio_chip *nmk_chip =
916 container_of(chip, struct nmk_gpio_chip, chip);
917 u32 bit = 1 << offset;
920 clk_enable(nmk_chip->clk);
922 value = (readl(nmk_chip->addr + NMK_GPIO_DAT) & bit) != 0;
924 clk_disable(nmk_chip->clk);
929 static void nmk_gpio_set_output(struct gpio_chip *chip, unsigned offset,
932 struct nmk_gpio_chip *nmk_chip =
933 container_of(chip, struct nmk_gpio_chip, chip);
935 clk_enable(nmk_chip->clk);
937 __nmk_gpio_set_output(nmk_chip, offset, val);
939 clk_disable(nmk_chip->clk);
942 static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset,
945 struct nmk_gpio_chip *nmk_chip =
946 container_of(chip, struct nmk_gpio_chip, chip);
948 clk_enable(nmk_chip->clk);
950 __nmk_gpio_make_output(nmk_chip, offset, val);
952 clk_disable(nmk_chip->clk);
957 static int nmk_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
959 struct nmk_gpio_chip *nmk_chip =
960 container_of(chip, struct nmk_gpio_chip, chip);
962 return irq_find_mapping(nmk_chip->domain, offset);
965 #ifdef CONFIG_DEBUG_FS
967 #include <linux/seq_file.h>
969 static void nmk_gpio_dbg_show_one(struct seq_file *s, struct gpio_chip *chip,
970 unsigned offset, unsigned gpio)
972 const char *label = gpiochip_is_requested(chip, offset);
973 struct nmk_gpio_chip *nmk_chip =
974 container_of(chip, struct nmk_gpio_chip, chip);
978 u32 bit = 1 << offset;
979 const char *modes[] = {
980 [NMK_GPIO_ALT_GPIO] = "gpio",
981 [NMK_GPIO_ALT_A] = "altA",
982 [NMK_GPIO_ALT_B] = "altB",
983 [NMK_GPIO_ALT_C] = "altC",
986 clk_enable(nmk_chip->clk);
987 is_out = !!(readl(nmk_chip->addr + NMK_GPIO_DIR) & bit);
988 pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & bit);
989 mode = nmk_gpio_get_mode(gpio);
991 seq_printf(s, " gpio-%-3d (%-20.20s) %s %s %s %s",
992 gpio, label ?: "(none)",
993 is_out ? "out" : "in ",
995 ? (chip->get(chip, offset) ? "hi" : "lo")
997 (mode < 0) ? "unknown" : modes[mode],
998 pull ? "pull" : "none");
1000 if (label && !is_out) {
1001 int irq = gpio_to_irq(gpio);
1002 struct irq_desc *desc = irq_to_desc(irq);
1004 /* This races with request_irq(), set_irq_type(),
1005 * and set_irq_wake() ... but those are "rare".
1007 if (irq >= 0 && desc->action) {
1009 u32 bitmask = nmk_gpio_get_bitmask(gpio);
1011 if (nmk_chip->edge_rising & bitmask)
1012 trigger = "edge-rising";
1013 else if (nmk_chip->edge_falling & bitmask)
1014 trigger = "edge-falling";
1016 trigger = "edge-undefined";
1018 seq_printf(s, " irq-%d %s%s",
1020 irqd_is_wakeup_set(&desc->irq_data)
1024 clk_disable(nmk_chip->clk);
1027 static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
1030 unsigned gpio = chip->base;
1032 for (i = 0; i < chip->ngpio; i++, gpio++) {
1033 nmk_gpio_dbg_show_one(s, chip, i, gpio);
1034 seq_printf(s, "\n");
1039 static inline void nmk_gpio_dbg_show_one(struct seq_file *s,
1040 struct gpio_chip *chip,
1041 unsigned offset, unsigned gpio)
1044 #define nmk_gpio_dbg_show NULL
1047 /* This structure is replicated for each GPIO block allocated at probe time */
1048 static struct gpio_chip nmk_gpio_template = {
1049 .request = nmk_gpio_request,
1050 .free = nmk_gpio_free,
1051 .direction_input = nmk_gpio_make_input,
1052 .get = nmk_gpio_get_input,
1053 .direction_output = nmk_gpio_make_output,
1054 .set = nmk_gpio_set_output,
1055 .to_irq = nmk_gpio_to_irq,
1056 .dbg_show = nmk_gpio_dbg_show,
1060 void nmk_gpio_clocks_enable(void)
1064 for (i = 0; i < NUM_BANKS; i++) {
1065 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
1070 clk_enable(chip->clk);
1074 void nmk_gpio_clocks_disable(void)
1078 for (i = 0; i < NUM_BANKS; i++) {
1079 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
1084 clk_disable(chip->clk);
1089 * Called from the suspend/resume path to only keep the real wakeup interrupts
1090 * (those that have had set_irq_wake() called on them) as wakeup interrupts,
1091 * and not the rest of the interrupts which we needed to have as wakeups for
1094 * PM ops are not used since this needs to be done at the end, after all the
1095 * other drivers are done with their suspend callbacks.
1097 void nmk_gpio_wakeups_suspend(void)
1101 for (i = 0; i < NUM_BANKS; i++) {
1102 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
1107 clk_enable(chip->clk);
1109 writel(chip->rwimsc & chip->real_wake,
1110 chip->addr + NMK_GPIO_RWIMSC);
1111 writel(chip->fwimsc & chip->real_wake,
1112 chip->addr + NMK_GPIO_FWIMSC);
1114 clk_disable(chip->clk);
1118 void nmk_gpio_wakeups_resume(void)
1122 for (i = 0; i < NUM_BANKS; i++) {
1123 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
1128 clk_enable(chip->clk);
1130 writel(chip->rwimsc, chip->addr + NMK_GPIO_RWIMSC);
1131 writel(chip->fwimsc, chip->addr + NMK_GPIO_FWIMSC);
1133 clk_disable(chip->clk);
1138 * Read the pull up/pull down status.
1139 * A bit set in 'pull_up' means that pull up
1140 * is selected if pull is enabled in PDIS register.
1141 * Note: only pull up/down set via this driver can
1142 * be detected due to HW limitations.
1144 void nmk_gpio_read_pull(int gpio_bank, u32 *pull_up)
1146 if (gpio_bank < NUM_BANKS) {
1147 struct nmk_gpio_chip *chip = nmk_gpio_chips[gpio_bank];
1152 *pull_up = chip->pull_up;
1156 int nmk_gpio_irq_map(struct irq_domain *d, unsigned int irq,
1157 irq_hw_number_t hwirq)
1159 struct nmk_gpio_chip *nmk_chip = d->host_data;
1164 irq_set_chip_and_handler(irq, &nmk_gpio_irq_chip, handle_edge_irq);
1165 set_irq_flags(irq, IRQF_VALID);
1166 irq_set_chip_data(irq, nmk_chip);
1167 irq_set_irq_type(irq, IRQ_TYPE_EDGE_FALLING);
1172 const struct irq_domain_ops nmk_gpio_irq_simple_ops = {
1173 .map = nmk_gpio_irq_map,
1174 .xlate = irq_domain_xlate_twocell,
1177 static int __devinit nmk_gpio_probe(struct platform_device *dev)
1179 struct nmk_gpio_platform_data *pdata = dev->dev.platform_data;
1180 struct device_node *np = dev->dev.of_node;
1181 struct nmk_gpio_chip *nmk_chip;
1182 struct gpio_chip *chip;
1183 struct resource *res;
1190 if (!pdata && !np) {
1191 dev_err(&dev->dev, "No platform data or device tree found\n");
1196 pdata = devm_kzalloc(&dev->dev, sizeof(*pdata), GFP_KERNEL);
1200 if (of_get_property(np, "st,supports-sleepmode", NULL))
1201 pdata->supports_sleepmode = true;
1203 if (of_property_read_u32(np, "gpio-bank", &dev->id)) {
1204 dev_err(&dev->dev, "gpio-bank property not found\n");
1209 pdata->first_gpio = dev->id * NMK_GPIO_PER_CHIP;
1210 pdata->num_gpio = NMK_GPIO_PER_CHIP;
1213 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
1219 irq = platform_get_irq(dev, 0);
1225 secondary_irq = platform_get_irq(dev, 1);
1226 if (secondary_irq >= 0 && !pdata->get_secondary_status) {
1231 base = devm_request_and_ioremap(&dev->dev, res);
1237 clk = devm_clk_get(&dev->dev, NULL);
1244 nmk_chip = devm_kzalloc(&dev->dev, sizeof(*nmk_chip), GFP_KERNEL);
1251 * The virt address in nmk_chip->addr is in the nomadik register space,
1252 * so we can simply convert the resource address, without remapping
1254 nmk_chip->bank = dev->id;
1255 nmk_chip->clk = clk;
1256 nmk_chip->addr = base;
1257 nmk_chip->chip = nmk_gpio_template;
1258 nmk_chip->parent_irq = irq;
1259 nmk_chip->secondary_parent_irq = secondary_irq;
1260 nmk_chip->get_secondary_status = pdata->get_secondary_status;
1261 nmk_chip->set_ioforce = pdata->set_ioforce;
1262 nmk_chip->sleepmode = pdata->supports_sleepmode;
1263 spin_lock_init(&nmk_chip->lock);
1265 chip = &nmk_chip->chip;
1266 chip->base = pdata->first_gpio;
1267 chip->ngpio = pdata->num_gpio;
1268 chip->label = pdata->name ?: dev_name(&dev->dev);
1269 chip->dev = &dev->dev;
1270 chip->owner = THIS_MODULE;
1272 clk_enable(nmk_chip->clk);
1273 nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI);
1274 clk_disable(nmk_chip->clk);
1276 #ifdef CONFIG_OF_GPIO
1280 ret = gpiochip_add(&nmk_chip->chip);
1284 BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips));
1286 nmk_gpio_chips[nmk_chip->bank] = nmk_chip;
1288 platform_set_drvdata(dev, nmk_chip);
1290 nmk_chip->domain = irq_domain_add_legacy(np, NMK_GPIO_PER_CHIP,
1291 NOMADIK_GPIO_TO_IRQ(pdata->first_gpio),
1292 0, &nmk_gpio_irq_simple_ops, nmk_chip);
1293 if (!nmk_chip->domain) {
1294 dev_err(&dev->dev, "failed to create irqdomain\n");
1299 nmk_gpio_init_irq(nmk_chip);
1301 dev_info(&dev->dev, "at address %p\n", nmk_chip->addr);
1306 dev_err(&dev->dev, "Failure %i for GPIO %i-%i\n", ret,
1307 pdata->first_gpio, pdata->first_gpio+31);
1312 static int nmk_get_groups_cnt(struct pinctrl_dev *pctldev)
1314 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1316 return npct->soc->ngroups;
1319 static const char *nmk_get_group_name(struct pinctrl_dev *pctldev,
1322 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1324 return npct->soc->groups[selector].name;
1327 static int nmk_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
1328 const unsigned **pins,
1331 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1333 *pins = npct->soc->groups[selector].pins;
1334 *num_pins = npct->soc->groups[selector].npins;
1338 static struct pinctrl_gpio_range *
1339 nmk_match_gpio_range(struct pinctrl_dev *pctldev, unsigned offset)
1341 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1344 for (i = 0; i < npct->soc->gpio_num_ranges; i++) {
1345 struct pinctrl_gpio_range *range;
1347 range = &npct->soc->gpio_ranges[i];
1348 if (offset >= range->pin_base &&
1349 offset <= (range->pin_base + range->npins - 1))
1355 static void nmk_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
1358 struct pinctrl_gpio_range *range;
1359 struct gpio_chip *chip;
1361 range = nmk_match_gpio_range(pctldev, offset);
1362 if (!range || !range->gc) {
1363 seq_printf(s, "invalid pin offset");
1367 nmk_gpio_dbg_show_one(s, chip, offset - chip->base, offset);
1370 static struct pinctrl_ops nmk_pinctrl_ops = {
1371 .get_groups_count = nmk_get_groups_cnt,
1372 .get_group_name = nmk_get_group_name,
1373 .get_group_pins = nmk_get_group_pins,
1374 .pin_dbg_show = nmk_pin_dbg_show,
1377 static int nmk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
1379 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1381 return npct->soc->nfunctions;
1384 static const char *nmk_pmx_get_func_name(struct pinctrl_dev *pctldev,
1387 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1389 return npct->soc->functions[function].name;
1392 static int nmk_pmx_get_func_groups(struct pinctrl_dev *pctldev,
1394 const char * const **groups,
1395 unsigned * const num_groups)
1397 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1399 *groups = npct->soc->functions[function].groups;
1400 *num_groups = npct->soc->functions[function].ngroups;
1405 static int nmk_pmx_enable(struct pinctrl_dev *pctldev, unsigned function,
1408 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1409 const struct nmk_pingroup *g;
1410 static unsigned int slpm[NUM_BANKS];
1411 unsigned long flags;
1416 g = &npct->soc->groups[group];
1418 if (g->altsetting < 0)
1421 dev_dbg(npct->dev, "enable group %s, %u pins\n", g->name, g->npins);
1424 * If we're setting altfunc C by setting both AFSLA and AFSLB to 1,
1425 * we may pass through an undesired state. In this case we take
1428 * Safe sequence used to switch IOs between GPIO and Alternate-C mode:
1429 * - Save SLPM registers (since we have a shadow register in the
1430 * nmk_chip we're using that as backup)
1431 * - Set SLPM=0 for the IOs you want to switch and others to 1
1432 * - Configure the GPIO registers for the IOs that are being switched
1434 * - Modify the AFLSA/B registers for the IOs that are being switched
1436 * - Restore SLPM registers
1437 * - Any spurious wake up event during switch sequence to be ignored
1440 * We REALLY need to save ALL slpm registers, because the external
1441 * IOFORCE will switch *all* ports to their sleepmode setting to as
1442 * to avoid glitches. (Not just one port!)
1444 glitch = (g->altsetting == NMK_GPIO_ALT_C);
1447 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
1449 /* Initially don't put any pins to sleep when switching */
1450 memset(slpm, 0xff, sizeof(slpm));
1453 * Then mask the pins that need to be sleeping now when we're
1454 * switching to the ALT C function.
1456 for (i = 0; i < g->npins; i++)
1457 slpm[g->pins[i] / NMK_GPIO_PER_CHIP] &= ~BIT(g->pins[i]);
1458 nmk_gpio_glitch_slpm_init(slpm);
1461 for (i = 0; i < g->npins; i++) {
1462 struct pinctrl_gpio_range *range;
1463 struct nmk_gpio_chip *nmk_chip;
1464 struct gpio_chip *chip;
1467 range = nmk_match_gpio_range(pctldev, g->pins[i]);
1470 "invalid pin offset %d in group %s at index %d\n",
1471 g->pins[i], g->name, i);
1475 dev_err(npct->dev, "GPIO chip missing in range for pin offset %d in group %s at index %d\n",
1476 g->pins[i], g->name, i);
1480 nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);
1481 dev_dbg(npct->dev, "setting pin %d to altsetting %d\n", g->pins[i], g->altsetting);
1483 clk_enable(nmk_chip->clk);
1484 bit = g->pins[i] % NMK_GPIO_PER_CHIP;
1486 * If the pin is switching to altfunc, and there was an
1487 * interrupt installed on it which has been lazy disabled,
1488 * actually mask the interrupt to prevent spurious interrupts
1489 * that would occur while the pin is under control of the
1490 * peripheral. Only SKE does this.
1492 nmk_gpio_disable_lazy_irq(nmk_chip, bit);
1494 __nmk_gpio_set_mode_safe(nmk_chip, bit, g->altsetting, glitch);
1495 clk_disable(nmk_chip->clk);
1498 /* When all pins are successfully reconfigured we get here */
1503 nmk_gpio_glitch_slpm_restore(slpm);
1504 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
1510 static void nmk_pmx_disable(struct pinctrl_dev *pctldev,
1511 unsigned function, unsigned group)
1513 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1514 const struct nmk_pingroup *g;
1516 g = &npct->soc->groups[group];
1518 if (g->altsetting < 0)
1521 /* Poke out the mux, set the pin to some default state? */
1522 dev_dbg(npct->dev, "disable group %s, %u pins\n", g->name, g->npins);
1525 int nmk_gpio_request_enable(struct pinctrl_dev *pctldev,
1526 struct pinctrl_gpio_range *range,
1529 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1530 struct nmk_gpio_chip *nmk_chip;
1531 struct gpio_chip *chip;
1535 dev_err(npct->dev, "invalid range\n");
1539 dev_err(npct->dev, "missing GPIO chip in range\n");
1543 nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);
1545 dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset);
1547 clk_enable(nmk_chip->clk);
1548 bit = offset % NMK_GPIO_PER_CHIP;
1549 /* There is no glitch when converting any pin to GPIO */
1550 __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);
1551 clk_disable(nmk_chip->clk);
1556 void nmk_gpio_disable_free(struct pinctrl_dev *pctldev,
1557 struct pinctrl_gpio_range *range,
1560 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1562 dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset);
1563 /* Set the pin to some default state, GPIO is usually default */
1566 static struct pinmux_ops nmk_pinmux_ops = {
1567 .get_functions_count = nmk_pmx_get_funcs_cnt,
1568 .get_function_name = nmk_pmx_get_func_name,
1569 .get_function_groups = nmk_pmx_get_func_groups,
1570 .enable = nmk_pmx_enable,
1571 .disable = nmk_pmx_disable,
1572 .gpio_request_enable = nmk_gpio_request_enable,
1573 .gpio_disable_free = nmk_gpio_disable_free,
1576 int nmk_pin_config_get(struct pinctrl_dev *pctldev,
1578 unsigned long *config)
1580 /* Not implemented */
1584 int nmk_pin_config_set(struct pinctrl_dev *pctldev,
1586 unsigned long config)
1588 static const char *pullnames[] = {
1589 [NMK_GPIO_PULL_NONE] = "none",
1590 [NMK_GPIO_PULL_UP] = "up",
1591 [NMK_GPIO_PULL_DOWN] = "down",
1592 [3] /* illegal */ = "??"
1594 static const char *slpmnames[] = {
1595 [NMK_GPIO_SLPM_INPUT] = "input/wakeup",
1596 [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup",
1598 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1599 struct nmk_gpio_chip *nmk_chip;
1600 struct pinctrl_gpio_range *range;
1601 struct gpio_chip *chip;
1605 * The pin config contains pin number and altfunction fields, here
1606 * we just ignore that part. It's being handled by the framework and
1607 * pinmux callback respectively.
1609 pin_cfg_t cfg = (pin_cfg_t) config;
1610 int pull = PIN_PULL(cfg);
1611 int slpm = PIN_SLPM(cfg);
1612 int output = PIN_DIR(cfg);
1613 int val = PIN_VAL(cfg);
1614 bool lowemi = PIN_LOWEMI(cfg);
1615 bool gpiomode = PIN_GPIOMODE(cfg);
1616 bool sleep = PIN_SLEEPMODE(cfg);
1618 range = nmk_match_gpio_range(pctldev, pin);
1620 dev_err(npct->dev, "invalid pin offset %d\n", pin);
1624 dev_err(npct->dev, "GPIO chip missing in range for pin %d\n",
1629 nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);
1632 int slpm_pull = PIN_SLPM_PULL(cfg);
1633 int slpm_output = PIN_SLPM_DIR(cfg);
1634 int slpm_val = PIN_SLPM_VAL(cfg);
1636 /* All pins go into GPIO mode at sleep */
1640 * The SLPM_* values are normal values + 1 to allow zero to
1641 * mean "same as normal".
1644 pull = slpm_pull - 1;
1646 output = slpm_output - 1;
1650 dev_dbg(nmk_chip->chip.dev, "pin %d: sleep pull %s, dir %s, val %s\n",
1652 slpm_pull ? pullnames[pull] : "same",
1653 slpm_output ? (output ? "output" : "input") : "same",
1654 slpm_val ? (val ? "high" : "low") : "same");
1657 dev_dbg(nmk_chip->chip.dev, "pin %d [%#lx]: pull %s, slpm %s (%s%s), lowemi %s\n",
1658 pin, cfg, pullnames[pull], slpmnames[slpm],
1659 output ? "output " : "input",
1660 output ? (val ? "high" : "low") : "",
1661 lowemi ? "on" : "off" );
1663 clk_enable(nmk_chip->clk);
1664 bit = pin % NMK_GPIO_PER_CHIP;
1666 /* No glitch when going to GPIO mode */
1667 __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);
1669 __nmk_gpio_make_output(nmk_chip, bit, val);
1671 __nmk_gpio_make_input(nmk_chip, bit);
1672 __nmk_gpio_set_pull(nmk_chip, bit, pull);
1674 /* TODO: isn't this only applicable on output pins? */
1675 __nmk_gpio_set_lowemi(nmk_chip, bit, lowemi);
1677 __nmk_gpio_set_slpm(nmk_chip, bit, slpm);
1678 clk_disable(nmk_chip->clk);
1682 static struct pinconf_ops nmk_pinconf_ops = {
1683 .pin_config_get = nmk_pin_config_get,
1684 .pin_config_set = nmk_pin_config_set,
1687 static struct pinctrl_desc nmk_pinctrl_desc = {
1688 .name = "pinctrl-nomadik",
1689 .pctlops = &nmk_pinctrl_ops,
1690 .pmxops = &nmk_pinmux_ops,
1691 .confops = &nmk_pinconf_ops,
1692 .owner = THIS_MODULE,
1695 static const struct of_device_id nmk_pinctrl_match[] = {
1697 .compatible = "stericsson,nmk_pinctrl",
1698 .data = (void *)PINCTRL_NMK_DB8500,
1703 static int __devinit nmk_pinctrl_probe(struct platform_device *pdev)
1705 const struct platform_device_id *platid = platform_get_device_id(pdev);
1706 struct device_node *np = pdev->dev.of_node;
1707 struct nmk_pinctrl *npct;
1708 unsigned int version = 0;
1711 npct = devm_kzalloc(&pdev->dev, sizeof(*npct), GFP_KERNEL);
1716 version = platid->driver_data;
1718 version = (unsigned int)
1719 of_match_device(nmk_pinctrl_match, &pdev->dev)->data;
1721 /* Poke in other ASIC variants here */
1722 if (version == PINCTRL_NMK_STN8815)
1723 nmk_pinctrl_stn8815_init(&npct->soc);
1724 if (version == PINCTRL_NMK_DB8500)
1725 nmk_pinctrl_db8500_init(&npct->soc);
1726 if (version == PINCTRL_NMK_DB8540)
1727 nmk_pinctrl_db8540_init(&npct->soc);
1730 * We need all the GPIO drivers to probe FIRST, or we will not be able
1731 * to obtain references to the struct gpio_chip * for them, and we
1732 * need this to proceed.
1734 for (i = 0; i < npct->soc->gpio_num_ranges; i++) {
1735 if (!nmk_gpio_chips[i]) {
1736 dev_warn(&pdev->dev, "GPIO chip %d not registered yet\n", i);
1737 return -EPROBE_DEFER;
1739 npct->soc->gpio_ranges[i].gc = &nmk_gpio_chips[i]->chip;
1742 nmk_pinctrl_desc.pins = npct->soc->pins;
1743 nmk_pinctrl_desc.npins = npct->soc->npins;
1744 npct->dev = &pdev->dev;
1745 npct->pctl = pinctrl_register(&nmk_pinctrl_desc, &pdev->dev, npct);
1747 dev_err(&pdev->dev, "could not register Nomadik pinctrl driver\n");
1751 /* We will handle a range of GPIO pins */
1752 for (i = 0; i < npct->soc->gpio_num_ranges; i++)
1753 pinctrl_add_gpio_range(npct->pctl, &npct->soc->gpio_ranges[i]);
1755 platform_set_drvdata(pdev, npct);
1756 dev_info(&pdev->dev, "initialized Nomadik pin control driver\n");
1761 static const struct of_device_id nmk_gpio_match[] = {
1762 { .compatible = "st,nomadik-gpio", },
1766 static struct platform_driver nmk_gpio_driver = {
1768 .owner = THIS_MODULE,
1770 .of_match_table = nmk_gpio_match,
1772 .probe = nmk_gpio_probe,
1775 static const struct platform_device_id nmk_pinctrl_id[] = {
1776 { "pinctrl-stn8815", PINCTRL_NMK_STN8815 },
1777 { "pinctrl-db8500", PINCTRL_NMK_DB8500 },
1778 { "pinctrl-db8540", PINCTRL_NMK_DB8540 },
1781 static struct platform_driver nmk_pinctrl_driver = {
1783 .owner = THIS_MODULE,
1784 .name = "pinctrl-nomadik",
1785 .of_match_table = nmk_pinctrl_match,
1787 .probe = nmk_pinctrl_probe,
1788 .id_table = nmk_pinctrl_id,
1791 static int __init nmk_gpio_init(void)
1795 ret = platform_driver_register(&nmk_gpio_driver);
1798 return platform_driver_register(&nmk_pinctrl_driver);
1801 core_initcall(nmk_gpio_init);
1803 MODULE_AUTHOR("Prafulla WADASKAR and Alessandro Rubini");
1804 MODULE_DESCRIPTION("Nomadik GPIO Driver");
1805 MODULE_LICENSE("GPL");