2 * Generic GPIO driver for logic cells found in the Nomadik SoC
4 * Copyright (C) 2008,2009 STMicroelectronics
5 * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it>
6 * Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com>
7 * Copyright (C) 2011 Linus Walleij <linus.walleij@linaro.org>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/init.h>
16 #include <linux/device.h>
17 #include <linux/platform_device.h>
19 #include <linux/clk.h>
20 #include <linux/err.h>
21 #include <linux/gpio.h>
22 #include <linux/spinlock.h>
23 #include <linux/interrupt.h>
24 #include <linux/irq.h>
25 #include <linux/irqdomain.h>
26 #include <linux/slab.h>
27 #include <linux/of_device.h>
28 #include <linux/pinctrl/pinctrl.h>
29 #include <linux/pinctrl/pinmux.h>
30 #include <linux/pinctrl/pinconf.h>
31 /* Since we request GPIOs from ourself */
32 #include <linux/pinctrl/consumer.h>
33 #include <linux/platform_data/pinctrl-nomadik.h>
34 #include <asm/mach/irq.h>
35 #include <mach/irqs.h>
36 #include "pinctrl-nomadik.h"
39 * The GPIO module in the Nomadik family of Systems-on-Chip is an
40 * AMBA device, managing 32 pins and alternate functions. The logic block
41 * is currently used in the Nomadik and ux500.
43 * Symbols in this file are called "nmk_gpio" for "nomadik gpio"
46 struct nmk_gpio_chip {
47 struct gpio_chip chip;
48 struct irq_domain *domain;
52 unsigned int parent_irq;
53 int secondary_parent_irq;
54 u32 (*get_secondary_status)(unsigned int bank);
55 void (*set_ioforce)(bool enable);
58 /* Keep track of configured edges */
71 * struct nmk_pinctrl - state container for the Nomadik pin controller
72 * @dev: containing device pointer
73 * @pctl: corresponding pin controller device
74 * @soc: SoC data for this specific chip
75 * @prcm_base: PRCM register range virtual base
79 struct pinctrl_dev *pctl;
80 const struct nmk_pinctrl_soc_data *soc;
81 void __iomem *prcm_base;
84 static struct nmk_gpio_chip *
85 nmk_gpio_chips[DIV_ROUND_UP(ARCH_NR_GPIOS, NMK_GPIO_PER_CHIP)];
87 static DEFINE_SPINLOCK(nmk_gpio_slpm_lock);
89 #define NUM_BANKS ARRAY_SIZE(nmk_gpio_chips)
91 static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip,
92 unsigned offset, int gpio_mode)
94 u32 bit = 1 << offset;
97 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~bit;
98 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~bit;
99 if (gpio_mode & NMK_GPIO_ALT_A)
101 if (gpio_mode & NMK_GPIO_ALT_B)
103 writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA);
104 writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB);
107 static void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip,
108 unsigned offset, enum nmk_gpio_slpm mode)
110 u32 bit = 1 << offset;
113 slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC);
114 if (mode == NMK_GPIO_SLPM_NOCHANGE)
118 writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC);
121 static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip,
122 unsigned offset, enum nmk_gpio_pull pull)
124 u32 bit = 1 << offset;
127 pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS);
128 if (pull == NMK_GPIO_PULL_NONE) {
130 nmk_chip->pull_up &= ~bit;
135 writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS);
137 if (pull == NMK_GPIO_PULL_UP) {
138 nmk_chip->pull_up |= bit;
139 writel(bit, nmk_chip->addr + NMK_GPIO_DATS);
140 } else if (pull == NMK_GPIO_PULL_DOWN) {
141 nmk_chip->pull_up &= ~bit;
142 writel(bit, nmk_chip->addr + NMK_GPIO_DATC);
146 static void __nmk_gpio_set_lowemi(struct nmk_gpio_chip *nmk_chip,
147 unsigned offset, bool lowemi)
149 u32 bit = BIT(offset);
150 bool enabled = nmk_chip->lowemi & bit;
152 if (lowemi == enabled)
156 nmk_chip->lowemi |= bit;
158 nmk_chip->lowemi &= ~bit;
160 writel_relaxed(nmk_chip->lowemi,
161 nmk_chip->addr + NMK_GPIO_LOWEMI);
164 static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip,
167 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC);
170 static void __nmk_gpio_set_output(struct nmk_gpio_chip *nmk_chip,
171 unsigned offset, int val)
174 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATS);
176 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATC);
179 static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip,
180 unsigned offset, int val)
182 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRS);
183 __nmk_gpio_set_output(nmk_chip, offset, val);
186 static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip,
187 unsigned offset, int gpio_mode,
190 u32 rwimsc = nmk_chip->rwimsc;
191 u32 fwimsc = nmk_chip->fwimsc;
193 if (glitch && nmk_chip->set_ioforce) {
194 u32 bit = BIT(offset);
196 /* Prevent spurious wakeups */
197 writel(rwimsc & ~bit, nmk_chip->addr + NMK_GPIO_RWIMSC);
198 writel(fwimsc & ~bit, nmk_chip->addr + NMK_GPIO_FWIMSC);
200 nmk_chip->set_ioforce(true);
203 __nmk_gpio_set_mode(nmk_chip, offset, gpio_mode);
205 if (glitch && nmk_chip->set_ioforce) {
206 nmk_chip->set_ioforce(false);
208 writel(rwimsc, nmk_chip->addr + NMK_GPIO_RWIMSC);
209 writel(fwimsc, nmk_chip->addr + NMK_GPIO_FWIMSC);
214 nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip *nmk_chip, unsigned offset)
216 u32 falling = nmk_chip->fimsc & BIT(offset);
217 u32 rising = nmk_chip->rimsc & BIT(offset);
218 int gpio = nmk_chip->chip.base + offset;
219 int irq = NOMADIK_GPIO_TO_IRQ(gpio);
220 struct irq_data *d = irq_get_irq_data(irq);
222 if (!rising && !falling)
225 if (!d || !irqd_irq_disabled(d))
229 nmk_chip->rimsc &= ~BIT(offset);
230 writel_relaxed(nmk_chip->rimsc,
231 nmk_chip->addr + NMK_GPIO_RIMSC);
235 nmk_chip->fimsc &= ~BIT(offset);
236 writel_relaxed(nmk_chip->fimsc,
237 nmk_chip->addr + NMK_GPIO_FIMSC);
240 dev_dbg(nmk_chip->chip.dev, "%d: clearing interrupt mask\n", gpio);
243 static void nmk_write_masked(void __iomem *reg, u32 mask, u32 value)
248 val = ((val & ~mask) | (value & mask));
252 static void nmk_prcm_altcx_set_mode(struct nmk_pinctrl *npct,
253 unsigned offset, unsigned alt_num)
259 const struct prcm_gpiocr_altcx_pin_desc *pin_desc;
260 const u16 *gpiocr_regs;
262 if (!npct->prcm_base)
265 if (alt_num > PRCM_IDX_GPIOCR_ALTC_MAX) {
266 dev_err(npct->dev, "PRCM GPIOCR: alternate-C%i is invalid\n",
271 for (i = 0 ; i < npct->soc->npins_altcx ; i++) {
272 if (npct->soc->altcx_pins[i].pin == offset)
275 if (i == npct->soc->npins_altcx) {
276 dev_dbg(npct->dev, "PRCM GPIOCR: pin %i is not found\n",
281 pin_desc = npct->soc->altcx_pins + i;
282 gpiocr_regs = npct->soc->prcm_gpiocr_registers;
285 * If alt_num is NULL, just clear current ALTCx selection
286 * to make sure we come back to a pure ALTC selection
289 for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) {
290 if (pin_desc->altcx[i].used == true) {
291 reg = gpiocr_regs[pin_desc->altcx[i].reg_index];
292 bit = pin_desc->altcx[i].control_bit;
293 if (readl(npct->prcm_base + reg) & BIT(bit)) {
294 nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0);
296 "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n",
304 alt_index = alt_num - 1;
305 if (pin_desc->altcx[alt_index].used == false) {
307 "PRCM GPIOCR: pin %i: alternate-C%i does not exist\n",
313 * Check if any other ALTCx functions are activated on this pin
314 * and disable it first.
316 for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) {
319 if (pin_desc->altcx[i].used == true) {
320 reg = gpiocr_regs[pin_desc->altcx[i].reg_index];
321 bit = pin_desc->altcx[i].control_bit;
322 if (readl(npct->prcm_base + reg) & BIT(bit)) {
323 nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0);
325 "PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n",
331 reg = gpiocr_regs[pin_desc->altcx[alt_index].reg_index];
332 bit = pin_desc->altcx[alt_index].control_bit;
333 dev_dbg(npct->dev, "PRCM GPIOCR: pin %i: alternate-C%i has been selected\n",
334 offset, alt_index+1);
335 nmk_write_masked(npct->prcm_base + reg, BIT(bit), BIT(bit));
338 static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset,
339 pin_cfg_t cfg, bool sleep, unsigned int *slpmregs)
341 static const char *afnames[] = {
342 [NMK_GPIO_ALT_GPIO] = "GPIO",
343 [NMK_GPIO_ALT_A] = "A",
344 [NMK_GPIO_ALT_B] = "B",
345 [NMK_GPIO_ALT_C] = "C"
347 static const char *pullnames[] = {
348 [NMK_GPIO_PULL_NONE] = "none",
349 [NMK_GPIO_PULL_UP] = "up",
350 [NMK_GPIO_PULL_DOWN] = "down",
351 [3] /* illegal */ = "??"
353 static const char *slpmnames[] = {
354 [NMK_GPIO_SLPM_INPUT] = "input/wakeup",
355 [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup",
358 int pin = PIN_NUM(cfg);
359 int pull = PIN_PULL(cfg);
360 int af = PIN_ALT(cfg);
361 int slpm = PIN_SLPM(cfg);
362 int output = PIN_DIR(cfg);
363 int val = PIN_VAL(cfg);
364 bool glitch = af == NMK_GPIO_ALT_C;
366 dev_dbg(nmk_chip->chip.dev, "pin %d [%#lx]: af %s, pull %s, slpm %s (%s%s)\n",
367 pin, cfg, afnames[af], pullnames[pull], slpmnames[slpm],
368 output ? "output " : "input",
369 output ? (val ? "high" : "low") : "");
372 int slpm_pull = PIN_SLPM_PULL(cfg);
373 int slpm_output = PIN_SLPM_DIR(cfg);
374 int slpm_val = PIN_SLPM_VAL(cfg);
376 af = NMK_GPIO_ALT_GPIO;
379 * The SLPM_* values are normal values + 1 to allow zero to
380 * mean "same as normal".
383 pull = slpm_pull - 1;
385 output = slpm_output - 1;
389 dev_dbg(nmk_chip->chip.dev, "pin %d: sleep pull %s, dir %s, val %s\n",
391 slpm_pull ? pullnames[pull] : "same",
392 slpm_output ? (output ? "output" : "input") : "same",
393 slpm_val ? (val ? "high" : "low") : "same");
397 __nmk_gpio_make_output(nmk_chip, offset, val);
399 __nmk_gpio_make_input(nmk_chip, offset);
400 __nmk_gpio_set_pull(nmk_chip, offset, pull);
403 __nmk_gpio_set_lowemi(nmk_chip, offset, PIN_LOWEMI(cfg));
406 * If the pin is switching to altfunc, and there was an interrupt
407 * installed on it which has been lazy disabled, actually mask the
408 * interrupt to prevent spurious interrupts that would occur while the
409 * pin is under control of the peripheral. Only SKE does this.
411 if (af != NMK_GPIO_ALT_GPIO)
412 nmk_gpio_disable_lazy_irq(nmk_chip, offset);
415 * If we've backed up the SLPM registers (glitch workaround), modify
416 * the backups since they will be restored.
419 if (slpm == NMK_GPIO_SLPM_NOCHANGE)
420 slpmregs[nmk_chip->bank] |= BIT(offset);
422 slpmregs[nmk_chip->bank] &= ~BIT(offset);
424 __nmk_gpio_set_slpm(nmk_chip, offset, slpm);
426 __nmk_gpio_set_mode_safe(nmk_chip, offset, af, glitch);
430 * Safe sequence used to switch IOs between GPIO and Alternate-C mode:
431 * - Save SLPM registers
432 * - Set SLPM=0 for the IOs you want to switch and others to 1
433 * - Configure the GPIO registers for the IOs that are being switched
435 * - Modify the AFLSA/B registers for the IOs that are being switched
437 * - Restore SLPM registers
438 * - Any spurious wake up event during switch sequence to be ignored and
441 static void nmk_gpio_glitch_slpm_init(unsigned int *slpm)
445 for (i = 0; i < NUM_BANKS; i++) {
446 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
447 unsigned int temp = slpm[i];
452 clk_enable(chip->clk);
454 slpm[i] = readl(chip->addr + NMK_GPIO_SLPC);
455 writel(temp, chip->addr + NMK_GPIO_SLPC);
459 static void nmk_gpio_glitch_slpm_restore(unsigned int *slpm)
463 for (i = 0; i < NUM_BANKS; i++) {
464 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
469 writel(slpm[i], chip->addr + NMK_GPIO_SLPC);
471 clk_disable(chip->clk);
475 static int __nmk_config_pins(pin_cfg_t *cfgs, int num, bool sleep)
477 static unsigned int slpm[NUM_BANKS];
483 for (i = 0; i < num; i++) {
484 if (PIN_ALT(cfgs[i]) == NMK_GPIO_ALT_C) {
490 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
493 memset(slpm, 0xff, sizeof(slpm));
495 for (i = 0; i < num; i++) {
496 int pin = PIN_NUM(cfgs[i]);
497 int offset = pin % NMK_GPIO_PER_CHIP;
499 if (PIN_ALT(cfgs[i]) == NMK_GPIO_ALT_C)
500 slpm[pin / NMK_GPIO_PER_CHIP] &= ~BIT(offset);
503 nmk_gpio_glitch_slpm_init(slpm);
506 for (i = 0; i < num; i++) {
507 struct nmk_gpio_chip *nmk_chip;
508 int pin = PIN_NUM(cfgs[i]);
510 nmk_chip = nmk_gpio_chips[pin / NMK_GPIO_PER_CHIP];
516 clk_enable(nmk_chip->clk);
517 spin_lock(&nmk_chip->lock);
518 __nmk_config_pin(nmk_chip, pin % NMK_GPIO_PER_CHIP,
519 cfgs[i], sleep, glitch ? slpm : NULL);
520 spin_unlock(&nmk_chip->lock);
521 clk_disable(nmk_chip->clk);
525 nmk_gpio_glitch_slpm_restore(slpm);
527 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
533 * nmk_config_pin - configure a pin's mux attributes
534 * @cfg: pin confguration
535 * @sleep: Non-zero to apply the sleep mode configuration
536 * Configures a pin's mode (alternate function or GPIO), its pull up status,
537 * and its sleep mode based on the specified configuration. The @cfg is
538 * usually one of the SoC specific macros defined in mach/<soc>-pins.h. These
539 * are constructed using, and can be further enhanced with, the macros in
540 * <linux/platform_data/pinctrl-nomadik.h>
542 * If a pin's mode is set to GPIO, it is configured as an input to avoid
543 * side-effects. The gpio can be manipulated later using standard GPIO API
546 int nmk_config_pin(pin_cfg_t cfg, bool sleep)
548 return __nmk_config_pins(&cfg, 1, sleep);
550 EXPORT_SYMBOL(nmk_config_pin);
553 * nmk_config_pins - configure several pins at once
554 * @cfgs: array of pin configurations
555 * @num: number of elments in the array
557 * Configures several pins using nmk_config_pin(). Refer to that function for
558 * further information.
560 int nmk_config_pins(pin_cfg_t *cfgs, int num)
562 return __nmk_config_pins(cfgs, num, false);
564 EXPORT_SYMBOL(nmk_config_pins);
566 int nmk_config_pins_sleep(pin_cfg_t *cfgs, int num)
568 return __nmk_config_pins(cfgs, num, true);
570 EXPORT_SYMBOL(nmk_config_pins_sleep);
573 * nmk_gpio_set_slpm() - configure the sleep mode of a pin
575 * @mode: NMK_GPIO_SLPM_INPUT or NMK_GPIO_SLPM_NOCHANGE,
577 * This register is actually in the pinmux layer, not the GPIO block itself.
578 * The GPIO1B_SLPM register defines the GPIO mode when SLEEP/DEEP-SLEEP
579 * mode is entered (i.e. when signal IOFORCE is HIGH by the platform code).
580 * Each GPIO can be configured to be forced into GPIO mode when IOFORCE is
581 * HIGH, overriding the normal setting defined by GPIO_AFSELx registers.
582 * When IOFORCE returns LOW (by software, after SLEEP/DEEP-SLEEP exit),
583 * the GPIOs return to the normal setting defined by GPIO_AFSELx registers.
585 * If @mode is NMK_GPIO_SLPM_INPUT, the corresponding GPIO is switched to GPIO
586 * mode when signal IOFORCE is HIGH (i.e. when SLEEP/DEEP-SLEEP mode is
587 * entered) regardless of the altfunction selected. Also wake-up detection is
590 * If @mode is NMK_GPIO_SLPM_NOCHANGE, the corresponding GPIO remains
591 * controlled by NMK_GPIO_DATC, NMK_GPIO_DATS, NMK_GPIO_DIR, NMK_GPIO_PDIS
592 * (for altfunction GPIO) or respective on-chip peripherals (for other
593 * altfuncs) when IOFORCE is HIGH. Also wake-up detection DISABLED.
595 * Note that enable_irq_wake() will automatically enable wakeup detection.
597 int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode)
599 struct nmk_gpio_chip *nmk_chip;
602 nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP];
606 clk_enable(nmk_chip->clk);
607 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
608 spin_lock(&nmk_chip->lock);
610 __nmk_gpio_set_slpm(nmk_chip, gpio % NMK_GPIO_PER_CHIP, mode);
612 spin_unlock(&nmk_chip->lock);
613 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
614 clk_disable(nmk_chip->clk);
620 * nmk_gpio_set_pull() - enable/disable pull up/down on a gpio
622 * @pull: one of NMK_GPIO_PULL_DOWN, NMK_GPIO_PULL_UP, and NMK_GPIO_PULL_NONE
624 * Enables/disables pull up/down on a specified pin. This only takes effect if
625 * the pin is configured as an input (either explicitly or by the alternate
628 * NOTE: If enabling the pull up/down, the caller must ensure that the GPIO is
629 * configured as an input. Otherwise, due to the way the controller registers
630 * work, this function will change the value output on the pin.
632 int nmk_gpio_set_pull(int gpio, enum nmk_gpio_pull pull)
634 struct nmk_gpio_chip *nmk_chip;
637 nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP];
641 clk_enable(nmk_chip->clk);
642 spin_lock_irqsave(&nmk_chip->lock, flags);
643 __nmk_gpio_set_pull(nmk_chip, gpio % NMK_GPIO_PER_CHIP, pull);
644 spin_unlock_irqrestore(&nmk_chip->lock, flags);
645 clk_disable(nmk_chip->clk);
652 * nmk_gpio_set_mode() - set the mux mode of a gpio pin
654 * @gpio_mode: one of NMK_GPIO_ALT_GPIO, NMK_GPIO_ALT_A,
655 * NMK_GPIO_ALT_B, and NMK_GPIO_ALT_C
657 * Sets the mode of the specified pin to one of the alternate functions or
660 int nmk_gpio_set_mode(int gpio, int gpio_mode)
662 struct nmk_gpio_chip *nmk_chip;
665 nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP];
669 clk_enable(nmk_chip->clk);
670 spin_lock_irqsave(&nmk_chip->lock, flags);
671 __nmk_gpio_set_mode(nmk_chip, gpio % NMK_GPIO_PER_CHIP, gpio_mode);
672 spin_unlock_irqrestore(&nmk_chip->lock, flags);
673 clk_disable(nmk_chip->clk);
677 EXPORT_SYMBOL(nmk_gpio_set_mode);
679 static int nmk_prcm_gpiocr_get_mode(struct pinctrl_dev *pctldev, int gpio)
684 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
685 const struct prcm_gpiocr_altcx_pin_desc *pin_desc;
686 const u16 *gpiocr_regs;
688 if (!npct->prcm_base)
689 return NMK_GPIO_ALT_C;
691 for (i = 0; i < npct->soc->npins_altcx; i++) {
692 if (npct->soc->altcx_pins[i].pin == gpio)
695 if (i == npct->soc->npins_altcx)
696 return NMK_GPIO_ALT_C;
698 pin_desc = npct->soc->altcx_pins + i;
699 gpiocr_regs = npct->soc->prcm_gpiocr_registers;
700 for (i = 0; i < PRCM_IDX_GPIOCR_ALTC_MAX; i++) {
701 if (pin_desc->altcx[i].used == true) {
702 reg = gpiocr_regs[pin_desc->altcx[i].reg_index];
703 bit = pin_desc->altcx[i].control_bit;
704 if (readl(npct->prcm_base + reg) & BIT(bit))
705 return NMK_GPIO_ALT_C+i+1;
708 return NMK_GPIO_ALT_C;
711 int nmk_gpio_get_mode(int gpio)
713 struct nmk_gpio_chip *nmk_chip;
714 u32 afunc, bfunc, bit;
716 nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP];
720 bit = 1 << (gpio % NMK_GPIO_PER_CHIP);
722 clk_enable(nmk_chip->clk);
724 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & bit;
725 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & bit;
727 clk_disable(nmk_chip->clk);
729 return (afunc ? NMK_GPIO_ALT_A : 0) | (bfunc ? NMK_GPIO_ALT_B : 0);
731 EXPORT_SYMBOL(nmk_gpio_get_mode);
735 static inline int nmk_gpio_get_bitmask(int gpio)
737 return 1 << (gpio % NMK_GPIO_PER_CHIP);
740 static void nmk_gpio_irq_ack(struct irq_data *d)
742 struct nmk_gpio_chip *nmk_chip;
744 nmk_chip = irq_data_get_irq_chip_data(d);
748 clk_enable(nmk_chip->clk);
749 writel(nmk_gpio_get_bitmask(d->hwirq), nmk_chip->addr + NMK_GPIO_IC);
750 clk_disable(nmk_chip->clk);
753 enum nmk_gpio_irq_type {
758 static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip,
759 int gpio, enum nmk_gpio_irq_type which,
762 u32 bitmask = nmk_gpio_get_bitmask(gpio);
768 if (which == NORMAL) {
769 rimscreg = NMK_GPIO_RIMSC;
770 fimscreg = NMK_GPIO_FIMSC;
771 rimscval = &nmk_chip->rimsc;
772 fimscval = &nmk_chip->fimsc;
774 rimscreg = NMK_GPIO_RWIMSC;
775 fimscreg = NMK_GPIO_FWIMSC;
776 rimscval = &nmk_chip->rwimsc;
777 fimscval = &nmk_chip->fwimsc;
780 /* we must individually set/clear the two edges */
781 if (nmk_chip->edge_rising & bitmask) {
783 *rimscval |= bitmask;
785 *rimscval &= ~bitmask;
786 writel(*rimscval, nmk_chip->addr + rimscreg);
788 if (nmk_chip->edge_falling & bitmask) {
790 *fimscval |= bitmask;
792 *fimscval &= ~bitmask;
793 writel(*fimscval, nmk_chip->addr + fimscreg);
797 static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip,
801 * Ensure WAKEUP_ENABLE is on. No need to disable it if wakeup is
802 * disabled, since setting SLPM to 1 increases power consumption, and
803 * wakeup is anyhow controlled by the RIMSC and FIMSC registers.
805 if (nmk_chip->sleepmode && on) {
806 __nmk_gpio_set_slpm(nmk_chip, gpio % NMK_GPIO_PER_CHIP,
807 NMK_GPIO_SLPM_WAKEUP_ENABLE);
810 __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, on);
813 static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable)
815 struct nmk_gpio_chip *nmk_chip;
819 nmk_chip = irq_data_get_irq_chip_data(d);
820 bitmask = nmk_gpio_get_bitmask(d->hwirq);
824 clk_enable(nmk_chip->clk);
825 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
826 spin_lock(&nmk_chip->lock);
828 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, enable);
830 if (!(nmk_chip->real_wake & bitmask))
831 __nmk_gpio_set_wake(nmk_chip, d->hwirq, enable);
833 spin_unlock(&nmk_chip->lock);
834 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
835 clk_disable(nmk_chip->clk);
840 static void nmk_gpio_irq_mask(struct irq_data *d)
842 nmk_gpio_irq_maskunmask(d, false);
845 static void nmk_gpio_irq_unmask(struct irq_data *d)
847 nmk_gpio_irq_maskunmask(d, true);
850 static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
852 struct nmk_gpio_chip *nmk_chip;
856 nmk_chip = irq_data_get_irq_chip_data(d);
859 bitmask = nmk_gpio_get_bitmask(d->hwirq);
861 clk_enable(nmk_chip->clk);
862 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
863 spin_lock(&nmk_chip->lock);
865 if (irqd_irq_disabled(d))
866 __nmk_gpio_set_wake(nmk_chip, d->hwirq, on);
869 nmk_chip->real_wake |= bitmask;
871 nmk_chip->real_wake &= ~bitmask;
873 spin_unlock(&nmk_chip->lock);
874 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
875 clk_disable(nmk_chip->clk);
880 static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type)
882 bool enabled = !irqd_irq_disabled(d);
883 bool wake = irqd_is_wakeup_set(d);
884 struct nmk_gpio_chip *nmk_chip;
888 nmk_chip = irq_data_get_irq_chip_data(d);
889 bitmask = nmk_gpio_get_bitmask(d->hwirq);
892 if (type & IRQ_TYPE_LEVEL_HIGH)
894 if (type & IRQ_TYPE_LEVEL_LOW)
897 clk_enable(nmk_chip->clk);
898 spin_lock_irqsave(&nmk_chip->lock, flags);
901 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, false);
904 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, false);
906 nmk_chip->edge_rising &= ~bitmask;
907 if (type & IRQ_TYPE_EDGE_RISING)
908 nmk_chip->edge_rising |= bitmask;
910 nmk_chip->edge_falling &= ~bitmask;
911 if (type & IRQ_TYPE_EDGE_FALLING)
912 nmk_chip->edge_falling |= bitmask;
915 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, true);
918 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, true);
920 spin_unlock_irqrestore(&nmk_chip->lock, flags);
921 clk_disable(nmk_chip->clk);
926 static unsigned int nmk_gpio_irq_startup(struct irq_data *d)
928 struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d);
930 clk_enable(nmk_chip->clk);
931 nmk_gpio_irq_unmask(d);
935 static void nmk_gpio_irq_shutdown(struct irq_data *d)
937 struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d);
939 nmk_gpio_irq_mask(d);
940 clk_disable(nmk_chip->clk);
943 static struct irq_chip nmk_gpio_irq_chip = {
944 .name = "Nomadik-GPIO",
945 .irq_ack = nmk_gpio_irq_ack,
946 .irq_mask = nmk_gpio_irq_mask,
947 .irq_unmask = nmk_gpio_irq_unmask,
948 .irq_set_type = nmk_gpio_irq_set_type,
949 .irq_set_wake = nmk_gpio_irq_set_wake,
950 .irq_startup = nmk_gpio_irq_startup,
951 .irq_shutdown = nmk_gpio_irq_shutdown,
952 .flags = IRQCHIP_MASK_ON_SUSPEND,
955 static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc,
958 struct nmk_gpio_chip *nmk_chip;
959 struct irq_chip *host_chip = irq_get_chip(irq);
961 chained_irq_enter(host_chip, desc);
963 nmk_chip = irq_get_handler_data(irq);
965 int bit = __ffs(status);
967 generic_handle_irq(irq_find_mapping(nmk_chip->domain, bit));
971 chained_irq_exit(host_chip, desc);
974 static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
976 struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq);
979 clk_enable(nmk_chip->clk);
980 status = readl(nmk_chip->addr + NMK_GPIO_IS);
981 clk_disable(nmk_chip->clk);
983 __nmk_gpio_irq_handler(irq, desc, status);
986 static void nmk_gpio_secondary_irq_handler(unsigned int irq,
987 struct irq_desc *desc)
989 struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq);
990 u32 status = nmk_chip->get_secondary_status(nmk_chip->bank);
992 __nmk_gpio_irq_handler(irq, desc, status);
995 static int nmk_gpio_init_irq(struct nmk_gpio_chip *nmk_chip)
997 irq_set_chained_handler(nmk_chip->parent_irq, nmk_gpio_irq_handler);
998 irq_set_handler_data(nmk_chip->parent_irq, nmk_chip);
1000 if (nmk_chip->secondary_parent_irq >= 0) {
1001 irq_set_chained_handler(nmk_chip->secondary_parent_irq,
1002 nmk_gpio_secondary_irq_handler);
1003 irq_set_handler_data(nmk_chip->secondary_parent_irq, nmk_chip);
1011 static int nmk_gpio_request(struct gpio_chip *chip, unsigned offset)
1014 * Map back to global GPIO space and request muxing, the direction
1015 * parameter does not matter for this controller.
1017 int gpio = chip->base + offset;
1019 return pinctrl_request_gpio(gpio);
1022 static void nmk_gpio_free(struct gpio_chip *chip, unsigned offset)
1024 int gpio = chip->base + offset;
1026 pinctrl_free_gpio(gpio);
1029 static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset)
1031 struct nmk_gpio_chip *nmk_chip =
1032 container_of(chip, struct nmk_gpio_chip, chip);
1034 clk_enable(nmk_chip->clk);
1036 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC);
1038 clk_disable(nmk_chip->clk);
1043 static int nmk_gpio_get_input(struct gpio_chip *chip, unsigned offset)
1045 struct nmk_gpio_chip *nmk_chip =
1046 container_of(chip, struct nmk_gpio_chip, chip);
1047 u32 bit = 1 << offset;
1050 clk_enable(nmk_chip->clk);
1052 value = (readl(nmk_chip->addr + NMK_GPIO_DAT) & bit) != 0;
1054 clk_disable(nmk_chip->clk);
1059 static void nmk_gpio_set_output(struct gpio_chip *chip, unsigned offset,
1062 struct nmk_gpio_chip *nmk_chip =
1063 container_of(chip, struct nmk_gpio_chip, chip);
1065 clk_enable(nmk_chip->clk);
1067 __nmk_gpio_set_output(nmk_chip, offset, val);
1069 clk_disable(nmk_chip->clk);
1072 static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset,
1075 struct nmk_gpio_chip *nmk_chip =
1076 container_of(chip, struct nmk_gpio_chip, chip);
1078 clk_enable(nmk_chip->clk);
1080 __nmk_gpio_make_output(nmk_chip, offset, val);
1082 clk_disable(nmk_chip->clk);
1087 static int nmk_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
1089 struct nmk_gpio_chip *nmk_chip =
1090 container_of(chip, struct nmk_gpio_chip, chip);
1092 return irq_create_mapping(nmk_chip->domain, offset);
1095 #ifdef CONFIG_DEBUG_FS
1097 #include <linux/seq_file.h>
1099 static void nmk_gpio_dbg_show_one(struct seq_file *s,
1100 struct pinctrl_dev *pctldev, struct gpio_chip *chip,
1101 unsigned offset, unsigned gpio)
1103 const char *label = gpiochip_is_requested(chip, offset);
1104 struct nmk_gpio_chip *nmk_chip =
1105 container_of(chip, struct nmk_gpio_chip, chip);
1109 u32 bit = 1 << offset;
1110 const char *modes[] = {
1111 [NMK_GPIO_ALT_GPIO] = "gpio",
1112 [NMK_GPIO_ALT_A] = "altA",
1113 [NMK_GPIO_ALT_B] = "altB",
1114 [NMK_GPIO_ALT_C] = "altC",
1115 [NMK_GPIO_ALT_C+1] = "altC1",
1116 [NMK_GPIO_ALT_C+2] = "altC2",
1117 [NMK_GPIO_ALT_C+3] = "altC3",
1118 [NMK_GPIO_ALT_C+4] = "altC4",
1121 clk_enable(nmk_chip->clk);
1122 is_out = !!(readl(nmk_chip->addr + NMK_GPIO_DIR) & bit);
1123 pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & bit);
1124 mode = nmk_gpio_get_mode(gpio);
1125 if ((mode == NMK_GPIO_ALT_C) && pctldev)
1126 mode = nmk_prcm_gpiocr_get_mode(pctldev, gpio);
1128 seq_printf(s, " gpio-%-3d (%-20.20s) %s %s %s %s",
1129 gpio, label ?: "(none)",
1130 is_out ? "out" : "in ",
1132 ? (chip->get(chip, offset) ? "hi" : "lo")
1134 (mode < 0) ? "unknown" : modes[mode],
1135 pull ? "pull" : "none");
1137 if (label && !is_out) {
1138 int irq = gpio_to_irq(gpio);
1139 struct irq_desc *desc = irq_to_desc(irq);
1141 /* This races with request_irq(), set_irq_type(),
1142 * and set_irq_wake() ... but those are "rare".
1144 if (irq >= 0 && desc->action) {
1146 u32 bitmask = nmk_gpio_get_bitmask(gpio);
1148 if (nmk_chip->edge_rising & bitmask)
1149 trigger = "edge-rising";
1150 else if (nmk_chip->edge_falling & bitmask)
1151 trigger = "edge-falling";
1153 trigger = "edge-undefined";
1155 seq_printf(s, " irq-%d %s%s",
1157 irqd_is_wakeup_set(&desc->irq_data)
1161 clk_disable(nmk_chip->clk);
1164 static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
1167 unsigned gpio = chip->base;
1169 for (i = 0; i < chip->ngpio; i++, gpio++) {
1170 nmk_gpio_dbg_show_one(s, NULL, chip, i, gpio);
1171 seq_printf(s, "\n");
1176 static inline void nmk_gpio_dbg_show_one(struct seq_file *s,
1177 struct pinctrl_dev *pctldev,
1178 struct gpio_chip *chip,
1179 unsigned offset, unsigned gpio)
1182 #define nmk_gpio_dbg_show NULL
1185 /* This structure is replicated for each GPIO block allocated at probe time */
1186 static struct gpio_chip nmk_gpio_template = {
1187 .request = nmk_gpio_request,
1188 .free = nmk_gpio_free,
1189 .direction_input = nmk_gpio_make_input,
1190 .get = nmk_gpio_get_input,
1191 .direction_output = nmk_gpio_make_output,
1192 .set = nmk_gpio_set_output,
1193 .to_irq = nmk_gpio_to_irq,
1194 .dbg_show = nmk_gpio_dbg_show,
1198 void nmk_gpio_clocks_enable(void)
1202 for (i = 0; i < NUM_BANKS; i++) {
1203 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
1208 clk_enable(chip->clk);
1212 void nmk_gpio_clocks_disable(void)
1216 for (i = 0; i < NUM_BANKS; i++) {
1217 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
1222 clk_disable(chip->clk);
1227 * Called from the suspend/resume path to only keep the real wakeup interrupts
1228 * (those that have had set_irq_wake() called on them) as wakeup interrupts,
1229 * and not the rest of the interrupts which we needed to have as wakeups for
1232 * PM ops are not used since this needs to be done at the end, after all the
1233 * other drivers are done with their suspend callbacks.
1235 void nmk_gpio_wakeups_suspend(void)
1239 for (i = 0; i < NUM_BANKS; i++) {
1240 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
1245 clk_enable(chip->clk);
1247 writel(chip->rwimsc & chip->real_wake,
1248 chip->addr + NMK_GPIO_RWIMSC);
1249 writel(chip->fwimsc & chip->real_wake,
1250 chip->addr + NMK_GPIO_FWIMSC);
1252 clk_disable(chip->clk);
1256 void nmk_gpio_wakeups_resume(void)
1260 for (i = 0; i < NUM_BANKS; i++) {
1261 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
1266 clk_enable(chip->clk);
1268 writel(chip->rwimsc, chip->addr + NMK_GPIO_RWIMSC);
1269 writel(chip->fwimsc, chip->addr + NMK_GPIO_FWIMSC);
1271 clk_disable(chip->clk);
1276 * Read the pull up/pull down status.
1277 * A bit set in 'pull_up' means that pull up
1278 * is selected if pull is enabled in PDIS register.
1279 * Note: only pull up/down set via this driver can
1280 * be detected due to HW limitations.
1282 void nmk_gpio_read_pull(int gpio_bank, u32 *pull_up)
1284 if (gpio_bank < NUM_BANKS) {
1285 struct nmk_gpio_chip *chip = nmk_gpio_chips[gpio_bank];
1290 *pull_up = chip->pull_up;
1294 static int nmk_gpio_irq_map(struct irq_domain *d, unsigned int irq,
1295 irq_hw_number_t hwirq)
1297 struct nmk_gpio_chip *nmk_chip = d->host_data;
1302 irq_set_chip_and_handler(irq, &nmk_gpio_irq_chip, handle_edge_irq);
1303 set_irq_flags(irq, IRQF_VALID);
1304 irq_set_chip_data(irq, nmk_chip);
1305 irq_set_irq_type(irq, IRQ_TYPE_EDGE_FALLING);
1310 const struct irq_domain_ops nmk_gpio_irq_simple_ops = {
1311 .map = nmk_gpio_irq_map,
1312 .xlate = irq_domain_xlate_twocell,
1315 static int nmk_gpio_probe(struct platform_device *dev)
1317 struct nmk_gpio_platform_data *pdata = dev->dev.platform_data;
1318 struct device_node *np = dev->dev.of_node;
1319 struct nmk_gpio_chip *nmk_chip;
1320 struct gpio_chip *chip;
1321 struct resource *res;
1329 if (!pdata && !np) {
1330 dev_err(&dev->dev, "No platform data or device tree found\n");
1335 pdata = devm_kzalloc(&dev->dev, sizeof(*pdata), GFP_KERNEL);
1339 if (of_get_property(np, "st,supports-sleepmode", NULL))
1340 pdata->supports_sleepmode = true;
1342 if (of_property_read_u32(np, "gpio-bank", &dev->id)) {
1343 dev_err(&dev->dev, "gpio-bank property not found\n");
1348 pdata->first_gpio = dev->id * NMK_GPIO_PER_CHIP;
1349 pdata->num_gpio = NMK_GPIO_PER_CHIP;
1352 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
1358 irq = platform_get_irq(dev, 0);
1364 secondary_irq = platform_get_irq(dev, 1);
1365 if (secondary_irq >= 0 && !pdata->get_secondary_status) {
1370 base = devm_request_and_ioremap(&dev->dev, res);
1376 clk = devm_clk_get(&dev->dev, NULL);
1383 nmk_chip = devm_kzalloc(&dev->dev, sizeof(*nmk_chip), GFP_KERNEL);
1390 * The virt address in nmk_chip->addr is in the nomadik register space,
1391 * so we can simply convert the resource address, without remapping
1393 nmk_chip->bank = dev->id;
1394 nmk_chip->clk = clk;
1395 nmk_chip->addr = base;
1396 nmk_chip->chip = nmk_gpio_template;
1397 nmk_chip->parent_irq = irq;
1398 nmk_chip->secondary_parent_irq = secondary_irq;
1399 nmk_chip->get_secondary_status = pdata->get_secondary_status;
1400 nmk_chip->set_ioforce = pdata->set_ioforce;
1401 nmk_chip->sleepmode = pdata->supports_sleepmode;
1402 spin_lock_init(&nmk_chip->lock);
1404 chip = &nmk_chip->chip;
1405 chip->base = pdata->first_gpio;
1406 chip->ngpio = pdata->num_gpio;
1407 chip->label = pdata->name ?: dev_name(&dev->dev);
1408 chip->dev = &dev->dev;
1409 chip->owner = THIS_MODULE;
1411 clk_enable(nmk_chip->clk);
1412 nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI);
1413 clk_disable(nmk_chip->clk);
1415 #ifdef CONFIG_OF_GPIO
1419 ret = gpiochip_add(&nmk_chip->chip);
1423 BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips));
1425 nmk_gpio_chips[nmk_chip->bank] = nmk_chip;
1427 platform_set_drvdata(dev, nmk_chip);
1430 irq_start = NOMADIK_GPIO_TO_IRQ(pdata->first_gpio);
1431 nmk_chip->domain = irq_domain_add_simple(np,
1432 NMK_GPIO_PER_CHIP, irq_start,
1433 &nmk_gpio_irq_simple_ops, nmk_chip);
1434 if (!nmk_chip->domain) {
1435 dev_err(&dev->dev, "failed to create irqdomain\n");
1440 nmk_gpio_init_irq(nmk_chip);
1442 dev_info(&dev->dev, "at address %p\n", nmk_chip->addr);
1447 dev_err(&dev->dev, "Failure %i for GPIO %i-%i\n", ret,
1448 pdata->first_gpio, pdata->first_gpio+31);
1453 static int nmk_get_groups_cnt(struct pinctrl_dev *pctldev)
1455 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1457 return npct->soc->ngroups;
1460 static const char *nmk_get_group_name(struct pinctrl_dev *pctldev,
1463 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1465 return npct->soc->groups[selector].name;
1468 static int nmk_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
1469 const unsigned **pins,
1472 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1474 *pins = npct->soc->groups[selector].pins;
1475 *num_pins = npct->soc->groups[selector].npins;
1479 static struct pinctrl_gpio_range *
1480 nmk_match_gpio_range(struct pinctrl_dev *pctldev, unsigned offset)
1482 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1485 for (i = 0; i < npct->soc->gpio_num_ranges; i++) {
1486 struct pinctrl_gpio_range *range;
1488 range = &npct->soc->gpio_ranges[i];
1489 if (offset >= range->pin_base &&
1490 offset <= (range->pin_base + range->npins - 1))
1496 static void nmk_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
1499 struct pinctrl_gpio_range *range;
1500 struct gpio_chip *chip;
1502 range = nmk_match_gpio_range(pctldev, offset);
1503 if (!range || !range->gc) {
1504 seq_printf(s, "invalid pin offset");
1508 nmk_gpio_dbg_show_one(s, pctldev, chip, offset - chip->base, offset);
1511 static struct pinctrl_ops nmk_pinctrl_ops = {
1512 .get_groups_count = nmk_get_groups_cnt,
1513 .get_group_name = nmk_get_group_name,
1514 .get_group_pins = nmk_get_group_pins,
1515 .pin_dbg_show = nmk_pin_dbg_show,
1518 static int nmk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
1520 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1522 return npct->soc->nfunctions;
1525 static const char *nmk_pmx_get_func_name(struct pinctrl_dev *pctldev,
1528 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1530 return npct->soc->functions[function].name;
1533 static int nmk_pmx_get_func_groups(struct pinctrl_dev *pctldev,
1535 const char * const **groups,
1536 unsigned * const num_groups)
1538 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1540 *groups = npct->soc->functions[function].groups;
1541 *num_groups = npct->soc->functions[function].ngroups;
1546 static int nmk_pmx_enable(struct pinctrl_dev *pctldev, unsigned function,
1549 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1550 const struct nmk_pingroup *g;
1551 static unsigned int slpm[NUM_BANKS];
1552 unsigned long flags;
1557 g = &npct->soc->groups[group];
1559 if (g->altsetting < 0)
1562 dev_dbg(npct->dev, "enable group %s, %u pins\n", g->name, g->npins);
1565 * If we're setting altfunc C by setting both AFSLA and AFSLB to 1,
1566 * we may pass through an undesired state. In this case we take
1569 * Safe sequence used to switch IOs between GPIO and Alternate-C mode:
1570 * - Save SLPM registers (since we have a shadow register in the
1571 * nmk_chip we're using that as backup)
1572 * - Set SLPM=0 for the IOs you want to switch and others to 1
1573 * - Configure the GPIO registers for the IOs that are being switched
1575 * - Modify the AFLSA/B registers for the IOs that are being switched
1577 * - Restore SLPM registers
1578 * - Any spurious wake up event during switch sequence to be ignored
1581 * We REALLY need to save ALL slpm registers, because the external
1582 * IOFORCE will switch *all* ports to their sleepmode setting to as
1583 * to avoid glitches. (Not just one port!)
1585 glitch = ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C);
1588 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
1590 /* Initially don't put any pins to sleep when switching */
1591 memset(slpm, 0xff, sizeof(slpm));
1594 * Then mask the pins that need to be sleeping now when we're
1595 * switching to the ALT C function.
1597 for (i = 0; i < g->npins; i++)
1598 slpm[g->pins[i] / NMK_GPIO_PER_CHIP] &= ~BIT(g->pins[i]);
1599 nmk_gpio_glitch_slpm_init(slpm);
1602 for (i = 0; i < g->npins; i++) {
1603 struct pinctrl_gpio_range *range;
1604 struct nmk_gpio_chip *nmk_chip;
1605 struct gpio_chip *chip;
1608 range = nmk_match_gpio_range(pctldev, g->pins[i]);
1611 "invalid pin offset %d in group %s at index %d\n",
1612 g->pins[i], g->name, i);
1616 dev_err(npct->dev, "GPIO chip missing in range for pin offset %d in group %s at index %d\n",
1617 g->pins[i], g->name, i);
1621 nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);
1622 dev_dbg(npct->dev, "setting pin %d to altsetting %d\n", g->pins[i], g->altsetting);
1624 clk_enable(nmk_chip->clk);
1625 bit = g->pins[i] % NMK_GPIO_PER_CHIP;
1627 * If the pin is switching to altfunc, and there was an
1628 * interrupt installed on it which has been lazy disabled,
1629 * actually mask the interrupt to prevent spurious interrupts
1630 * that would occur while the pin is under control of the
1631 * peripheral. Only SKE does this.
1633 nmk_gpio_disable_lazy_irq(nmk_chip, bit);
1635 __nmk_gpio_set_mode_safe(nmk_chip, bit,
1636 (g->altsetting & NMK_GPIO_ALT_C), glitch);
1637 clk_disable(nmk_chip->clk);
1640 * Call PRCM GPIOCR config function in case ALTC
1641 * has been selected:
1642 * - If selection is a ALTCx, some bits in PRCM GPIOCR registers
1644 * - If selection is pure ALTC and previous selection was ALTCx,
1645 * then some bits in PRCM GPIOCR registers must be cleared.
1647 if ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C)
1648 nmk_prcm_altcx_set_mode(npct, g->pins[i],
1649 g->altsetting >> NMK_GPIO_ALT_CX_SHIFT);
1652 /* When all pins are successfully reconfigured we get here */
1657 nmk_gpio_glitch_slpm_restore(slpm);
1658 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
1664 static void nmk_pmx_disable(struct pinctrl_dev *pctldev,
1665 unsigned function, unsigned group)
1667 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1668 const struct nmk_pingroup *g;
1670 g = &npct->soc->groups[group];
1672 if (g->altsetting < 0)
1675 /* Poke out the mux, set the pin to some default state? */
1676 dev_dbg(npct->dev, "disable group %s, %u pins\n", g->name, g->npins);
1679 static int nmk_gpio_request_enable(struct pinctrl_dev *pctldev,
1680 struct pinctrl_gpio_range *range,
1683 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1684 struct nmk_gpio_chip *nmk_chip;
1685 struct gpio_chip *chip;
1689 dev_err(npct->dev, "invalid range\n");
1693 dev_err(npct->dev, "missing GPIO chip in range\n");
1697 nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);
1699 dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset);
1701 clk_enable(nmk_chip->clk);
1702 bit = offset % NMK_GPIO_PER_CHIP;
1703 /* There is no glitch when converting any pin to GPIO */
1704 __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);
1705 clk_disable(nmk_chip->clk);
1710 static void nmk_gpio_disable_free(struct pinctrl_dev *pctldev,
1711 struct pinctrl_gpio_range *range,
1714 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1716 dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset);
1717 /* Set the pin to some default state, GPIO is usually default */
1720 static struct pinmux_ops nmk_pinmux_ops = {
1721 .get_functions_count = nmk_pmx_get_funcs_cnt,
1722 .get_function_name = nmk_pmx_get_func_name,
1723 .get_function_groups = nmk_pmx_get_func_groups,
1724 .enable = nmk_pmx_enable,
1725 .disable = nmk_pmx_disable,
1726 .gpio_request_enable = nmk_gpio_request_enable,
1727 .gpio_disable_free = nmk_gpio_disable_free,
1730 static int nmk_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin,
1731 unsigned long *config)
1733 /* Not implemented */
1737 static int nmk_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin,
1738 unsigned long config)
1740 static const char *pullnames[] = {
1741 [NMK_GPIO_PULL_NONE] = "none",
1742 [NMK_GPIO_PULL_UP] = "up",
1743 [NMK_GPIO_PULL_DOWN] = "down",
1744 [3] /* illegal */ = "??"
1746 static const char *slpmnames[] = {
1747 [NMK_GPIO_SLPM_INPUT] = "input/wakeup",
1748 [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup",
1750 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1751 struct nmk_gpio_chip *nmk_chip;
1752 struct pinctrl_gpio_range *range;
1753 struct gpio_chip *chip;
1757 * The pin config contains pin number and altfunction fields, here
1758 * we just ignore that part. It's being handled by the framework and
1759 * pinmux callback respectively.
1761 pin_cfg_t cfg = (pin_cfg_t) config;
1762 int pull = PIN_PULL(cfg);
1763 int slpm = PIN_SLPM(cfg);
1764 int output = PIN_DIR(cfg);
1765 int val = PIN_VAL(cfg);
1766 bool lowemi = PIN_LOWEMI(cfg);
1767 bool gpiomode = PIN_GPIOMODE(cfg);
1768 bool sleep = PIN_SLEEPMODE(cfg);
1770 range = nmk_match_gpio_range(pctldev, pin);
1772 dev_err(npct->dev, "invalid pin offset %d\n", pin);
1776 dev_err(npct->dev, "GPIO chip missing in range for pin %d\n",
1781 nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);
1784 int slpm_pull = PIN_SLPM_PULL(cfg);
1785 int slpm_output = PIN_SLPM_DIR(cfg);
1786 int slpm_val = PIN_SLPM_VAL(cfg);
1788 /* All pins go into GPIO mode at sleep */
1792 * The SLPM_* values are normal values + 1 to allow zero to
1793 * mean "same as normal".
1796 pull = slpm_pull - 1;
1798 output = slpm_output - 1;
1802 dev_dbg(nmk_chip->chip.dev, "pin %d: sleep pull %s, dir %s, val %s\n",
1804 slpm_pull ? pullnames[pull] : "same",
1805 slpm_output ? (output ? "output" : "input") : "same",
1806 slpm_val ? (val ? "high" : "low") : "same");
1809 dev_dbg(nmk_chip->chip.dev, "pin %d [%#lx]: pull %s, slpm %s (%s%s), lowemi %s\n",
1810 pin, cfg, pullnames[pull], slpmnames[slpm],
1811 output ? "output " : "input",
1812 output ? (val ? "high" : "low") : "",
1813 lowemi ? "on" : "off" );
1815 clk_enable(nmk_chip->clk);
1816 bit = pin % NMK_GPIO_PER_CHIP;
1818 /* No glitch when going to GPIO mode */
1819 __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);
1821 __nmk_gpio_make_output(nmk_chip, bit, val);
1823 __nmk_gpio_make_input(nmk_chip, bit);
1824 __nmk_gpio_set_pull(nmk_chip, bit, pull);
1826 /* TODO: isn't this only applicable on output pins? */
1827 __nmk_gpio_set_lowemi(nmk_chip, bit, lowemi);
1829 __nmk_gpio_set_slpm(nmk_chip, bit, slpm);
1830 clk_disable(nmk_chip->clk);
1834 static struct pinconf_ops nmk_pinconf_ops = {
1835 .pin_config_get = nmk_pin_config_get,
1836 .pin_config_set = nmk_pin_config_set,
1839 static struct pinctrl_desc nmk_pinctrl_desc = {
1840 .name = "pinctrl-nomadik",
1841 .pctlops = &nmk_pinctrl_ops,
1842 .pmxops = &nmk_pinmux_ops,
1843 .confops = &nmk_pinconf_ops,
1844 .owner = THIS_MODULE,
1847 static const struct of_device_id nmk_pinctrl_match[] = {
1849 .compatible = "stericsson,nmk_pinctrl",
1850 .data = (void *)PINCTRL_NMK_DB8500,
1855 static int nmk_pinctrl_probe(struct platform_device *pdev)
1857 const struct platform_device_id *platid = platform_get_device_id(pdev);
1858 struct device_node *np = pdev->dev.of_node;
1859 struct nmk_pinctrl *npct;
1860 struct resource *res;
1861 unsigned int version = 0;
1864 npct = devm_kzalloc(&pdev->dev, sizeof(*npct), GFP_KERNEL);
1869 version = platid->driver_data;
1871 const struct of_device_id *match;
1873 match = of_match_device(nmk_pinctrl_match, &pdev->dev);
1876 version = (unsigned int) match->data;
1879 /* Poke in other ASIC variants here */
1880 if (version == PINCTRL_NMK_STN8815)
1881 nmk_pinctrl_stn8815_init(&npct->soc);
1882 if (version == PINCTRL_NMK_DB8500)
1883 nmk_pinctrl_db8500_init(&npct->soc);
1884 if (version == PINCTRL_NMK_DB8540)
1885 nmk_pinctrl_db8540_init(&npct->soc);
1887 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1889 npct->prcm_base = devm_ioremap(&pdev->dev, res->start,
1890 resource_size(res));
1891 if (!npct->prcm_base) {
1893 "failed to ioremap PRCM registers\n");
1896 } else if (version == PINCTRL_NMK_STN8815) {
1897 dev_info(&pdev->dev,
1898 "No PRCM base, assume no ALT-Cx control is available\n");
1900 dev_err(&pdev->dev, "missing PRCM base address\n");
1905 * We need all the GPIO drivers to probe FIRST, or we will not be able
1906 * to obtain references to the struct gpio_chip * for them, and we
1907 * need this to proceed.
1909 for (i = 0; i < npct->soc->gpio_num_ranges; i++) {
1910 if (!nmk_gpio_chips[npct->soc->gpio_ranges[i].id]) {
1911 dev_warn(&pdev->dev, "GPIO chip %d not registered yet\n", i);
1912 return -EPROBE_DEFER;
1914 npct->soc->gpio_ranges[i].gc = &nmk_gpio_chips[npct->soc->gpio_ranges[i].id]->chip;
1917 nmk_pinctrl_desc.pins = npct->soc->pins;
1918 nmk_pinctrl_desc.npins = npct->soc->npins;
1919 npct->dev = &pdev->dev;
1921 npct->pctl = pinctrl_register(&nmk_pinctrl_desc, &pdev->dev, npct);
1923 dev_err(&pdev->dev, "could not register Nomadik pinctrl driver\n");
1927 /* We will handle a range of GPIO pins */
1928 for (i = 0; i < npct->soc->gpio_num_ranges; i++)
1929 pinctrl_add_gpio_range(npct->pctl, &npct->soc->gpio_ranges[i]);
1931 platform_set_drvdata(pdev, npct);
1932 dev_info(&pdev->dev, "initialized Nomadik pin control driver\n");
1937 static const struct of_device_id nmk_gpio_match[] = {
1938 { .compatible = "st,nomadik-gpio", },
1942 static struct platform_driver nmk_gpio_driver = {
1944 .owner = THIS_MODULE,
1946 .of_match_table = nmk_gpio_match,
1948 .probe = nmk_gpio_probe,
1951 static const struct platform_device_id nmk_pinctrl_id[] = {
1952 { "pinctrl-stn8815", PINCTRL_NMK_STN8815 },
1953 { "pinctrl-db8500", PINCTRL_NMK_DB8500 },
1954 { "pinctrl-db8540", PINCTRL_NMK_DB8540 },
1958 static struct platform_driver nmk_pinctrl_driver = {
1960 .owner = THIS_MODULE,
1961 .name = "pinctrl-nomadik",
1962 .of_match_table = nmk_pinctrl_match,
1964 .probe = nmk_pinctrl_probe,
1965 .id_table = nmk_pinctrl_id,
1968 static int __init nmk_gpio_init(void)
1972 ret = platform_driver_register(&nmk_gpio_driver);
1975 return platform_driver_register(&nmk_pinctrl_driver);
1978 core_initcall(nmk_gpio_init);
1980 MODULE_AUTHOR("Prafulla WADASKAR and Alessandro Rubini");
1981 MODULE_DESCRIPTION("Nomadik GPIO Driver");
1982 MODULE_LICENSE("GPL");