drivers/pinctrl/pinctrl-palmas.c

   1 /*
   2  * pinctrl-palmas.c -- TI PALMAS series pin control driver.
   3  *
   4  * Copyright (c) 2013, NVIDIA Corporation.
   5  *
   6  * Author: Laxman Dewangan <ldewangan@nvidia.com>
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation version 2.
  11  *
  12  * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind,
  13  * whether express or implied; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
  20  * 02111-1307, USA
  21  */
  22
  23 #include <linux/delay.h>
  24 #include <linux/module.h>
  25 #include <linux/mfd/palmas.h>
  26 #include <linux/of.h>
  27 #include <linux/of_device.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/pinctrl/machine.h>
  30 #include <linux/pinctrl/pinctrl.h>
  31 #include <linux/pinctrl/pinconf-generic.h>
  32 #include <linux/pinctrl/pinconf.h>
  33 #include <linux/pinctrl/pinmux.h>
  34 #include <linux/pm.h>
  35 #include <linux/slab.h>
  36
  37 #include "core.h"
  38 #include "pinconf.h"
  39 #include "pinctrl-utils.h"
  40
  41 #define PALMAS_PIN_GPIO0_ID                             0
  42 #define PALMAS_PIN_GPIO1_VBUS_LED1_PWM1                 1
  43 #define PALMAS_PIN_GPIO2_REGEN_LED2_PWM2                2
  44 #define PALMAS_PIN_GPIO3_CHRG_DET                       3
  45 #define PALMAS_PIN_GPIO4_SYSEN1                         4
  46 #define PALMAS_PIN_GPIO5_CLK32KGAUDIO_USB_PSEL          5
  47 #define PALMAS_PIN_GPIO6_SYSEN2                         6
  48 #define PALMAS_PIN_GPIO7_MSECURE_PWRHOLD                7
  49 #define PALMAS_PIN_GPIO8_SIM1RSTI                       8
  50 #define PALMAS_PIN_GPIO9_LOW_VBAT                       9
  51 #define PALMAS_PIN_GPIO10_WIRELESS_CHRG1                10
  52 #define PALMAS_PIN_GPIO11_RCM                           11
  53 #define PALMAS_PIN_GPIO12_SIM2RSTO                      12
  54 #define PALMAS_PIN_GPIO13                               13
  55 #define PALMAS_PIN_GPIO14                               14
  56 #define PALMAS_PIN_GPIO15_SIM2RSTI                      15
  57 #define PALMAS_PIN_VAC                                  16
  58 #define PALMAS_PIN_POWERGOOD_USB_PSEL                   17
  59 #define PALMAS_PIN_NRESWARM                             18
  60 #define PALMAS_PIN_PWRDOWN                              19
  61 #define PALMAS_PIN_GPADC_START                          20
  62 #define PALMAS_PIN_RESET_IN                             21
  63 #define PALMAS_PIN_NSLEEP                               22
  64 #define PALMAS_PIN_ENABLE1                              23
  65 #define PALMAS_PIN_ENABLE2                              24
  66 #define PALMAS_PIN_INT                                  25
  67 #define PALMAS_PIN_NUM                                  (PALMAS_PIN_INT + 1)
  68
  69 struct palmas_pin_function {
  70         const char *name;
  71         const char * const *groups;
  72         unsigned ngroups;
  73 };
  74
  75 struct palmas_pctrl_chip_info {
  76         struct device *dev;
  77         struct pinctrl_dev *pctl;
  78         struct palmas *palmas;
  79         int pins_current_opt[PALMAS_PIN_NUM];
  80         const struct palmas_pin_function *functions;
  81         unsigned num_functions;
  82         const struct palmas_pingroup *pin_groups;
  83         int num_pin_groups;
  84         const struct pinctrl_pin_desc *pins;
  85         unsigned num_pins;
  86 };
  87
  88 static const struct pinctrl_pin_desc palmas_pins_desc[] = {
  89         PINCTRL_PIN(PALMAS_PIN_GPIO0_ID, "gpio0"),
  90         PINCTRL_PIN(PALMAS_PIN_GPIO1_VBUS_LED1_PWM1, "gpio1"),
  91         PINCTRL_PIN(PALMAS_PIN_GPIO2_REGEN_LED2_PWM2, "gpio2"),
  92         PINCTRL_PIN(PALMAS_PIN_GPIO3_CHRG_DET, "gpio3"),
  93         PINCTRL_PIN(PALMAS_PIN_GPIO4_SYSEN1, "gpio4"),
  94         PINCTRL_PIN(PALMAS_PIN_GPIO5_CLK32KGAUDIO_USB_PSEL, "gpio5"),
  95         PINCTRL_PIN(PALMAS_PIN_GPIO6_SYSEN2, "gpio6"),
  96         PINCTRL_PIN(PALMAS_PIN_GPIO7_MSECURE_PWRHOLD, "gpio7"),
  97         PINCTRL_PIN(PALMAS_PIN_GPIO8_SIM1RSTI, "gpio8"),
  98         PINCTRL_PIN(PALMAS_PIN_GPIO9_LOW_VBAT, "gpio9"),
  99         PINCTRL_PIN(PALMAS_PIN_GPIO10_WIRELESS_CHRG1, "gpio10"),
 100         PINCTRL_PIN(PALMAS_PIN_GPIO11_RCM, "gpio11"),
 101         PINCTRL_PIN(PALMAS_PIN_GPIO12_SIM2RSTO, "gpio12"),
 102         PINCTRL_PIN(PALMAS_PIN_GPIO13, "gpio13"),
 103         PINCTRL_PIN(PALMAS_PIN_GPIO14, "gpio14"),
 104         PINCTRL_PIN(PALMAS_PIN_GPIO15_SIM2RSTI, "gpio15"),
 105         PINCTRL_PIN(PALMAS_PIN_VAC, "vac"),
 106         PINCTRL_PIN(PALMAS_PIN_POWERGOOD_USB_PSEL, "powergood"),
 107         PINCTRL_PIN(PALMAS_PIN_NRESWARM, "nreswarm"),
 108         PINCTRL_PIN(PALMAS_PIN_PWRDOWN, "pwrdown"),
 109         PINCTRL_PIN(PALMAS_PIN_GPADC_START, "gpadc_start"),
 110         PINCTRL_PIN(PALMAS_PIN_RESET_IN, "reset_in"),
 111         PINCTRL_PIN(PALMAS_PIN_NSLEEP, "nsleep"),
 112         PINCTRL_PIN(PALMAS_PIN_ENABLE1, "enable1"),
 113         PINCTRL_PIN(PALMAS_PIN_ENABLE2, "enable2"),
 114         PINCTRL_PIN(PALMAS_PIN_INT, "int"),
 115 };
 116
 117 static const char * const opt0_groups[] = {
 118         "gpio0",
 119         "gpio1",
 120         "gpio2",
 121         "gpio3",
 122         "gpio4",
 123         "gpio5",
 124         "gpio6",
 125         "gpio7",
 126         "gpio8",
 127         "gpio9",
 128         "gpio10",
 129         "gpio11",
 130         "gpio12",
 131         "gpio13",
 132         "gpio14",
 133         "gpio15",
 134         "vac",
 135         "powergood",
 136         "nreswarm",
 137         "pwrdown",
 138         "gpadc_start",
 139         "reset_in",
 140         "nsleep",
 141         "enable1",
 142         "enable2",
 143         "int",
 144 };
 145
 146 static const char * const opt1_groups[] = {
 147         "gpio0",
 148         "gpio1",
 149         "gpio2",
 150         "gpio3",
 151         "gpio4",
 152         "gpio5",
 153         "gpio6",
 154         "gpio7",
 155         "gpio8",
 156         "gpio9",
 157         "gpio10",
 158         "gpio11",
 159         "gpio12",
 160         "gpio15",
 161         "vac",
 162         "powergood",
 163 };
 164
 165 static const char * const opt2_groups[] = {
 166         "gpio1",
 167         "gpio2",
 168         "gpio5",
 169         "gpio7",
 170 };
 171
 172 static const char * const opt3_groups[] = {
 173         "gpio1",
 174         "gpio2",
 175 };
 176
 177 static const char * const gpio_groups[] = {
 178         "gpio0",
 179         "gpio1",
 180         "gpio2",
 181         "gpio3",
 182         "gpio4",
 183         "gpio5",
 184         "gpio6",
 185         "gpio7",
 186         "gpio8",
 187         "gpio9",
 188         "gpio10",
 189         "gpio11",
 190         "gpio12",
 191         "gpio13",
 192         "gpio14",
 193         "gpio15",
 194 };
 195
 196 static const char * const led_groups[] = {
 197         "gpio1",
 198         "gpio2",
 199 };
 200
 201 static const char * const pwm_groups[] = {
 202         "gpio1",
 203         "gpio2",
 204 };
 205
 206 static const char * const regen_groups[] = {
 207         "gpio2",
 208 };
 209
 210 static const char * const sysen_groups[] = {
 211         "gpio4",
 212         "gpio6",
 213 };
 214
 215 static const char * const clk32kgaudio_groups[] = {
 216         "gpio5",
 217 };
 218
 219 static const char * const id_groups[] = {
 220         "gpio0",
 221 };
 222
 223 static const char * const vbus_det_groups[] = {
 224         "gpio1",
 225 };
 226
 227 static const char * const chrg_det_groups[] = {
 228         "gpio3",
 229 };
 230
 231 static const char * const vac_groups[] = {
 232         "vac",
 233 };
 234
 235 static const char * const vacok_groups[] = {
 236         "vac",
 237 };
 238
 239 static const char * const powergood_groups[] = {
 240         "powergood",
 241 };
 242
 243 static const char * const usb_psel_groups[] = {
 244         "gpio5",
 245         "powergood",
 246 };
 247
 248 static const char * const msecure_groups[] = {
 249         "gpio7",
 250 };
 251
 252 static const char * const pwrhold_groups[] = {
 253         "gpio7",
 254 };
 255
 256 static const char * const int_groups[] = {
 257         "int",
 258 };
 259
 260 static const char * const nreswarm_groups[] = {
 261         "nreswarm",
 262 };
 263
 264 static const char * const simrsto_groups[] = {
 265         "gpio12",
 266 };
 267
 268 static const char * const simrsti_groups[] = {
 269         "gpio8",
 270         "gpio15",
 271 };
 272
 273 static const char * const low_vbat_groups[] = {
 274         "gpio9",
 275 };
 276
 277 static const char * const wireless_chrg1_groups[] = {
 278         "gpio10",
 279 };
 280
 281 static const char * const rcm_groups[] = {
 282         "gpio11",
 283 };
 284
 285 static const char * const pwrdown_groups[] = {
 286         "pwrdown",
 287 };
 288
 289 static const char * const gpadc_start_groups[] = {
 290         "gpadc_start",
 291 };
 292
 293 static const char * const reset_in_groups[] = {
 294         "reset_in",
 295 };
 296
 297 static const char * const nsleep_groups[] = {
 298         "nsleep",
 299 };
 300
 301 static const char * const enable_groups[] = {
 302         "enable1",
 303         "enable2",
 304 };
 305
 306 #define FUNCTION_GROUPS                                 \
 307         FUNCTION_GROUP(opt0, OPTION0),                  \
 308         FUNCTION_GROUP(opt1, OPTION1),                  \
 309         FUNCTION_GROUP(opt2, OPTION2),                  \
 310         FUNCTION_GROUP(opt3, OPTION3),                  \
 311         FUNCTION_GROUP(gpio, GPIO),                     \
 312         FUNCTION_GROUP(led, LED),                       \
 313         FUNCTION_GROUP(pwm, PWM),                       \
 314         FUNCTION_GROUP(regen, REGEN),                   \
 315         FUNCTION_GROUP(sysen, SYSEN),                   \
 316         FUNCTION_GROUP(clk32kgaudio, CLK32KGAUDIO),     \
 317         FUNCTION_GROUP(id, ID),                         \
 318         FUNCTION_GROUP(vbus_det, VBUS_DET),             \
 319         FUNCTION_GROUP(chrg_det, CHRG_DET),             \
 320         FUNCTION_GROUP(vac, VAC),                       \
 321         FUNCTION_GROUP(vacok, VACOK),                   \
 322         FUNCTION_GROUP(powergood, POWERGOOD),           \
 323         FUNCTION_GROUP(usb_psel, USB_PSEL),             \
 324         FUNCTION_GROUP(msecure, MSECURE),               \
 325         FUNCTION_GROUP(pwrhold, PWRHOLD),               \
 326         FUNCTION_GROUP(int, INT),                       \
 327         FUNCTION_GROUP(nreswarm, NRESWARM),             \
 328         FUNCTION_GROUP(simrsto, SIMRSTO),               \
 329         FUNCTION_GROUP(simrsti, SIMRSTI),               \
 330         FUNCTION_GROUP(low_vbat, LOW_VBAT),             \
 331         FUNCTION_GROUP(wireless_chrg1, WIRELESS_CHRG1), \
 332         FUNCTION_GROUP(rcm, RCM),                       \
 333         FUNCTION_GROUP(pwrdown, PWRDOWN),               \
 334         FUNCTION_GROUP(gpadc_start, GPADC_START),       \
 335         FUNCTION_GROUP(reset_in, RESET_IN),             \
 336         FUNCTION_GROUP(nsleep, NSLEEP),                 \
 337         FUNCTION_GROUP(enable, ENABLE)
 338
 339 static const struct palmas_pin_function palmas_pin_function[] = {
 340 #undef FUNCTION_GROUP
 341 #define FUNCTION_GROUP(fname, mux)                      \
 342         {                                               \
 343                 .name = #fname,                         \
 344                 .groups = fname##_groups,               \
 345                 .ngroups = ARRAY_SIZE(fname##_groups),  \
 346         }
 347
 348         FUNCTION_GROUPS,
 349 };
 350
 351 enum palmas_pinmux {
 352 #undef FUNCTION_GROUP
 353 #define FUNCTION_GROUP(fname, mux)      PALMAS_PINMUX_##mux
 354         FUNCTION_GROUPS,
 355         PALMAS_PINMUX_NA = 0xFFFF,
 356 };
 357
 358 struct palmas_pins_pullup_dn_info {
 359         int pullup_dn_reg_base;
 360         int pullup_dn_reg_add;
 361         int pullup_dn_mask;
 362         int normal_val;
 363         int pull_up_val;
 364         int pull_dn_val;
 365 };
 366
 367 struct palmas_pins_od_info {
 368         int od_reg_base;
 369         int od_reg_add;
 370         int od_mask;
 371         int od_enable;
 372         int od_disable;
 373 };
 374
 375 struct palmas_pin_info {
 376         enum palmas_pinmux mux_opt;
 377         const struct palmas_pins_pullup_dn_info *pud_info;
 378         const struct palmas_pins_od_info *od_info;
 379 };
 380
 381 struct palmas_pingroup {
 382         const char *name;
 383         const unsigned pins[1];
 384         unsigned npins;
 385         unsigned mux_reg_base;
 386         unsigned mux_reg_add;
 387         unsigned mux_reg_mask;
 388         unsigned mux_bit_shift;
 389         const struct palmas_pin_info *opt[4];
 390 };
 391
 392 #define PULL_UP_DN(_name, _rbase, _add, _mask, _nv, _uv, _dv)           \
 393 static const struct palmas_pins_pullup_dn_info pud_##_name##_info = {   \
 394         .pullup_dn_reg_base = PALMAS_##_rbase##_BASE,                   \
 395         .pullup_dn_reg_add = _add,                                      \
 396         .pullup_dn_mask = _mask,                                        \
 397         .normal_val = _nv,                                              \
 398         .pull_up_val = _uv,                                             \
 399         .pull_dn_val = _dv,                                             \
 400 }
 401
 402 PULL_UP_DN(nreswarm,    PU_PD_OD,       PALMAS_PU_PD_INPUT_CTRL1,       0x2,    0x0,    0x2,    -1);
 403 PULL_UP_DN(pwrdown,     PU_PD_OD,       PALMAS_PU_PD_INPUT_CTRL1,       0x4,    0x0,    -1,     0x4);
 404 PULL_UP_DN(gpadc_start, PU_PD_OD,       PALMAS_PU_PD_INPUT_CTRL1,       0x30,   0x0,    0x20,   0x10);
 405 PULL_UP_DN(reset_in,    PU_PD_OD,       PALMAS_PU_PD_INPUT_CTRL1,       0x40,   0x0,    -1,     0x40);
 406 PULL_UP_DN(nsleep,      PU_PD_OD,       PALMAS_PU_PD_INPUT_CTRL2,       0x3,    0x0,    0x2,    0x1);
 407 PULL_UP_DN(enable1,     PU_PD_OD,       PALMAS_PU_PD_INPUT_CTRL2,       0xC,    0x0,    0x8,    0x4);
 408 PULL_UP_DN(enable2,     PU_PD_OD,       PALMAS_PU_PD_INPUT_CTRL2,       0x30,   0x0,    0x20,   0x10);
 409 PULL_UP_DN(vacok,       PU_PD_OD,       PALMAS_PU_PD_INPUT_CTRL3,       0x40,   0x0,    -1,     0x40);
 410 PULL_UP_DN(chrg_det,    PU_PD_OD,       PALMAS_PU_PD_INPUT_CTRL3,       0x10,   0x0,    -1,     0x10);
 411 PULL_UP_DN(pwrhold,     PU_PD_OD,       PALMAS_PU_PD_INPUT_CTRL3,       0x4,    0x0,    -1,     0x4);
 412 PULL_UP_DN(msecure,     PU_PD_OD,       PALMAS_PU_PD_INPUT_CTRL3,       0x1,    0x0,    -1,     0x1);
 413 PULL_UP_DN(id,          USB_OTG,        PALMAS_USB_ID_CTRL_SET,         0x40,   0x0,    0x40,   -1);
 414 PULL_UP_DN(gpio0,       GPIO,           PALMAS_PU_PD_GPIO_CTRL1,        0x04,   0,      -1,     1);
 415 PULL_UP_DN(gpio1,       GPIO,           PALMAS_PU_PD_GPIO_CTRL1,        0x0C,   0,      0x8,    0x4);
 416 PULL_UP_DN(gpio2,       GPIO,           PALMAS_PU_PD_GPIO_CTRL1,        0x30,   0x0,    0x20,   0x10);
 417 PULL_UP_DN(gpio3,       GPIO,           PALMAS_PU_PD_GPIO_CTRL1,        0x40,   0x0,    -1,     0x40);
 418 PULL_UP_DN(gpio4,       GPIO,           PALMAS_PU_PD_GPIO_CTRL2,        0x03,   0x0,    0x2,    0x1);
 419 PULL_UP_DN(gpio5,       GPIO,           PALMAS_PU_PD_GPIO_CTRL2,        0x0c,   0x0,    0x8,    0x4);
 420 PULL_UP_DN(gpio6,       GPIO,           PALMAS_PU_PD_GPIO_CTRL2,        0x30,   0x0,    0x20,   0x10);
 421 PULL_UP_DN(gpio7,       GPIO,           PALMAS_PU_PD_GPIO_CTRL2,        0x40,   0x0,    -1,     0x40);
 422 PULL_UP_DN(gpio9,       GPIO,           PALMAS_PU_PD_GPIO_CTRL3,        0x0C,   0x0,    0x8,    0x4);
 423 PULL_UP_DN(gpio10,      GPIO,           PALMAS_PU_PD_GPIO_CTRL3,        0x30,   0x0,    0x20,   0x10);
 424 PULL_UP_DN(gpio11,      GPIO,           PALMAS_PU_PD_GPIO_CTRL3,        0xC0,   0x0,    0x80,   0x40);
 425 PULL_UP_DN(gpio13,      GPIO,           PALMAS_PU_PD_GPIO_CTRL4,        0x04,   0x0,    -1,     0x04);
 426 PULL_UP_DN(gpio14,      GPIO,           PALMAS_PU_PD_GPIO_CTRL4,        0x30,   0x0,    0x20,   0x10);
 427
 428 #define OD_INFO(_name, _rbase, _add, _mask, _ev, _dv)           \
 429 static const struct palmas_pins_od_info od_##_name##_info = {   \
 430         .od_reg_base = PALMAS_##_rbase##_BASE,                  \
 431         .od_reg_add = _add,                                     \
 432         .od_mask = _mask,                                       \
 433         .od_enable = _ev,                                       \
 434         .od_disable = _dv,                                      \
 435 }
 436
 437 OD_INFO(gpio1,  GPIO,   PALMAS_OD_OUTPUT_GPIO_CTRL,     0x1,    0x1,    0x0);
 438 OD_INFO(gpio2,  GPIO,   PALMAS_OD_OUTPUT_GPIO_CTRL,     0x2,    0x2,    0x0);
 439 OD_INFO(gpio5,  GPIO,   PALMAS_OD_OUTPUT_GPIO_CTRL,     0x20,   0x20,   0x0);
 440 OD_INFO(gpio10, GPIO,   PALMAS_OD_OUTPUT_GPIO_CTRL2,    0x04,   0x04,   0x0);
 441 OD_INFO(gpio13, GPIO,   PALMAS_OD_OUTPUT_GPIO_CTRL2,    0x20,   0x20,   0x0);
 442 OD_INFO(int,            PU_PD_OD,       PALMAS_OD_OUTPUT_CTRL,  0x8,    0x8,    0x0);
 443 OD_INFO(pwm1,           PU_PD_OD,       PALMAS_OD_OUTPUT_CTRL,  0x20,   0x20,   0x0);
 444 OD_INFO(pwm2,           PU_PD_OD,       PALMAS_OD_OUTPUT_CTRL,  0x80,   0x80,   0x0);
 445 OD_INFO(vbus_det,       PU_PD_OD,       PALMAS_OD_OUTPUT_CTRL,  0x40,   0x40,   0x0);
 446
 447 #define PIN_INFO(_name, _id, _pud_info, _od_info)               \
 448 static const struct palmas_pin_info pin_##_name##_info = {      \
 449         .mux_opt = PALMAS_PINMUX_##_id,                         \
 450         .pud_info = _pud_info,                                  \
 451         .od_info = _od_info                                     \
 452 }
 453
 454 PIN_INFO(gpio0,         GPIO,           &pud_gpio0_info,        NULL);
 455 PIN_INFO(gpio1,         GPIO,           &pud_gpio1_info,        &od_gpio1_info);
 456 PIN_INFO(gpio2,         GPIO,           &pud_gpio2_info,        &od_gpio2_info);
 457 PIN_INFO(gpio3,         GPIO,           &pud_gpio3_info,        NULL);
 458 PIN_INFO(gpio4,         GPIO,           &pud_gpio4_info,        NULL);
 459 PIN_INFO(gpio5,         GPIO,           &pud_gpio5_info,        &od_gpio5_info);
 460 PIN_INFO(gpio6,         GPIO,           &pud_gpio6_info,        NULL);
 461 PIN_INFO(gpio7,         GPIO,           &pud_gpio7_info,        NULL);
 462 PIN_INFO(gpio8,         GPIO,           NULL,                   NULL);
 463 PIN_INFO(gpio9,         GPIO,           &pud_gpio9_info,        NULL);
 464 PIN_INFO(gpio10,        GPIO,           &pud_gpio10_info,       &od_gpio10_info);
 465 PIN_INFO(gpio11,        GPIO,           &pud_gpio11_info,       NULL);
 466 PIN_INFO(gpio12,        GPIO,           NULL,                   NULL);
 467 PIN_INFO(gpio13,        GPIO,           &pud_gpio13_info,       &od_gpio13_info);
 468 PIN_INFO(gpio14,        GPIO,           &pud_gpio14_info,       NULL);
 469 PIN_INFO(gpio15,        GPIO,           NULL,                   NULL);
 470 PIN_INFO(id,            ID,             &pud_id_info,           NULL);
 471 PIN_INFO(led1,          LED,            NULL,                   NULL);
 472 PIN_INFO(led2,          LED,            NULL,                   NULL);
 473 PIN_INFO(regen,         REGEN,          NULL,                   NULL);
 474 PIN_INFO(sysen1,        SYSEN,          NULL,                   NULL);
 475 PIN_INFO(sysen2,        SYSEN,          NULL,                   NULL);
 476 PIN_INFO(int,           INT,            NULL,                   &od_int_info);
 477 PIN_INFO(pwm1,          PWM,            NULL,                   &od_pwm1_info);
 478 PIN_INFO(pwm2,          PWM,            NULL,                   &od_pwm2_info);
 479 PIN_INFO(vacok,         VACOK,          &pud_vacok_info,        NULL);
 480 PIN_INFO(chrg_det,      CHRG_DET,       &pud_chrg_det_info,     NULL);
 481 PIN_INFO(pwrhold,       PWRHOLD,        &pud_pwrhold_info,      NULL);
 482 PIN_INFO(msecure,       MSECURE,        &pud_msecure_info,      NULL);
 483 PIN_INFO(nreswarm,      NA,             &pud_nreswarm_info,     NULL);
 484 PIN_INFO(pwrdown,       NA,             &pud_pwrdown_info,      NULL);
 485 PIN_INFO(gpadc_start,   NA,             &pud_gpadc_start_info,  NULL);
 486 PIN_INFO(reset_in,      NA,             &pud_reset_in_info,     NULL);
 487 PIN_INFO(nsleep,        NA,             &pud_nsleep_info,       NULL);
 488 PIN_INFO(enable1,       NA,             &pud_enable1_info,      NULL);
 489 PIN_INFO(enable2,       NA,             &pud_enable2_info,      NULL);
 490 PIN_INFO(clk32kgaudio,  CLK32KGAUDIO,   NULL,                   NULL);
 491 PIN_INFO(usb_psel,      USB_PSEL,       NULL,                   NULL);
 492 PIN_INFO(vac,           VAC,            NULL,                   NULL);
 493 PIN_INFO(powergood,     POWERGOOD,      NULL,                   NULL);
 494 PIN_INFO(vbus_det,      VBUS_DET,       NULL,                   &od_vbus_det_info);
 495 PIN_INFO(sim1rsti,      SIMRSTI,        NULL,                   NULL);
 496 PIN_INFO(low_vbat,      LOW_VBAT,       NULL,                   NULL);
 497 PIN_INFO(rcm,           RCM,            NULL,                   NULL);
 498 PIN_INFO(sim2rsto,      SIMRSTO,        NULL,                   NULL);
 499 PIN_INFO(sim2rsti,      SIMRSTI,        NULL,                   NULL);
 500 PIN_INFO(wireless_chrg1,        WIRELESS_CHRG1, NULL,           NULL);
 501
 502 #define PALMAS_PRIMARY_SECONDARY_NONE   0
 503 #define PALMAS_NONE_BASE                0
 504 #define PALMAS_PRIMARY_SECONDARY_INPUT3 PALMAS_PU_PD_INPUT_CTRL3
 505
 506 #define PALMAS_PINGROUP(pg_name, pin_id, base, reg, _mask, _bshift, o0, o1, o2, o3)  \
 507         {                                                               \
 508                 .name = #pg_name,                                       \
 509                 .pins = {PALMAS_PIN_##pin_id},                          \
 510                 .npins = 1,                                             \
 511                 .mux_reg_base = PALMAS_##base##_BASE,                   \
 512                 .mux_reg_add = PALMAS_PRIMARY_SECONDARY_##reg,          \
 513                 .mux_reg_mask = _mask,                                  \
 514                 .mux_bit_shift = _bshift,                               \
 515                 .opt = {                                                \
 516                         o0,                                             \
 517                         o1,                                             \
 518                         o2,                                             \
 519                         o3,                                             \
 520                 },                                                      \
 521         }
 522
 523 static const struct palmas_pingroup tps65913_pingroups[] = {
 524         PALMAS_PINGROUP(gpio0,  GPIO0_ID,                       PU_PD_OD,       PAD1,   0x4,    0x2,    &pin_gpio0_info,        &pin_id_info,           NULL,           NULL),
 525         PALMAS_PINGROUP(gpio1,  GPIO1_VBUS_LED1_PWM1,           PU_PD_OD,       PAD1,   0x18,   0x3,    &pin_gpio1_info,        &pin_vbus_det_info,     &pin_led1_info, &pin_pwm1_info),
 526         PALMAS_PINGROUP(gpio2,  GPIO2_REGEN_LED2_PWM2,          PU_PD_OD,       PAD1,   0x60,   0x5,    &pin_gpio2_info,        &pin_regen_info,        &pin_led2_info, &pin_pwm2_info),
 527         PALMAS_PINGROUP(gpio3,  GPIO3_CHRG_DET,                 PU_PD_OD,       PAD1,   0x80,   0x7,    &pin_gpio3_info,        &pin_chrg_det_info,     NULL,           NULL),
 528         PALMAS_PINGROUP(gpio4,  GPIO4_SYSEN1,                   PU_PD_OD,       PAD1,   0x01,   0x0,    &pin_gpio4_info,        &pin_sysen1_info,       NULL,           NULL),
 529         PALMAS_PINGROUP(gpio5,  GPIO5_CLK32KGAUDIO_USB_PSEL,    PU_PD_OD,       PAD2,   0x6,    0x1,    &pin_gpio5_info,        &pin_clk32kgaudio_info, &pin_usb_psel_info,     NULL),
 530         PALMAS_PINGROUP(gpio6,  GPIO6_SYSEN2,                   PU_PD_OD,       PAD2,   0x08,   0x3,    &pin_gpio6_info,        &pin_sysen2_info,       NULL,           NULL),
 531         PALMAS_PINGROUP(gpio7,  GPIO7_MSECURE_PWRHOLD,          PU_PD_OD,       PAD2,   0x30,   0x4,    &pin_gpio7_info,        &pin_msecure_info,      &pin_pwrhold_info,      NULL),
 532         PALMAS_PINGROUP(vac,    VAC,                            PU_PD_OD,       PAD1,   0x02,   0x1,    &pin_vac_info,          &pin_vacok_info,        NULL,           NULL),
 533         PALMAS_PINGROUP(powergood,      POWERGOOD_USB_PSEL,     PU_PD_OD,       PAD1,   0x01,   0x0,    &pin_powergood_info,    &pin_usb_psel_info,     NULL,   NULL),
 534         PALMAS_PINGROUP(nreswarm,       NRESWARM,               NONE,           NONE,   0x0,    0x0,    &pin_nreswarm_info,     NULL,                   NULL,           NULL),
 535         PALMAS_PINGROUP(pwrdown,        PWRDOWN,                NONE,           NONE,   0x0,    0x0,    &pin_pwrdown_info,      NULL,                   NULL,           NULL),
 536         PALMAS_PINGROUP(gpadc_start,    GPADC_START,            NONE,           NONE,   0x0,    0x0,    &pin_gpadc_start_info,  NULL,                   NULL,           NULL),
 537         PALMAS_PINGROUP(reset_in,       RESET_IN,               NONE,           NONE,   0x0,    0x0,    &pin_reset_in_info,     NULL,                   NULL,           NULL),
 538         PALMAS_PINGROUP(nsleep,         NSLEEP,                 NONE,           NONE,   0x0,    0x0,    &pin_nsleep_info,       NULL,                   NULL,           NULL),
 539         PALMAS_PINGROUP(enable1,        ENABLE1,                NONE,           NONE,   0x0,    0x0,    &pin_enable1_info,      NULL,                   NULL,           NULL),
 540         PALMAS_PINGROUP(enable2,        ENABLE2,                NONE,           NONE,   0x0,    0x0,    &pin_enable2_info,      NULL,                   NULL,           NULL),
 541         PALMAS_PINGROUP(int,            INT,                    NONE,           NONE,   0x0,    0x0,    &pin_int_info,          NULL,                   NULL,           NULL),
 542 };
 543
 544 static const struct palmas_pingroup tps80036_pingroups[] = {
 545         PALMAS_PINGROUP(gpio0,  GPIO0_ID,                       PU_PD_OD,       PAD1,   0x4,    0x2,    &pin_gpio0_info,        &pin_id_info,           NULL,           NULL),
 546         PALMAS_PINGROUP(gpio1,  GPIO1_VBUS_LED1_PWM1,           PU_PD_OD,       PAD1,   0x18,   0x3,    &pin_gpio1_info,        &pin_vbus_det_info,     &pin_led1_info, &pin_pwm1_info),
 547         PALMAS_PINGROUP(gpio2,  GPIO2_REGEN_LED2_PWM2,          PU_PD_OD,       PAD1,   0x60,   0x5,    &pin_gpio2_info,        &pin_regen_info,        &pin_led2_info, &pin_pwm2_info),
 548         PALMAS_PINGROUP(gpio3,  GPIO3_CHRG_DET,                 PU_PD_OD,       PAD1,   0x80,   0x7,    &pin_gpio3_info,        &pin_chrg_det_info,     NULL,           NULL),
 549         PALMAS_PINGROUP(gpio4,  GPIO4_SYSEN1,                   PU_PD_OD,       PAD1,   0x01,   0x0,    &pin_gpio4_info,        &pin_sysen1_info,       NULL,           NULL),
 550         PALMAS_PINGROUP(gpio5,  GPIO5_CLK32KGAUDIO_USB_PSEL,    PU_PD_OD,       PAD2,   0x6,    0x1,    &pin_gpio5_info,        &pin_clk32kgaudio_info, &pin_usb_psel_info,     NULL),
 551         PALMAS_PINGROUP(gpio6,  GPIO6_SYSEN2,                   PU_PD_OD,       PAD2,   0x08,   0x3,    &pin_gpio6_info,        &pin_sysen2_info,       NULL,           NULL),
 552         PALMAS_PINGROUP(gpio7,  GPIO7_MSECURE_PWRHOLD,          PU_PD_OD,       PAD2,   0x30,   0x4,    &pin_gpio7_info,        &pin_msecure_info,      &pin_pwrhold_info,      NULL),
 553         PALMAS_PINGROUP(gpio8,  GPIO8_SIM1RSTI,                 PU_PD_OD,       PAD4,   0x01,   0x0,    &pin_gpio8_info,        &pin_sim1rsti_info,     NULL,           NULL),
 554         PALMAS_PINGROUP(gpio9,  GPIO9_LOW_VBAT,                 PU_PD_OD,       PAD4,   0x02,   0x1,    &pin_gpio9_info,        &pin_low_vbat_info,     NULL,           NULL),
 555         PALMAS_PINGROUP(gpio10, GPIO10_WIRELESS_CHRG1,          PU_PD_OD,       PAD4,   0x04,   0x2,    &pin_gpio10_info,       &pin_wireless_chrg1_info,       NULL,   NULL),
 556         PALMAS_PINGROUP(gpio11, GPIO11_RCM,                     PU_PD_OD,       PAD4,   0x08,   0x3,    &pin_gpio11_info,       &pin_rcm_info,          NULL,           NULL),
 557         PALMAS_PINGROUP(gpio12, GPIO12_SIM2RSTO,                PU_PD_OD,       PAD4,   0x10,   0x4,    &pin_gpio12_info,       &pin_sim2rsto_info,     NULL,           NULL),
 558         PALMAS_PINGROUP(gpio13, GPIO13,                         NONE,           NONE,   0x00,   0x0,    &pin_gpio13_info,       NULL,                   NULL,           NULL),
 559         PALMAS_PINGROUP(gpio14, GPIO14,                         NONE,           NONE,   0x00,   0x0,    &pin_gpio14_info,       NULL,                   NULL,           NULL),
 560         PALMAS_PINGROUP(gpio15, GPIO15_SIM2RSTI,                PU_PD_OD,       PAD4,   0x80,   0x7,    &pin_gpio15_info,       &pin_sim2rsti_info,     NULL,           NULL),
 561         PALMAS_PINGROUP(vac,    VAC,                            PU_PD_OD,       PAD1,   0x02,   0x1,    &pin_vac_info,          &pin_vacok_info,        NULL,           NULL),
 562         PALMAS_PINGROUP(powergood,      POWERGOOD_USB_PSEL,     PU_PD_OD,       PAD1,   0x01,   0x0,    &pin_powergood_info,    &pin_usb_psel_info,     NULL,   NULL),
 563         PALMAS_PINGROUP(nreswarm,       NRESWARM,               NONE,           NONE,   0x0,    0x0,    &pin_nreswarm_info,     NULL,                   NULL,           NULL),
 564         PALMAS_PINGROUP(pwrdown,        PWRDOWN,                NONE,           NONE,   0x0,    0x0,    &pin_pwrdown_info,      NULL,                   NULL,           NULL),
 565         PALMAS_PINGROUP(gpadc_start,    GPADC_START,            NONE,           NONE,   0x0,    0x0,    &pin_gpadc_start_info,  NULL,                   NULL,           NULL),
 566         PALMAS_PINGROUP(reset_in,       RESET_IN,               NONE,           NONE,   0x0,    0x0,    &pin_reset_in_info,     NULL,                   NULL,           NULL),
 567         PALMAS_PINGROUP(nsleep,         NSLEEP,                 NONE,           NONE,   0x0,    0x0,    &pin_nsleep_info,       NULL,                   NULL,           NULL),
 568         PALMAS_PINGROUP(enable1,        ENABLE1,                NONE,           NONE,   0x0,    0x0,    &pin_enable1_info,      NULL,                   NULL,           NULL),
 569         PALMAS_PINGROUP(enable2,        ENABLE2,                NONE,           NONE,   0x0,    0x0,    &pin_enable2_info,      NULL,                   NULL,           NULL),
 570         PALMAS_PINGROUP(int,            INT,                    NONE,           NONE,   0x0,    0x0,    &pin_int_info,          NULL,                   NULL,           NULL),
 571 };
 572
 573 static int palmas_pinctrl_get_pin_mux(struct palmas_pctrl_chip_info *pci)
 574 {
 575         const struct palmas_pingroup *g;
 576         unsigned int val;
 577         int ret;
 578         int i;
 579
 580         for (i = 0; i < pci->num_pin_groups; ++i) {
 581                 g = &pci->pin_groups[i];
 582                 if (g->mux_reg_base == PALMAS_NONE_BASE) {
 583                         pci->pins_current_opt[i] = 0;
 584                         continue;
 585                 }
 586                 ret = palmas_read(pci->palmas, g->mux_reg_base,
 587                                 g->mux_reg_add, &val);
 588                 if (ret < 0) {
 589                         dev_err(pci->dev, "mux_reg 0x%02x read failed: %d\n",
 590                                         g->mux_reg_add, ret);
 591                         return ret;
 592                 }
 593                 val &= g->mux_reg_mask;
 594                 pci->pins_current_opt[i] = val >> g->mux_bit_shift;
 595         }
 596         return 0;
 597 }
 598
 599 static int palmas_pinctrl_set_dvfs1(struct palmas_pctrl_chip_info *pci,
 600                 bool enable)
 601 {
 602         int ret;
 603         int val;
 604
 605         val = enable ? PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1 : 0;
 606         ret = palmas_update_bits(pci->palmas, PALMAS_PU_PD_OD_BASE,
 607                         PALMAS_PRIMARY_SECONDARY_PAD3,
 608                         PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1, val);
 609         if (ret < 0)
 610                 dev_err(pci->dev, "SECONDARY_PAD3 update failed %d\n", ret);
 611         return ret;
 612 }
 613
 614 static int palmas_pinctrl_set_dvfs2(struct palmas_pctrl_chip_info *pci,
 615                 bool enable)
 616 {
 617         int ret;
 618         int val;
 619
 620         val = enable ? PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2 : 0;
 621         ret = palmas_update_bits(pci->palmas, PALMAS_PU_PD_OD_BASE,
 622                         PALMAS_PRIMARY_SECONDARY_PAD3,
 623                         PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2, val);
 624         if (ret < 0)
 625                 dev_err(pci->dev, "SECONDARY_PAD3 update failed %d\n", ret);
 626         return ret;
 627 }
 628
 629 static int palmas_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
 630 {
 631         struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev);
 632
 633         return pci->num_pin_groups;
 634 }
 635
 636 static const char *palmas_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
 637                 unsigned group)
 638 {
 639         struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev);
 640
 641         return pci->pin_groups[group].name;
 642 }
 643
 644 static int palmas_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
 645                 unsigned group, const unsigned **pins, unsigned *num_pins)
 646 {
 647         struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev);
 648
 649         *pins = pci->pin_groups[group].pins;
 650         *num_pins = pci->pin_groups[group].npins;
 651         return 0;
 652 }
 653
 654 static const struct pinctrl_ops palmas_pinctrl_ops = {
 655         .get_groups_count = palmas_pinctrl_get_groups_count,
 656         .get_group_name = palmas_pinctrl_get_group_name,
 657         .get_group_pins = palmas_pinctrl_get_group_pins,
 658         .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
 659         .dt_free_map = pinctrl_utils_dt_free_map,
 660 };
 661
 662 static int palmas_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
 663 {
 664         struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev);
 665
 666         return pci->num_functions;
 667 }
 668
 669 static const char *palmas_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
 670                         unsigned function)
 671 {
 672         struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev);
 673
 674         return pci->functions[function].name;
 675 }
 676
 677 static int palmas_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
 678                 unsigned function, const char * const **groups,
 679                 unsigned * const num_groups)
 680 {
 681         struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev);
 682
 683         *groups = pci->functions[function].groups;
 684         *num_groups = pci->functions[function].ngroups;
 685         return 0;
 686 }
 687
 688 static int palmas_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned function,
 689                 unsigned group)
 690 {
 691         struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev);
 692         const struct palmas_pingroup *g;
 693         int i;
 694         int ret;
 695
 696         g = &pci->pin_groups[group];
 697
 698         /* If direct option is provided here */
 699         if (function <= PALMAS_PINMUX_OPTION3) {
 700                 if (!g->opt[function]) {
 701                         dev_err(pci->dev, "Pin %s does not support option %d\n",
 702                                 g->name, function);
 703                         return -EINVAL;
 704                 }
 705                 i = function;
 706         } else {
 707                 for (i = 0; i < ARRAY_SIZE(g->opt); i++) {
 708                         if (!g->opt[i])
 709                                 continue;
 710                         if (g->opt[i]->mux_opt == function)
 711                                 break;
 712                 }
 713                 if (WARN_ON(i == ARRAY_SIZE(g->opt))) {
 714                         dev_err(pci->dev, "Pin %s does not support option %d\n",
 715                                 g->name, function);
 716                         return -EINVAL;
 717                 }
 718         }
 719
 720         if (g->mux_reg_base == PALMAS_NONE_BASE) {
 721                 if (WARN_ON(i != 0))
 722                         return -EINVAL;
 723                 return 0;
 724         }
 725
 726         dev_dbg(pci->dev, "%s(): Base0x%02x:0x%02x:0x%02x:0x%02x\n",
 727                         __func__, g->mux_reg_base, g->mux_reg_add,
 728                         g->mux_reg_mask, i << g->mux_bit_shift);
 729
 730         ret = palmas_update_bits(pci->palmas, g->mux_reg_base, g->mux_reg_add,
 731                         g->mux_reg_mask, i << g->mux_bit_shift);
 732         if (ret < 0) {
 733                 dev_err(pci->dev, "Reg 0x%02x update failed: %d\n",
 734                                 g->mux_reg_add, ret);
 735                 return ret;
 736         }
 737         pci->pins_current_opt[group] = i;
 738         return 0;
 739 }
 740
 741 static const struct pinmux_ops palmas_pinmux_ops = {
 742         .get_functions_count = palmas_pinctrl_get_funcs_count,
 743         .get_function_name = palmas_pinctrl_get_func_name,
 744         .get_function_groups = palmas_pinctrl_get_func_groups,
 745         .enable = palmas_pinctrl_enable,
 746 };
 747
 748 static int palmas_pinconf_get(struct pinctrl_dev *pctldev,
 749                         unsigned pin, unsigned long *config)
 750 {
 751         struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev);
 752         enum pin_config_param param = pinconf_to_config_param(*config);
 753         const struct palmas_pingroup *g;
 754         const struct palmas_pin_info *opt;
 755         unsigned int val;
 756         int ret;
 757         int base, add;
 758         int rval;
 759         int arg;
 760         int group_nr;
 761
 762         for (group_nr = 0; group_nr < pci->num_pin_groups; ++group_nr) {
 763                 if (pci->pin_groups[group_nr].pins[0] == pin)
 764                         break;
 765         }
 766
 767         if (group_nr == pci->num_pin_groups) {
 768                 dev_err(pci->dev,
 769                         "Pinconf is not supported for pin-id %d\n", pin);
 770                 return -ENOTSUPP;
 771         }
 772
 773         g = &pci->pin_groups[group_nr];
 774         opt = g->opt[pci->pins_current_opt[group_nr]];
 775         if (!opt) {
 776                 dev_err(pci->dev,
 777                         "Pinconf is not supported for pin %s\n", g->name);
 778                 return -ENOTSUPP;
 779         }
 780
 781         switch (param) {
 782         case PIN_CONFIG_BIAS_DISABLE:
 783         case PIN_CONFIG_BIAS_PULL_UP:
 784         case PIN_CONFIG_BIAS_PULL_DOWN:
 785                 if (!opt->pud_info) {
 786                         dev_err(pci->dev,
 787                                 "PULL control not supported for pin %s\n",
 788                                 g->name);
 789                         return -ENOTSUPP;
 790                 }
 791                 base = opt->pud_info->pullup_dn_reg_base;
 792                 add = opt->pud_info->pullup_dn_reg_add;
 793                 ret = palmas_read(pci->palmas, base, add, &val);
 794                 if (ret < 0) {
 795                         dev_err(pci->dev, "Reg 0x%02x read failed: %d\n",
 796                                 add, ret);
 797                         return ret;
 798                 }
 799
 800                 rval = val & opt->pud_info->pullup_dn_mask;
 801                 arg = 0;
 802                 if ((opt->pud_info->normal_val >= 0) &&
 803                                 (opt->pud_info->normal_val == rval) &&
 804                                 (param == PIN_CONFIG_BIAS_DISABLE))
 805                         arg = 1;
 806                 else if ((opt->pud_info->pull_up_val >= 0) &&
 807                                 (opt->pud_info->pull_up_val == rval) &&
 808                                 (param == PIN_CONFIG_BIAS_PULL_UP))
 809                         arg = 1;
 810                 else if ((opt->pud_info->pull_dn_val >= 0) &&
 811                                 (opt->pud_info->pull_dn_val == rval) &&
 812                                 (param == PIN_CONFIG_BIAS_PULL_DOWN))
 813                         arg = 1;
 814                 break;
 815
 816         case PIN_CONFIG_DRIVE_OPEN_DRAIN:
 817                 if (!opt->od_info) {
 818                         dev_err(pci->dev,
 819                                 "OD control not supported for pin %s\n",
 820                                 g->name);
 821                         return -ENOTSUPP;
 822                 }
 823                 base = opt->od_info->od_reg_base;
 824                 add = opt->od_info->od_reg_add;
 825                 ret = palmas_read(pci->palmas, base, add, &val);
 826                 if (ret < 0) {
 827                         dev_err(pci->dev, "Reg 0x%02x read failed: %d\n",
 828                                 add, ret);
 829                         return ret;
 830                 }
 831                 rval = val & opt->od_info->od_mask;
 832                 arg = -1;
 833                 if ((opt->od_info->od_disable >= 0) &&
 834                                 (opt->od_info->od_disable == rval))
 835                         arg = 0;
 836                 else if ((opt->od_info->od_enable >= 0) &&
 837                                         (opt->od_info->od_enable == rval))
 838                         arg = 1;
 839                 if (arg < 0) {
 840                         dev_err(pci->dev,
 841                                 "OD control not supported for pin %s\n",
 842                                 g->name);
 843                         return -ENOTSUPP;
 844                 }
 845                 break;
 846
 847         default:
 848                 dev_err(pci->dev, "Properties not supported\n");
 849                 return -ENOTSUPP;
 850         }
 851
 852         *config = pinconf_to_config_packed(param, (u16)arg);
 853         return 0;
 854 }
 855
 856 static int palmas_pinconf_set(struct pinctrl_dev *pctldev,
 857                         unsigned pin, unsigned long *configs,
 858                         unsigned num_configs)
 859 {
 860         struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev);
 861         enum pin_config_param param;
 862         u16 param_val;
 863         const struct palmas_pingroup *g;
 864         const struct palmas_pin_info *opt;
 865         int ret;
 866         int base, add, mask;
 867         int rval;
 868         int group_nr;
 869         int i;
 870
 871         for (group_nr = 0; group_nr < pci->num_pin_groups; ++group_nr) {
 872                 if (pci->pin_groups[group_nr].pins[0] == pin)
 873                         break;
 874         }
 875
 876         if (group_nr == pci->num_pin_groups) {
 877                 dev_err(pci->dev,
 878                         "Pinconf is not supported for pin-id %d\n", pin);
 879                 return -ENOTSUPP;
 880         }
 881
 882         g = &pci->pin_groups[group_nr];
 883         opt = g->opt[pci->pins_current_opt[group_nr]];
 884         if (!opt) {
 885                 dev_err(pci->dev,
 886                         "Pinconf is not supported for pin %s\n", g->name);
 887                 return -ENOTSUPP;
 888         }
 889
 890         for (i = 0; i < num_configs; i++) {
 891                 param = pinconf_to_config_param(configs[i]);
 892                 param_val = pinconf_to_config_argument(configs[i]);
 893
 894                 switch (param) {
 895                 case PIN_CONFIG_BIAS_DISABLE:
 896                 case PIN_CONFIG_BIAS_PULL_UP:
 897                 case PIN_CONFIG_BIAS_PULL_DOWN:
 898                         if (!opt->pud_info) {
 899                                 dev_err(pci->dev,
 900                                         "PULL control not supported for pin %s\n",
 901                                         g->name);
 902                                 return -ENOTSUPP;
 903                         }
 904                         base = opt->pud_info->pullup_dn_reg_base;
 905                         add = opt->pud_info->pullup_dn_reg_add;
 906                         mask = opt->pud_info->pullup_dn_mask;
 907
 908                         if (param == PIN_CONFIG_BIAS_DISABLE)
 909                                 rval = opt->pud_info->normal_val;
 910                         else if (param == PIN_CONFIG_BIAS_PULL_UP)
 911                                 rval = opt->pud_info->pull_up_val;
 912                         else
 913                                 rval = opt->pud_info->pull_dn_val;
 914
 915                         if (rval < 0) {
 916                                 dev_err(pci->dev,
 917                                         "PULL control not supported for pin %s\n",
 918                                         g->name);
 919                                 return -ENOTSUPP;
 920                         }
 921                         break;
 922
 923                 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
 924                         if (!opt->od_info) {
 925                                 dev_err(pci->dev,
 926                                         "OD control not supported for pin %s\n",
 927                                         g->name);
 928                                 return -ENOTSUPP;
 929                         }
 930                         base = opt->od_info->od_reg_base;
 931                         add = opt->od_info->od_reg_add;
 932                         mask = opt->od_info->od_mask;
 933                         if (param_val == 0)
 934                                 rval = opt->od_info->od_disable;
 935                         else
 936                                 rval = opt->od_info->od_enable;
 937                         if (rval < 0) {
 938                                 dev_err(pci->dev,
 939                                         "OD control not supported for pin %s\n",
 940                                         g->name);
 941                                 return -ENOTSUPP;
 942                         }
 943                         break;
 944                 default:
 945                         dev_err(pci->dev, "Properties not supported\n");
 946                         return -ENOTSUPP;
 947                 }
 948
 949                 dev_dbg(pci->dev, "%s(): Add0x%02x:0x%02x:0x%02x:0x%02x\n",
 950                                 __func__, base, add, mask, rval);
 951                 ret = palmas_update_bits(pci->palmas, base, add, mask, rval);
 952                 if (ret < 0) {
 953                         dev_err(pci->dev, "Reg 0x%02x update failed: %d\n",
 954                                 add, ret);
 955                         return ret;
 956                 }
 957         } /* for each config */
 958
 959         return 0;
 960 }
 961
 962 static const struct pinconf_ops palmas_pinconf_ops = {
 963         .pin_config_get = palmas_pinconf_get,
 964         .pin_config_set = palmas_pinconf_set,
 965 };
 966
 967 static struct pinctrl_desc palmas_pinctrl_desc = {
 968         .pctlops = &palmas_pinctrl_ops,
 969         .pmxops = &palmas_pinmux_ops,
 970         .confops = &palmas_pinconf_ops,
 971         .owner = THIS_MODULE,
 972 };
 973
 974 struct palmas_pinctrl_data {
 975         const struct palmas_pingroup *pin_groups;
 976         int num_pin_groups;
 977 };
 978
 979 static struct palmas_pinctrl_data tps65913_pinctrl_data = {
 980         .pin_groups = tps65913_pingroups,
 981         .num_pin_groups = ARRAY_SIZE(tps65913_pingroups),
 982 };
 983
 984 static struct palmas_pinctrl_data tps80036_pinctrl_data = {
 985         .pin_groups = tps80036_pingroups,
 986         .num_pin_groups = ARRAY_SIZE(tps80036_pingroups),
 987 };
 988
 989 static struct of_device_id palmas_pinctrl_of_match[] = {
 990         { .compatible = "ti,palmas-pinctrl", .data = &tps65913_pinctrl_data},
 991         { .compatible = "ti,tps65913-pinctrl", .data = &tps65913_pinctrl_data},
 992         { .compatible = "ti,tps80036-pinctrl", .data = &tps80036_pinctrl_data},
 993         { },
 994 };
 995 MODULE_DEVICE_TABLE(of, palmas_pinctrl_of_match);
 996
 997 static int palmas_pinctrl_probe(struct platform_device *pdev)
 998 {
 999         struct palmas_pctrl_chip_info *pci;
1000         const struct palmas_pinctrl_data *pinctrl_data = &tps65913_pinctrl_data;
1001         int ret;
1002         bool enable_dvfs1 = false;
1003         bool enable_dvfs2 = false;
1004
1005         if (pdev->dev.of_node) {
1006                 const struct of_device_id *match;
1007                 match = of_match_device(palmas_pinctrl_of_match, &pdev->dev);
1008                 pinctrl_data = match->data;
1009                 enable_dvfs1 = of_property_read_bool(pdev->dev.of_node,
1010                                         "ti,palmas-enable-dvfs1");
1011                 enable_dvfs2 = of_property_read_bool(pdev->dev.of_node,
1012                                         "ti,palmas-enable-dvfs2");
1013         }
1014
1015         pci = devm_kzalloc(&pdev->dev, sizeof(*pci), GFP_KERNEL);
1016         if (!pci) {
1017                 dev_err(&pdev->dev, "Malloc for pci failed\n");
1018                 return -ENOMEM;
1019         }
1020
1021         pci->dev = &pdev->dev;
1022         pci->palmas = dev_get_drvdata(pdev->dev.parent);
1023
1024         pci->pins = palmas_pins_desc;
1025         pci->num_pins = ARRAY_SIZE(palmas_pins_desc);
1026         pci->functions = palmas_pin_function;
1027         pci->num_functions = ARRAY_SIZE(palmas_pin_function);
1028         pci->pin_groups = pinctrl_data->pin_groups;
1029         pci->num_pin_groups = pinctrl_data->num_pin_groups;
1030
1031         platform_set_drvdata(pdev, pci);
1032
1033         palmas_pinctrl_set_dvfs1(pci, enable_dvfs1);
1034         palmas_pinctrl_set_dvfs2(pci, enable_dvfs2);
1035         ret = palmas_pinctrl_get_pin_mux(pci);
1036         if (ret < 0) {
1037                 dev_err(&pdev->dev,
1038                         "Reading pinctrol option register failed: %d\n", ret);
1039                 return ret;
1040         }
1041
1042         palmas_pinctrl_desc.name = dev_name(&pdev->dev);
1043         palmas_pinctrl_desc.pins = palmas_pins_desc;
1044         palmas_pinctrl_desc.npins = ARRAY_SIZE(palmas_pins_desc);
1045         pci->pctl = pinctrl_register(&palmas_pinctrl_desc, &pdev->dev, pci);
1046         if (!pci->pctl) {
1047                 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
1048                 return -ENODEV;
1049         }
1050         return 0;
1051 }
1052
1053 static int palmas_pinctrl_remove(struct platform_device *pdev)
1054 {
1055         struct palmas_pctrl_chip_info *pci = platform_get_drvdata(pdev);
1056
1057         pinctrl_unregister(pci->pctl);
1058         return 0;
1059 }
1060
1061 static struct platform_driver palmas_pinctrl_driver = {
1062         .driver = {
1063                 .name = "palmas-pinctrl",
1064                 .owner = THIS_MODULE,
1065                 .of_match_table = palmas_pinctrl_of_match,
1066         },
1067         .probe = palmas_pinctrl_probe,
1068         .remove = palmas_pinctrl_remove,
1069 };
1070
1071 module_platform_driver(palmas_pinctrl_driver);
1072
1073 MODULE_DESCRIPTION("Palmas pin control driver");
1074 MODULE_AUTHOR("Laxman Dewangan<ldewangan@nvidia.com>");
1075 MODULE_ALIAS("platform:palmas-pinctrl");
1076 MODULE_LICENSE("GPL v2");