2 * Pinctrl driver for Rockchip SoCs
4 * Copyright (c) 2013 MundoReader S.L.
5 * Author: Heiko Stuebner <heiko@sntech.de>
7 * With some ideas taken from pinctrl-samsung:
8 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
9 * http://www.samsung.com
10 * Copyright (c) 2012 Linaro Ltd
11 * http://www.linaro.org
14 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as published
18 * by the Free Software Foundation.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
26 #include <linux/init.h>
27 #include <linux/platform_device.h>
29 #include <linux/bitops.h>
30 #include <linux/gpio.h>
31 #include <linux/of_address.h>
32 #include <linux/of_irq.h>
33 #include <linux/pinctrl/machine.h>
34 #include <linux/pinctrl/pinconf.h>
35 #include <linux/pinctrl/pinctrl.h>
36 #include <linux/pinctrl/pinmux.h>
37 #include <linux/pinctrl/pinconf-generic.h>
38 #include <linux/irqchip/chained_irq.h>
39 #include <linux/clk.h>
40 #include <linux/regmap.h>
41 #include <linux/mfd/syscon.h>
42 #include <dt-bindings/pinctrl/rockchip.h>
47 /* GPIO control registers */
48 #define GPIO_SWPORT_DR 0x00
49 #define GPIO_SWPORT_DDR 0x04
50 #define GPIO_INTEN 0x30
51 #define GPIO_INTMASK 0x34
52 #define GPIO_INTTYPE_LEVEL 0x38
53 #define GPIO_INT_POLARITY 0x3c
54 #define GPIO_INT_STATUS 0x40
55 #define GPIO_INT_RAWSTATUS 0x44
56 #define GPIO_DEBOUNCE 0x48
57 #define GPIO_PORTS_EOI 0x4c
58 #define GPIO_EXT_PORT 0x50
59 #define GPIO_LS_SYNC 0x60
61 enum rockchip_pinctrl_type {
72 * Encode variants of iomux registers into a type variable
74 #define IOMUX_GPIO_ONLY BIT(0)
75 #define IOMUX_WIDTH_4BIT BIT(1)
76 #define IOMUX_SOURCE_PMU BIT(2)
77 #define IOMUX_UNROUTED BIT(3)
78 #define IOMUX_WIDTH_3BIT BIT(4)
79 #define IOMUX_RECALCED BIT(5)
82 * @type: iomux variant using IOMUX_* constants
83 * @offset: if initialized to -1 it will be autocalculated, by specifying
84 * an initial offset value the relevant source offset can be reset
85 * to a new value for autocalculating the following iomux registers.
87 struct rockchip_iomux {
93 * enum type index corresponding to rockchip_perpin_drv_list arrays index.
95 enum rockchip_pin_drv_type {
96 DRV_TYPE_IO_DEFAULT = 0,
97 DRV_TYPE_IO_1V8_OR_3V0,
99 DRV_TYPE_IO_1V8_3V0_AUTO,
100 DRV_TYPE_IO_3V3_ONLY,
105 * enum type index corresponding to rockchip_pull_list arrays index.
107 enum rockchip_pin_pull_type {
108 PULL_TYPE_IO_DEFAULT = 0,
109 PULL_TYPE_IO_1V8_ONLY,
114 * @drv_type: drive strength variant using rockchip_perpin_drv_type
115 * @offset: if initialized to -1 it will be autocalculated, by specifying
116 * an initial offset value the relevant source offset can be reset
117 * to a new value for autocalculating the following drive strength
118 * registers. if used chips own cal_drv func instead to calculate
119 * registers offset, the variant could be ignored.
121 struct rockchip_drv {
122 enum rockchip_pin_drv_type drv_type;
127 * @reg_base: register base of the gpio bank
128 * @reg_pull: optional separate register for additional pull settings
129 * @clk: clock of the gpio bank
130 * @irq: interrupt of the gpio bank
131 * @saved_masks: Saved content of GPIO_INTEN at suspend time.
132 * @pin_base: first pin number
133 * @nr_pins: number of pins in this bank
134 * @name: name of the bank
135 * @bank_num: number of the bank, to account for holes
136 * @iomux: array describing the 4 iomux sources of the bank
137 * @drv: array describing the 4 drive strength sources of the bank
138 * @pull_type: array describing the 4 pull type sources of the bank
139 * @valid: are all necessary informations present
140 * @of_node: dt node of this bank
141 * @drvdata: common pinctrl basedata
142 * @domain: irqdomain of the gpio bank
143 * @gpio_chip: gpiolib chip
144 * @grange: gpio range
145 * @slock: spinlock for the gpio bank
146 * @irq_lock: bus lock for irq chip
147 * @new_irqs: newly configured irqs which must be muxed as GPIOs in
148 * irq_bus_sync_unlock()
150 struct rockchip_pin_bank {
151 void __iomem *reg_base;
152 struct regmap *regmap_pull;
160 struct rockchip_iomux iomux[4];
161 struct rockchip_drv drv[4];
162 enum rockchip_pin_pull_type pull_type[4];
164 struct device_node *of_node;
165 struct rockchip_pinctrl *drvdata;
166 struct irq_domain *domain;
167 struct gpio_chip gpio_chip;
168 struct pinctrl_gpio_range grange;
169 raw_spinlock_t slock;
170 u32 toggle_edge_mode;
171 struct mutex irq_lock;
175 #define PIN_BANK(id, pins, label) \
188 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \
194 { .type = iom0, .offset = -1 }, \
195 { .type = iom1, .offset = -1 }, \
196 { .type = iom2, .offset = -1 }, \
197 { .type = iom3, .offset = -1 }, \
201 #define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \
213 { .drv_type = type0, .offset = -1 }, \
214 { .drv_type = type1, .offset = -1 }, \
215 { .drv_type = type2, .offset = -1 }, \
216 { .drv_type = type3, .offset = -1 }, \
220 #define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1, \
221 drv2, drv3, pull0, pull1, \
234 { .drv_type = drv0, .offset = -1 }, \
235 { .drv_type = drv1, .offset = -1 }, \
236 { .drv_type = drv2, .offset = -1 }, \
237 { .drv_type = drv3, .offset = -1 }, \
239 .pull_type[0] = pull0, \
240 .pull_type[1] = pull1, \
241 .pull_type[2] = pull2, \
242 .pull_type[3] = pull3, \
245 #define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1, \
246 iom2, iom3, drv0, drv1, drv2, \
247 drv3, offset0, offset1, \
254 { .type = iom0, .offset = -1 }, \
255 { .type = iom1, .offset = -1 }, \
256 { .type = iom2, .offset = -1 }, \
257 { .type = iom3, .offset = -1 }, \
260 { .drv_type = drv0, .offset = offset0 }, \
261 { .drv_type = drv1, .offset = offset1 }, \
262 { .drv_type = drv2, .offset = offset2 }, \
263 { .drv_type = drv3, .offset = offset3 }, \
267 #define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins, \
268 label, iom0, iom1, iom2, \
269 iom3, drv0, drv1, drv2, \
270 drv3, offset0, offset1, \
271 offset2, offset3, pull0, \
272 pull1, pull2, pull3) \
278 { .type = iom0, .offset = -1 }, \
279 { .type = iom1, .offset = -1 }, \
280 { .type = iom2, .offset = -1 }, \
281 { .type = iom3, .offset = -1 }, \
284 { .drv_type = drv0, .offset = offset0 }, \
285 { .drv_type = drv1, .offset = offset1 }, \
286 { .drv_type = drv2, .offset = offset2 }, \
287 { .drv_type = drv3, .offset = offset3 }, \
289 .pull_type[0] = pull0, \
290 .pull_type[1] = pull1, \
291 .pull_type[2] = pull2, \
292 .pull_type[3] = pull3, \
297 struct rockchip_pin_ctrl {
298 struct rockchip_pin_bank *pin_banks;
302 enum rockchip_pinctrl_type type;
308 void (*pull_calc_reg)(struct rockchip_pin_bank *bank,
309 int pin_num, struct regmap **regmap,
311 void (*drv_calc_reg)(struct rockchip_pin_bank *bank,
312 int pin_num, struct regmap **regmap,
314 void (*iomux_recalc)(u8 bank_num, int pin, int *reg,
316 int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank,
317 int pin_num, struct regmap **regmap,
321 struct rockchip_pin_config {
323 unsigned long *configs;
324 unsigned int nconfigs;
328 * struct rockchip_pin_group: represent group of pins of a pinmux function.
329 * @name: name of the pin group, used to lookup the group.
330 * @pins: the pins included in this group.
331 * @npins: number of pins included in this group.
332 * @func: the mux function number to be programmed when selected.
333 * @configs: the config values to be set for each pin
334 * @nconfigs: number of configs for each pin
336 struct rockchip_pin_group {
340 struct rockchip_pin_config *data;
344 * struct rockchip_pmx_func: represent a pin function.
345 * @name: name of the pin function, used to lookup the function.
346 * @groups: one or more names of pin groups that provide this function.
347 * @num_groups: number of groups included in @groups.
349 struct rockchip_pmx_func {
355 struct rockchip_pinctrl {
356 struct regmap *regmap_base;
358 struct regmap *regmap_pull;
359 struct regmap *regmap_pmu;
361 struct rockchip_pin_ctrl *ctrl;
362 struct pinctrl_desc pctl;
363 struct pinctrl_dev *pctl_dev;
364 struct rockchip_pin_group *groups;
365 unsigned int ngroups;
366 struct rockchip_pmx_func *functions;
367 unsigned int nfunctions;
371 * struct rockchip_mux_recalced_data: represent a pin iomux data.
374 * @bit: index at register.
375 * @reg: register offset.
378 struct rockchip_mux_recalced_data {
386 static struct regmap_config rockchip_regmap_config = {
392 static inline const struct rockchip_pin_group *pinctrl_name_to_group(
393 const struct rockchip_pinctrl *info,
398 for (i = 0; i < info->ngroups; i++) {
399 if (!strcmp(info->groups[i].name, name))
400 return &info->groups[i];
407 * given a pin number that is local to a pin controller, find out the pin bank
408 * and the register base of the pin bank.
410 static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info,
413 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
415 while (pin >= (b->pin_base + b->nr_pins))
421 static struct rockchip_pin_bank *bank_num_to_bank(
422 struct rockchip_pinctrl *info,
425 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
428 for (i = 0; i < info->ctrl->nr_banks; i++, b++) {
429 if (b->bank_num == num)
433 return ERR_PTR(-EINVAL);
437 * Pinctrl_ops handling
440 static int rockchip_get_groups_count(struct pinctrl_dev *pctldev)
442 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
444 return info->ngroups;
447 static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev,
450 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
452 return info->groups[selector].name;
455 static int rockchip_get_group_pins(struct pinctrl_dev *pctldev,
456 unsigned selector, const unsigned **pins,
459 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
461 if (selector >= info->ngroups)
464 *pins = info->groups[selector].pins;
465 *npins = info->groups[selector].npins;
470 static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev,
471 struct device_node *np,
472 struct pinctrl_map **map, unsigned *num_maps)
474 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
475 const struct rockchip_pin_group *grp;
476 struct pinctrl_map *new_map;
477 struct device_node *parent;
482 * first find the group of this node and check if we need to create
483 * config maps for pins
485 grp = pinctrl_name_to_group(info, np->name);
487 dev_err(info->dev, "unable to find group for node %s\n",
492 map_num += grp->npins;
493 new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num,
502 parent = of_get_parent(np);
504 devm_kfree(pctldev->dev, new_map);
507 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
508 new_map[0].data.mux.function = parent->name;
509 new_map[0].data.mux.group = np->name;
512 /* create config map */
514 for (i = 0; i < grp->npins; i++) {
515 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
516 new_map[i].data.configs.group_or_pin =
517 pin_get_name(pctldev, grp->pins[i]);
518 new_map[i].data.configs.configs = grp->data[i].configs;
519 new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
522 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
523 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
528 static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
529 struct pinctrl_map *map, unsigned num_maps)
533 static const struct pinctrl_ops rockchip_pctrl_ops = {
534 .get_groups_count = rockchip_get_groups_count,
535 .get_group_name = rockchip_get_group_name,
536 .get_group_pins = rockchip_get_group_pins,
537 .dt_node_to_map = rockchip_dt_node_to_map,
538 .dt_free_map = rockchip_dt_free_map,
545 static const struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = {
567 static void rk3328_recalc_mux(u8 bank_num, int pin, int *reg,
570 const struct rockchip_mux_recalced_data *data = NULL;
573 for (i = 0; i < ARRAY_SIZE(rk3328_mux_recalced_data); i++)
574 if (rk3328_mux_recalced_data[i].num == bank_num &&
575 rk3328_mux_recalced_data[i].pin == pin) {
576 data = &rk3328_mux_recalced_data[i];
588 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
590 struct rockchip_pinctrl *info = bank->drvdata;
591 struct rockchip_pin_ctrl *ctrl = info->ctrl;
592 int iomux_num = (pin / 8);
593 struct regmap *regmap;
595 int reg, ret, mask, mux_type;
601 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
602 dev_err(info->dev, "pin %d is unrouted\n", pin);
606 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
609 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
610 ? info->regmap_pmu : info->regmap_base;
612 /* get basic quadrupel of mux registers and the correct reg inside */
613 mux_type = bank->iomux[iomux_num].type;
614 reg = bank->iomux[iomux_num].offset;
615 if (mux_type & IOMUX_WIDTH_4BIT) {
620 } else if (mux_type & IOMUX_WIDTH_3BIT) {
623 bit = (pin % 8 % 5) * 3;
630 if (ctrl->iomux_recalc && (mux_type & IOMUX_RECALCED))
631 ctrl->iomux_recalc(bank->bank_num, pin, ®, &bit, &mask);
633 ret = regmap_read(regmap, reg, &val);
637 return ((val >> bit) & mask);
640 static int rockchip_verify_mux(struct rockchip_pin_bank *bank,
643 struct rockchip_pinctrl *info = bank->drvdata;
644 int iomux_num = (pin / 8);
649 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
650 dev_err(info->dev, "pin %d is unrouted\n", pin);
654 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
655 if (mux != RK_FUNC_GPIO) {
657 "pin %d only supports a gpio mux\n", pin);
666 * Set a new mux function for a pin.
668 * The register is divided into the upper and lower 16 bit. When changing
669 * a value, the previous register value is not read and changed. Instead
670 * it seems the changed bits are marked in the upper 16 bit, while the
671 * changed value gets set in the same offset in the lower 16 bit.
672 * All pin settings seem to be 2 bit wide in both the upper and lower
674 * @bank: pin bank to change
675 * @pin: pin to change
676 * @mux: new mux function to set
678 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
680 struct rockchip_pinctrl *info = bank->drvdata;
681 struct rockchip_pin_ctrl *ctrl = info->ctrl;
682 int iomux_num = (pin / 8);
683 struct regmap *regmap;
684 int reg, ret, mask, mux_type;
688 ret = rockchip_verify_mux(bank, pin, mux);
692 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
695 dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n",
696 bank->bank_num, pin, mux);
698 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
699 ? info->regmap_pmu : info->regmap_base;
701 /* get basic quadrupel of mux registers and the correct reg inside */
702 mux_type = bank->iomux[iomux_num].type;
703 reg = bank->iomux[iomux_num].offset;
704 if (mux_type & IOMUX_WIDTH_4BIT) {
709 } else if (mux_type & IOMUX_WIDTH_3BIT) {
712 bit = (pin % 8 % 5) * 3;
719 if (ctrl->iomux_recalc && (mux_type & IOMUX_RECALCED))
720 ctrl->iomux_recalc(bank->bank_num, pin, ®, &bit, &mask);
722 data = (mask << (bit + 16));
723 rmask = data | (data >> 16);
724 data |= (mux & mask) << bit;
725 ret = regmap_update_bits(regmap, reg, rmask, data);
730 #define RV1108_PULL_PMU_OFFSET 0x10
731 #define RV1108_PULL_OFFSET 0x110
732 #define RV1108_PULL_PINS_PER_REG 8
733 #define RV1108_PULL_BITS_PER_PIN 2
734 #define RV1108_PULL_BANK_STRIDE 16
736 static void rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
737 int pin_num, struct regmap **regmap,
740 struct rockchip_pinctrl *info = bank->drvdata;
742 /* The first 24 pins of the first bank are located in PMU */
743 if (bank->bank_num == 0) {
744 *regmap = info->regmap_pmu;
745 *reg = RV1108_PULL_PMU_OFFSET;
747 *reg = RV1108_PULL_OFFSET;
748 *regmap = info->regmap_base;
749 /* correct the offset, as we're starting with the 2nd bank */
751 *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE;
754 *reg += ((pin_num / RV1108_PULL_PINS_PER_REG) * 4);
755 *bit = (pin_num % RV1108_PULL_PINS_PER_REG);
756 *bit *= RV1108_PULL_BITS_PER_PIN;
759 #define RV1108_DRV_PMU_OFFSET 0x20
760 #define RV1108_DRV_GRF_OFFSET 0x210
761 #define RV1108_DRV_BITS_PER_PIN 2
762 #define RV1108_DRV_PINS_PER_REG 8
763 #define RV1108_DRV_BANK_STRIDE 16
765 static void rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
766 int pin_num, struct regmap **regmap,
769 struct rockchip_pinctrl *info = bank->drvdata;
771 /* The first 24 pins of the first bank are located in PMU */
772 if (bank->bank_num == 0) {
773 *regmap = info->regmap_pmu;
774 *reg = RV1108_DRV_PMU_OFFSET;
776 *regmap = info->regmap_base;
777 *reg = RV1108_DRV_GRF_OFFSET;
779 /* correct the offset, as we're starting with the 2nd bank */
781 *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE;
784 *reg += ((pin_num / RV1108_DRV_PINS_PER_REG) * 4);
785 *bit = pin_num % RV1108_DRV_PINS_PER_REG;
786 *bit *= RV1108_DRV_BITS_PER_PIN;
789 #define RK2928_PULL_OFFSET 0x118
790 #define RK2928_PULL_PINS_PER_REG 16
791 #define RK2928_PULL_BANK_STRIDE 8
793 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
794 int pin_num, struct regmap **regmap,
797 struct rockchip_pinctrl *info = bank->drvdata;
799 *regmap = info->regmap_base;
800 *reg = RK2928_PULL_OFFSET;
801 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
802 *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4;
804 *bit = pin_num % RK2928_PULL_PINS_PER_REG;
807 #define RK3188_PULL_OFFSET 0x164
808 #define RK3188_PULL_BITS_PER_PIN 2
809 #define RK3188_PULL_PINS_PER_REG 8
810 #define RK3188_PULL_BANK_STRIDE 16
811 #define RK3188_PULL_PMU_OFFSET 0x64
813 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
814 int pin_num, struct regmap **regmap,
817 struct rockchip_pinctrl *info = bank->drvdata;
819 /* The first 12 pins of the first bank are located elsewhere */
820 if (bank->bank_num == 0 && pin_num < 12) {
821 *regmap = info->regmap_pmu ? info->regmap_pmu
823 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0;
824 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
825 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
826 *bit *= RK3188_PULL_BITS_PER_PIN;
828 *regmap = info->regmap_pull ? info->regmap_pull
830 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET;
832 /* correct the offset, as it is the 2nd pull register */
834 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
835 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
838 * The bits in these registers have an inverse ordering
839 * with the lowest pin being in bits 15:14 and the highest
842 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG);
843 *bit *= RK3188_PULL_BITS_PER_PIN;
847 #define RK3288_PULL_OFFSET 0x140
848 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
849 int pin_num, struct regmap **regmap,
852 struct rockchip_pinctrl *info = bank->drvdata;
854 /* The first 24 pins of the first bank are located in PMU */
855 if (bank->bank_num == 0) {
856 *regmap = info->regmap_pmu;
857 *reg = RK3188_PULL_PMU_OFFSET;
859 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
860 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
861 *bit *= RK3188_PULL_BITS_PER_PIN;
863 *regmap = info->regmap_base;
864 *reg = RK3288_PULL_OFFSET;
866 /* correct the offset, as we're starting with the 2nd bank */
868 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
869 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
871 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
872 *bit *= RK3188_PULL_BITS_PER_PIN;
876 #define RK3288_DRV_PMU_OFFSET 0x70
877 #define RK3288_DRV_GRF_OFFSET 0x1c0
878 #define RK3288_DRV_BITS_PER_PIN 2
879 #define RK3288_DRV_PINS_PER_REG 8
880 #define RK3288_DRV_BANK_STRIDE 16
882 static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
883 int pin_num, struct regmap **regmap,
886 struct rockchip_pinctrl *info = bank->drvdata;
888 /* The first 24 pins of the first bank are located in PMU */
889 if (bank->bank_num == 0) {
890 *regmap = info->regmap_pmu;
891 *reg = RK3288_DRV_PMU_OFFSET;
893 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
894 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
895 *bit *= RK3288_DRV_BITS_PER_PIN;
897 *regmap = info->regmap_base;
898 *reg = RK3288_DRV_GRF_OFFSET;
900 /* correct the offset, as we're starting with the 2nd bank */
902 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
903 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
905 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
906 *bit *= RK3288_DRV_BITS_PER_PIN;
910 #define RK3228_PULL_OFFSET 0x100
912 static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
913 int pin_num, struct regmap **regmap,
916 struct rockchip_pinctrl *info = bank->drvdata;
918 *regmap = info->regmap_base;
919 *reg = RK3228_PULL_OFFSET;
920 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
921 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
923 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
924 *bit *= RK3188_PULL_BITS_PER_PIN;
927 #define RK3228_DRV_GRF_OFFSET 0x200
929 static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
930 int pin_num, struct regmap **regmap,
933 struct rockchip_pinctrl *info = bank->drvdata;
935 *regmap = info->regmap_base;
936 *reg = RK3228_DRV_GRF_OFFSET;
937 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
938 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
940 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
941 *bit *= RK3288_DRV_BITS_PER_PIN;
944 #define RK3368_PULL_GRF_OFFSET 0x100
945 #define RK3368_PULL_PMU_OFFSET 0x10
947 static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
948 int pin_num, struct regmap **regmap,
951 struct rockchip_pinctrl *info = bank->drvdata;
953 /* The first 32 pins of the first bank are located in PMU */
954 if (bank->bank_num == 0) {
955 *regmap = info->regmap_pmu;
956 *reg = RK3368_PULL_PMU_OFFSET;
958 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
959 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
960 *bit *= RK3188_PULL_BITS_PER_PIN;
962 *regmap = info->regmap_base;
963 *reg = RK3368_PULL_GRF_OFFSET;
965 /* correct the offset, as we're starting with the 2nd bank */
967 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
968 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
970 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
971 *bit *= RK3188_PULL_BITS_PER_PIN;
975 #define RK3368_DRV_PMU_OFFSET 0x20
976 #define RK3368_DRV_GRF_OFFSET 0x200
978 static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
979 int pin_num, struct regmap **regmap,
982 struct rockchip_pinctrl *info = bank->drvdata;
984 /* The first 32 pins of the first bank are located in PMU */
985 if (bank->bank_num == 0) {
986 *regmap = info->regmap_pmu;
987 *reg = RK3368_DRV_PMU_OFFSET;
989 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
990 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
991 *bit *= RK3288_DRV_BITS_PER_PIN;
993 *regmap = info->regmap_base;
994 *reg = RK3368_DRV_GRF_OFFSET;
996 /* correct the offset, as we're starting with the 2nd bank */
998 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
999 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1001 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1002 *bit *= RK3288_DRV_BITS_PER_PIN;
1006 #define RK3399_PULL_GRF_OFFSET 0xe040
1007 #define RK3399_PULL_PMU_OFFSET 0x40
1008 #define RK3399_DRV_3BITS_PER_PIN 3
1010 static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1011 int pin_num, struct regmap **regmap,
1014 struct rockchip_pinctrl *info = bank->drvdata;
1016 /* The bank0:16 and bank1:32 pins are located in PMU */
1017 if ((bank->bank_num == 0) || (bank->bank_num == 1)) {
1018 *regmap = info->regmap_pmu;
1019 *reg = RK3399_PULL_PMU_OFFSET;
1021 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1023 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1024 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1025 *bit *= RK3188_PULL_BITS_PER_PIN;
1027 *regmap = info->regmap_base;
1028 *reg = RK3399_PULL_GRF_OFFSET;
1030 /* correct the offset, as we're starting with the 3rd bank */
1032 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1033 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1035 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1036 *bit *= RK3188_PULL_BITS_PER_PIN;
1040 static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1041 int pin_num, struct regmap **regmap,
1044 struct rockchip_pinctrl *info = bank->drvdata;
1045 int drv_num = (pin_num / 8);
1047 /* The bank0:16 and bank1:32 pins are located in PMU */
1048 if ((bank->bank_num == 0) || (bank->bank_num == 1))
1049 *regmap = info->regmap_pmu;
1051 *regmap = info->regmap_base;
1053 *reg = bank->drv[drv_num].offset;
1054 if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
1055 (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY))
1056 *bit = (pin_num % 8) * 3;
1058 *bit = (pin_num % 8) * 2;
1061 static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = {
1062 { 2, 4, 8, 12, -1, -1, -1, -1 },
1063 { 3, 6, 9, 12, -1, -1, -1, -1 },
1064 { 5, 10, 15, 20, -1, -1, -1, -1 },
1065 { 4, 6, 8, 10, 12, 14, 16, 18 },
1066 { 4, 7, 10, 13, 16, 19, 22, 26 }
1069 static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank,
1072 struct rockchip_pinctrl *info = bank->drvdata;
1073 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1074 struct regmap *regmap;
1076 u32 data, temp, rmask_bits;
1078 int drv_type = bank->drv[pin_num / 8].drv_type;
1080 ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit);
1083 case DRV_TYPE_IO_1V8_3V0_AUTO:
1084 case DRV_TYPE_IO_3V3_ONLY:
1085 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
1088 /* regular case, nothing to do */
1092 * drive-strength offset is special, as it is
1093 * spread over 2 registers
1095 ret = regmap_read(regmap, reg, &data);
1099 ret = regmap_read(regmap, reg + 0x4, &temp);
1104 * the bit data[15] contains bit 0 of the value
1105 * while temp[1:0] contains bits 2 and 1
1112 return rockchip_perpin_drv_list[drv_type][data];
1114 /* setting fully enclosed in the second register */
1119 dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n",
1125 case DRV_TYPE_IO_DEFAULT:
1126 case DRV_TYPE_IO_1V8_OR_3V0:
1127 case DRV_TYPE_IO_1V8_ONLY:
1128 rmask_bits = RK3288_DRV_BITS_PER_PIN;
1131 dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
1136 ret = regmap_read(regmap, reg, &data);
1141 data &= (1 << rmask_bits) - 1;
1143 return rockchip_perpin_drv_list[drv_type][data];
1146 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
1147 int pin_num, int strength)
1149 struct rockchip_pinctrl *info = bank->drvdata;
1150 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1151 struct regmap *regmap;
1153 u32 data, rmask, rmask_bits, temp;
1155 int drv_type = bank->drv[pin_num / 8].drv_type;
1157 dev_dbg(info->dev, "setting drive of GPIO%d-%d to %d\n",
1158 bank->bank_num, pin_num, strength);
1160 ctrl->drv_calc_reg(bank, pin_num, ®map, ®, &bit);
1163 for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) {
1164 if (rockchip_perpin_drv_list[drv_type][i] == strength) {
1167 } else if (rockchip_perpin_drv_list[drv_type][i] < 0) {
1168 ret = rockchip_perpin_drv_list[drv_type][i];
1174 dev_err(info->dev, "unsupported driver strength %d\n",
1180 case DRV_TYPE_IO_1V8_3V0_AUTO:
1181 case DRV_TYPE_IO_3V3_ONLY:
1182 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
1185 /* regular case, nothing to do */
1189 * drive-strength offset is special, as it is spread
1190 * over 2 registers, the bit data[15] contains bit 0
1191 * of the value while temp[1:0] contains bits 2 and 1
1193 data = (ret & 0x1) << 15;
1194 temp = (ret >> 0x1) & 0x3;
1196 rmask = BIT(15) | BIT(31);
1198 ret = regmap_update_bits(regmap, reg, rmask, data);
1202 rmask = 0x3 | (0x3 << 16);
1203 temp |= (0x3 << 16);
1205 ret = regmap_update_bits(regmap, reg, rmask, temp);
1209 /* setting fully enclosed in the second register */
1214 dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n",
1219 case DRV_TYPE_IO_DEFAULT:
1220 case DRV_TYPE_IO_1V8_OR_3V0:
1221 case DRV_TYPE_IO_1V8_ONLY:
1222 rmask_bits = RK3288_DRV_BITS_PER_PIN;
1225 dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
1230 /* enable the write to the equivalent lower bits */
1231 data = ((1 << rmask_bits) - 1) << (bit + 16);
1232 rmask = data | (data >> 16);
1233 data |= (ret << bit);
1235 ret = regmap_update_bits(regmap, reg, rmask, data);
1240 static int rockchip_pull_list[PULL_TYPE_MAX][4] = {
1242 PIN_CONFIG_BIAS_DISABLE,
1243 PIN_CONFIG_BIAS_PULL_UP,
1244 PIN_CONFIG_BIAS_PULL_DOWN,
1245 PIN_CONFIG_BIAS_BUS_HOLD
1248 PIN_CONFIG_BIAS_DISABLE,
1249 PIN_CONFIG_BIAS_PULL_DOWN,
1250 PIN_CONFIG_BIAS_DISABLE,
1251 PIN_CONFIG_BIAS_PULL_UP
1255 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
1257 struct rockchip_pinctrl *info = bank->drvdata;
1258 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1259 struct regmap *regmap;
1260 int reg, ret, pull_type;
1264 /* rk3066b does support any pulls */
1265 if (ctrl->type == RK3066B)
1266 return PIN_CONFIG_BIAS_DISABLE;
1268 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit);
1270 ret = regmap_read(regmap, reg, &data);
1274 switch (ctrl->type) {
1276 return !(data & BIT(bit))
1277 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
1278 : PIN_CONFIG_BIAS_DISABLE;
1284 pull_type = bank->pull_type[pin_num / 8];
1286 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
1288 return rockchip_pull_list[pull_type][data];
1290 dev_err(info->dev, "unsupported pinctrl type\n");
1295 static int rockchip_set_pull(struct rockchip_pin_bank *bank,
1296 int pin_num, int pull)
1298 struct rockchip_pinctrl *info = bank->drvdata;
1299 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1300 struct regmap *regmap;
1301 int reg, ret, i, pull_type;
1305 dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n",
1306 bank->bank_num, pin_num, pull);
1308 /* rk3066b does support any pulls */
1309 if (ctrl->type == RK3066B)
1310 return pull ? -EINVAL : 0;
1312 ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit);
1314 switch (ctrl->type) {
1316 data = BIT(bit + 16);
1317 if (pull == PIN_CONFIG_BIAS_DISABLE)
1319 ret = regmap_write(regmap, reg, data);
1326 pull_type = bank->pull_type[pin_num / 8];
1328 for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]);
1330 if (rockchip_pull_list[pull_type][i] == pull) {
1337 dev_err(info->dev, "unsupported pull setting %d\n",
1342 /* enable the write to the equivalent lower bits */
1343 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
1344 rmask = data | (data >> 16);
1345 data |= (ret << bit);
1347 ret = regmap_update_bits(regmap, reg, rmask, data);
1350 dev_err(info->dev, "unsupported pinctrl type\n");
1357 #define RK3328_SCHMITT_BITS_PER_PIN 1
1358 #define RK3328_SCHMITT_PINS_PER_REG 16
1359 #define RK3328_SCHMITT_BANK_STRIDE 8
1360 #define RK3328_SCHMITT_GRF_OFFSET 0x380
1362 static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1364 struct regmap **regmap,
1367 struct rockchip_pinctrl *info = bank->drvdata;
1369 *regmap = info->regmap_base;
1370 *reg = RK3328_SCHMITT_GRF_OFFSET;
1372 *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE;
1373 *reg += ((pin_num / RK3328_SCHMITT_PINS_PER_REG) * 4);
1374 *bit = pin_num % RK3328_SCHMITT_PINS_PER_REG;
1379 static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num)
1381 struct rockchip_pinctrl *info = bank->drvdata;
1382 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1383 struct regmap *regmap;
1388 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit);
1392 ret = regmap_read(regmap, reg, &data);
1400 static int rockchip_set_schmitt(struct rockchip_pin_bank *bank,
1401 int pin_num, int enable)
1403 struct rockchip_pinctrl *info = bank->drvdata;
1404 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1405 struct regmap *regmap;
1410 dev_dbg(info->dev, "setting input schmitt of GPIO%d-%d to %d\n",
1411 bank->bank_num, pin_num, enable);
1413 ret = ctrl->schmitt_calc_reg(bank, pin_num, ®map, ®, &bit);
1417 /* enable the write to the equivalent lower bits */
1418 data = BIT(bit + 16) | (enable << bit);
1419 rmask = BIT(bit + 16) | BIT(bit);
1421 return regmap_update_bits(regmap, reg, rmask, data);
1425 * Pinmux_ops handling
1428 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
1430 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1432 return info->nfunctions;
1435 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev,
1438 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1440 return info->functions[selector].name;
1443 static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
1444 unsigned selector, const char * const **groups,
1445 unsigned * const num_groups)
1447 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1449 *groups = info->functions[selector].groups;
1450 *num_groups = info->functions[selector].ngroups;
1455 static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
1458 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1459 const unsigned int *pins = info->groups[group].pins;
1460 const struct rockchip_pin_config *data = info->groups[group].data;
1461 struct rockchip_pin_bank *bank;
1464 dev_dbg(info->dev, "enable function %s group %s\n",
1465 info->functions[selector].name, info->groups[group].name);
1468 * for each pin in the pin group selected, program the correspoding pin
1469 * pin function number in the config register.
1471 for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
1472 bank = pin_to_bank(info, pins[cnt]);
1473 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
1480 /* revert the already done pin settings */
1481 for (cnt--; cnt >= 0; cnt--)
1482 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
1490 static int rockchip_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
1492 struct rockchip_pin_bank *bank = gpiochip_get_data(chip);
1495 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
1497 return !(data & BIT(offset));
1501 * The calls to gpio_direction_output() and gpio_direction_input()
1502 * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
1503 * function called from the gpiolib interface).
1505 static int _rockchip_pmx_gpio_set_direction(struct gpio_chip *chip,
1506 int pin, bool input)
1508 struct rockchip_pin_bank *bank;
1510 unsigned long flags;
1513 bank = gpiochip_get_data(chip);
1515 ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO);
1519 clk_enable(bank->clk);
1520 raw_spin_lock_irqsave(&bank->slock, flags);
1522 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
1523 /* set bit to 1 for output, 0 for input */
1528 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
1530 raw_spin_unlock_irqrestore(&bank->slock, flags);
1531 clk_disable(bank->clk);
1536 static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
1537 struct pinctrl_gpio_range *range,
1538 unsigned offset, bool input)
1540 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1541 struct gpio_chip *chip;
1545 pin = offset - chip->base;
1546 dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
1547 offset, range->name, pin, input ? "input" : "output");
1549 return _rockchip_pmx_gpio_set_direction(chip, offset - chip->base,
1553 static const struct pinmux_ops rockchip_pmx_ops = {
1554 .get_functions_count = rockchip_pmx_get_funcs_count,
1555 .get_function_name = rockchip_pmx_get_func_name,
1556 .get_function_groups = rockchip_pmx_get_groups,
1557 .set_mux = rockchip_pmx_set,
1558 .gpio_set_direction = rockchip_pmx_gpio_set_direction,
1562 * Pinconf_ops handling
1565 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
1566 enum pin_config_param pull)
1568 switch (ctrl->type) {
1570 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
1571 pull == PIN_CONFIG_BIAS_DISABLE);
1573 return pull ? false : true;
1579 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
1585 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value);
1586 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset);
1588 /* set the pin config settings for a specified pin */
1589 static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
1590 unsigned long *configs, unsigned num_configs)
1592 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1593 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
1594 enum pin_config_param param;
1599 for (i = 0; i < num_configs; i++) {
1600 param = pinconf_to_config_param(configs[i]);
1601 arg = pinconf_to_config_argument(configs[i]);
1604 case PIN_CONFIG_BIAS_DISABLE:
1605 rc = rockchip_set_pull(bank, pin - bank->pin_base,
1610 case PIN_CONFIG_BIAS_PULL_UP:
1611 case PIN_CONFIG_BIAS_PULL_DOWN:
1612 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
1613 case PIN_CONFIG_BIAS_BUS_HOLD:
1614 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
1620 rc = rockchip_set_pull(bank, pin - bank->pin_base,
1625 case PIN_CONFIG_OUTPUT:
1626 rockchip_gpio_set(&bank->gpio_chip,
1627 pin - bank->pin_base, arg);
1628 rc = _rockchip_pmx_gpio_set_direction(&bank->gpio_chip,
1629 pin - bank->pin_base, false);
1633 case PIN_CONFIG_DRIVE_STRENGTH:
1634 /* rk3288 is the first with per-pin drive-strength */
1635 if (!info->ctrl->drv_calc_reg)
1638 rc = rockchip_set_drive_perpin(bank,
1639 pin - bank->pin_base, arg);
1643 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
1644 if (!info->ctrl->schmitt_calc_reg)
1647 rc = rockchip_set_schmitt(bank,
1648 pin - bank->pin_base, arg);
1656 } /* for each config */
1661 /* get the pin config settings for a specified pin */
1662 static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
1663 unsigned long *config)
1665 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1666 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
1667 enum pin_config_param param = pinconf_to_config_param(*config);
1672 case PIN_CONFIG_BIAS_DISABLE:
1673 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
1678 case PIN_CONFIG_BIAS_PULL_UP:
1679 case PIN_CONFIG_BIAS_PULL_DOWN:
1680 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
1681 case PIN_CONFIG_BIAS_BUS_HOLD:
1682 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
1685 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
1690 case PIN_CONFIG_OUTPUT:
1691 rc = rockchip_get_mux(bank, pin - bank->pin_base);
1692 if (rc != RK_FUNC_GPIO)
1695 rc = rockchip_gpio_get(&bank->gpio_chip, pin - bank->pin_base);
1701 case PIN_CONFIG_DRIVE_STRENGTH:
1702 /* rk3288 is the first with per-pin drive-strength */
1703 if (!info->ctrl->drv_calc_reg)
1706 rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base);
1712 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
1713 if (!info->ctrl->schmitt_calc_reg)
1716 rc = rockchip_get_schmitt(bank, pin - bank->pin_base);
1727 *config = pinconf_to_config_packed(param, arg);
1732 static const struct pinconf_ops rockchip_pinconf_ops = {
1733 .pin_config_get = rockchip_pinconf_get,
1734 .pin_config_set = rockchip_pinconf_set,
1738 static const struct of_device_id rockchip_bank_match[] = {
1739 { .compatible = "rockchip,gpio-bank" },
1740 { .compatible = "rockchip,rk3188-gpio-bank0" },
1744 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
1745 struct device_node *np)
1747 struct device_node *child;
1749 for_each_child_of_node(np, child) {
1750 if (of_match_node(rockchip_bank_match, child))
1754 info->ngroups += of_get_child_count(child);
1758 static int rockchip_pinctrl_parse_groups(struct device_node *np,
1759 struct rockchip_pin_group *grp,
1760 struct rockchip_pinctrl *info,
1763 struct rockchip_pin_bank *bank;
1770 dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
1772 /* Initialise group */
1773 grp->name = np->name;
1776 * the binding format is rockchip,pins = <bank pin mux CONFIG>,
1777 * do sanity check and calculate pins number
1779 list = of_get_property(np, "rockchip,pins", &size);
1780 /* we do not check return since it's safe node passed down */
1781 size /= sizeof(*list);
1782 if (!size || size % 4) {
1783 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
1787 grp->npins = size / 4;
1789 grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
1791 grp->data = devm_kzalloc(info->dev, grp->npins *
1792 sizeof(struct rockchip_pin_config),
1794 if (!grp->pins || !grp->data)
1797 for (i = 0, j = 0; i < size; i += 4, j++) {
1798 const __be32 *phandle;
1799 struct device_node *np_config;
1801 num = be32_to_cpu(*list++);
1802 bank = bank_num_to_bank(info, num);
1804 return PTR_ERR(bank);
1806 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++);
1807 grp->data[j].func = be32_to_cpu(*list++);
1813 np_config = of_find_node_by_phandle(be32_to_cpup(phandle));
1814 ret = pinconf_generic_parse_dt_config(np_config, NULL,
1815 &grp->data[j].configs, &grp->data[j].nconfigs);
1823 static int rockchip_pinctrl_parse_functions(struct device_node *np,
1824 struct rockchip_pinctrl *info,
1827 struct device_node *child;
1828 struct rockchip_pmx_func *func;
1829 struct rockchip_pin_group *grp;
1831 static u32 grp_index;
1834 dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
1836 func = &info->functions[index];
1838 /* Initialise function */
1839 func->name = np->name;
1840 func->ngroups = of_get_child_count(np);
1841 if (func->ngroups <= 0)
1844 func->groups = devm_kzalloc(info->dev,
1845 func->ngroups * sizeof(char *), GFP_KERNEL);
1849 for_each_child_of_node(np, child) {
1850 func->groups[i] = child->name;
1851 grp = &info->groups[grp_index++];
1852 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++);
1862 static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
1863 struct rockchip_pinctrl *info)
1865 struct device *dev = &pdev->dev;
1866 struct device_node *np = dev->of_node;
1867 struct device_node *child;
1871 rockchip_pinctrl_child_count(info, np);
1873 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
1874 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
1876 info->functions = devm_kzalloc(dev, info->nfunctions *
1877 sizeof(struct rockchip_pmx_func),
1879 if (!info->functions) {
1880 dev_err(dev, "failed to allocate memory for function list\n");
1884 info->groups = devm_kzalloc(dev, info->ngroups *
1885 sizeof(struct rockchip_pin_group),
1887 if (!info->groups) {
1888 dev_err(dev, "failed allocate memory for ping group list\n");
1894 for_each_child_of_node(np, child) {
1895 if (of_match_node(rockchip_bank_match, child))
1898 ret = rockchip_pinctrl_parse_functions(child, info, i++);
1900 dev_err(&pdev->dev, "failed to parse function\n");
1909 static int rockchip_pinctrl_register(struct platform_device *pdev,
1910 struct rockchip_pinctrl *info)
1912 struct pinctrl_desc *ctrldesc = &info->pctl;
1913 struct pinctrl_pin_desc *pindesc, *pdesc;
1914 struct rockchip_pin_bank *pin_bank;
1918 ctrldesc->name = "rockchip-pinctrl";
1919 ctrldesc->owner = THIS_MODULE;
1920 ctrldesc->pctlops = &rockchip_pctrl_ops;
1921 ctrldesc->pmxops = &rockchip_pmx_ops;
1922 ctrldesc->confops = &rockchip_pinconf_ops;
1924 pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) *
1925 info->ctrl->nr_pins, GFP_KERNEL);
1927 dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n");
1930 ctrldesc->pins = pindesc;
1931 ctrldesc->npins = info->ctrl->nr_pins;
1934 for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) {
1935 pin_bank = &info->ctrl->pin_banks[bank];
1936 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
1938 pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
1939 pin_bank->name, pin);
1944 ret = rockchip_pinctrl_parse_dt(pdev, info);
1948 info->pctl_dev = devm_pinctrl_register(&pdev->dev, ctrldesc, info);
1949 if (IS_ERR(info->pctl_dev)) {
1950 dev_err(&pdev->dev, "could not register pinctrl driver\n");
1951 return PTR_ERR(info->pctl_dev);
1954 for (bank = 0; bank < info->ctrl->nr_banks; ++bank) {
1955 pin_bank = &info->ctrl->pin_banks[bank];
1956 pin_bank->grange.name = pin_bank->name;
1957 pin_bank->grange.id = bank;
1958 pin_bank->grange.pin_base = pin_bank->pin_base;
1959 pin_bank->grange.base = pin_bank->gpio_chip.base;
1960 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio;
1961 pin_bank->grange.gc = &pin_bank->gpio_chip;
1962 pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange);
1972 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
1974 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
1975 void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR;
1976 unsigned long flags;
1979 clk_enable(bank->clk);
1980 raw_spin_lock_irqsave(&bank->slock, flags);
1983 data &= ~BIT(offset);
1985 data |= BIT(offset);
1988 raw_spin_unlock_irqrestore(&bank->slock, flags);
1989 clk_disable(bank->clk);
1993 * Returns the level of the pin for input direction and setting of the DR
1994 * register for output gpios.
1996 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset)
1998 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
2001 clk_enable(bank->clk);
2002 data = readl(bank->reg_base + GPIO_EXT_PORT);
2003 clk_disable(bank->clk);
2010 * gpiolib gpio_direction_input callback function. The setting of the pin
2011 * mux function as 'gpio input' will be handled by the pinctrl susbsystem
2014 static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
2016 return pinctrl_gpio_direction_input(gc->base + offset);
2020 * gpiolib gpio_direction_output callback function. The setting of the pin
2021 * mux function as 'gpio output' will be handled by the pinctrl susbsystem
2024 static int rockchip_gpio_direction_output(struct gpio_chip *gc,
2025 unsigned offset, int value)
2027 rockchip_gpio_set(gc, offset, value);
2028 return pinctrl_gpio_direction_output(gc->base + offset);
2032 * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
2033 * and a virtual IRQ, if not already present.
2035 static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
2037 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
2043 virq = irq_create_mapping(bank->domain, offset);
2045 return (virq) ? : -ENXIO;
2048 static const struct gpio_chip rockchip_gpiolib_chip = {
2049 .request = gpiochip_generic_request,
2050 .free = gpiochip_generic_free,
2051 .set = rockchip_gpio_set,
2052 .get = rockchip_gpio_get,
2053 .get_direction = rockchip_gpio_get_direction,
2054 .direction_input = rockchip_gpio_direction_input,
2055 .direction_output = rockchip_gpio_direction_output,
2056 .to_irq = rockchip_gpio_to_irq,
2057 .owner = THIS_MODULE,
2061 * Interrupt handling
2064 static void rockchip_irq_demux(struct irq_desc *desc)
2066 struct irq_chip *chip = irq_desc_get_chip(desc);
2067 struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc);
2070 dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name);
2072 chained_irq_enter(chip, desc);
2074 pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS);
2077 unsigned int irq, virq;
2081 virq = irq_linear_revmap(bank->domain, irq);
2084 dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq);
2088 dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq);
2091 * Triggering IRQ on both rising and falling edge
2092 * needs manual intervention.
2094 if (bank->toggle_edge_mode & BIT(irq)) {
2095 u32 data, data_old, polarity;
2096 unsigned long flags;
2098 data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT);
2100 raw_spin_lock_irqsave(&bank->slock, flags);
2102 polarity = readl_relaxed(bank->reg_base +
2104 if (data & BIT(irq))
2105 polarity &= ~BIT(irq);
2107 polarity |= BIT(irq);
2109 bank->reg_base + GPIO_INT_POLARITY);
2111 raw_spin_unlock_irqrestore(&bank->slock, flags);
2114 data = readl_relaxed(bank->reg_base +
2116 } while ((data & BIT(irq)) != (data_old & BIT(irq)));
2119 generic_handle_irq(virq);
2122 chained_irq_exit(chip, desc);
2125 static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
2127 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2128 struct rockchip_pin_bank *bank = gc->private;
2129 u32 mask = BIT(d->hwirq);
2133 unsigned long flags;
2136 /* make sure the pin is configured as gpio input */
2137 ret = rockchip_verify_mux(bank, d->hwirq, RK_FUNC_GPIO);
2141 bank->new_irqs |= mask;
2143 raw_spin_lock_irqsave(&bank->slock, flags);
2145 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
2147 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
2149 raw_spin_unlock_irqrestore(&bank->slock, flags);
2151 if (type & IRQ_TYPE_EDGE_BOTH)
2152 irq_set_handler_locked(d, handle_edge_irq);
2154 irq_set_handler_locked(d, handle_level_irq);
2156 raw_spin_lock_irqsave(&bank->slock, flags);
2159 level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL);
2160 polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY);
2163 case IRQ_TYPE_EDGE_BOTH:
2164 bank->toggle_edge_mode |= mask;
2168 * Determine gpio state. If 1 next interrupt should be falling
2171 data = readl(bank->reg_base + GPIO_EXT_PORT);
2177 case IRQ_TYPE_EDGE_RISING:
2178 bank->toggle_edge_mode &= ~mask;
2182 case IRQ_TYPE_EDGE_FALLING:
2183 bank->toggle_edge_mode &= ~mask;
2187 case IRQ_TYPE_LEVEL_HIGH:
2188 bank->toggle_edge_mode &= ~mask;
2192 case IRQ_TYPE_LEVEL_LOW:
2193 bank->toggle_edge_mode &= ~mask;
2199 raw_spin_unlock_irqrestore(&bank->slock, flags);
2203 writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL);
2204 writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY);
2207 raw_spin_unlock_irqrestore(&bank->slock, flags);
2212 static void rockchip_irq_suspend(struct irq_data *d)
2214 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2215 struct rockchip_pin_bank *bank = gc->private;
2217 clk_enable(bank->clk);
2218 bank->saved_masks = irq_reg_readl(gc, GPIO_INTMASK);
2219 irq_reg_writel(gc, ~gc->wake_active, GPIO_INTMASK);
2220 clk_disable(bank->clk);
2223 static void rockchip_irq_resume(struct irq_data *d)
2225 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2226 struct rockchip_pin_bank *bank = gc->private;
2228 clk_enable(bank->clk);
2229 irq_reg_writel(gc, bank->saved_masks, GPIO_INTMASK);
2230 clk_disable(bank->clk);
2233 static void rockchip_irq_enable(struct irq_data *d)
2235 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2236 struct rockchip_pin_bank *bank = gc->private;
2238 clk_enable(bank->clk);
2239 irq_gc_mask_clr_bit(d);
2242 static void rockchip_irq_disable(struct irq_data *d)
2244 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2245 struct rockchip_pin_bank *bank = gc->private;
2247 irq_gc_mask_set_bit(d);
2248 clk_disable(bank->clk);
2251 static void rockchip_irq_bus_lock(struct irq_data *d)
2253 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2254 struct rockchip_pin_bank *bank = gc->private;
2256 clk_enable(bank->clk);
2257 mutex_lock(&bank->irq_lock);
2260 static void rockchip_irq_bus_sync_unlock(struct irq_data *d)
2262 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2263 struct rockchip_pin_bank *bank = gc->private;
2265 while (bank->new_irqs) {
2266 unsigned int irq = __ffs(bank->new_irqs);
2269 ret = rockchip_set_mux(bank, irq, RK_FUNC_GPIO);
2272 bank->new_irqs &= ~BIT(irq);
2275 mutex_unlock(&bank->irq_lock);
2276 clk_disable(bank->clk);
2279 static int rockchip_interrupts_register(struct platform_device *pdev,
2280 struct rockchip_pinctrl *info)
2282 struct rockchip_pin_ctrl *ctrl = info->ctrl;
2283 struct rockchip_pin_bank *bank = ctrl->pin_banks;
2284 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
2285 struct irq_chip_generic *gc;
2289 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2291 dev_warn(&pdev->dev, "bank %s is not valid\n",
2296 ret = clk_enable(bank->clk);
2298 dev_err(&pdev->dev, "failed to enable clock for bank %s\n",
2303 bank->domain = irq_domain_add_linear(bank->of_node, 32,
2304 &irq_generic_chip_ops, NULL);
2305 if (!bank->domain) {
2306 dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n",
2308 clk_disable(bank->clk);
2312 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
2313 "rockchip_gpio_irq", handle_level_irq,
2314 clr, 0, IRQ_GC_INIT_MASK_CACHE);
2316 dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n",
2318 irq_domain_remove(bank->domain);
2319 clk_disable(bank->clk);
2324 * Linux assumes that all interrupts start out disabled/masked.
2325 * Our driver only uses the concept of masked and always keeps
2326 * things enabled, so for us that's all masked and all enabled.
2328 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTMASK);
2329 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTEN);
2331 gc = irq_get_domain_generic_chip(bank->domain, 0);
2332 gc->reg_base = bank->reg_base;
2334 gc->chip_types[0].regs.mask = GPIO_INTMASK;
2335 gc->chip_types[0].regs.ack = GPIO_PORTS_EOI;
2336 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
2337 gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit;
2338 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit;
2339 gc->chip_types[0].chip.irq_enable = rockchip_irq_enable;
2340 gc->chip_types[0].chip.irq_disable = rockchip_irq_disable;
2341 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
2342 gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend;
2343 gc->chip_types[0].chip.irq_resume = rockchip_irq_resume;
2344 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
2345 gc->chip_types[0].chip.irq_bus_lock = rockchip_irq_bus_lock;
2346 gc->chip_types[0].chip.irq_bus_sync_unlock =
2347 rockchip_irq_bus_sync_unlock;
2348 gc->wake_enabled = IRQ_MSK(bank->nr_pins);
2350 irq_set_chained_handler_and_data(bank->irq,
2351 rockchip_irq_demux, bank);
2353 /* map the gpio irqs here, when the clock is still running */
2354 for (j = 0 ; j < 32 ; j++)
2355 irq_create_mapping(bank->domain, j);
2357 clk_disable(bank->clk);
2363 static int rockchip_gpiolib_register(struct platform_device *pdev,
2364 struct rockchip_pinctrl *info)
2366 struct rockchip_pin_ctrl *ctrl = info->ctrl;
2367 struct rockchip_pin_bank *bank = ctrl->pin_banks;
2368 struct gpio_chip *gc;
2372 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2374 dev_warn(&pdev->dev, "bank %s is not valid\n",
2379 bank->gpio_chip = rockchip_gpiolib_chip;
2381 gc = &bank->gpio_chip;
2382 gc->base = bank->pin_base;
2383 gc->ngpio = bank->nr_pins;
2384 gc->parent = &pdev->dev;
2385 gc->of_node = bank->of_node;
2386 gc->label = bank->name;
2388 ret = gpiochip_add_data(gc, bank);
2390 dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n",
2396 rockchip_interrupts_register(pdev, info);
2401 for (--i, --bank; i >= 0; --i, --bank) {
2404 gpiochip_remove(&bank->gpio_chip);
2409 static int rockchip_gpiolib_unregister(struct platform_device *pdev,
2410 struct rockchip_pinctrl *info)
2412 struct rockchip_pin_ctrl *ctrl = info->ctrl;
2413 struct rockchip_pin_bank *bank = ctrl->pin_banks;
2416 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2419 gpiochip_remove(&bank->gpio_chip);
2425 static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
2426 struct rockchip_pinctrl *info)
2428 struct resource res;
2431 if (of_address_to_resource(bank->of_node, 0, &res)) {
2432 dev_err(info->dev, "cannot find IO resource for bank\n");
2436 bank->reg_base = devm_ioremap_resource(info->dev, &res);
2437 if (IS_ERR(bank->reg_base))
2438 return PTR_ERR(bank->reg_base);
2441 * special case, where parts of the pull setting-registers are
2442 * part of the PMU register space
2444 if (of_device_is_compatible(bank->of_node,
2445 "rockchip,rk3188-gpio-bank0")) {
2446 struct device_node *node;
2448 node = of_parse_phandle(bank->of_node->parent,
2451 if (of_address_to_resource(bank->of_node, 1, &res)) {
2452 dev_err(info->dev, "cannot find IO resource for bank\n");
2456 base = devm_ioremap_resource(info->dev, &res);
2458 return PTR_ERR(base);
2459 rockchip_regmap_config.max_register =
2460 resource_size(&res) - 4;
2461 rockchip_regmap_config.name =
2462 "rockchip,rk3188-gpio-bank0-pull";
2463 bank->regmap_pull = devm_regmap_init_mmio(info->dev,
2465 &rockchip_regmap_config);
2469 bank->irq = irq_of_parse_and_map(bank->of_node, 0);
2471 bank->clk = of_clk_get(bank->of_node, 0);
2472 if (IS_ERR(bank->clk))
2473 return PTR_ERR(bank->clk);
2475 return clk_prepare(bank->clk);
2478 static const struct of_device_id rockchip_pinctrl_dt_match[];
2480 /* retrieve the soc specific data */
2481 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
2482 struct rockchip_pinctrl *d,
2483 struct platform_device *pdev)
2485 const struct of_device_id *match;
2486 struct device_node *node = pdev->dev.of_node;
2487 struct device_node *np;
2488 struct rockchip_pin_ctrl *ctrl;
2489 struct rockchip_pin_bank *bank;
2490 int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j;
2492 match = of_match_node(rockchip_pinctrl_dt_match, node);
2493 ctrl = (struct rockchip_pin_ctrl *)match->data;
2495 for_each_child_of_node(node, np) {
2496 if (!of_find_property(np, "gpio-controller", NULL))
2499 bank = ctrl->pin_banks;
2500 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2501 if (!strcmp(bank->name, np->name)) {
2504 if (!rockchip_get_bank_data(bank, d))
2512 grf_offs = ctrl->grf_mux_offset;
2513 pmu_offs = ctrl->pmu_mux_offset;
2514 drv_pmu_offs = ctrl->pmu_drv_offset;
2515 drv_grf_offs = ctrl->grf_drv_offset;
2516 bank = ctrl->pin_banks;
2517 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2520 raw_spin_lock_init(&bank->slock);
2521 mutex_init(&bank->irq_lock);
2523 bank->pin_base = ctrl->nr_pins;
2524 ctrl->nr_pins += bank->nr_pins;
2526 /* calculate iomux and drv offsets */
2527 for (j = 0; j < 4; j++) {
2528 struct rockchip_iomux *iom = &bank->iomux[j];
2529 struct rockchip_drv *drv = &bank->drv[j];
2532 if (bank_pins >= bank->nr_pins)
2535 /* preset iomux offset value, set new start value */
2536 if (iom->offset >= 0) {
2537 if (iom->type & IOMUX_SOURCE_PMU)
2538 pmu_offs = iom->offset;
2540 grf_offs = iom->offset;
2541 } else { /* set current iomux offset */
2542 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ?
2543 pmu_offs : grf_offs;
2546 /* preset drv offset value, set new start value */
2547 if (drv->offset >= 0) {
2548 if (iom->type & IOMUX_SOURCE_PMU)
2549 drv_pmu_offs = drv->offset;
2551 drv_grf_offs = drv->offset;
2552 } else { /* set current drv offset */
2553 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ?
2554 drv_pmu_offs : drv_grf_offs;
2557 dev_dbg(d->dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n",
2558 i, j, iom->offset, drv->offset);
2561 * Increase offset according to iomux width.
2562 * 4bit iomux'es are spread over two registers.
2564 inc = (iom->type & (IOMUX_WIDTH_4BIT |
2565 IOMUX_WIDTH_3BIT)) ? 8 : 4;
2566 if (iom->type & IOMUX_SOURCE_PMU)
2572 * Increase offset according to drv width.
2573 * 3bit drive-strenth'es are spread over two registers.
2575 if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
2576 (drv->drv_type == DRV_TYPE_IO_3V3_ONLY))
2581 if (iom->type & IOMUX_SOURCE_PMU)
2582 drv_pmu_offs += inc;
2584 drv_grf_offs += inc;
2593 #define RK3288_GRF_GPIO6C_IOMUX 0x64
2594 #define GPIO6C6_SEL_WRITE_ENABLE BIT(28)
2596 static u32 rk3288_grf_gpio6c_iomux;
2598 static int __maybe_unused rockchip_pinctrl_suspend(struct device *dev)
2600 struct rockchip_pinctrl *info = dev_get_drvdata(dev);
2601 int ret = pinctrl_force_sleep(info->pctl_dev);
2607 * RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save
2608 * the setting here, and restore it at resume.
2610 if (info->ctrl->type == RK3288) {
2611 ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
2612 &rk3288_grf_gpio6c_iomux);
2614 pinctrl_force_default(info->pctl_dev);
2622 static int __maybe_unused rockchip_pinctrl_resume(struct device *dev)
2624 struct rockchip_pinctrl *info = dev_get_drvdata(dev);
2625 int ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
2626 rk3288_grf_gpio6c_iomux |
2627 GPIO6C6_SEL_WRITE_ENABLE);
2632 return pinctrl_force_default(info->pctl_dev);
2635 static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend,
2636 rockchip_pinctrl_resume);
2638 static int rockchip_pinctrl_probe(struct platform_device *pdev)
2640 struct rockchip_pinctrl *info;
2641 struct device *dev = &pdev->dev;
2642 struct rockchip_pin_ctrl *ctrl;
2643 struct device_node *np = pdev->dev.of_node, *node;
2644 struct resource *res;
2648 if (!dev->of_node) {
2649 dev_err(dev, "device tree node not found\n");
2653 info = devm_kzalloc(dev, sizeof(struct rockchip_pinctrl), GFP_KERNEL);
2659 ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
2661 dev_err(dev, "driver data not available\n");
2666 node = of_parse_phandle(np, "rockchip,grf", 0);
2668 info->regmap_base = syscon_node_to_regmap(node);
2669 if (IS_ERR(info->regmap_base))
2670 return PTR_ERR(info->regmap_base);
2672 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2673 base = devm_ioremap_resource(&pdev->dev, res);
2675 return PTR_ERR(base);
2677 rockchip_regmap_config.max_register = resource_size(res) - 4;
2678 rockchip_regmap_config.name = "rockchip,pinctrl";
2679 info->regmap_base = devm_regmap_init_mmio(&pdev->dev, base,
2680 &rockchip_regmap_config);
2682 /* to check for the old dt-bindings */
2683 info->reg_size = resource_size(res);
2685 /* Honor the old binding, with pull registers as 2nd resource */
2686 if (ctrl->type == RK3188 && info->reg_size < 0x200) {
2687 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2688 base = devm_ioremap_resource(&pdev->dev, res);
2690 return PTR_ERR(base);
2692 rockchip_regmap_config.max_register =
2693 resource_size(res) - 4;
2694 rockchip_regmap_config.name = "rockchip,pinctrl-pull";
2695 info->regmap_pull = devm_regmap_init_mmio(&pdev->dev,
2697 &rockchip_regmap_config);
2701 /* try to find the optional reference to the pmu syscon */
2702 node = of_parse_phandle(np, "rockchip,pmu", 0);
2704 info->regmap_pmu = syscon_node_to_regmap(node);
2705 if (IS_ERR(info->regmap_pmu))
2706 return PTR_ERR(info->regmap_pmu);
2709 ret = rockchip_gpiolib_register(pdev, info);
2713 ret = rockchip_pinctrl_register(pdev, info);
2715 rockchip_gpiolib_unregister(pdev, info);
2719 platform_set_drvdata(pdev, info);
2724 static struct rockchip_pin_bank rv1108_pin_banks[] = {
2725 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
2729 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
2730 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0),
2731 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0),
2734 static struct rockchip_pin_ctrl rv1108_pin_ctrl = {
2735 .pin_banks = rv1108_pin_banks,
2736 .nr_banks = ARRAY_SIZE(rv1108_pin_banks),
2737 .label = "RV1108-GPIO",
2739 .grf_mux_offset = 0x10,
2740 .pmu_mux_offset = 0x0,
2741 .pull_calc_reg = rv1108_calc_pull_reg_and_bit,
2742 .drv_calc_reg = rv1108_calc_drv_reg_and_bit,
2745 static struct rockchip_pin_bank rk2928_pin_banks[] = {
2746 PIN_BANK(0, 32, "gpio0"),
2747 PIN_BANK(1, 32, "gpio1"),
2748 PIN_BANK(2, 32, "gpio2"),
2749 PIN_BANK(3, 32, "gpio3"),
2752 static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
2753 .pin_banks = rk2928_pin_banks,
2754 .nr_banks = ARRAY_SIZE(rk2928_pin_banks),
2755 .label = "RK2928-GPIO",
2757 .grf_mux_offset = 0xa8,
2758 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
2761 static struct rockchip_pin_bank rk3036_pin_banks[] = {
2762 PIN_BANK(0, 32, "gpio0"),
2763 PIN_BANK(1, 32, "gpio1"),
2764 PIN_BANK(2, 32, "gpio2"),
2767 static struct rockchip_pin_ctrl rk3036_pin_ctrl = {
2768 .pin_banks = rk3036_pin_banks,
2769 .nr_banks = ARRAY_SIZE(rk3036_pin_banks),
2770 .label = "RK3036-GPIO",
2772 .grf_mux_offset = 0xa8,
2773 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
2776 static struct rockchip_pin_bank rk3066a_pin_banks[] = {
2777 PIN_BANK(0, 32, "gpio0"),
2778 PIN_BANK(1, 32, "gpio1"),
2779 PIN_BANK(2, 32, "gpio2"),
2780 PIN_BANK(3, 32, "gpio3"),
2781 PIN_BANK(4, 32, "gpio4"),
2782 PIN_BANK(6, 16, "gpio6"),
2785 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
2786 .pin_banks = rk3066a_pin_banks,
2787 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks),
2788 .label = "RK3066a-GPIO",
2790 .grf_mux_offset = 0xa8,
2791 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
2794 static struct rockchip_pin_bank rk3066b_pin_banks[] = {
2795 PIN_BANK(0, 32, "gpio0"),
2796 PIN_BANK(1, 32, "gpio1"),
2797 PIN_BANK(2, 32, "gpio2"),
2798 PIN_BANK(3, 32, "gpio3"),
2801 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
2802 .pin_banks = rk3066b_pin_banks,
2803 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks),
2804 .label = "RK3066b-GPIO",
2806 .grf_mux_offset = 0x60,
2809 static struct rockchip_pin_bank rk3188_pin_banks[] = {
2810 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
2811 PIN_BANK(1, 32, "gpio1"),
2812 PIN_BANK(2, 32, "gpio2"),
2813 PIN_BANK(3, 32, "gpio3"),
2816 static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
2817 .pin_banks = rk3188_pin_banks,
2818 .nr_banks = ARRAY_SIZE(rk3188_pin_banks),
2819 .label = "RK3188-GPIO",
2821 .grf_mux_offset = 0x60,
2822 .pull_calc_reg = rk3188_calc_pull_reg_and_bit,
2825 static struct rockchip_pin_bank rk3228_pin_banks[] = {
2826 PIN_BANK(0, 32, "gpio0"),
2827 PIN_BANK(1, 32, "gpio1"),
2828 PIN_BANK(2, 32, "gpio2"),
2829 PIN_BANK(3, 32, "gpio3"),
2832 static struct rockchip_pin_ctrl rk3228_pin_ctrl = {
2833 .pin_banks = rk3228_pin_banks,
2834 .nr_banks = ARRAY_SIZE(rk3228_pin_banks),
2835 .label = "RK3228-GPIO",
2837 .grf_mux_offset = 0x0,
2838 .pull_calc_reg = rk3228_calc_pull_reg_and_bit,
2839 .drv_calc_reg = rk3228_calc_drv_reg_and_bit,
2842 static struct rockchip_pin_bank rk3288_pin_banks[] = {
2843 PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU,
2848 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED,
2853 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED),
2854 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT),
2855 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
2860 PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED,
2865 PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED),
2866 PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0,
2871 PIN_BANK(8, 16, "gpio8"),
2874 static struct rockchip_pin_ctrl rk3288_pin_ctrl = {
2875 .pin_banks = rk3288_pin_banks,
2876 .nr_banks = ARRAY_SIZE(rk3288_pin_banks),
2877 .label = "RK3288-GPIO",
2879 .grf_mux_offset = 0x0,
2880 .pmu_mux_offset = 0x84,
2881 .pull_calc_reg = rk3288_calc_pull_reg_and_bit,
2882 .drv_calc_reg = rk3288_calc_drv_reg_and_bit,
2885 static struct rockchip_pin_bank rk3328_pin_banks[] = {
2886 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0),
2887 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
2888 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0,
2889 IOMUX_WIDTH_3BIT | IOMUX_RECALCED,
2890 IOMUX_WIDTH_3BIT | IOMUX_RECALCED,
2892 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
2894 IOMUX_WIDTH_3BIT | IOMUX_RECALCED,
2899 static struct rockchip_pin_ctrl rk3328_pin_ctrl = {
2900 .pin_banks = rk3328_pin_banks,
2901 .nr_banks = ARRAY_SIZE(rk3328_pin_banks),
2902 .label = "RK3328-GPIO",
2904 .grf_mux_offset = 0x0,
2905 .pull_calc_reg = rk3228_calc_pull_reg_and_bit,
2906 .drv_calc_reg = rk3228_calc_drv_reg_and_bit,
2907 .iomux_recalc = rk3328_recalc_mux,
2908 .schmitt_calc_reg = rk3328_calc_schmitt_reg_and_bit,
2911 static struct rockchip_pin_bank rk3368_pin_banks[] = {
2912 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
2917 PIN_BANK(1, 32, "gpio1"),
2918 PIN_BANK(2, 32, "gpio2"),
2919 PIN_BANK(3, 32, "gpio3"),
2922 static struct rockchip_pin_ctrl rk3368_pin_ctrl = {
2923 .pin_banks = rk3368_pin_banks,
2924 .nr_banks = ARRAY_SIZE(rk3368_pin_banks),
2925 .label = "RK3368-GPIO",
2927 .grf_mux_offset = 0x0,
2928 .pmu_mux_offset = 0x0,
2929 .pull_calc_reg = rk3368_calc_pull_reg_and_bit,
2930 .drv_calc_reg = rk3368_calc_drv_reg_and_bit,
2933 static struct rockchip_pin_bank rk3399_pin_banks[] = {
2934 PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0",
2939 DRV_TYPE_IO_1V8_ONLY,
2940 DRV_TYPE_IO_1V8_ONLY,
2941 DRV_TYPE_IO_DEFAULT,
2942 DRV_TYPE_IO_DEFAULT,
2947 PULL_TYPE_IO_1V8_ONLY,
2948 PULL_TYPE_IO_1V8_ONLY,
2949 PULL_TYPE_IO_DEFAULT,
2950 PULL_TYPE_IO_DEFAULT
2952 PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU,
2956 DRV_TYPE_IO_1V8_OR_3V0,
2957 DRV_TYPE_IO_1V8_OR_3V0,
2958 DRV_TYPE_IO_1V8_OR_3V0,
2959 DRV_TYPE_IO_1V8_OR_3V0,
2965 PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0,
2966 DRV_TYPE_IO_1V8_OR_3V0,
2967 DRV_TYPE_IO_1V8_ONLY,
2968 DRV_TYPE_IO_1V8_ONLY,
2969 PULL_TYPE_IO_DEFAULT,
2970 PULL_TYPE_IO_DEFAULT,
2971 PULL_TYPE_IO_1V8_ONLY,
2972 PULL_TYPE_IO_1V8_ONLY
2974 PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY,
2975 DRV_TYPE_IO_3V3_ONLY,
2976 DRV_TYPE_IO_3V3_ONLY,
2977 DRV_TYPE_IO_1V8_OR_3V0
2979 PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0,
2980 DRV_TYPE_IO_1V8_3V0_AUTO,
2981 DRV_TYPE_IO_1V8_OR_3V0,
2982 DRV_TYPE_IO_1V8_OR_3V0
2986 static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
2987 .pin_banks = rk3399_pin_banks,
2988 .nr_banks = ARRAY_SIZE(rk3399_pin_banks),
2989 .label = "RK3399-GPIO",
2991 .grf_mux_offset = 0xe000,
2992 .pmu_mux_offset = 0x0,
2993 .grf_drv_offset = 0xe100,
2994 .pmu_drv_offset = 0x80,
2995 .pull_calc_reg = rk3399_calc_pull_reg_and_bit,
2996 .drv_calc_reg = rk3399_calc_drv_reg_and_bit,
2999 static const struct of_device_id rockchip_pinctrl_dt_match[] = {
3000 { .compatible = "rockchip,rv1108-pinctrl",
3001 .data = (void *)&rv1108_pin_ctrl },
3002 { .compatible = "rockchip,rk2928-pinctrl",
3003 .data = (void *)&rk2928_pin_ctrl },
3004 { .compatible = "rockchip,rk3036-pinctrl",
3005 .data = (void *)&rk3036_pin_ctrl },
3006 { .compatible = "rockchip,rk3066a-pinctrl",
3007 .data = (void *)&rk3066a_pin_ctrl },
3008 { .compatible = "rockchip,rk3066b-pinctrl",
3009 .data = (void *)&rk3066b_pin_ctrl },
3010 { .compatible = "rockchip,rk3188-pinctrl",
3011 .data = (void *)&rk3188_pin_ctrl },
3012 { .compatible = "rockchip,rk3228-pinctrl",
3013 .data = (void *)&rk3228_pin_ctrl },
3014 { .compatible = "rockchip,rk3288-pinctrl",
3015 .data = (void *)&rk3288_pin_ctrl },
3016 { .compatible = "rockchip,rk3328-pinctrl",
3017 .data = (void *)&rk3328_pin_ctrl },
3018 { .compatible = "rockchip,rk3368-pinctrl",
3019 .data = (void *)&rk3368_pin_ctrl },
3020 { .compatible = "rockchip,rk3399-pinctrl",
3021 .data = (void *)&rk3399_pin_ctrl },
3025 static struct platform_driver rockchip_pinctrl_driver = {
3026 .probe = rockchip_pinctrl_probe,
3028 .name = "rockchip-pinctrl",
3029 .pm = &rockchip_pinctrl_dev_pm_ops,
3030 .of_match_table = rockchip_pinctrl_dt_match,
3034 static int __init rockchip_pinctrl_drv_register(void)
3036 return platform_driver_register(&rockchip_pinctrl_driver);
3038 postcore_initcall(rockchip_pinctrl_drv_register);