drivers/pinctrl/pinctrl-rockchip.c

   1 /*
   2  * Pinctrl driver for Rockchip SoCs
   3  *
   4  * Copyright (c) 2013 MundoReader S.L.
   5  * Author: Heiko Stuebner <heiko@sntech.de>
   6  *
   7  * With some ideas taken from pinctrl-samsung:
   8  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
   9  *              http://www.samsung.com
  10  * Copyright (c) 2012 Linaro Ltd
  11  *              http://www.linaro.org
  12  *
  13  * and pinctrl-at91:
  14  * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as published
  18  * by the Free Software Foundation.
  19  *
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  * GNU General Public License for more details.
  24  */
  25
  26 #include <linux/module.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/io.h>
  29 #include <linux/bitops.h>
  30 #include <linux/gpio.h>
  31 #include <linux/of_address.h>
  32 #include <linux/of_irq.h>
  33 #include <linux/pinctrl/machine.h>
  34 #include <linux/pinctrl/pinconf.h>
  35 #include <linux/pinctrl/pinctrl.h>
  36 #include <linux/pinctrl/pinmux.h>
  37 #include <linux/pinctrl/pinconf-generic.h>
  38 #include <linux/irqchip/chained_irq.h>
  39 #include <linux/clk.h>
  40 #include <dt-bindings/pinctrl/rockchip.h>
  41
  42 #include "core.h"
  43 #include "pinconf.h"
  44
  45 /* GPIO control registers */
  46 #define GPIO_SWPORT_DR          0x00
  47 #define GPIO_SWPORT_DDR         0x04
  48 #define GPIO_INTEN              0x30
  49 #define GPIO_INTMASK            0x34
  50 #define GPIO_INTTYPE_LEVEL      0x38
  51 #define GPIO_INT_POLARITY       0x3c
  52 #define GPIO_INT_STATUS         0x40
  53 #define GPIO_INT_RAWSTATUS      0x44
  54 #define GPIO_DEBOUNCE           0x48
  55 #define GPIO_PORTS_EOI          0x4c
  56 #define GPIO_EXT_PORT           0x50
  57 #define GPIO_LS_SYNC            0x60
  58
  59 enum rockchip_pinctrl_type {
  60         RK2928,
  61         RK3066B,
  62         RK3188,
  63 };
  64
  65 enum rockchip_pin_bank_type {
  66         COMMON_BANK,
  67 };
  68
  69 /**
  70  * @reg_base: register base of the gpio bank
  71  * @clk: clock of the gpio bank
  72  * @irq: interrupt of the gpio bank
  73  * @pin_base: first pin number
  74  * @nr_pins: number of pins in this bank
  75  * @name: name of the bank
  76  * @bank_num: number of the bank, to account for holes
  77  * @valid: are all necessary informations present
  78  * @of_node: dt node of this bank
  79  * @drvdata: common pinctrl basedata
  80  * @domain: irqdomain of the gpio bank
  81  * @gpio_chip: gpiolib chip
  82  * @grange: gpio range
  83  * @slock: spinlock for the gpio bank
  84  */
  85 struct rockchip_pin_bank {
  86         void __iomem                    *reg_base;
  87         struct clk                      *clk;
  88         int                             irq;
  89         u32                             pin_base;
  90         u8                              nr_pins;
  91         char                            *name;
  92         u8                              bank_num;
  93         enum rockchip_pin_bank_type     bank_type;
  94         bool                            valid;
  95         struct device_node              *of_node;
  96         struct rockchip_pinctrl         *drvdata;
  97         struct irq_domain               *domain;
  98         struct gpio_chip                gpio_chip;
  99         struct pinctrl_gpio_range       grange;
 100         spinlock_t                      slock;
 101
 102 };
 103
 104 #define PIN_BANK(id, pins, label)                       \
 105         {                                               \
 106                 .bank_num       = id,                   \
 107                 .nr_pins        = pins,                 \
 108                 .name           = label,                \
 109         }
 110
 111 /**
 112  */
 113 struct rockchip_pin_ctrl {
 114         struct rockchip_pin_bank        *pin_banks;
 115         u32                             nr_banks;
 116         u32                             nr_pins;
 117         char                            *label;
 118         enum rockchip_pinctrl_type      type;
 119         int                             mux_offset;
 120         void    (*pull_calc_reg)(struct rockchip_pin_bank *bank, int pin_num,
 121                                  void __iomem **reg, u8 *bit);
 122 };
 123
 124 struct rockchip_pin_config {
 125         unsigned int            func;
 126         unsigned long           *configs;
 127         unsigned int            nconfigs;
 128 };
 129
 130 /**
 131  * struct rockchip_pin_group: represent group of pins of a pinmux function.
 132  * @name: name of the pin group, used to lookup the group.
 133  * @pins: the pins included in this group.
 134  * @npins: number of pins included in this group.
 135  * @func: the mux function number to be programmed when selected.
 136  * @configs: the config values to be set for each pin
 137  * @nconfigs: number of configs for each pin
 138  */
 139 struct rockchip_pin_group {
 140         const char                      *name;
 141         unsigned int                    npins;
 142         unsigned int                    *pins;
 143         struct rockchip_pin_config      *data;
 144 };
 145
 146 /**
 147  * struct rockchip_pmx_func: represent a pin function.
 148  * @name: name of the pin function, used to lookup the function.
 149  * @groups: one or more names of pin groups that provide this function.
 150  * @num_groups: number of groups included in @groups.
 151  */
 152 struct rockchip_pmx_func {
 153         const char              *name;
 154         const char              **groups;
 155         u8                      ngroups;
 156 };
 157
 158 struct rockchip_pinctrl {
 159         void __iomem                    *reg_base;
 160         struct device                   *dev;
 161         struct rockchip_pin_ctrl        *ctrl;
 162         struct pinctrl_desc             pctl;
 163         struct pinctrl_dev              *pctl_dev;
 164         struct rockchip_pin_group       *groups;
 165         unsigned int                    ngroups;
 166         struct rockchip_pmx_func        *functions;
 167         unsigned int                    nfunctions;
 168 };
 169
 170 static inline struct rockchip_pin_bank *gc_to_pin_bank(struct gpio_chip *gc)
 171 {
 172         return container_of(gc, struct rockchip_pin_bank, gpio_chip);
 173 }
 174
 175 static const inline struct rockchip_pin_group *pinctrl_name_to_group(
 176                                         const struct rockchip_pinctrl *info,
 177                                         const char *name)
 178 {
 179         int i;
 180
 181         for (i = 0; i < info->ngroups; i++) {
 182                 if (!strcmp(info->groups[i].name, name))
 183                         return &info->groups[i];
 184         }
 185
 186         return NULL;
 187 }
 188
 189 /*
 190  * given a pin number that is local to a pin controller, find out the pin bank
 191  * and the register base of the pin bank.
 192  */
 193 static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info,
 194                                                                 unsigned pin)
 195 {
 196         struct rockchip_pin_bank *b = info->ctrl->pin_banks;
 197
 198         while (pin >= (b->pin_base + b->nr_pins))
 199                 b++;
 200
 201         return b;
 202 }
 203
 204 static struct rockchip_pin_bank *bank_num_to_bank(
 205                                         struct rockchip_pinctrl *info,
 206                                         unsigned num)
 207 {
 208         struct rockchip_pin_bank *b = info->ctrl->pin_banks;
 209         int i;
 210
 211         for (i = 0; i < info->ctrl->nr_banks; i++, b++) {
 212                 if (b->bank_num == num)
 213                         return b;
 214         }
 215
 216         return ERR_PTR(-EINVAL);
 217 }
 218
 219 /*
 220  * Pinctrl_ops handling
 221  */
 222
 223 static int rockchip_get_groups_count(struct pinctrl_dev *pctldev)
 224 {
 225         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 226
 227         return info->ngroups;
 228 }
 229
 230 static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev,
 231                                                         unsigned selector)
 232 {
 233         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 234
 235         return info->groups[selector].name;
 236 }
 237
 238 static int rockchip_get_group_pins(struct pinctrl_dev *pctldev,
 239                                       unsigned selector, const unsigned **pins,
 240                                       unsigned *npins)
 241 {
 242         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 243
 244         if (selector >= info->ngroups)
 245                 return -EINVAL;
 246
 247         *pins = info->groups[selector].pins;
 248         *npins = info->groups[selector].npins;
 249
 250         return 0;
 251 }
 252
 253 static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev,
 254                                  struct device_node *np,
 255                                  struct pinctrl_map **map, unsigned *num_maps)
 256 {
 257         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 258         const struct rockchip_pin_group *grp;
 259         struct pinctrl_map *new_map;
 260         struct device_node *parent;
 261         int map_num = 1;
 262         int i;
 263
 264         /*
 265          * first find the group of this node and check if we need to create
 266          * config maps for pins
 267          */
 268         grp = pinctrl_name_to_group(info, np->name);
 269         if (!grp) {
 270                 dev_err(info->dev, "unable to find group for node %s\n",
 271                         np->name);
 272                 return -EINVAL;
 273         }
 274
 275         map_num += grp->npins;
 276         new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num,
 277                                                                 GFP_KERNEL);
 278         if (!new_map)
 279                 return -ENOMEM;
 280
 281         *map = new_map;
 282         *num_maps = map_num;
 283
 284         /* create mux map */
 285         parent = of_get_parent(np);
 286         if (!parent) {
 287                 devm_kfree(pctldev->dev, new_map);
 288                 return -EINVAL;
 289         }
 290         new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
 291         new_map[0].data.mux.function = parent->name;
 292         new_map[0].data.mux.group = np->name;
 293         of_node_put(parent);
 294
 295         /* create config map */
 296         new_map++;
 297         for (i = 0; i < grp->npins; i++) {
 298                 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
 299                 new_map[i].data.configs.group_or_pin =
 300                                 pin_get_name(pctldev, grp->pins[i]);
 301                 new_map[i].data.configs.configs = grp->data[i].configs;
 302                 new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
 303         }
 304
 305         dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
 306                 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
 307
 308         return 0;
 309 }
 310
 311 static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
 312                                     struct pinctrl_map *map, unsigned num_maps)
 313 {
 314 }
 315
 316 static const struct pinctrl_ops rockchip_pctrl_ops = {
 317         .get_groups_count       = rockchip_get_groups_count,
 318         .get_group_name         = rockchip_get_group_name,
 319         .get_group_pins         = rockchip_get_group_pins,
 320         .dt_node_to_map         = rockchip_dt_node_to_map,
 321         .dt_free_map            = rockchip_dt_free_map,
 322 };
 323
 324 /*
 325  * Hardware access
 326  */
 327
 328 /*
 329  * Set a new mux function for a pin.
 330  *
 331  * The register is divided into the upper and lower 16 bit. When changing
 332  * a value, the previous register value is not read and changed. Instead
 333  * it seems the changed bits are marked in the upper 16 bit, while the
 334  * changed value gets set in the same offset in the lower 16 bit.
 335  * All pin settings seem to be 2 bit wide in both the upper and lower
 336  * parts.
 337  * @bank: pin bank to change
 338  * @pin: pin to change
 339  * @mux: new mux function to set
 340  */
 341 static void rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
 342 {
 343         struct rockchip_pinctrl *info = bank->drvdata;
 344         void __iomem *reg = info->reg_base + info->ctrl->mux_offset;
 345         unsigned long flags;
 346         u8 bit;
 347         u32 data;
 348
 349         dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n",
 350                                                 bank->bank_num, pin, mux);
 351
 352         /* get basic quadrupel of mux registers and the correct reg inside */
 353         reg += bank->bank_num * 0x10;
 354         reg += (pin / 8) * 4;
 355         bit = (pin % 8) * 2;
 356
 357         spin_lock_irqsave(&bank->slock, flags);
 358
 359         data = (3 << (bit + 16));
 360         data |= (mux & 3) << bit;
 361         writel(data, reg);
 362
 363         spin_unlock_irqrestore(&bank->slock, flags);
 364 }
 365
 366 #define RK2928_PULL_OFFSET              0x118
 367 #define RK2928_PULL_PINS_PER_REG        16
 368 #define RK2928_PULL_BANK_STRIDE         8
 369
 370 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
 371                                     int pin_num, void __iomem **reg, u8 *bit)
 372 {
 373         struct rockchip_pinctrl *info = bank->drvdata;
 374
 375         *reg = info->reg_base + RK2928_PULL_OFFSET;
 376         *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
 377         *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4;
 378
 379         *bit = pin_num % RK2928_PULL_PINS_PER_REG;
 380 };
 381
 382 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
 383 {
 384         struct rockchip_pinctrl *info = bank->drvdata;
 385         struct rockchip_pin_ctrl *ctrl = info->ctrl;
 386         void __iomem *reg;
 387         u8 bit;
 388
 389         /* rk3066b does support any pulls */
 390         if (ctrl->type == RK3066B)
 391                 return PIN_CONFIG_BIAS_DISABLE;
 392
 393         switch (ctrl->type) {
 394         case RK2928:
 395                 ctrl->pull_calc_reg(bank, pin_num, &reg, &bit);
 396                 return !(readl_relaxed(reg) & BIT(bit))
 397                                 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
 398                                 : PIN_CONFIG_BIAS_DISABLE;
 399         case RK3188:
 400                 dev_err(info->dev, "pull support for rk31xx not implemented\n");
 401                 return -EIO;
 402         default:
 403                 dev_err(info->dev, "unsupported pinctrl type\n");
 404                 return -EINVAL;
 405         };
 406 }
 407
 408 static int rockchip_set_pull(struct rockchip_pin_bank *bank,
 409                                         int pin_num, int pull)
 410 {
 411         struct rockchip_pinctrl *info = bank->drvdata;
 412         struct rockchip_pin_ctrl *ctrl = info->ctrl;
 413         void __iomem *reg;
 414         unsigned long flags;
 415         u8 bit;
 416         u32 data;
 417
 418         dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n",
 419                  bank->bank_num, pin_num, pull);
 420
 421         /* rk3066b does support any pulls */
 422         if (ctrl->type == RK3066B)
 423                 return pull ? -EINVAL : 0;
 424
 425         switch (ctrl->type) {
 426         case RK2928:
 427                 if (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT &&
 428                                         pull != PIN_CONFIG_BIAS_DISABLE) {
 429                         dev_err(info->dev, "only PIN_DEFAULT and DISABLE allowed\n");
 430                         return -EINVAL;
 431                 }
 432
 433                 ctrl->pull_calc_reg(bank, pin_num, &reg, &bit);
 434
 435                 spin_lock_irqsave(&bank->slock, flags);
 436
 437                 data = BIT(bit + 16);
 438                 if (pull == PIN_CONFIG_BIAS_DISABLE)
 439                         data |= BIT(bit);
 440                 writel(data, reg);
 441
 442                 spin_unlock_irqrestore(&bank->slock, flags);
 443                 break;
 444         case RK3188:
 445                 dev_err(info->dev, "pull support for rk31xx not implemented\n");
 446                 return -EIO;
 447         default:
 448                 dev_err(info->dev, "unsupported pinctrl type\n");
 449                 return -EINVAL;
 450         }
 451
 452         return 0;
 453 }
 454
 455 /*
 456  * Pinmux_ops handling
 457  */
 458
 459 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
 460 {
 461         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 462
 463         return info->nfunctions;
 464 }
 465
 466 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev,
 467                                           unsigned selector)
 468 {
 469         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 470
 471         return info->functions[selector].name;
 472 }
 473
 474 static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
 475                                 unsigned selector, const char * const **groups,
 476                                 unsigned * const num_groups)
 477 {
 478         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 479
 480         *groups = info->functions[selector].groups;
 481         *num_groups = info->functions[selector].ngroups;
 482
 483         return 0;
 484 }
 485
 486 static int rockchip_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
 487                                                             unsigned group)
 488 {
 489         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 490         const unsigned int *pins = info->groups[group].pins;
 491         const struct rockchip_pin_config *data = info->groups[group].data;
 492         struct rockchip_pin_bank *bank;
 493         int cnt;
 494
 495         dev_dbg(info->dev, "enable function %s group %s\n",
 496                 info->functions[selector].name, info->groups[group].name);
 497
 498         /*
 499          * for each pin in the pin group selected, program the correspoding pin
 500          * pin function number in the config register.
 501          */
 502         for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
 503                 bank = pin_to_bank(info, pins[cnt]);
 504                 rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
 505                                  data[cnt].func);
 506         }
 507
 508         return 0;
 509 }
 510
 511 static void rockchip_pmx_disable(struct pinctrl_dev *pctldev,
 512                                         unsigned selector, unsigned group)
 513 {
 514         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 515         const unsigned int *pins = info->groups[group].pins;
 516         struct rockchip_pin_bank *bank;
 517         int cnt;
 518
 519         dev_dbg(info->dev, "disable function %s group %s\n",
 520                 info->functions[selector].name, info->groups[group].name);
 521
 522         for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
 523                 bank = pin_to_bank(info, pins[cnt]);
 524                 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
 525         }
 526 }
 527
 528 /*
 529  * The calls to gpio_direction_output() and gpio_direction_input()
 530  * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
 531  * function called from the gpiolib interface).
 532  */
 533 static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
 534                                               struct pinctrl_gpio_range *range,
 535                                               unsigned offset, bool input)
 536 {
 537         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 538         struct rockchip_pin_bank *bank;
 539         struct gpio_chip *chip;
 540         int pin;
 541         u32 data;
 542
 543         chip = range->gc;
 544         bank = gc_to_pin_bank(chip);
 545         pin = offset - chip->base;
 546
 547         dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
 548                  offset, range->name, pin, input ? "input" : "output");
 549
 550         rockchip_set_mux(bank, pin, RK_FUNC_GPIO);
 551
 552         data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
 553         /* set bit to 1 for output, 0 for input */
 554         if (!input)
 555                 data |= BIT(pin);
 556         else
 557                 data &= ~BIT(pin);
 558         writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
 559
 560         return 0;
 561 }
 562
 563 static const struct pinmux_ops rockchip_pmx_ops = {
 564         .get_functions_count    = rockchip_pmx_get_funcs_count,
 565         .get_function_name      = rockchip_pmx_get_func_name,
 566         .get_function_groups    = rockchip_pmx_get_groups,
 567         .enable                 = rockchip_pmx_enable,
 568         .disable                = rockchip_pmx_disable,
 569         .gpio_set_direction     = rockchip_pmx_gpio_set_direction,
 570 };
 571
 572 /*
 573  * Pinconf_ops handling
 574  */
 575
 576 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
 577                                         enum pin_config_param pull)
 578 {
 579         switch (ctrl->type) {
 580         case RK2928:
 581                 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
 582                                         pull == PIN_CONFIG_BIAS_DISABLE);
 583         case RK3066B:
 584                 return pull ? false : true;
 585         case RK3188:
 586                 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
 587         }
 588
 589         return false;
 590 }
 591
 592 /* set the pin config settings for a specified pin */
 593 static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
 594                                 unsigned long *configs, unsigned num_configs)
 595 {
 596         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 597         struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
 598         enum pin_config_param param;
 599         u16 arg;
 600         int i;
 601         int rc;
 602
 603         for (i = 0; i < num_configs; i++) {
 604                 param = pinconf_to_config_param(configs[i]);
 605                 arg = pinconf_to_config_argument(configs[i]);
 606
 607                 switch (param) {
 608                 case PIN_CONFIG_BIAS_DISABLE:
 609                         rc =  rockchip_set_pull(bank, pin - bank->pin_base,
 610                                 param);
 611                         if (rc)
 612                                 return rc;
 613                         break;
 614                 case PIN_CONFIG_BIAS_PULL_UP:
 615                 case PIN_CONFIG_BIAS_PULL_DOWN:
 616                 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
 617                         if (!rockchip_pinconf_pull_valid(info->ctrl, param))
 618                                 return -ENOTSUPP;
 619
 620                         if (!arg)
 621                                 return -EINVAL;
 622
 623                         rc = rockchip_set_pull(bank, pin - bank->pin_base,
 624                                 param);
 625                         if (rc)
 626                                 return rc;
 627                         break;
 628                 default:
 629                         return -ENOTSUPP;
 630                         break;
 631                 }
 632         } /* for each config */
 633
 634         return 0;
 635 }
 636
 637 /* get the pin config settings for a specified pin */
 638 static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
 639                                                         unsigned long *config)
 640 {
 641         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 642         struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
 643         enum pin_config_param param = pinconf_to_config_param(*config);
 644
 645         switch (param) {
 646         case PIN_CONFIG_BIAS_DISABLE:
 647                 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
 648                         return -EINVAL;
 649
 650                 *config = 0;
 651                 break;
 652         case PIN_CONFIG_BIAS_PULL_UP:
 653         case PIN_CONFIG_BIAS_PULL_DOWN:
 654         case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
 655                 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
 656                         return -ENOTSUPP;
 657
 658                 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
 659                         return -EINVAL;
 660
 661                 *config = 1;
 662                 break;
 663         default:
 664                 return -ENOTSUPP;
 665                 break;
 666         }
 667
 668         return 0;
 669 }
 670
 671 static const struct pinconf_ops rockchip_pinconf_ops = {
 672         .pin_config_get                 = rockchip_pinconf_get,
 673         .pin_config_set                 = rockchip_pinconf_set,
 674 };
 675
 676 static const struct of_device_id rockchip_bank_match[] = {
 677         { .compatible = "rockchip,gpio-bank" },
 678         {},
 679 };
 680
 681 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
 682                                                 struct device_node *np)
 683 {
 684         struct device_node *child;
 685
 686         for_each_child_of_node(np, child) {
 687                 if (of_match_node(rockchip_bank_match, child))
 688                         continue;
 689
 690                 info->nfunctions++;
 691                 info->ngroups += of_get_child_count(child);
 692         }
 693 }
 694
 695 static int rockchip_pinctrl_parse_groups(struct device_node *np,
 696                                               struct rockchip_pin_group *grp,
 697                                               struct rockchip_pinctrl *info,
 698                                               u32 index)
 699 {
 700         struct rockchip_pin_bank *bank;
 701         int size;
 702         const __be32 *list;
 703         int num;
 704         int i, j;
 705         int ret;
 706
 707         dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
 708
 709         /* Initialise group */
 710         grp->name = np->name;
 711
 712         /*
 713          * the binding format is rockchip,pins = <bank pin mux CONFIG>,
 714          * do sanity check and calculate pins number
 715          */
 716         list = of_get_property(np, "rockchip,pins", &size);
 717         /* we do not check return since it's safe node passed down */
 718         size /= sizeof(*list);
 719         if (!size || size % 4) {
 720                 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
 721                 return -EINVAL;
 722         }
 723
 724         grp->npins = size / 4;
 725
 726         grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
 727                                                 GFP_KERNEL);
 728         grp->data = devm_kzalloc(info->dev, grp->npins *
 729                                           sizeof(struct rockchip_pin_config),
 730                                         GFP_KERNEL);
 731         if (!grp->pins || !grp->data)
 732                 return -ENOMEM;
 733
 734         for (i = 0, j = 0; i < size; i += 4, j++) {
 735                 const __be32 *phandle;
 736                 struct device_node *np_config;
 737
 738                 num = be32_to_cpu(*list++);
 739                 bank = bank_num_to_bank(info, num);
 740                 if (IS_ERR(bank))
 741                         return PTR_ERR(bank);
 742
 743                 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++);
 744                 grp->data[j].func = be32_to_cpu(*list++);
 745
 746                 phandle = list++;
 747                 if (!phandle)
 748                         return -EINVAL;
 749
 750                 np_config = of_find_node_by_phandle(be32_to_cpup(phandle));
 751                 ret = pinconf_generic_parse_dt_config(np_config,
 752                                 &grp->data[j].configs, &grp->data[j].nconfigs);
 753                 if (ret)
 754                         return ret;
 755         }
 756
 757         return 0;
 758 }
 759
 760 static int rockchip_pinctrl_parse_functions(struct device_node *np,
 761                                                 struct rockchip_pinctrl *info,
 762                                                 u32 index)
 763 {
 764         struct device_node *child;
 765         struct rockchip_pmx_func *func;
 766         struct rockchip_pin_group *grp;
 767         int ret;
 768         static u32 grp_index;
 769         u32 i = 0;
 770
 771         dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
 772
 773         func = &info->functions[index];
 774
 775         /* Initialise function */
 776         func->name = np->name;
 777         func->ngroups = of_get_child_count(np);
 778         if (func->ngroups <= 0)
 779                 return 0;
 780
 781         func->groups = devm_kzalloc(info->dev,
 782                         func->ngroups * sizeof(char *), GFP_KERNEL);
 783         if (!func->groups)
 784                 return -ENOMEM;
 785
 786         for_each_child_of_node(np, child) {
 787                 func->groups[i] = child->name;
 788                 grp = &info->groups[grp_index++];
 789                 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++);
 790                 if (ret)
 791                         return ret;
 792         }
 793
 794         return 0;
 795 }
 796
 797 static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
 798                                               struct rockchip_pinctrl *info)
 799 {
 800         struct device *dev = &pdev->dev;
 801         struct device_node *np = dev->of_node;
 802         struct device_node *child;
 803         int ret;
 804         int i;
 805
 806         rockchip_pinctrl_child_count(info, np);
 807
 808         dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
 809         dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
 810
 811         info->functions = devm_kzalloc(dev, info->nfunctions *
 812                                               sizeof(struct rockchip_pmx_func),
 813                                               GFP_KERNEL);
 814         if (!info->functions) {
 815                 dev_err(dev, "failed to allocate memory for function list\n");
 816                 return -EINVAL;
 817         }
 818
 819         info->groups = devm_kzalloc(dev, info->ngroups *
 820                                             sizeof(struct rockchip_pin_group),
 821                                             GFP_KERNEL);
 822         if (!info->groups) {
 823                 dev_err(dev, "failed allocate memory for ping group list\n");
 824                 return -EINVAL;
 825         }
 826
 827         i = 0;
 828
 829         for_each_child_of_node(np, child) {
 830                 if (of_match_node(rockchip_bank_match, child))
 831                         continue;
 832
 833                 ret = rockchip_pinctrl_parse_functions(child, info, i++);
 834                 if (ret) {
 835                         dev_err(&pdev->dev, "failed to parse function\n");
 836                         return ret;
 837                 }
 838         }
 839
 840         return 0;
 841 }
 842
 843 static int rockchip_pinctrl_register(struct platform_device *pdev,
 844                                         struct rockchip_pinctrl *info)
 845 {
 846         struct pinctrl_desc *ctrldesc = &info->pctl;
 847         struct pinctrl_pin_desc *pindesc, *pdesc;
 848         struct rockchip_pin_bank *pin_bank;
 849         int pin, bank, ret;
 850         int k;
 851
 852         ctrldesc->name = "rockchip-pinctrl";
 853         ctrldesc->owner = THIS_MODULE;
 854         ctrldesc->pctlops = &rockchip_pctrl_ops;
 855         ctrldesc->pmxops = &rockchip_pmx_ops;
 856         ctrldesc->confops = &rockchip_pinconf_ops;
 857
 858         pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) *
 859                         info->ctrl->nr_pins, GFP_KERNEL);
 860         if (!pindesc) {
 861                 dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n");
 862                 return -ENOMEM;
 863         }
 864         ctrldesc->pins = pindesc;
 865         ctrldesc->npins = info->ctrl->nr_pins;
 866
 867         pdesc = pindesc;
 868         for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) {
 869                 pin_bank = &info->ctrl->pin_banks[bank];
 870                 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
 871                         pdesc->number = k;
 872                         pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
 873                                                 pin_bank->name, pin);
 874                         pdesc++;
 875                 }
 876         }
 877
 878         info->pctl_dev = pinctrl_register(ctrldesc, &pdev->dev, info);
 879         if (!info->pctl_dev) {
 880                 dev_err(&pdev->dev, "could not register pinctrl driver\n");
 881                 return -EINVAL;
 882         }
 883
 884         for (bank = 0; bank < info->ctrl->nr_banks; ++bank) {
 885                 pin_bank = &info->ctrl->pin_banks[bank];
 886                 pin_bank->grange.name = pin_bank->name;
 887                 pin_bank->grange.id = bank;
 888                 pin_bank->grange.pin_base = pin_bank->pin_base;
 889                 pin_bank->grange.base = pin_bank->gpio_chip.base;
 890                 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio;
 891                 pin_bank->grange.gc = &pin_bank->gpio_chip;
 892                 pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange);
 893         }
 894
 895         ret = rockchip_pinctrl_parse_dt(pdev, info);
 896         if (ret) {
 897                 pinctrl_unregister(info->pctl_dev);
 898                 return ret;
 899         }
 900
 901         return 0;
 902 }
 903
 904 /*
 905  * GPIO handling
 906  */
 907
 908 static int rockchip_gpio_request(struct gpio_chip *chip, unsigned offset)
 909 {
 910         return pinctrl_request_gpio(chip->base + offset);
 911 }
 912
 913 static void rockchip_gpio_free(struct gpio_chip *chip, unsigned offset)
 914 {
 915         pinctrl_free_gpio(chip->base + offset);
 916 }
 917
 918 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
 919 {
 920         struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
 921         void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR;
 922         unsigned long flags;
 923         u32 data;
 924
 925         spin_lock_irqsave(&bank->slock, flags);
 926
 927         data = readl(reg);
 928         data &= ~BIT(offset);
 929         if (value)
 930                 data |= BIT(offset);
 931         writel(data, reg);
 932
 933         spin_unlock_irqrestore(&bank->slock, flags);
 934 }
 935
 936 /*
 937  * Returns the level of the pin for input direction and setting of the DR
 938  * register for output gpios.
 939  */
 940 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset)
 941 {
 942         struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
 943         u32 data;
 944
 945         data = readl(bank->reg_base + GPIO_EXT_PORT);
 946         data >>= offset;
 947         data &= 1;
 948         return data;
 949 }
 950
 951 /*
 952  * gpiolib gpio_direction_input callback function. The setting of the pin
 953  * mux function as 'gpio input' will be handled by the pinctrl susbsystem
 954  * interface.
 955  */
 956 static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
 957 {
 958         return pinctrl_gpio_direction_input(gc->base + offset);
 959 }
 960
 961 /*
 962  * gpiolib gpio_direction_output callback function. The setting of the pin
 963  * mux function as 'gpio output' will be handled by the pinctrl susbsystem
 964  * interface.
 965  */
 966 static int rockchip_gpio_direction_output(struct gpio_chip *gc,
 967                                           unsigned offset, int value)
 968 {
 969         rockchip_gpio_set(gc, offset, value);
 970         return pinctrl_gpio_direction_output(gc->base + offset);
 971 }
 972
 973 /*
 974  * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
 975  * and a virtual IRQ, if not already present.
 976  */
 977 static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
 978 {
 979         struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
 980         unsigned int virq;
 981
 982         if (!bank->domain)
 983                 return -ENXIO;
 984
 985         virq = irq_create_mapping(bank->domain, offset);
 986
 987         return (virq) ? : -ENXIO;
 988 }
 989
 990 static const struct gpio_chip rockchip_gpiolib_chip = {
 991         .request = rockchip_gpio_request,
 992         .free = rockchip_gpio_free,
 993         .set = rockchip_gpio_set,
 994         .get = rockchip_gpio_get,
 995         .direction_input = rockchip_gpio_direction_input,
 996         .direction_output = rockchip_gpio_direction_output,
 997         .to_irq = rockchip_gpio_to_irq,
 998         .owner = THIS_MODULE,
 999 };
1000
1001 /*
1002  * Interrupt handling
1003  */
1004
1005 static void rockchip_irq_demux(unsigned int irq, struct irq_desc *desc)
1006 {
1007         struct irq_chip *chip = irq_get_chip(irq);
1008         struct rockchip_pin_bank *bank = irq_get_handler_data(irq);
1009         u32 pend;
1010
1011         dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name);
1012
1013         chained_irq_enter(chip, desc);
1014
1015         pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS);
1016
1017         while (pend) {
1018                 unsigned int virq;
1019
1020                 irq = __ffs(pend);
1021                 pend &= ~BIT(irq);
1022                 virq = irq_linear_revmap(bank->domain, irq);
1023
1024                 if (!virq) {
1025                         dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq);
1026                         continue;
1027                 }
1028
1029                 dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq);
1030
1031                 generic_handle_irq(virq);
1032         }
1033
1034         chained_irq_exit(chip, desc);
1035 }
1036
1037 static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
1038 {
1039         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
1040         struct rockchip_pin_bank *bank = gc->private;
1041         u32 mask = BIT(d->hwirq);
1042         u32 polarity;
1043         u32 level;
1044         u32 data;
1045
1046         if (type & IRQ_TYPE_EDGE_BOTH)
1047                 __irq_set_handler_locked(d->irq, handle_edge_irq);
1048         else
1049                 __irq_set_handler_locked(d->irq, handle_level_irq);
1050
1051         irq_gc_lock(gc);
1052
1053         level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL);
1054         polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY);
1055
1056         switch (type) {
1057         case IRQ_TYPE_EDGE_RISING:
1058                 level |= mask;
1059                 polarity |= mask;
1060                 break;
1061         case IRQ_TYPE_EDGE_FALLING:
1062                 level |= mask;
1063                 polarity &= ~mask;
1064                 break;
1065         case IRQ_TYPE_LEVEL_HIGH:
1066                 level &= ~mask;
1067                 polarity |= mask;
1068                 break;
1069         case IRQ_TYPE_LEVEL_LOW:
1070                 level &= ~mask;
1071                 polarity &= ~mask;
1072                 break;
1073         default:
1074                 irq_gc_unlock(gc);
1075                 return -EINVAL;
1076         }
1077
1078         writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL);
1079         writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY);
1080
1081         irq_gc_unlock(gc);
1082
1083         /* make sure the pin is configured as gpio input */
1084         rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO);
1085         data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
1086         data &= ~mask;
1087         writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
1088
1089         return 0;
1090 }
1091
1092 static int rockchip_interrupts_register(struct platform_device *pdev,
1093                                                 struct rockchip_pinctrl *info)
1094 {
1095         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1096         struct rockchip_pin_bank *bank = ctrl->pin_banks;
1097         unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
1098         struct irq_chip_generic *gc;
1099         int ret;
1100         int i;
1101
1102         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1103                 if (!bank->valid) {
1104                         dev_warn(&pdev->dev, "bank %s is not valid\n",
1105                                  bank->name);
1106                         continue;
1107                 }
1108
1109                 bank->domain = irq_domain_add_linear(bank->of_node, 32,
1110                                                 &irq_generic_chip_ops, NULL);
1111                 if (!bank->domain) {
1112                         dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n",
1113                                  bank->name);
1114                         continue;
1115                 }
1116
1117                 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
1118                                          "rockchip_gpio_irq", handle_level_irq,
1119                                          clr, 0, IRQ_GC_INIT_MASK_CACHE);
1120                 if (ret) {
1121                         dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n",
1122                                 bank->name);
1123                         irq_domain_remove(bank->domain);
1124                         continue;
1125                 }
1126
1127                 gc = irq_get_domain_generic_chip(bank->domain, 0);
1128                 gc->reg_base = bank->reg_base;
1129                 gc->private = bank;
1130                 gc->chip_types[0].regs.mask = GPIO_INTEN;
1131                 gc->chip_types[0].regs.ack = GPIO_PORTS_EOI;
1132                 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
1133                 gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
1134                 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
1135                 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
1136                 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
1137
1138                 irq_set_handler_data(bank->irq, bank);
1139                 irq_set_chained_handler(bank->irq, rockchip_irq_demux);
1140         }
1141
1142         return 0;
1143 }
1144
1145 static int rockchip_gpiolib_register(struct platform_device *pdev,
1146                                                 struct rockchip_pinctrl *info)
1147 {
1148         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1149         struct rockchip_pin_bank *bank = ctrl->pin_banks;
1150         struct gpio_chip *gc;
1151         int ret;
1152         int i;
1153
1154         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1155                 if (!bank->valid) {
1156                         dev_warn(&pdev->dev, "bank %s is not valid\n",
1157                                  bank->name);
1158                         continue;
1159                 }
1160
1161                 bank->gpio_chip = rockchip_gpiolib_chip;
1162
1163                 gc = &bank->gpio_chip;
1164                 gc->base = bank->pin_base;
1165                 gc->ngpio = bank->nr_pins;
1166                 gc->dev = &pdev->dev;
1167                 gc->of_node = bank->of_node;
1168                 gc->label = bank->name;
1169
1170                 ret = gpiochip_add(gc);
1171                 if (ret) {
1172                         dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n",
1173                                                         gc->label, ret);
1174                         goto fail;
1175                 }
1176         }
1177
1178         rockchip_interrupts_register(pdev, info);
1179
1180         return 0;
1181
1182 fail:
1183         for (--i, --bank; i >= 0; --i, --bank) {
1184                 if (!bank->valid)
1185                         continue;
1186
1187                 if (gpiochip_remove(&bank->gpio_chip))
1188                         dev_err(&pdev->dev, "gpio chip %s remove failed\n",
1189                                                         bank->gpio_chip.label);
1190         }
1191         return ret;
1192 }
1193
1194 static int rockchip_gpiolib_unregister(struct platform_device *pdev,
1195                                                 struct rockchip_pinctrl *info)
1196 {
1197         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1198         struct rockchip_pin_bank *bank = ctrl->pin_banks;
1199         int ret = 0;
1200         int i;
1201
1202         for (i = 0; !ret && i < ctrl->nr_banks; ++i, ++bank) {
1203                 if (!bank->valid)
1204                         continue;
1205
1206                 ret = gpiochip_remove(&bank->gpio_chip);
1207         }
1208
1209         if (ret)
1210                 dev_err(&pdev->dev, "gpio chip remove failed\n");
1211
1212         return ret;
1213 }
1214
1215 static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
1216                                   struct device *dev)
1217 {
1218         struct resource res;
1219
1220         if (of_address_to_resource(bank->of_node, 0, &res)) {
1221                 dev_err(dev, "cannot find IO resource for bank\n");
1222                 return -ENOENT;
1223         }
1224
1225         bank->reg_base = devm_ioremap_resource(dev, &res);
1226         if (IS_ERR(bank->reg_base))
1227                 return PTR_ERR(bank->reg_base);
1228
1229         bank->bank_type = COMMON_BANK;
1230
1231         bank->irq = irq_of_parse_and_map(bank->of_node, 0);
1232
1233         bank->clk = of_clk_get(bank->of_node, 0);
1234         if (IS_ERR(bank->clk))
1235                 return PTR_ERR(bank->clk);
1236
1237         return clk_prepare_enable(bank->clk);
1238 }
1239
1240 static const struct of_device_id rockchip_pinctrl_dt_match[];
1241
1242 /* retrieve the soc specific data */
1243 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
1244                                                 struct rockchip_pinctrl *d,
1245                                                 struct platform_device *pdev)
1246 {
1247         const struct of_device_id *match;
1248         struct device_node *node = pdev->dev.of_node;
1249         struct device_node *np;
1250         struct rockchip_pin_ctrl *ctrl;
1251         struct rockchip_pin_bank *bank;
1252         int i;
1253
1254         match = of_match_node(rockchip_pinctrl_dt_match, node);
1255         ctrl = (struct rockchip_pin_ctrl *)match->data;
1256
1257         for_each_child_of_node(node, np) {
1258                 if (!of_find_property(np, "gpio-controller", NULL))
1259                         continue;
1260
1261                 bank = ctrl->pin_banks;
1262                 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1263                         if (!strcmp(bank->name, np->name)) {
1264                                 bank->of_node = np;
1265
1266                                 if (!rockchip_get_bank_data(bank, &pdev->dev))
1267                                         bank->valid = true;
1268
1269                                 break;
1270                         }
1271                 }
1272         }
1273
1274         bank = ctrl->pin_banks;
1275         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1276                 spin_lock_init(&bank->slock);
1277                 bank->drvdata = d;
1278                 bank->pin_base = ctrl->nr_pins;
1279                 ctrl->nr_pins += bank->nr_pins;
1280         }
1281
1282         return ctrl;
1283 }
1284
1285 static int rockchip_pinctrl_probe(struct platform_device *pdev)
1286 {
1287         struct rockchip_pinctrl *info;
1288         struct device *dev = &pdev->dev;
1289         struct rockchip_pin_ctrl *ctrl;
1290         struct resource *res;
1291         int ret;
1292
1293         if (!dev->of_node) {
1294                 dev_err(dev, "device tree node not found\n");
1295                 return -ENODEV;
1296         }
1297
1298         info = devm_kzalloc(dev, sizeof(struct rockchip_pinctrl), GFP_KERNEL);
1299         if (!info)
1300                 return -ENOMEM;
1301
1302         ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
1303         if (!ctrl) {
1304                 dev_err(dev, "driver data not available\n");
1305                 return -EINVAL;
1306         }
1307         info->ctrl = ctrl;
1308         info->dev = dev;
1309
1310         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1311         info->reg_base = devm_ioremap_resource(&pdev->dev, res);
1312         if (IS_ERR(info->reg_base))
1313                 return PTR_ERR(info->reg_base);
1314
1315         ret = rockchip_gpiolib_register(pdev, info);
1316         if (ret)
1317                 return ret;
1318
1319         ret = rockchip_pinctrl_register(pdev, info);
1320         if (ret) {
1321                 rockchip_gpiolib_unregister(pdev, info);
1322                 return ret;
1323         }
1324
1325         platform_set_drvdata(pdev, info);
1326
1327         return 0;
1328 }
1329
1330 static struct rockchip_pin_bank rk2928_pin_banks[] = {
1331         PIN_BANK(0, 32, "gpio0"),
1332         PIN_BANK(1, 32, "gpio1"),
1333         PIN_BANK(2, 32, "gpio2"),
1334         PIN_BANK(3, 32, "gpio3"),
1335 };
1336
1337 static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
1338                 .pin_banks              = rk2928_pin_banks,
1339                 .nr_banks               = ARRAY_SIZE(rk2928_pin_banks),
1340                 .label                  = "RK2928-GPIO",
1341                 .type                   = RK2928,
1342                 .mux_offset             = 0xa8,
1343                 .pull_calc_reg          = rk2928_calc_pull_reg_and_bit,
1344 };
1345
1346 static struct rockchip_pin_bank rk3066a_pin_banks[] = {
1347         PIN_BANK(0, 32, "gpio0"),
1348         PIN_BANK(1, 32, "gpio1"),
1349         PIN_BANK(2, 32, "gpio2"),
1350         PIN_BANK(3, 32, "gpio3"),
1351         PIN_BANK(4, 32, "gpio4"),
1352         PIN_BANK(6, 16, "gpio6"),
1353 };
1354
1355 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
1356                 .pin_banks              = rk3066a_pin_banks,
1357                 .nr_banks               = ARRAY_SIZE(rk3066a_pin_banks),
1358                 .label                  = "RK3066a-GPIO",
1359                 .type                   = RK2928,
1360                 .mux_offset             = 0xa8,
1361                 .pull_calc_reg          = rk2928_calc_pull_reg_and_bit,
1362 };
1363
1364 static struct rockchip_pin_bank rk3066b_pin_banks[] = {
1365         PIN_BANK(0, 32, "gpio0"),
1366         PIN_BANK(1, 32, "gpio1"),
1367         PIN_BANK(2, 32, "gpio2"),
1368         PIN_BANK(3, 32, "gpio3"),
1369 };
1370
1371 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
1372                 .pin_banks      = rk3066b_pin_banks,
1373                 .nr_banks       = ARRAY_SIZE(rk3066b_pin_banks),
1374                 .label          = "RK3066b-GPIO",
1375                 .type           = RK3066B,
1376                 .mux_offset     = 0x60,
1377 };
1378
1379 static struct rockchip_pin_bank rk3188_pin_banks[] = {
1380         PIN_BANK(0, 32, "gpio0"),
1381         PIN_BANK(1, 32, "gpio1"),
1382         PIN_BANK(2, 32, "gpio2"),
1383         PIN_BANK(3, 32, "gpio3"),
1384 };
1385
1386 static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
1387                 .pin_banks              = rk3188_pin_banks,
1388                 .nr_banks               = ARRAY_SIZE(rk3188_pin_banks),
1389                 .label                  = "RK3188-GPIO",
1390                 .type                   = RK3188,
1391                 .mux_offset             = 0x68,
1392 };
1393
1394 static const struct of_device_id rockchip_pinctrl_dt_match[] = {
1395         { .compatible = "rockchip,rk2928-pinctrl",
1396                 .data = (void *)&rk2928_pin_ctrl },
1397         { .compatible = "rockchip,rk3066a-pinctrl",
1398                 .data = (void *)&rk3066a_pin_ctrl },
1399         { .compatible = "rockchip,rk3066b-pinctrl",
1400                 .data = (void *)&rk3066b_pin_ctrl },
1401         { .compatible = "rockchip,rk3188-pinctrl",
1402                 .data = (void *)&rk3188_pin_ctrl },
1403         {},
1404 };
1405 MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match);
1406
1407 static struct platform_driver rockchip_pinctrl_driver = {
1408         .probe          = rockchip_pinctrl_probe,
1409         .driver = {
1410                 .name   = "rockchip-pinctrl",
1411                 .owner  = THIS_MODULE,
1412                 .of_match_table = rockchip_pinctrl_dt_match,
1413         },
1414 };
1415
1416 static int __init rockchip_pinctrl_drv_register(void)
1417 {
1418         return platform_driver_register(&rockchip_pinctrl_driver);
1419 }
1420 postcore_initcall(rockchip_pinctrl_drv_register);
1421
1422 MODULE_AUTHOR("Heiko Stuebner <heiko@sntech.de>");
1423 MODULE_DESCRIPTION("Rockchip pinctrl driver");
1424 MODULE_LICENSE("GPL v2");