drivers/pinctrl/pinctrl-rockchip.c

   1 /*
   2  * Pinctrl driver for Rockchip SoCs
   3  *
   4  * Copyright (c) 2013 MundoReader S.L.
   5  * Author: Heiko Stuebner <heiko@sntech.de>
   6  *
   7  * With some ideas taken from pinctrl-samsung:
   8  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
   9  *              http://www.samsung.com
  10  * Copyright (c) 2012 Linaro Ltd
  11  *              http://www.linaro.org
  12  *
  13  * and pinctrl-at91:
  14  * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as published
  18  * by the Free Software Foundation.
  19  *
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  * GNU General Public License for more details.
  24  */
  25
  26 #include <linux/module.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/io.h>
  29 #include <linux/bitops.h>
  30 #include <linux/gpio.h>
  31 #include <linux/of_address.h>
  32 #include <linux/of_irq.h>
  33 #include <linux/pinctrl/machine.h>
  34 #include <linux/pinctrl/pinconf.h>
  35 #include <linux/pinctrl/pinctrl.h>
  36 #include <linux/pinctrl/pinmux.h>
  37 #include <linux/pinctrl/pinconf-generic.h>
  38 #include <linux/irqchip/chained_irq.h>
  39 #include <linux/clk.h>
  40 #include <dt-bindings/pinctrl/rockchip.h>
  41
  42 #include "core.h"
  43 #include "pinconf.h"
  44
  45 /* GPIO control registers */
  46 #define GPIO_SWPORT_DR          0x00
  47 #define GPIO_SWPORT_DDR         0x04
  48 #define GPIO_INTEN              0x30
  49 #define GPIO_INTMASK            0x34
  50 #define GPIO_INTTYPE_LEVEL      0x38
  51 #define GPIO_INT_POLARITY       0x3c
  52 #define GPIO_INT_STATUS         0x40
  53 #define GPIO_INT_RAWSTATUS      0x44
  54 #define GPIO_DEBOUNCE           0x48
  55 #define GPIO_PORTS_EOI          0x4c
  56 #define GPIO_EXT_PORT           0x50
  57 #define GPIO_LS_SYNC            0x60
  58
  59 enum rockchip_pinctrl_type {
  60         RK2928,
  61         RK3066B,
  62         RK3188,
  63 };
  64
  65 /**
  66  * @reg_base: register base of the gpio bank
  67  * @clk: clock of the gpio bank
  68  * @irq: interrupt of the gpio bank
  69  * @pin_base: first pin number
  70  * @nr_pins: number of pins in this bank
  71  * @name: name of the bank
  72  * @bank_num: number of the bank, to account for holes
  73  * @valid: are all necessary informations present
  74  * @of_node: dt node of this bank
  75  * @drvdata: common pinctrl basedata
  76  * @domain: irqdomain of the gpio bank
  77  * @gpio_chip: gpiolib chip
  78  * @grange: gpio range
  79  * @slock: spinlock for the gpio bank
  80  */
  81 struct rockchip_pin_bank {
  82         void __iomem                    *reg_base;
  83         struct clk                      *clk;
  84         int                             irq;
  85         u32                             pin_base;
  86         u8                              nr_pins;
  87         char                            *name;
  88         u8                              bank_num;
  89         bool                            valid;
  90         struct device_node              *of_node;
  91         struct rockchip_pinctrl         *drvdata;
  92         struct irq_domain               *domain;
  93         struct gpio_chip                gpio_chip;
  94         struct pinctrl_gpio_range       grange;
  95         spinlock_t                      slock;
  96
  97 };
  98
  99 #define PIN_BANK(id, pins, label)                       \
 100         {                                               \
 101                 .bank_num       = id,                   \
 102                 .nr_pins        = pins,                 \
 103                 .name           = label,                \
 104         }
 105
 106 /**
 107  */
 108 struct rockchip_pin_ctrl {
 109         struct rockchip_pin_bank        *pin_banks;
 110         u32                             nr_banks;
 111         u32                             nr_pins;
 112         char                            *label;
 113         enum rockchip_pinctrl_type      type;
 114         int                             mux_offset;
 115         void    (*pull_calc_reg)(struct rockchip_pin_bank *bank, int pin_num,
 116                                  void __iomem **reg, u8 *bit);
 117 };
 118
 119 struct rockchip_pin_config {
 120         unsigned int            func;
 121         unsigned long           *configs;
 122         unsigned int            nconfigs;
 123 };
 124
 125 /**
 126  * struct rockchip_pin_group: represent group of pins of a pinmux function.
 127  * @name: name of the pin group, used to lookup the group.
 128  * @pins: the pins included in this group.
 129  * @npins: number of pins included in this group.
 130  * @func: the mux function number to be programmed when selected.
 131  * @configs: the config values to be set for each pin
 132  * @nconfigs: number of configs for each pin
 133  */
 134 struct rockchip_pin_group {
 135         const char                      *name;
 136         unsigned int                    npins;
 137         unsigned int                    *pins;
 138         struct rockchip_pin_config      *data;
 139 };
 140
 141 /**
 142  * struct rockchip_pmx_func: represent a pin function.
 143  * @name: name of the pin function, used to lookup the function.
 144  * @groups: one or more names of pin groups that provide this function.
 145  * @num_groups: number of groups included in @groups.
 146  */
 147 struct rockchip_pmx_func {
 148         const char              *name;
 149         const char              **groups;
 150         u8                      ngroups;
 151 };
 152
 153 struct rockchip_pinctrl {
 154         void __iomem                    *reg_base;
 155         struct device                   *dev;
 156         struct rockchip_pin_ctrl        *ctrl;
 157         struct pinctrl_desc             pctl;
 158         struct pinctrl_dev              *pctl_dev;
 159         struct rockchip_pin_group       *groups;
 160         unsigned int                    ngroups;
 161         struct rockchip_pmx_func        *functions;
 162         unsigned int                    nfunctions;
 163 };
 164
 165 static inline struct rockchip_pin_bank *gc_to_pin_bank(struct gpio_chip *gc)
 166 {
 167         return container_of(gc, struct rockchip_pin_bank, gpio_chip);
 168 }
 169
 170 static const inline struct rockchip_pin_group *pinctrl_name_to_group(
 171                                         const struct rockchip_pinctrl *info,
 172                                         const char *name)
 173 {
 174         int i;
 175
 176         for (i = 0; i < info->ngroups; i++) {
 177                 if (!strcmp(info->groups[i].name, name))
 178                         return &info->groups[i];
 179         }
 180
 181         return NULL;
 182 }
 183
 184 /*
 185  * given a pin number that is local to a pin controller, find out the pin bank
 186  * and the register base of the pin bank.
 187  */
 188 static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info,
 189                                                                 unsigned pin)
 190 {
 191         struct rockchip_pin_bank *b = info->ctrl->pin_banks;
 192
 193         while (pin >= (b->pin_base + b->nr_pins))
 194                 b++;
 195
 196         return b;
 197 }
 198
 199 static struct rockchip_pin_bank *bank_num_to_bank(
 200                                         struct rockchip_pinctrl *info,
 201                                         unsigned num)
 202 {
 203         struct rockchip_pin_bank *b = info->ctrl->pin_banks;
 204         int i;
 205
 206         for (i = 0; i < info->ctrl->nr_banks; i++, b++) {
 207                 if (b->bank_num == num)
 208                         return b;
 209         }
 210
 211         return ERR_PTR(-EINVAL);
 212 }
 213
 214 /*
 215  * Pinctrl_ops handling
 216  */
 217
 218 static int rockchip_get_groups_count(struct pinctrl_dev *pctldev)
 219 {
 220         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 221
 222         return info->ngroups;
 223 }
 224
 225 static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev,
 226                                                         unsigned selector)
 227 {
 228         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 229
 230         return info->groups[selector].name;
 231 }
 232
 233 static int rockchip_get_group_pins(struct pinctrl_dev *pctldev,
 234                                       unsigned selector, const unsigned **pins,
 235                                       unsigned *npins)
 236 {
 237         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 238
 239         if (selector >= info->ngroups)
 240                 return -EINVAL;
 241
 242         *pins = info->groups[selector].pins;
 243         *npins = info->groups[selector].npins;
 244
 245         return 0;
 246 }
 247
 248 static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev,
 249                                  struct device_node *np,
 250                                  struct pinctrl_map **map, unsigned *num_maps)
 251 {
 252         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 253         const struct rockchip_pin_group *grp;
 254         struct pinctrl_map *new_map;
 255         struct device_node *parent;
 256         int map_num = 1;
 257         int i;
 258
 259         /*
 260          * first find the group of this node and check if we need to create
 261          * config maps for pins
 262          */
 263         grp = pinctrl_name_to_group(info, np->name);
 264         if (!grp) {
 265                 dev_err(info->dev, "unable to find group for node %s\n",
 266                         np->name);
 267                 return -EINVAL;
 268         }
 269
 270         map_num += grp->npins;
 271         new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num,
 272                                                                 GFP_KERNEL);
 273         if (!new_map)
 274                 return -ENOMEM;
 275
 276         *map = new_map;
 277         *num_maps = map_num;
 278
 279         /* create mux map */
 280         parent = of_get_parent(np);
 281         if (!parent) {
 282                 devm_kfree(pctldev->dev, new_map);
 283                 return -EINVAL;
 284         }
 285         new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
 286         new_map[0].data.mux.function = parent->name;
 287         new_map[0].data.mux.group = np->name;
 288         of_node_put(parent);
 289
 290         /* create config map */
 291         new_map++;
 292         for (i = 0; i < grp->npins; i++) {
 293                 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
 294                 new_map[i].data.configs.group_or_pin =
 295                                 pin_get_name(pctldev, grp->pins[i]);
 296                 new_map[i].data.configs.configs = grp->data[i].configs;
 297                 new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
 298         }
 299
 300         dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
 301                 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
 302
 303         return 0;
 304 }
 305
 306 static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
 307                                     struct pinctrl_map *map, unsigned num_maps)
 308 {
 309 }
 310
 311 static const struct pinctrl_ops rockchip_pctrl_ops = {
 312         .get_groups_count       = rockchip_get_groups_count,
 313         .get_group_name         = rockchip_get_group_name,
 314         .get_group_pins         = rockchip_get_group_pins,
 315         .dt_node_to_map         = rockchip_dt_node_to_map,
 316         .dt_free_map            = rockchip_dt_free_map,
 317 };
 318
 319 /*
 320  * Hardware access
 321  */
 322
 323 /*
 324  * Set a new mux function for a pin.
 325  *
 326  * The register is divided into the upper and lower 16 bit. When changing
 327  * a value, the previous register value is not read and changed. Instead
 328  * it seems the changed bits are marked in the upper 16 bit, while the
 329  * changed value gets set in the same offset in the lower 16 bit.
 330  * All pin settings seem to be 2 bit wide in both the upper and lower
 331  * parts.
 332  * @bank: pin bank to change
 333  * @pin: pin to change
 334  * @mux: new mux function to set
 335  */
 336 static void rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
 337 {
 338         struct rockchip_pinctrl *info = bank->drvdata;
 339         void __iomem *reg = info->reg_base + info->ctrl->mux_offset;
 340         unsigned long flags;
 341         u8 bit;
 342         u32 data;
 343
 344         dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n",
 345                                                 bank->bank_num, pin, mux);
 346
 347         /* get basic quadrupel of mux registers and the correct reg inside */
 348         reg += bank->bank_num * 0x10;
 349         reg += (pin / 8) * 4;
 350         bit = (pin % 8) * 2;
 351
 352         spin_lock_irqsave(&bank->slock, flags);
 353
 354         data = (3 << (bit + 16));
 355         data |= (mux & 3) << bit;
 356         writel(data, reg);
 357
 358         spin_unlock_irqrestore(&bank->slock, flags);
 359 }
 360
 361 #define RK2928_PULL_OFFSET              0x118
 362 #define RK2928_PULL_PINS_PER_REG        16
 363 #define RK2928_PULL_BANK_STRIDE         8
 364
 365 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
 366                                     int pin_num, void __iomem **reg, u8 *bit)
 367 {
 368         struct rockchip_pinctrl *info = bank->drvdata;
 369
 370         *reg = info->reg_base + RK2928_PULL_OFFSET;
 371         *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
 372         *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4;
 373
 374         *bit = pin_num % RK2928_PULL_PINS_PER_REG;
 375 };
 376
 377 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
 378 {
 379         struct rockchip_pinctrl *info = bank->drvdata;
 380         struct rockchip_pin_ctrl *ctrl = info->ctrl;
 381         void __iomem *reg;
 382         u8 bit;
 383
 384         /* rk3066b does support any pulls */
 385         if (ctrl->type == RK3066B)
 386                 return PIN_CONFIG_BIAS_DISABLE;
 387
 388         switch (ctrl->type) {
 389         case RK2928:
 390                 ctrl->pull_calc_reg(bank, pin_num, &reg, &bit);
 391                 return !(readl_relaxed(reg) & BIT(bit))
 392                                 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
 393                                 : PIN_CONFIG_BIAS_DISABLE;
 394         case RK3188:
 395                 dev_err(info->dev, "pull support for rk31xx not implemented\n");
 396                 return -EIO;
 397         default:
 398                 dev_err(info->dev, "unsupported pinctrl type\n");
 399                 return -EINVAL;
 400         };
 401 }
 402
 403 static int rockchip_set_pull(struct rockchip_pin_bank *bank,
 404                                         int pin_num, int pull)
 405 {
 406         struct rockchip_pinctrl *info = bank->drvdata;
 407         struct rockchip_pin_ctrl *ctrl = info->ctrl;
 408         void __iomem *reg;
 409         unsigned long flags;
 410         u8 bit;
 411         u32 data;
 412
 413         dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n",
 414                  bank->bank_num, pin_num, pull);
 415
 416         /* rk3066b does support any pulls */
 417         if (ctrl->type == RK3066B)
 418                 return pull ? -EINVAL : 0;
 419
 420         switch (ctrl->type) {
 421         case RK2928:
 422                 if (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT &&
 423                                         pull != PIN_CONFIG_BIAS_DISABLE) {
 424                         dev_err(info->dev, "only PIN_DEFAULT and DISABLE allowed\n");
 425                         return -EINVAL;
 426                 }
 427
 428                 ctrl->pull_calc_reg(bank, pin_num, &reg, &bit);
 429
 430                 spin_lock_irqsave(&bank->slock, flags);
 431
 432                 data = BIT(bit + 16);
 433                 if (pull == PIN_CONFIG_BIAS_DISABLE)
 434                         data |= BIT(bit);
 435                 writel(data, reg);
 436
 437                 spin_unlock_irqrestore(&bank->slock, flags);
 438                 break;
 439         case RK3188:
 440                 dev_err(info->dev, "pull support for rk31xx not implemented\n");
 441                 return -EIO;
 442         default:
 443                 dev_err(info->dev, "unsupported pinctrl type\n");
 444                 return -EINVAL;
 445         }
 446
 447         return 0;
 448 }
 449
 450 /*
 451  * Pinmux_ops handling
 452  */
 453
 454 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
 455 {
 456         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 457
 458         return info->nfunctions;
 459 }
 460
 461 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev,
 462                                           unsigned selector)
 463 {
 464         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 465
 466         return info->functions[selector].name;
 467 }
 468
 469 static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
 470                                 unsigned selector, const char * const **groups,
 471                                 unsigned * const num_groups)
 472 {
 473         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 474
 475         *groups = info->functions[selector].groups;
 476         *num_groups = info->functions[selector].ngroups;
 477
 478         return 0;
 479 }
 480
 481 static int rockchip_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
 482                                                             unsigned group)
 483 {
 484         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 485         const unsigned int *pins = info->groups[group].pins;
 486         const struct rockchip_pin_config *data = info->groups[group].data;
 487         struct rockchip_pin_bank *bank;
 488         int cnt;
 489
 490         dev_dbg(info->dev, "enable function %s group %s\n",
 491                 info->functions[selector].name, info->groups[group].name);
 492
 493         /*
 494          * for each pin in the pin group selected, program the correspoding pin
 495          * pin function number in the config register.
 496          */
 497         for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
 498                 bank = pin_to_bank(info, pins[cnt]);
 499                 rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
 500                                  data[cnt].func);
 501         }
 502
 503         return 0;
 504 }
 505
 506 static void rockchip_pmx_disable(struct pinctrl_dev *pctldev,
 507                                         unsigned selector, unsigned group)
 508 {
 509         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 510         const unsigned int *pins = info->groups[group].pins;
 511         struct rockchip_pin_bank *bank;
 512         int cnt;
 513
 514         dev_dbg(info->dev, "disable function %s group %s\n",
 515                 info->functions[selector].name, info->groups[group].name);
 516
 517         for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
 518                 bank = pin_to_bank(info, pins[cnt]);
 519                 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
 520         }
 521 }
 522
 523 /*
 524  * The calls to gpio_direction_output() and gpio_direction_input()
 525  * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
 526  * function called from the gpiolib interface).
 527  */
 528 static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
 529                                               struct pinctrl_gpio_range *range,
 530                                               unsigned offset, bool input)
 531 {
 532         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 533         struct rockchip_pin_bank *bank;
 534         struct gpio_chip *chip;
 535         int pin;
 536         u32 data;
 537
 538         chip = range->gc;
 539         bank = gc_to_pin_bank(chip);
 540         pin = offset - chip->base;
 541
 542         dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
 543                  offset, range->name, pin, input ? "input" : "output");
 544
 545         rockchip_set_mux(bank, pin, RK_FUNC_GPIO);
 546
 547         data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
 548         /* set bit to 1 for output, 0 for input */
 549         if (!input)
 550                 data |= BIT(pin);
 551         else
 552                 data &= ~BIT(pin);
 553         writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
 554
 555         return 0;
 556 }
 557
 558 static const struct pinmux_ops rockchip_pmx_ops = {
 559         .get_functions_count    = rockchip_pmx_get_funcs_count,
 560         .get_function_name      = rockchip_pmx_get_func_name,
 561         .get_function_groups    = rockchip_pmx_get_groups,
 562         .enable                 = rockchip_pmx_enable,
 563         .disable                = rockchip_pmx_disable,
 564         .gpio_set_direction     = rockchip_pmx_gpio_set_direction,
 565 };
 566
 567 /*
 568  * Pinconf_ops handling
 569  */
 570
 571 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
 572                                         enum pin_config_param pull)
 573 {
 574         switch (ctrl->type) {
 575         case RK2928:
 576                 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
 577                                         pull == PIN_CONFIG_BIAS_DISABLE);
 578         case RK3066B:
 579                 return pull ? false : true;
 580         case RK3188:
 581                 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
 582         }
 583
 584         return false;
 585 }
 586
 587 /* set the pin config settings for a specified pin */
 588 static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
 589                                 unsigned long *configs, unsigned num_configs)
 590 {
 591         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 592         struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
 593         enum pin_config_param param;
 594         u16 arg;
 595         int i;
 596         int rc;
 597
 598         for (i = 0; i < num_configs; i++) {
 599                 param = pinconf_to_config_param(configs[i]);
 600                 arg = pinconf_to_config_argument(configs[i]);
 601
 602                 switch (param) {
 603                 case PIN_CONFIG_BIAS_DISABLE:
 604                         rc =  rockchip_set_pull(bank, pin - bank->pin_base,
 605                                 param);
 606                         if (rc)
 607                                 return rc;
 608                         break;
 609                 case PIN_CONFIG_BIAS_PULL_UP:
 610                 case PIN_CONFIG_BIAS_PULL_DOWN:
 611                 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
 612                         if (!rockchip_pinconf_pull_valid(info->ctrl, param))
 613                                 return -ENOTSUPP;
 614
 615                         if (!arg)
 616                                 return -EINVAL;
 617
 618                         rc = rockchip_set_pull(bank, pin - bank->pin_base,
 619                                 param);
 620                         if (rc)
 621                                 return rc;
 622                         break;
 623                 default:
 624                         return -ENOTSUPP;
 625                         break;
 626                 }
 627         } /* for each config */
 628
 629         return 0;
 630 }
 631
 632 /* get the pin config settings for a specified pin */
 633 static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
 634                                                         unsigned long *config)
 635 {
 636         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 637         struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
 638         enum pin_config_param param = pinconf_to_config_param(*config);
 639
 640         switch (param) {
 641         case PIN_CONFIG_BIAS_DISABLE:
 642                 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
 643                         return -EINVAL;
 644
 645                 *config = 0;
 646                 break;
 647         case PIN_CONFIG_BIAS_PULL_UP:
 648         case PIN_CONFIG_BIAS_PULL_DOWN:
 649         case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
 650                 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
 651                         return -ENOTSUPP;
 652
 653                 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
 654                         return -EINVAL;
 655
 656                 *config = 1;
 657                 break;
 658         default:
 659                 return -ENOTSUPP;
 660                 break;
 661         }
 662
 663         return 0;
 664 }
 665
 666 static const struct pinconf_ops rockchip_pinconf_ops = {
 667         .pin_config_get                 = rockchip_pinconf_get,
 668         .pin_config_set                 = rockchip_pinconf_set,
 669 };
 670
 671 static const char *gpio_compat = "rockchip,gpio-bank";
 672
 673 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
 674                                                 struct device_node *np)
 675 {
 676         struct device_node *child;
 677
 678         for_each_child_of_node(np, child) {
 679                 if (of_device_is_compatible(child, gpio_compat))
 680                         continue;
 681
 682                 info->nfunctions++;
 683                 info->ngroups += of_get_child_count(child);
 684         }
 685 }
 686
 687 static int rockchip_pinctrl_parse_groups(struct device_node *np,
 688                                               struct rockchip_pin_group *grp,
 689                                               struct rockchip_pinctrl *info,
 690                                               u32 index)
 691 {
 692         struct rockchip_pin_bank *bank;
 693         int size;
 694         const __be32 *list;
 695         int num;
 696         int i, j;
 697         int ret;
 698
 699         dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
 700
 701         /* Initialise group */
 702         grp->name = np->name;
 703
 704         /*
 705          * the binding format is rockchip,pins = <bank pin mux CONFIG>,
 706          * do sanity check and calculate pins number
 707          */
 708         list = of_get_property(np, "rockchip,pins", &size);
 709         /* we do not check return since it's safe node passed down */
 710         size /= sizeof(*list);
 711         if (!size || size % 4) {
 712                 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
 713                 return -EINVAL;
 714         }
 715
 716         grp->npins = size / 4;
 717
 718         grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
 719                                                 GFP_KERNEL);
 720         grp->data = devm_kzalloc(info->dev, grp->npins *
 721                                           sizeof(struct rockchip_pin_config),
 722                                         GFP_KERNEL);
 723         if (!grp->pins || !grp->data)
 724                 return -ENOMEM;
 725
 726         for (i = 0, j = 0; i < size; i += 4, j++) {
 727                 const __be32 *phandle;
 728                 struct device_node *np_config;
 729
 730                 num = be32_to_cpu(*list++);
 731                 bank = bank_num_to_bank(info, num);
 732                 if (IS_ERR(bank))
 733                         return PTR_ERR(bank);
 734
 735                 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++);
 736                 grp->data[j].func = be32_to_cpu(*list++);
 737
 738                 phandle = list++;
 739                 if (!phandle)
 740                         return -EINVAL;
 741
 742                 np_config = of_find_node_by_phandle(be32_to_cpup(phandle));
 743                 ret = pinconf_generic_parse_dt_config(np_config,
 744                                 &grp->data[j].configs, &grp->data[j].nconfigs);
 745                 if (ret)
 746                         return ret;
 747         }
 748
 749         return 0;
 750 }
 751
 752 static int rockchip_pinctrl_parse_functions(struct device_node *np,
 753                                                 struct rockchip_pinctrl *info,
 754                                                 u32 index)
 755 {
 756         struct device_node *child;
 757         struct rockchip_pmx_func *func;
 758         struct rockchip_pin_group *grp;
 759         int ret;
 760         static u32 grp_index;
 761         u32 i = 0;
 762
 763         dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
 764
 765         func = &info->functions[index];
 766
 767         /* Initialise function */
 768         func->name = np->name;
 769         func->ngroups = of_get_child_count(np);
 770         if (func->ngroups <= 0)
 771                 return 0;
 772
 773         func->groups = devm_kzalloc(info->dev,
 774                         func->ngroups * sizeof(char *), GFP_KERNEL);
 775         if (!func->groups)
 776                 return -ENOMEM;
 777
 778         for_each_child_of_node(np, child) {
 779                 func->groups[i] = child->name;
 780                 grp = &info->groups[grp_index++];
 781                 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++);
 782                 if (ret)
 783                         return ret;
 784         }
 785
 786         return 0;
 787 }
 788
 789 static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
 790                                               struct rockchip_pinctrl *info)
 791 {
 792         struct device *dev = &pdev->dev;
 793         struct device_node *np = dev->of_node;
 794         struct device_node *child;
 795         int ret;
 796         int i;
 797
 798         rockchip_pinctrl_child_count(info, np);
 799
 800         dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
 801         dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
 802
 803         info->functions = devm_kzalloc(dev, info->nfunctions *
 804                                               sizeof(struct rockchip_pmx_func),
 805                                               GFP_KERNEL);
 806         if (!info->functions) {
 807                 dev_err(dev, "failed to allocate memory for function list\n");
 808                 return -EINVAL;
 809         }
 810
 811         info->groups = devm_kzalloc(dev, info->ngroups *
 812                                             sizeof(struct rockchip_pin_group),
 813                                             GFP_KERNEL);
 814         if (!info->groups) {
 815                 dev_err(dev, "failed allocate memory for ping group list\n");
 816                 return -EINVAL;
 817         }
 818
 819         i = 0;
 820
 821         for_each_child_of_node(np, child) {
 822                 if (of_device_is_compatible(child, gpio_compat))
 823                         continue;
 824                 ret = rockchip_pinctrl_parse_functions(child, info, i++);
 825                 if (ret) {
 826                         dev_err(&pdev->dev, "failed to parse function\n");
 827                         return ret;
 828                 }
 829         }
 830
 831         return 0;
 832 }
 833
 834 static int rockchip_pinctrl_register(struct platform_device *pdev,
 835                                         struct rockchip_pinctrl *info)
 836 {
 837         struct pinctrl_desc *ctrldesc = &info->pctl;
 838         struct pinctrl_pin_desc *pindesc, *pdesc;
 839         struct rockchip_pin_bank *pin_bank;
 840         int pin, bank, ret;
 841         int k;
 842
 843         ctrldesc->name = "rockchip-pinctrl";
 844         ctrldesc->owner = THIS_MODULE;
 845         ctrldesc->pctlops = &rockchip_pctrl_ops;
 846         ctrldesc->pmxops = &rockchip_pmx_ops;
 847         ctrldesc->confops = &rockchip_pinconf_ops;
 848
 849         pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) *
 850                         info->ctrl->nr_pins, GFP_KERNEL);
 851         if (!pindesc) {
 852                 dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n");
 853                 return -ENOMEM;
 854         }
 855         ctrldesc->pins = pindesc;
 856         ctrldesc->npins = info->ctrl->nr_pins;
 857
 858         pdesc = pindesc;
 859         for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) {
 860                 pin_bank = &info->ctrl->pin_banks[bank];
 861                 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
 862                         pdesc->number = k;
 863                         pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
 864                                                 pin_bank->name, pin);
 865                         pdesc++;
 866                 }
 867         }
 868
 869         info->pctl_dev = pinctrl_register(ctrldesc, &pdev->dev, info);
 870         if (!info->pctl_dev) {
 871                 dev_err(&pdev->dev, "could not register pinctrl driver\n");
 872                 return -EINVAL;
 873         }
 874
 875         for (bank = 0; bank < info->ctrl->nr_banks; ++bank) {
 876                 pin_bank = &info->ctrl->pin_banks[bank];
 877                 pin_bank->grange.name = pin_bank->name;
 878                 pin_bank->grange.id = bank;
 879                 pin_bank->grange.pin_base = pin_bank->pin_base;
 880                 pin_bank->grange.base = pin_bank->gpio_chip.base;
 881                 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio;
 882                 pin_bank->grange.gc = &pin_bank->gpio_chip;
 883                 pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange);
 884         }
 885
 886         ret = rockchip_pinctrl_parse_dt(pdev, info);
 887         if (ret) {
 888                 pinctrl_unregister(info->pctl_dev);
 889                 return ret;
 890         }
 891
 892         return 0;
 893 }
 894
 895 /*
 896  * GPIO handling
 897  */
 898
 899 static int rockchip_gpio_request(struct gpio_chip *chip, unsigned offset)
 900 {
 901         return pinctrl_request_gpio(chip->base + offset);
 902 }
 903
 904 static void rockchip_gpio_free(struct gpio_chip *chip, unsigned offset)
 905 {
 906         pinctrl_free_gpio(chip->base + offset);
 907 }
 908
 909 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
 910 {
 911         struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
 912         void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR;
 913         unsigned long flags;
 914         u32 data;
 915
 916         spin_lock_irqsave(&bank->slock, flags);
 917
 918         data = readl(reg);
 919         data &= ~BIT(offset);
 920         if (value)
 921                 data |= BIT(offset);
 922         writel(data, reg);
 923
 924         spin_unlock_irqrestore(&bank->slock, flags);
 925 }
 926
 927 /*
 928  * Returns the level of the pin for input direction and setting of the DR
 929  * register for output gpios.
 930  */
 931 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset)
 932 {
 933         struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
 934         u32 data;
 935
 936         data = readl(bank->reg_base + GPIO_EXT_PORT);
 937         data >>= offset;
 938         data &= 1;
 939         return data;
 940 }
 941
 942 /*
 943  * gpiolib gpio_direction_input callback function. The setting of the pin
 944  * mux function as 'gpio input' will be handled by the pinctrl susbsystem
 945  * interface.
 946  */
 947 static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
 948 {
 949         return pinctrl_gpio_direction_input(gc->base + offset);
 950 }
 951
 952 /*
 953  * gpiolib gpio_direction_output callback function. The setting of the pin
 954  * mux function as 'gpio output' will be handled by the pinctrl susbsystem
 955  * interface.
 956  */
 957 static int rockchip_gpio_direction_output(struct gpio_chip *gc,
 958                                           unsigned offset, int value)
 959 {
 960         rockchip_gpio_set(gc, offset, value);
 961         return pinctrl_gpio_direction_output(gc->base + offset);
 962 }
 963
 964 /*
 965  * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
 966  * and a virtual IRQ, if not already present.
 967  */
 968 static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
 969 {
 970         struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
 971         unsigned int virq;
 972
 973         if (!bank->domain)
 974                 return -ENXIO;
 975
 976         virq = irq_create_mapping(bank->domain, offset);
 977
 978         return (virq) ? : -ENXIO;
 979 }
 980
 981 static const struct gpio_chip rockchip_gpiolib_chip = {
 982         .request = rockchip_gpio_request,
 983         .free = rockchip_gpio_free,
 984         .set = rockchip_gpio_set,
 985         .get = rockchip_gpio_get,
 986         .direction_input = rockchip_gpio_direction_input,
 987         .direction_output = rockchip_gpio_direction_output,
 988         .to_irq = rockchip_gpio_to_irq,
 989         .owner = THIS_MODULE,
 990 };
 991
 992 /*
 993  * Interrupt handling
 994  */
 995
 996 static void rockchip_irq_demux(unsigned int irq, struct irq_desc *desc)
 997 {
 998         struct irq_chip *chip = irq_get_chip(irq);
 999         struct rockchip_pin_bank *bank = irq_get_handler_data(irq);
1000         u32 pend;
1001
1002         dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name);
1003
1004         chained_irq_enter(chip, desc);
1005
1006         pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS);
1007
1008         while (pend) {
1009                 unsigned int virq;
1010
1011                 irq = __ffs(pend);
1012                 pend &= ~BIT(irq);
1013                 virq = irq_linear_revmap(bank->domain, irq);
1014
1015                 if (!virq) {
1016                         dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq);
1017                         continue;
1018                 }
1019
1020                 dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq);
1021
1022                 generic_handle_irq(virq);
1023         }
1024
1025         chained_irq_exit(chip, desc);
1026 }
1027
1028 static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
1029 {
1030         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
1031         struct rockchip_pin_bank *bank = gc->private;
1032         u32 mask = BIT(d->hwirq);
1033         u32 polarity;
1034         u32 level;
1035         u32 data;
1036
1037         if (type & IRQ_TYPE_EDGE_BOTH)
1038                 __irq_set_handler_locked(d->irq, handle_edge_irq);
1039         else
1040                 __irq_set_handler_locked(d->irq, handle_level_irq);
1041
1042         irq_gc_lock(gc);
1043
1044         level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL);
1045         polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY);
1046
1047         switch (type) {
1048         case IRQ_TYPE_EDGE_RISING:
1049                 level |= mask;
1050                 polarity |= mask;
1051                 break;
1052         case IRQ_TYPE_EDGE_FALLING:
1053                 level |= mask;
1054                 polarity &= ~mask;
1055                 break;
1056         case IRQ_TYPE_LEVEL_HIGH:
1057                 level &= ~mask;
1058                 polarity |= mask;
1059                 break;
1060         case IRQ_TYPE_LEVEL_LOW:
1061                 level &= ~mask;
1062                 polarity &= ~mask;
1063                 break;
1064         default:
1065                 irq_gc_unlock(gc);
1066                 return -EINVAL;
1067         }
1068
1069         writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL);
1070         writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY);
1071
1072         irq_gc_unlock(gc);
1073
1074         /* make sure the pin is configured as gpio input */
1075         rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO);
1076         data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
1077         data &= ~mask;
1078         writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
1079
1080         return 0;
1081 }
1082
1083 static int rockchip_interrupts_register(struct platform_device *pdev,
1084                                                 struct rockchip_pinctrl *info)
1085 {
1086         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1087         struct rockchip_pin_bank *bank = ctrl->pin_banks;
1088         unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
1089         struct irq_chip_generic *gc;
1090         int ret;
1091         int i;
1092
1093         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1094                 if (!bank->valid) {
1095                         dev_warn(&pdev->dev, "bank %s is not valid\n",
1096                                  bank->name);
1097                         continue;
1098                 }
1099
1100                 bank->domain = irq_domain_add_linear(bank->of_node, 32,
1101                                                 &irq_generic_chip_ops, NULL);
1102                 if (!bank->domain) {
1103                         dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n",
1104                                  bank->name);
1105                         continue;
1106                 }
1107
1108                 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
1109                                          "rockchip_gpio_irq", handle_level_irq,
1110                                          clr, 0, IRQ_GC_INIT_MASK_CACHE);
1111                 if (ret) {
1112                         dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n",
1113                                 bank->name);
1114                         irq_domain_remove(bank->domain);
1115                         continue;
1116                 }
1117
1118                 gc = irq_get_domain_generic_chip(bank->domain, 0);
1119                 gc->reg_base = bank->reg_base;
1120                 gc->private = bank;
1121                 gc->chip_types[0].regs.mask = GPIO_INTEN;
1122                 gc->chip_types[0].regs.ack = GPIO_PORTS_EOI;
1123                 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
1124                 gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
1125                 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
1126                 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
1127                 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
1128
1129                 irq_set_handler_data(bank->irq, bank);
1130                 irq_set_chained_handler(bank->irq, rockchip_irq_demux);
1131         }
1132
1133         return 0;
1134 }
1135
1136 static int rockchip_gpiolib_register(struct platform_device *pdev,
1137                                                 struct rockchip_pinctrl *info)
1138 {
1139         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1140         struct rockchip_pin_bank *bank = ctrl->pin_banks;
1141         struct gpio_chip *gc;
1142         int ret;
1143         int i;
1144
1145         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1146                 if (!bank->valid) {
1147                         dev_warn(&pdev->dev, "bank %s is not valid\n",
1148                                  bank->name);
1149                         continue;
1150                 }
1151
1152                 bank->gpio_chip = rockchip_gpiolib_chip;
1153
1154                 gc = &bank->gpio_chip;
1155                 gc->base = bank->pin_base;
1156                 gc->ngpio = bank->nr_pins;
1157                 gc->dev = &pdev->dev;
1158                 gc->of_node = bank->of_node;
1159                 gc->label = bank->name;
1160
1161                 ret = gpiochip_add(gc);
1162                 if (ret) {
1163                         dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n",
1164                                                         gc->label, ret);
1165                         goto fail;
1166                 }
1167         }
1168
1169         rockchip_interrupts_register(pdev, info);
1170
1171         return 0;
1172
1173 fail:
1174         for (--i, --bank; i >= 0; --i, --bank) {
1175                 if (!bank->valid)
1176                         continue;
1177
1178                 if (gpiochip_remove(&bank->gpio_chip))
1179                         dev_err(&pdev->dev, "gpio chip %s remove failed\n",
1180                                                         bank->gpio_chip.label);
1181         }
1182         return ret;
1183 }
1184
1185 static int rockchip_gpiolib_unregister(struct platform_device *pdev,
1186                                                 struct rockchip_pinctrl *info)
1187 {
1188         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1189         struct rockchip_pin_bank *bank = ctrl->pin_banks;
1190         int ret = 0;
1191         int i;
1192
1193         for (i = 0; !ret && i < ctrl->nr_banks; ++i, ++bank) {
1194                 if (!bank->valid)
1195                         continue;
1196
1197                 ret = gpiochip_remove(&bank->gpio_chip);
1198         }
1199
1200         if (ret)
1201                 dev_err(&pdev->dev, "gpio chip remove failed\n");
1202
1203         return ret;
1204 }
1205
1206 static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
1207                                   struct device *dev)
1208 {
1209         struct resource res;
1210
1211         if (of_address_to_resource(bank->of_node, 0, &res)) {
1212                 dev_err(dev, "cannot find IO resource for bank\n");
1213                 return -ENOENT;
1214         }
1215
1216         bank->reg_base = devm_ioremap_resource(dev, &res);
1217         if (IS_ERR(bank->reg_base))
1218                 return PTR_ERR(bank->reg_base);
1219
1220         bank->irq = irq_of_parse_and_map(bank->of_node, 0);
1221
1222         bank->clk = of_clk_get(bank->of_node, 0);
1223         if (IS_ERR(bank->clk))
1224                 return PTR_ERR(bank->clk);
1225
1226         return clk_prepare_enable(bank->clk);
1227 }
1228
1229 static const struct of_device_id rockchip_pinctrl_dt_match[];
1230
1231 /* retrieve the soc specific data */
1232 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
1233                                                 struct rockchip_pinctrl *d,
1234                                                 struct platform_device *pdev)
1235 {
1236         const struct of_device_id *match;
1237         struct device_node *node = pdev->dev.of_node;
1238         struct device_node *np;
1239         struct rockchip_pin_ctrl *ctrl;
1240         struct rockchip_pin_bank *bank;
1241         int i;
1242
1243         match = of_match_node(rockchip_pinctrl_dt_match, node);
1244         ctrl = (struct rockchip_pin_ctrl *)match->data;
1245
1246         for_each_child_of_node(node, np) {
1247                 if (!of_find_property(np, "gpio-controller", NULL))
1248                         continue;
1249
1250                 bank = ctrl->pin_banks;
1251                 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1252                         if (!strcmp(bank->name, np->name)) {
1253                                 bank->of_node = np;
1254
1255                                 if (!rockchip_get_bank_data(bank, &pdev->dev))
1256                                         bank->valid = true;
1257
1258                                 break;
1259                         }
1260                 }
1261         }
1262
1263         bank = ctrl->pin_banks;
1264         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
1265                 spin_lock_init(&bank->slock);
1266                 bank->drvdata = d;
1267                 bank->pin_base = ctrl->nr_pins;
1268                 ctrl->nr_pins += bank->nr_pins;
1269         }
1270
1271         return ctrl;
1272 }
1273
1274 static int rockchip_pinctrl_probe(struct platform_device *pdev)
1275 {
1276         struct rockchip_pinctrl *info;
1277         struct device *dev = &pdev->dev;
1278         struct rockchip_pin_ctrl *ctrl;
1279         struct resource *res;
1280         int ret;
1281
1282         if (!dev->of_node) {
1283                 dev_err(dev, "device tree node not found\n");
1284                 return -ENODEV;
1285         }
1286
1287         info = devm_kzalloc(dev, sizeof(struct rockchip_pinctrl), GFP_KERNEL);
1288         if (!info)
1289                 return -ENOMEM;
1290
1291         ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
1292         if (!ctrl) {
1293                 dev_err(dev, "driver data not available\n");
1294                 return -EINVAL;
1295         }
1296         info->ctrl = ctrl;
1297         info->dev = dev;
1298
1299         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1300         info->reg_base = devm_ioremap_resource(&pdev->dev, res);
1301         if (IS_ERR(info->reg_base))
1302                 return PTR_ERR(info->reg_base);
1303
1304         ret = rockchip_gpiolib_register(pdev, info);
1305         if (ret)
1306                 return ret;
1307
1308         ret = rockchip_pinctrl_register(pdev, info);
1309         if (ret) {
1310                 rockchip_gpiolib_unregister(pdev, info);
1311                 return ret;
1312         }
1313
1314         platform_set_drvdata(pdev, info);
1315
1316         return 0;
1317 }
1318
1319 static struct rockchip_pin_bank rk2928_pin_banks[] = {
1320         PIN_BANK(0, 32, "gpio0"),
1321         PIN_BANK(1, 32, "gpio1"),
1322         PIN_BANK(2, 32, "gpio2"),
1323         PIN_BANK(3, 32, "gpio3"),
1324 };
1325
1326 static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
1327                 .pin_banks              = rk2928_pin_banks,
1328                 .nr_banks               = ARRAY_SIZE(rk2928_pin_banks),
1329                 .label                  = "RK2928-GPIO",
1330                 .type                   = RK2928,
1331                 .mux_offset             = 0xa8,
1332                 .pull_calc_reg          = rk2928_calc_pull_reg_and_bit,
1333 };
1334
1335 static struct rockchip_pin_bank rk3066a_pin_banks[] = {
1336         PIN_BANK(0, 32, "gpio0"),
1337         PIN_BANK(1, 32, "gpio1"),
1338         PIN_BANK(2, 32, "gpio2"),
1339         PIN_BANK(3, 32, "gpio3"),
1340         PIN_BANK(4, 32, "gpio4"),
1341         PIN_BANK(6, 16, "gpio6"),
1342 };
1343
1344 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
1345                 .pin_banks              = rk3066a_pin_banks,
1346                 .nr_banks               = ARRAY_SIZE(rk3066a_pin_banks),
1347                 .label                  = "RK3066a-GPIO",
1348                 .type                   = RK2928,
1349                 .mux_offset             = 0xa8,
1350                 .pull_calc_reg          = rk2928_calc_pull_reg_and_bit,
1351 };
1352
1353 static struct rockchip_pin_bank rk3066b_pin_banks[] = {
1354         PIN_BANK(0, 32, "gpio0"),
1355         PIN_BANK(1, 32, "gpio1"),
1356         PIN_BANK(2, 32, "gpio2"),
1357         PIN_BANK(3, 32, "gpio3"),
1358 };
1359
1360 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
1361                 .pin_banks      = rk3066b_pin_banks,
1362                 .nr_banks       = ARRAY_SIZE(rk3066b_pin_banks),
1363                 .label          = "RK3066b-GPIO",
1364                 .type           = RK3066B,
1365                 .mux_offset     = 0x60,
1366 };
1367
1368 static struct rockchip_pin_bank rk3188_pin_banks[] = {
1369         PIN_BANK(0, 32, "gpio0"),
1370         PIN_BANK(1, 32, "gpio1"),
1371         PIN_BANK(2, 32, "gpio2"),
1372         PIN_BANK(3, 32, "gpio3"),
1373 };
1374
1375 static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
1376                 .pin_banks              = rk3188_pin_banks,
1377                 .nr_banks               = ARRAY_SIZE(rk3188_pin_banks),
1378                 .label                  = "RK3188-GPIO",
1379                 .type                   = RK3188,
1380                 .mux_offset             = 0x68,
1381 };
1382
1383 static const struct of_device_id rockchip_pinctrl_dt_match[] = {
1384         { .compatible = "rockchip,rk2928-pinctrl",
1385                 .data = (void *)&rk2928_pin_ctrl },
1386         { .compatible = "rockchip,rk3066a-pinctrl",
1387                 .data = (void *)&rk3066a_pin_ctrl },
1388         { .compatible = "rockchip,rk3066b-pinctrl",
1389                 .data = (void *)&rk3066b_pin_ctrl },
1390         { .compatible = "rockchip,rk3188-pinctrl",
1391                 .data = (void *)&rk3188_pin_ctrl },
1392         {},
1393 };
1394 MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match);
1395
1396 static struct platform_driver rockchip_pinctrl_driver = {
1397         .probe          = rockchip_pinctrl_probe,
1398         .driver = {
1399                 .name   = "rockchip-pinctrl",
1400                 .owner  = THIS_MODULE,
1401                 .of_match_table = rockchip_pinctrl_dt_match,
1402         },
1403 };
1404
1405 static int __init rockchip_pinctrl_drv_register(void)
1406 {
1407         return platform_driver_register(&rockchip_pinctrl_driver);
1408 }
1409 postcore_initcall(rockchip_pinctrl_drv_register);
1410
1411 MODULE_AUTHOR("Heiko Stuebner <heiko@sntech.de>");
1412 MODULE_DESCRIPTION("Rockchip pinctrl driver");
1413 MODULE_LICENSE("GPL v2");