drivers/pinctrl/pinctrl-rockchip.c

   1 /*
   2  * Pinctrl driver for Rockchip SoCs
   3  *
   4  * Copyright (c) 2013 MundoReader S.L.
   5  * Author: Heiko Stuebner <heiko@sntech.de>
   6  *
   7  * With some ideas taken from pinctrl-samsung:
   8  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
   9  *              http://www.samsung.com
  10  * Copyright (c) 2012 Linaro Ltd
  11  *              http://www.linaro.org
  12  *
  13  * and pinctrl-at91:
  14  * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as published
  18  * by the Free Software Foundation.
  19  *
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  * GNU General Public License for more details.
  24  */
  25
  26 #include <linux/init.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/io.h>
  29 #include <linux/bitops.h>
  30 #include <linux/gpio.h>
  31 #include <linux/of_address.h>
  32 #include <linux/of_irq.h>
  33 #include <linux/pinctrl/machine.h>
  34 #include <linux/pinctrl/pinconf.h>
  35 #include <linux/pinctrl/pinctrl.h>
  36 #include <linux/pinctrl/pinmux.h>
  37 #include <linux/pinctrl/pinconf-generic.h>
  38 #include <linux/irqchip/chained_irq.h>
  39 #include <linux/clk.h>
  40 #include <linux/regmap.h>
  41 #include <linux/mfd/syscon.h>
  42 #include <dt-bindings/pinctrl/rockchip.h>
  43
  44 #include "core.h"
  45 #include "pinconf.h"
  46
  47 /* GPIO control registers */
  48 #define GPIO_SWPORT_DR          0x00
  49 #define GPIO_SWPORT_DDR         0x04
  50 #define GPIO_INTEN              0x30
  51 #define GPIO_INTMASK            0x34
  52 #define GPIO_INTTYPE_LEVEL      0x38
  53 #define GPIO_INT_POLARITY       0x3c
  54 #define GPIO_INT_STATUS         0x40
  55 #define GPIO_INT_RAWSTATUS      0x44
  56 #define GPIO_DEBOUNCE           0x48
  57 #define GPIO_PORTS_EOI          0x4c
  58 #define GPIO_EXT_PORT           0x50
  59 #define GPIO_LS_SYNC            0x60
  60
  61 enum rockchip_pinctrl_type {
  62         RV1108,
  63         RK2928,
  64         RK3066B,
  65         RK3188,
  66         RK3288,
  67         RK3368,
  68         RK3399,
  69 };
  70
  71 /**
  72  * Encode variants of iomux registers into a type variable
  73  */
  74 #define IOMUX_GPIO_ONLY         BIT(0)
  75 #define IOMUX_WIDTH_4BIT        BIT(1)
  76 #define IOMUX_SOURCE_PMU        BIT(2)
  77 #define IOMUX_UNROUTED          BIT(3)
  78 #define IOMUX_WIDTH_3BIT        BIT(4)
  79 #define IOMUX_RECALCED          BIT(5)
  80
  81 /**
  82  * @type: iomux variant using IOMUX_* constants
  83  * @offset: if initialized to -1 it will be autocalculated, by specifying
  84  *          an initial offset value the relevant source offset can be reset
  85  *          to a new value for autocalculating the following iomux registers.
  86  */
  87 struct rockchip_iomux {
  88         int                             type;
  89         int                             offset;
  90 };
  91
  92 /**
  93  * enum type index corresponding to rockchip_perpin_drv_list arrays index.
  94  */
  95 enum rockchip_pin_drv_type {
  96         DRV_TYPE_IO_DEFAULT = 0,
  97         DRV_TYPE_IO_1V8_OR_3V0,
  98         DRV_TYPE_IO_1V8_ONLY,
  99         DRV_TYPE_IO_1V8_3V0_AUTO,
 100         DRV_TYPE_IO_3V3_ONLY,
 101         DRV_TYPE_MAX
 102 };
 103
 104 /**
 105  * enum type index corresponding to rockchip_pull_list arrays index.
 106  */
 107 enum rockchip_pin_pull_type {
 108         PULL_TYPE_IO_DEFAULT = 0,
 109         PULL_TYPE_IO_1V8_ONLY,
 110         PULL_TYPE_MAX
 111 };
 112
 113 /**
 114  * @drv_type: drive strength variant using rockchip_perpin_drv_type
 115  * @offset: if initialized to -1 it will be autocalculated, by specifying
 116  *          an initial offset value the relevant source offset can be reset
 117  *          to a new value for autocalculating the following drive strength
 118  *          registers. if used chips own cal_drv func instead to calculate
 119  *          registers offset, the variant could be ignored.
 120  */
 121 struct rockchip_drv {
 122         enum rockchip_pin_drv_type      drv_type;
 123         int                             offset;
 124 };
 125
 126 /**
 127  * @reg_base: register base of the gpio bank
 128  * @reg_pull: optional separate register for additional pull settings
 129  * @clk: clock of the gpio bank
 130  * @irq: interrupt of the gpio bank
 131  * @saved_masks: Saved content of GPIO_INTEN at suspend time.
 132  * @pin_base: first pin number
 133  * @nr_pins: number of pins in this bank
 134  * @name: name of the bank
 135  * @bank_num: number of the bank, to account for holes
 136  * @iomux: array describing the 4 iomux sources of the bank
 137  * @drv: array describing the 4 drive strength sources of the bank
 138  * @pull_type: array describing the 4 pull type sources of the bank
 139  * @valid: are all necessary informations present
 140  * @of_node: dt node of this bank
 141  * @drvdata: common pinctrl basedata
 142  * @domain: irqdomain of the gpio bank
 143  * @gpio_chip: gpiolib chip
 144  * @grange: gpio range
 145  * @slock: spinlock for the gpio bank
 146  */
 147 struct rockchip_pin_bank {
 148         void __iomem                    *reg_base;
 149         struct regmap                   *regmap_pull;
 150         struct clk                      *clk;
 151         int                             irq;
 152         u32                             saved_masks;
 153         u32                             pin_base;
 154         u8                              nr_pins;
 155         char                            *name;
 156         u8                              bank_num;
 157         struct rockchip_iomux           iomux[4];
 158         struct rockchip_drv             drv[4];
 159         enum rockchip_pin_pull_type     pull_type[4];
 160         bool                            valid;
 161         struct device_node              *of_node;
 162         struct rockchip_pinctrl         *drvdata;
 163         struct irq_domain               *domain;
 164         struct gpio_chip                gpio_chip;
 165         struct pinctrl_gpio_range       grange;
 166         spinlock_t                      slock;
 167         u32                             toggle_edge_mode;
 168 };
 169
 170 #define PIN_BANK(id, pins, label)                       \
 171         {                                               \
 172                 .bank_num       = id,                   \
 173                 .nr_pins        = pins,                 \
 174                 .name           = label,                \
 175                 .iomux          = {                     \
 176                         { .offset = -1 },               \
 177                         { .offset = -1 },               \
 178                         { .offset = -1 },               \
 179                         { .offset = -1 },               \
 180                 },                                      \
 181         }
 182
 183 #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3)   \
 184         {                                                               \
 185                 .bank_num       = id,                                   \
 186                 .nr_pins        = pins,                                 \
 187                 .name           = label,                                \
 188                 .iomux          = {                                     \
 189                         { .type = iom0, .offset = -1 },                 \
 190                         { .type = iom1, .offset = -1 },                 \
 191                         { .type = iom2, .offset = -1 },                 \
 192                         { .type = iom3, .offset = -1 },                 \
 193                 },                                                      \
 194         }
 195
 196 #define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \
 197         {                                                               \
 198                 .bank_num       = id,                                   \
 199                 .nr_pins        = pins,                                 \
 200                 .name           = label,                                \
 201                 .iomux          = {                                     \
 202                         { .offset = -1 },                               \
 203                         { .offset = -1 },                               \
 204                         { .offset = -1 },                               \
 205                         { .offset = -1 },                               \
 206                 },                                                      \
 207                 .drv            = {                                     \
 208                         { .drv_type = type0, .offset = -1 },            \
 209                         { .drv_type = type1, .offset = -1 },            \
 210                         { .drv_type = type2, .offset = -1 },            \
 211                         { .drv_type = type3, .offset = -1 },            \
 212                 },                                                      \
 213         }
 214
 215 #define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1,      \
 216                                       drv2, drv3, pull0, pull1,         \
 217                                       pull2, pull3)                     \
 218         {                                                               \
 219                 .bank_num       = id,                                   \
 220                 .nr_pins        = pins,                                 \
 221                 .name           = label,                                \
 222                 .iomux          = {                                     \
 223                         { .offset = -1 },                               \
 224                         { .offset = -1 },                               \
 225                         { .offset = -1 },                               \
 226                         { .offset = -1 },                               \
 227                 },                                                      \
 228                 .drv            = {                                     \
 229                         { .drv_type = drv0, .offset = -1 },             \
 230                         { .drv_type = drv1, .offset = -1 },             \
 231                         { .drv_type = drv2, .offset = -1 },             \
 232                         { .drv_type = drv3, .offset = -1 },             \
 233                 },                                                      \
 234                 .pull_type[0] = pull0,                                  \
 235                 .pull_type[1] = pull1,                                  \
 236                 .pull_type[2] = pull2,                                  \
 237                 .pull_type[3] = pull3,                                  \
 238         }
 239
 240 #define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1,    \
 241                                         iom2, iom3, drv0, drv1, drv2,   \
 242                                         drv3, offset0, offset1,         \
 243                                         offset2, offset3)               \
 244         {                                                               \
 245                 .bank_num       = id,                                   \
 246                 .nr_pins        = pins,                                 \
 247                 .name           = label,                                \
 248                 .iomux          = {                                     \
 249                         { .type = iom0, .offset = -1 },                 \
 250                         { .type = iom1, .offset = -1 },                 \
 251                         { .type = iom2, .offset = -1 },                 \
 252                         { .type = iom3, .offset = -1 },                 \
 253                 },                                                      \
 254                 .drv            = {                                     \
 255                         { .drv_type = drv0, .offset = offset0 },        \
 256                         { .drv_type = drv1, .offset = offset1 },        \
 257                         { .drv_type = drv2, .offset = offset2 },        \
 258                         { .drv_type = drv3, .offset = offset3 },        \
 259                 },                                                      \
 260         }
 261
 262 #define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins,      \
 263                                               label, iom0, iom1, iom2,  \
 264                                               iom3, drv0, drv1, drv2,   \
 265                                               drv3, offset0, offset1,   \
 266                                               offset2, offset3, pull0,  \
 267                                               pull1, pull2, pull3)      \
 268         {                                                               \
 269                 .bank_num       = id,                                   \
 270                 .nr_pins        = pins,                                 \
 271                 .name           = label,                                \
 272                 .iomux          = {                                     \
 273                         { .type = iom0, .offset = -1 },                 \
 274                         { .type = iom1, .offset = -1 },                 \
 275                         { .type = iom2, .offset = -1 },                 \
 276                         { .type = iom3, .offset = -1 },                 \
 277                 },                                                      \
 278                 .drv            = {                                     \
 279                         { .drv_type = drv0, .offset = offset0 },        \
 280                         { .drv_type = drv1, .offset = offset1 },        \
 281                         { .drv_type = drv2, .offset = offset2 },        \
 282                         { .drv_type = drv3, .offset = offset3 },        \
 283                 },                                                      \
 284                 .pull_type[0] = pull0,                                  \
 285                 .pull_type[1] = pull1,                                  \
 286                 .pull_type[2] = pull2,                                  \
 287                 .pull_type[3] = pull3,                                  \
 288         }
 289
 290 /**
 291  */
 292 struct rockchip_pin_ctrl {
 293         struct rockchip_pin_bank        *pin_banks;
 294         u32                             nr_banks;
 295         u32                             nr_pins;
 296         char                            *label;
 297         enum rockchip_pinctrl_type      type;
 298         int                             grf_mux_offset;
 299         int                             pmu_mux_offset;
 300         int                             grf_drv_offset;
 301         int                             pmu_drv_offset;
 302
 303         void    (*pull_calc_reg)(struct rockchip_pin_bank *bank,
 304                                     int pin_num, struct regmap **regmap,
 305                                     int *reg, u8 *bit);
 306         void    (*drv_calc_reg)(struct rockchip_pin_bank *bank,
 307                                     int pin_num, struct regmap **regmap,
 308                                     int *reg, u8 *bit);
 309         void    (*iomux_recalc)(u8 bank_num, int pin, int *reg,
 310                                 u8 *bit, int *mask);
 311         int     (*schmitt_calc_reg)(struct rockchip_pin_bank *bank,
 312                                     int pin_num, struct regmap **regmap,
 313                                     int *reg, u8 *bit);
 314 };
 315
 316 struct rockchip_pin_config {
 317         unsigned int            func;
 318         unsigned long           *configs;
 319         unsigned int            nconfigs;
 320 };
 321
 322 /**
 323  * struct rockchip_pin_group: represent group of pins of a pinmux function.
 324  * @name: name of the pin group, used to lookup the group.
 325  * @pins: the pins included in this group.
 326  * @npins: number of pins included in this group.
 327  * @func: the mux function number to be programmed when selected.
 328  * @configs: the config values to be set for each pin
 329  * @nconfigs: number of configs for each pin
 330  */
 331 struct rockchip_pin_group {
 332         const char                      *name;
 333         unsigned int                    npins;
 334         unsigned int                    *pins;
 335         struct rockchip_pin_config      *data;
 336 };
 337
 338 /**
 339  * struct rockchip_pmx_func: represent a pin function.
 340  * @name: name of the pin function, used to lookup the function.
 341  * @groups: one or more names of pin groups that provide this function.
 342  * @num_groups: number of groups included in @groups.
 343  */
 344 struct rockchip_pmx_func {
 345         const char              *name;
 346         const char              **groups;
 347         u8                      ngroups;
 348 };
 349
 350 struct rockchip_pinctrl {
 351         struct regmap                   *regmap_base;
 352         int                             reg_size;
 353         struct regmap                   *regmap_pull;
 354         struct regmap                   *regmap_pmu;
 355         struct device                   *dev;
 356         struct rockchip_pin_ctrl        *ctrl;
 357         struct pinctrl_desc             pctl;
 358         struct pinctrl_dev              *pctl_dev;
 359         struct rockchip_pin_group       *groups;
 360         unsigned int                    ngroups;
 361         struct rockchip_pmx_func        *functions;
 362         unsigned int                    nfunctions;
 363 };
 364
 365 /**
 366  * struct rockchip_mux_recalced_data: represent a pin iomux data.
 367  * @num: bank number.
 368  * @pin: pin number.
 369  * @bit: index at register.
 370  * @reg: register offset.
 371  * @mask: mask bit
 372  */
 373 struct rockchip_mux_recalced_data {
 374         u8 num;
 375         u8 pin;
 376         u8 reg;
 377         u8 bit;
 378         u8 mask;
 379 };
 380
 381 static struct regmap_config rockchip_regmap_config = {
 382         .reg_bits = 32,
 383         .val_bits = 32,
 384         .reg_stride = 4,
 385 };
 386
 387 static inline const struct rockchip_pin_group *pinctrl_name_to_group(
 388                                         const struct rockchip_pinctrl *info,
 389                                         const char *name)
 390 {
 391         int i;
 392
 393         for (i = 0; i < info->ngroups; i++) {
 394                 if (!strcmp(info->groups[i].name, name))
 395                         return &info->groups[i];
 396         }
 397
 398         return NULL;
 399 }
 400
 401 /*
 402  * given a pin number that is local to a pin controller, find out the pin bank
 403  * and the register base of the pin bank.
 404  */
 405 static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info,
 406                                                                 unsigned pin)
 407 {
 408         struct rockchip_pin_bank *b = info->ctrl->pin_banks;
 409
 410         while (pin >= (b->pin_base + b->nr_pins))
 411                 b++;
 412
 413         return b;
 414 }
 415
 416 static struct rockchip_pin_bank *bank_num_to_bank(
 417                                         struct rockchip_pinctrl *info,
 418                                         unsigned num)
 419 {
 420         struct rockchip_pin_bank *b = info->ctrl->pin_banks;
 421         int i;
 422
 423         for (i = 0; i < info->ctrl->nr_banks; i++, b++) {
 424                 if (b->bank_num == num)
 425                         return b;
 426         }
 427
 428         return ERR_PTR(-EINVAL);
 429 }
 430
 431 /*
 432  * Pinctrl_ops handling
 433  */
 434
 435 static int rockchip_get_groups_count(struct pinctrl_dev *pctldev)
 436 {
 437         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 438
 439         return info->ngroups;
 440 }
 441
 442 static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev,
 443                                                         unsigned selector)
 444 {
 445         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 446
 447         return info->groups[selector].name;
 448 }
 449
 450 static int rockchip_get_group_pins(struct pinctrl_dev *pctldev,
 451                                       unsigned selector, const unsigned **pins,
 452                                       unsigned *npins)
 453 {
 454         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 455
 456         if (selector >= info->ngroups)
 457                 return -EINVAL;
 458
 459         *pins = info->groups[selector].pins;
 460         *npins = info->groups[selector].npins;
 461
 462         return 0;
 463 }
 464
 465 static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev,
 466                                  struct device_node *np,
 467                                  struct pinctrl_map **map, unsigned *num_maps)
 468 {
 469         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 470         const struct rockchip_pin_group *grp;
 471         struct pinctrl_map *new_map;
 472         struct device_node *parent;
 473         int map_num = 1;
 474         int i;
 475
 476         /*
 477          * first find the group of this node and check if we need to create
 478          * config maps for pins
 479          */
 480         grp = pinctrl_name_to_group(info, np->name);
 481         if (!grp) {
 482                 dev_err(info->dev, "unable to find group for node %s\n",
 483                         np->name);
 484                 return -EINVAL;
 485         }
 486
 487         map_num += grp->npins;
 488         new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num,
 489                                                                 GFP_KERNEL);
 490         if (!new_map)
 491                 return -ENOMEM;
 492
 493         *map = new_map;
 494         *num_maps = map_num;
 495
 496         /* create mux map */
 497         parent = of_get_parent(np);
 498         if (!parent) {
 499                 devm_kfree(pctldev->dev, new_map);
 500                 return -EINVAL;
 501         }
 502         new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
 503         new_map[0].data.mux.function = parent->name;
 504         new_map[0].data.mux.group = np->name;
 505         of_node_put(parent);
 506
 507         /* create config map */
 508         new_map++;
 509         for (i = 0; i < grp->npins; i++) {
 510                 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
 511                 new_map[i].data.configs.group_or_pin =
 512                                 pin_get_name(pctldev, grp->pins[i]);
 513                 new_map[i].data.configs.configs = grp->data[i].configs;
 514                 new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
 515         }
 516
 517         dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
 518                 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
 519
 520         return 0;
 521 }
 522
 523 static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
 524                                     struct pinctrl_map *map, unsigned num_maps)
 525 {
 526 }
 527
 528 static const struct pinctrl_ops rockchip_pctrl_ops = {
 529         .get_groups_count       = rockchip_get_groups_count,
 530         .get_group_name         = rockchip_get_group_name,
 531         .get_group_pins         = rockchip_get_group_pins,
 532         .dt_node_to_map         = rockchip_dt_node_to_map,
 533         .dt_free_map            = rockchip_dt_free_map,
 534 };
 535
 536 /*
 537  * Hardware access
 538  */
 539
 540 static const struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = {
 541         {
 542                 .num = 2,
 543                 .pin = 12,
 544                 .reg = 0x24,
 545                 .bit = 8,
 546                 .mask = 0x3
 547         }, {
 548                 .num = 2,
 549                 .pin = 15,
 550                 .reg = 0x28,
 551                 .bit = 0,
 552                 .mask = 0x7
 553         }, {
 554                 .num = 2,
 555                 .pin = 23,
 556                 .reg = 0x30,
 557                 .bit = 14,
 558                 .mask = 0x3
 559         },
 560 };
 561
 562 static void rk3328_recalc_mux(u8 bank_num, int pin, int *reg,
 563                               u8 *bit, int *mask)
 564 {
 565         const struct rockchip_mux_recalced_data *data = NULL;
 566         int i;
 567
 568         for (i = 0; i < ARRAY_SIZE(rk3328_mux_recalced_data); i++)
 569                 if (rk3328_mux_recalced_data[i].num == bank_num &&
 570                     rk3328_mux_recalced_data[i].pin == pin) {
 571                         data = &rk3328_mux_recalced_data[i];
 572                         break;
 573                 }
 574
 575         if (!data)
 576                 return;
 577
 578         *reg = data->reg;
 579         *mask = data->mask;
 580         *bit = data->bit;
 581 }
 582
 583 static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
 584 {
 585         struct rockchip_pinctrl *info = bank->drvdata;
 586         struct rockchip_pin_ctrl *ctrl = info->ctrl;
 587         int iomux_num = (pin / 8);
 588         struct regmap *regmap;
 589         unsigned int val;
 590         int reg, ret, mask, mux_type;
 591         u8 bit;
 592
 593         if (iomux_num > 3)
 594                 return -EINVAL;
 595
 596         if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
 597                 dev_err(info->dev, "pin %d is unrouted\n", pin);
 598                 return -EINVAL;
 599         }
 600
 601         if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
 602                 return RK_FUNC_GPIO;
 603
 604         regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
 605                                 ? info->regmap_pmu : info->regmap_base;
 606
 607         /* get basic quadrupel of mux registers and the correct reg inside */
 608         mux_type = bank->iomux[iomux_num].type;
 609         reg = bank->iomux[iomux_num].offset;
 610         if (mux_type & IOMUX_WIDTH_4BIT) {
 611                 if ((pin % 8) >= 4)
 612                         reg += 0x4;
 613                 bit = (pin % 4) * 4;
 614                 mask = 0xf;
 615         } else if (mux_type & IOMUX_WIDTH_3BIT) {
 616                 if ((pin % 8) >= 5)
 617                         reg += 0x4;
 618                 bit = (pin % 8 % 5) * 3;
 619                 mask = 0x7;
 620         } else {
 621                 bit = (pin % 8) * 2;
 622                 mask = 0x3;
 623         }
 624
 625         if (ctrl->iomux_recalc && (mux_type & IOMUX_RECALCED))
 626                 ctrl->iomux_recalc(bank->bank_num, pin, &reg, &bit, &mask);
 627
 628         ret = regmap_read(regmap, reg, &val);
 629         if (ret)
 630                 return ret;
 631
 632         return ((val >> bit) & mask);
 633 }
 634
 635 /*
 636  * Set a new mux function for a pin.
 637  *
 638  * The register is divided into the upper and lower 16 bit. When changing
 639  * a value, the previous register value is not read and changed. Instead
 640  * it seems the changed bits are marked in the upper 16 bit, while the
 641  * changed value gets set in the same offset in the lower 16 bit.
 642  * All pin settings seem to be 2 bit wide in both the upper and lower
 643  * parts.
 644  * @bank: pin bank to change
 645  * @pin: pin to change
 646  * @mux: new mux function to set
 647  */
 648 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
 649 {
 650         struct rockchip_pinctrl *info = bank->drvdata;
 651         struct rockchip_pin_ctrl *ctrl = info->ctrl;
 652         int iomux_num = (pin / 8);
 653         struct regmap *regmap;
 654         int reg, ret, mask, mux_type;
 655         unsigned long flags;
 656         u8 bit;
 657         u32 data, rmask;
 658
 659         if (iomux_num > 3)
 660                 return -EINVAL;
 661
 662         if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
 663                 dev_err(info->dev, "pin %d is unrouted\n", pin);
 664                 return -EINVAL;
 665         }
 666
 667         if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
 668                 if (mux != RK_FUNC_GPIO) {
 669                         dev_err(info->dev,
 670                                 "pin %d only supports a gpio mux\n", pin);
 671                         return -ENOTSUPP;
 672                 } else {
 673                         return 0;
 674                 }
 675         }
 676
 677         dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n",
 678                                                 bank->bank_num, pin, mux);
 679
 680         regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
 681                                 ? info->regmap_pmu : info->regmap_base;
 682
 683         /* get basic quadrupel of mux registers and the correct reg inside */
 684         mux_type = bank->iomux[iomux_num].type;
 685         reg = bank->iomux[iomux_num].offset;
 686         if (mux_type & IOMUX_WIDTH_4BIT) {
 687                 if ((pin % 8) >= 4)
 688                         reg += 0x4;
 689                 bit = (pin % 4) * 4;
 690                 mask = 0xf;
 691         } else if (mux_type & IOMUX_WIDTH_3BIT) {
 692                 if ((pin % 8) >= 5)
 693                         reg += 0x4;
 694                 bit = (pin % 8 % 5) * 3;
 695                 mask = 0x7;
 696         } else {
 697                 bit = (pin % 8) * 2;
 698                 mask = 0x3;
 699         }
 700
 701         if (ctrl->iomux_recalc && (mux_type & IOMUX_RECALCED))
 702                 ctrl->iomux_recalc(bank->bank_num, pin, &reg, &bit, &mask);
 703
 704         spin_lock_irqsave(&bank->slock, flags);
 705
 706         data = (mask << (bit + 16));
 707         rmask = data | (data >> 16);
 708         data |= (mux & mask) << bit;
 709         ret = regmap_update_bits(regmap, reg, rmask, data);
 710
 711         spin_unlock_irqrestore(&bank->slock, flags);
 712
 713         return ret;
 714 }
 715
 716 #define RV1108_PULL_PMU_OFFSET          0x10
 717 #define RV1108_PULL_OFFSET              0x110
 718 #define RV1108_PULL_PINS_PER_REG        8
 719 #define RV1108_PULL_BITS_PER_PIN        2
 720 #define RV1108_PULL_BANK_STRIDE         16
 721
 722 static void rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
 723                                          int pin_num, struct regmap **regmap,
 724                                          int *reg, u8 *bit)
 725 {
 726         struct rockchip_pinctrl *info = bank->drvdata;
 727
 728         /* The first 24 pins of the first bank are located in PMU */
 729         if (bank->bank_num == 0) {
 730                 *regmap = info->regmap_pmu;
 731                 *reg = RV1108_PULL_PMU_OFFSET;
 732         } else {
 733                 *reg = RV1108_PULL_OFFSET;
 734                 *regmap = info->regmap_base;
 735                 /* correct the offset, as we're starting with the 2nd bank */
 736                 *reg -= 0x10;
 737                 *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE;
 738         }
 739
 740         *reg += ((pin_num / RV1108_PULL_PINS_PER_REG) * 4);
 741         *bit = (pin_num % RV1108_PULL_PINS_PER_REG);
 742         *bit *= RV1108_PULL_BITS_PER_PIN;
 743 }
 744
 745 #define RV1108_DRV_PMU_OFFSET           0x20
 746 #define RV1108_DRV_GRF_OFFSET           0x210
 747 #define RV1108_DRV_BITS_PER_PIN         2
 748 #define RV1108_DRV_PINS_PER_REG         8
 749 #define RV1108_DRV_BANK_STRIDE          16
 750
 751 static void rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
 752                                         int pin_num, struct regmap **regmap,
 753                                         int *reg, u8 *bit)
 754 {
 755         struct rockchip_pinctrl *info = bank->drvdata;
 756
 757         /* The first 24 pins of the first bank are located in PMU */
 758         if (bank->bank_num == 0) {
 759                 *regmap = info->regmap_pmu;
 760                 *reg = RV1108_DRV_PMU_OFFSET;
 761         } else {
 762                 *regmap = info->regmap_base;
 763                 *reg = RV1108_DRV_GRF_OFFSET;
 764
 765                 /* correct the offset, as we're starting with the 2nd bank */
 766                 *reg -= 0x10;
 767                 *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE;
 768         }
 769
 770         *reg += ((pin_num / RV1108_DRV_PINS_PER_REG) * 4);
 771         *bit = pin_num % RV1108_DRV_PINS_PER_REG;
 772         *bit *= RV1108_DRV_BITS_PER_PIN;
 773 }
 774
 775 #define RK2928_PULL_OFFSET              0x118
 776 #define RK2928_PULL_PINS_PER_REG        16
 777 #define RK2928_PULL_BANK_STRIDE         8
 778
 779 static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
 780                                     int pin_num, struct regmap **regmap,
 781                                     int *reg, u8 *bit)
 782 {
 783         struct rockchip_pinctrl *info = bank->drvdata;
 784
 785         *regmap = info->regmap_base;
 786         *reg = RK2928_PULL_OFFSET;
 787         *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
 788         *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4;
 789
 790         *bit = pin_num % RK2928_PULL_PINS_PER_REG;
 791 };
 792
 793 #define RK3188_PULL_OFFSET              0x164
 794 #define RK3188_PULL_BITS_PER_PIN        2
 795 #define RK3188_PULL_PINS_PER_REG        8
 796 #define RK3188_PULL_BANK_STRIDE         16
 797 #define RK3188_PULL_PMU_OFFSET          0x64
 798
 799 static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
 800                                     int pin_num, struct regmap **regmap,
 801                                     int *reg, u8 *bit)
 802 {
 803         struct rockchip_pinctrl *info = bank->drvdata;
 804
 805         /* The first 12 pins of the first bank are located elsewhere */
 806         if (bank->bank_num == 0 && pin_num < 12) {
 807                 *regmap = info->regmap_pmu ? info->regmap_pmu
 808                                            : bank->regmap_pull;
 809                 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0;
 810                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
 811                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
 812                 *bit *= RK3188_PULL_BITS_PER_PIN;
 813         } else {
 814                 *regmap = info->regmap_pull ? info->regmap_pull
 815                                             : info->regmap_base;
 816                 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET;
 817
 818                 /* correct the offset, as it is the 2nd pull register */
 819                 *reg -= 4;
 820                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
 821                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
 822
 823                 /*
 824                  * The bits in these registers have an inverse ordering
 825                  * with the lowest pin being in bits 15:14 and the highest
 826                  * pin in bits 1:0
 827                  */
 828                 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG);
 829                 *bit *= RK3188_PULL_BITS_PER_PIN;
 830         }
 831 }
 832
 833 #define RK3288_PULL_OFFSET              0x140
 834 static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
 835                                     int pin_num, struct regmap **regmap,
 836                                     int *reg, u8 *bit)
 837 {
 838         struct rockchip_pinctrl *info = bank->drvdata;
 839
 840         /* The first 24 pins of the first bank are located in PMU */
 841         if (bank->bank_num == 0) {
 842                 *regmap = info->regmap_pmu;
 843                 *reg = RK3188_PULL_PMU_OFFSET;
 844
 845                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
 846                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
 847                 *bit *= RK3188_PULL_BITS_PER_PIN;
 848         } else {
 849                 *regmap = info->regmap_base;
 850                 *reg = RK3288_PULL_OFFSET;
 851
 852                 /* correct the offset, as we're starting with the 2nd bank */
 853                 *reg -= 0x10;
 854                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
 855                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
 856
 857                 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
 858                 *bit *= RK3188_PULL_BITS_PER_PIN;
 859         }
 860 }
 861
 862 #define RK3288_DRV_PMU_OFFSET           0x70
 863 #define RK3288_DRV_GRF_OFFSET           0x1c0
 864 #define RK3288_DRV_BITS_PER_PIN         2
 865 #define RK3288_DRV_PINS_PER_REG         8
 866 #define RK3288_DRV_BANK_STRIDE          16
 867
 868 static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
 869                                     int pin_num, struct regmap **regmap,
 870                                     int *reg, u8 *bit)
 871 {
 872         struct rockchip_pinctrl *info = bank->drvdata;
 873
 874         /* The first 24 pins of the first bank are located in PMU */
 875         if (bank->bank_num == 0) {
 876                 *regmap = info->regmap_pmu;
 877                 *reg = RK3288_DRV_PMU_OFFSET;
 878
 879                 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
 880                 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
 881                 *bit *= RK3288_DRV_BITS_PER_PIN;
 882         } else {
 883                 *regmap = info->regmap_base;
 884                 *reg = RK3288_DRV_GRF_OFFSET;
 885
 886                 /* correct the offset, as we're starting with the 2nd bank */
 887                 *reg -= 0x10;
 888                 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
 889                 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
 890
 891                 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
 892                 *bit *= RK3288_DRV_BITS_PER_PIN;
 893         }
 894 }
 895
 896 #define RK3228_PULL_OFFSET              0x100
 897
 898 static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
 899                                     int pin_num, struct regmap **regmap,
 900                                     int *reg, u8 *bit)
 901 {
 902         struct rockchip_pinctrl *info = bank->drvdata;
 903
 904         *regmap = info->regmap_base;
 905         *reg = RK3228_PULL_OFFSET;
 906         *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
 907         *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
 908
 909         *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
 910         *bit *= RK3188_PULL_BITS_PER_PIN;
 911 }
 912
 913 #define RK3228_DRV_GRF_OFFSET           0x200
 914
 915 static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
 916                                     int pin_num, struct regmap **regmap,
 917                                     int *reg, u8 *bit)
 918 {
 919         struct rockchip_pinctrl *info = bank->drvdata;
 920
 921         *regmap = info->regmap_base;
 922         *reg = RK3228_DRV_GRF_OFFSET;
 923         *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
 924         *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
 925
 926         *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
 927         *bit *= RK3288_DRV_BITS_PER_PIN;
 928 }
 929
 930 #define RK3368_PULL_GRF_OFFSET          0x100
 931 #define RK3368_PULL_PMU_OFFSET          0x10
 932
 933 static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
 934                                     int pin_num, struct regmap **regmap,
 935                                     int *reg, u8 *bit)
 936 {
 937         struct rockchip_pinctrl *info = bank->drvdata;
 938
 939         /* The first 32 pins of the first bank are located in PMU */
 940         if (bank->bank_num == 0) {
 941                 *regmap = info->regmap_pmu;
 942                 *reg = RK3368_PULL_PMU_OFFSET;
 943
 944                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
 945                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
 946                 *bit *= RK3188_PULL_BITS_PER_PIN;
 947         } else {
 948                 *regmap = info->regmap_base;
 949                 *reg = RK3368_PULL_GRF_OFFSET;
 950
 951                 /* correct the offset, as we're starting with the 2nd bank */
 952                 *reg -= 0x10;
 953                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
 954                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
 955
 956                 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
 957                 *bit *= RK3188_PULL_BITS_PER_PIN;
 958         }
 959 }
 960
 961 #define RK3368_DRV_PMU_OFFSET           0x20
 962 #define RK3368_DRV_GRF_OFFSET           0x200
 963
 964 static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
 965                                     int pin_num, struct regmap **regmap,
 966                                     int *reg, u8 *bit)
 967 {
 968         struct rockchip_pinctrl *info = bank->drvdata;
 969
 970         /* The first 32 pins of the first bank are located in PMU */
 971         if (bank->bank_num == 0) {
 972                 *regmap = info->regmap_pmu;
 973                 *reg = RK3368_DRV_PMU_OFFSET;
 974
 975                 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
 976                 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
 977                 *bit *= RK3288_DRV_BITS_PER_PIN;
 978         } else {
 979                 *regmap = info->regmap_base;
 980                 *reg = RK3368_DRV_GRF_OFFSET;
 981
 982                 /* correct the offset, as we're starting with the 2nd bank */
 983                 *reg -= 0x10;
 984                 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
 985                 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
 986
 987                 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
 988                 *bit *= RK3288_DRV_BITS_PER_PIN;
 989         }
 990 }
 991
 992 #define RK3399_PULL_GRF_OFFSET          0xe040
 993 #define RK3399_PULL_PMU_OFFSET          0x40
 994 #define RK3399_DRV_3BITS_PER_PIN        3
 995
 996 static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
 997                                          int pin_num, struct regmap **regmap,
 998                                          int *reg, u8 *bit)
 999 {
1000         struct rockchip_pinctrl *info = bank->drvdata;
1001
1002         /* The bank0:16 and bank1:32 pins are located in PMU */
1003         if ((bank->bank_num == 0) || (bank->bank_num == 1)) {
1004                 *regmap = info->regmap_pmu;
1005                 *reg = RK3399_PULL_PMU_OFFSET;
1006
1007                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1008
1009                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1010                 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1011                 *bit *= RK3188_PULL_BITS_PER_PIN;
1012         } else {
1013                 *regmap = info->regmap_base;
1014                 *reg = RK3399_PULL_GRF_OFFSET;
1015
1016                 /* correct the offset, as we're starting with the 3rd bank */
1017                 *reg -= 0x20;
1018                 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1019                 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1020
1021                 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1022                 *bit *= RK3188_PULL_BITS_PER_PIN;
1023         }
1024 }
1025
1026 static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1027                                         int pin_num, struct regmap **regmap,
1028                                         int *reg, u8 *bit)
1029 {
1030         struct rockchip_pinctrl *info = bank->drvdata;
1031         int drv_num = (pin_num / 8);
1032
1033         /*  The bank0:16 and bank1:32 pins are located in PMU */
1034         if ((bank->bank_num == 0) || (bank->bank_num == 1))
1035                 *regmap = info->regmap_pmu;
1036         else
1037                 *regmap = info->regmap_base;
1038
1039         *reg = bank->drv[drv_num].offset;
1040         if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
1041             (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY))
1042                 *bit = (pin_num % 8) * 3;
1043         else
1044                 *bit = (pin_num % 8) * 2;
1045 }
1046
1047 static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = {
1048         { 2, 4, 8, 12, -1, -1, -1, -1 },
1049         { 3, 6, 9, 12, -1, -1, -1, -1 },
1050         { 5, 10, 15, 20, -1, -1, -1, -1 },
1051         { 4, 6, 8, 10, 12, 14, 16, 18 },
1052         { 4, 7, 10, 13, 16, 19, 22, 26 }
1053 };
1054
1055 static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank,
1056                                      int pin_num)
1057 {
1058         struct rockchip_pinctrl *info = bank->drvdata;
1059         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1060         struct regmap *regmap;
1061         int reg, ret;
1062         u32 data, temp, rmask_bits;
1063         u8 bit;
1064         int drv_type = bank->drv[pin_num / 8].drv_type;
1065
1066         ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
1067
1068         switch (drv_type) {
1069         case DRV_TYPE_IO_1V8_3V0_AUTO:
1070         case DRV_TYPE_IO_3V3_ONLY:
1071                 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
1072                 switch (bit) {
1073                 case 0 ... 12:
1074                         /* regular case, nothing to do */
1075                         break;
1076                 case 15:
1077                         /*
1078                          * drive-strength offset is special, as it is
1079                          * spread over 2 registers
1080                          */
1081                         ret = regmap_read(regmap, reg, &data);
1082                         if (ret)
1083                                 return ret;
1084
1085                         ret = regmap_read(regmap, reg + 0x4, &temp);
1086                         if (ret)
1087                                 return ret;
1088
1089                         /*
1090                          * the bit data[15] contains bit 0 of the value
1091                          * while temp[1:0] contains bits 2 and 1
1092                          */
1093                         data >>= 15;
1094                         temp &= 0x3;
1095                         temp <<= 1;
1096                         data |= temp;
1097
1098                         return rockchip_perpin_drv_list[drv_type][data];
1099                 case 18 ... 21:
1100                         /* setting fully enclosed in the second register */
1101                         reg += 4;
1102                         bit -= 16;
1103                         break;
1104                 default:
1105                         dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n",
1106                                 bit, drv_type);
1107                         return -EINVAL;
1108                 }
1109
1110                 break;
1111         case DRV_TYPE_IO_DEFAULT:
1112         case DRV_TYPE_IO_1V8_OR_3V0:
1113         case DRV_TYPE_IO_1V8_ONLY:
1114                 rmask_bits = RK3288_DRV_BITS_PER_PIN;
1115                 break;
1116         default:
1117                 dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
1118                         drv_type);
1119                 return -EINVAL;
1120         }
1121
1122         ret = regmap_read(regmap, reg, &data);
1123         if (ret)
1124                 return ret;
1125
1126         data >>= bit;
1127         data &= (1 << rmask_bits) - 1;
1128
1129         return rockchip_perpin_drv_list[drv_type][data];
1130 }
1131
1132 static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
1133                                      int pin_num, int strength)
1134 {
1135         struct rockchip_pinctrl *info = bank->drvdata;
1136         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1137         struct regmap *regmap;
1138         unsigned long flags;
1139         int reg, ret, i;
1140         u32 data, rmask, rmask_bits, temp;
1141         u8 bit;
1142         int drv_type = bank->drv[pin_num / 8].drv_type;
1143
1144         dev_dbg(info->dev, "setting drive of GPIO%d-%d to %d\n",
1145                 bank->bank_num, pin_num, strength);
1146
1147         ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
1148
1149         ret = -EINVAL;
1150         for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) {
1151                 if (rockchip_perpin_drv_list[drv_type][i] == strength) {
1152                         ret = i;
1153                         break;
1154                 } else if (rockchip_perpin_drv_list[drv_type][i] < 0) {
1155                         ret = rockchip_perpin_drv_list[drv_type][i];
1156                         break;
1157                 }
1158         }
1159
1160         if (ret < 0) {
1161                 dev_err(info->dev, "unsupported driver strength %d\n",
1162                         strength);
1163                 return ret;
1164         }
1165
1166         spin_lock_irqsave(&bank->slock, flags);
1167
1168         switch (drv_type) {
1169         case DRV_TYPE_IO_1V8_3V0_AUTO:
1170         case DRV_TYPE_IO_3V3_ONLY:
1171                 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
1172                 switch (bit) {
1173                 case 0 ... 12:
1174                         /* regular case, nothing to do */
1175                         break;
1176                 case 15:
1177                         /*
1178                          * drive-strength offset is special, as it is spread
1179                          * over 2 registers, the bit data[15] contains bit 0
1180                          * of the value while temp[1:0] contains bits 2 and 1
1181                          */
1182                         data = (ret & 0x1) << 15;
1183                         temp = (ret >> 0x1) & 0x3;
1184
1185                         rmask = BIT(15) | BIT(31);
1186                         data |= BIT(31);
1187                         ret = regmap_update_bits(regmap, reg, rmask, data);
1188                         if (ret) {
1189                                 spin_unlock_irqrestore(&bank->slock, flags);
1190                                 return ret;
1191                         }
1192
1193                         rmask = 0x3 | (0x3 << 16);
1194                         temp |= (0x3 << 16);
1195                         reg += 0x4;
1196                         ret = regmap_update_bits(regmap, reg, rmask, temp);
1197
1198                         spin_unlock_irqrestore(&bank->slock, flags);
1199                         return ret;
1200                 case 18 ... 21:
1201                         /* setting fully enclosed in the second register */
1202                         reg += 4;
1203                         bit -= 16;
1204                         break;
1205                 default:
1206                         spin_unlock_irqrestore(&bank->slock, flags);
1207                         dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n",
1208                                 bit, drv_type);
1209                         return -EINVAL;
1210                 }
1211                 break;
1212         case DRV_TYPE_IO_DEFAULT:
1213         case DRV_TYPE_IO_1V8_OR_3V0:
1214         case DRV_TYPE_IO_1V8_ONLY:
1215                 rmask_bits = RK3288_DRV_BITS_PER_PIN;
1216                 break;
1217         default:
1218                 spin_unlock_irqrestore(&bank->slock, flags);
1219                 dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
1220                         drv_type);
1221                 return -EINVAL;
1222         }
1223
1224         /* enable the write to the equivalent lower bits */
1225         data = ((1 << rmask_bits) - 1) << (bit + 16);
1226         rmask = data | (data >> 16);
1227         data |= (ret << bit);
1228
1229         ret = regmap_update_bits(regmap, reg, rmask, data);
1230         spin_unlock_irqrestore(&bank->slock, flags);
1231
1232         return ret;
1233 }
1234
1235 static int rockchip_pull_list[PULL_TYPE_MAX][4] = {
1236         {
1237                 PIN_CONFIG_BIAS_DISABLE,
1238                 PIN_CONFIG_BIAS_PULL_UP,
1239                 PIN_CONFIG_BIAS_PULL_DOWN,
1240                 PIN_CONFIG_BIAS_BUS_HOLD
1241         },
1242         {
1243                 PIN_CONFIG_BIAS_DISABLE,
1244                 PIN_CONFIG_BIAS_PULL_DOWN,
1245                 PIN_CONFIG_BIAS_DISABLE,
1246                 PIN_CONFIG_BIAS_PULL_UP
1247         },
1248 };
1249
1250 static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
1251 {
1252         struct rockchip_pinctrl *info = bank->drvdata;
1253         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1254         struct regmap *regmap;
1255         int reg, ret, pull_type;
1256         u8 bit;
1257         u32 data;
1258
1259         /* rk3066b does support any pulls */
1260         if (ctrl->type == RK3066B)
1261                 return PIN_CONFIG_BIAS_DISABLE;
1262
1263         ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
1264
1265         ret = regmap_read(regmap, reg, &data);
1266         if (ret)
1267                 return ret;
1268
1269         switch (ctrl->type) {
1270         case RK2928:
1271                 return !(data & BIT(bit))
1272                                 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
1273                                 : PIN_CONFIG_BIAS_DISABLE;
1274         case RV1108:
1275         case RK3188:
1276         case RK3288:
1277         case RK3368:
1278         case RK3399:
1279                 pull_type = bank->pull_type[pin_num / 8];
1280                 data >>= bit;
1281                 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
1282
1283                 return rockchip_pull_list[pull_type][data];
1284         default:
1285                 dev_err(info->dev, "unsupported pinctrl type\n");
1286                 return -EINVAL;
1287         };
1288 }
1289
1290 static int rockchip_set_pull(struct rockchip_pin_bank *bank,
1291                                         int pin_num, int pull)
1292 {
1293         struct rockchip_pinctrl *info = bank->drvdata;
1294         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1295         struct regmap *regmap;
1296         int reg, ret, i, pull_type;
1297         unsigned long flags;
1298         u8 bit;
1299         u32 data, rmask;
1300
1301         dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n",
1302                  bank->bank_num, pin_num, pull);
1303
1304         /* rk3066b does support any pulls */
1305         if (ctrl->type == RK3066B)
1306                 return pull ? -EINVAL : 0;
1307
1308         ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
1309
1310         switch (ctrl->type) {
1311         case RK2928:
1312                 spin_lock_irqsave(&bank->slock, flags);
1313
1314                 data = BIT(bit + 16);
1315                 if (pull == PIN_CONFIG_BIAS_DISABLE)
1316                         data |= BIT(bit);
1317                 ret = regmap_write(regmap, reg, data);
1318
1319                 spin_unlock_irqrestore(&bank->slock, flags);
1320                 break;
1321         case RV1108:
1322         case RK3188:
1323         case RK3288:
1324         case RK3368:
1325         case RK3399:
1326                 pull_type = bank->pull_type[pin_num / 8];
1327                 ret = -EINVAL;
1328                 for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]);
1329                         i++) {
1330                         if (rockchip_pull_list[pull_type][i] == pull) {
1331                                 ret = i;
1332                                 break;
1333                         }
1334                 }
1335
1336                 if (ret < 0) {
1337                         dev_err(info->dev, "unsupported pull setting %d\n",
1338                                 pull);
1339                         return ret;
1340                 }
1341
1342                 spin_lock_irqsave(&bank->slock, flags);
1343
1344                 /* enable the write to the equivalent lower bits */
1345                 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
1346                 rmask = data | (data >> 16);
1347                 data |= (ret << bit);
1348
1349                 ret = regmap_update_bits(regmap, reg, rmask, data);
1350
1351                 spin_unlock_irqrestore(&bank->slock, flags);
1352                 break;
1353         default:
1354                 dev_err(info->dev, "unsupported pinctrl type\n");
1355                 return -EINVAL;
1356         }
1357
1358         return ret;
1359 }
1360
1361 #define RK3328_SCHMITT_BITS_PER_PIN             1
1362 #define RK3328_SCHMITT_PINS_PER_REG             16
1363 #define RK3328_SCHMITT_BANK_STRIDE              8
1364 #define RK3328_SCHMITT_GRF_OFFSET               0x380
1365
1366 static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1367                                            int pin_num,
1368                                            struct regmap **regmap,
1369                                            int *reg, u8 *bit)
1370 {
1371         struct rockchip_pinctrl *info = bank->drvdata;
1372
1373         *regmap = info->regmap_base;
1374         *reg = RK3328_SCHMITT_GRF_OFFSET;
1375
1376         *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE;
1377         *reg += ((pin_num / RK3328_SCHMITT_PINS_PER_REG) * 4);
1378         *bit = pin_num % RK3328_SCHMITT_PINS_PER_REG;
1379
1380         return 0;
1381 }
1382
1383 static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num)
1384 {
1385         struct rockchip_pinctrl *info = bank->drvdata;
1386         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1387         struct regmap *regmap;
1388         int reg, ret;
1389         u8 bit;
1390         u32 data;
1391
1392         ret = ctrl->schmitt_calc_reg(bank, pin_num, &regmap, &reg, &bit);
1393         if (ret)
1394                 return ret;
1395
1396         ret = regmap_read(regmap, reg, &data);
1397         if (ret)
1398                 return ret;
1399
1400         data >>= bit;
1401         return data & 0x1;
1402 }
1403
1404 static int rockchip_set_schmitt(struct rockchip_pin_bank *bank,
1405                                 int pin_num, int enable)
1406 {
1407         struct rockchip_pinctrl *info = bank->drvdata;
1408         struct rockchip_pin_ctrl *ctrl = info->ctrl;
1409         struct regmap *regmap;
1410         int reg, ret;
1411         unsigned long flags;
1412         u8 bit;
1413         u32 data, rmask;
1414
1415         dev_dbg(info->dev, "setting input schmitt of GPIO%d-%d to %d\n",
1416                 bank->bank_num, pin_num, enable);
1417
1418         ret = ctrl->schmitt_calc_reg(bank, pin_num, &regmap, &reg, &bit);
1419         if (ret)
1420                 return ret;
1421
1422         spin_lock_irqsave(&bank->slock, flags);
1423
1424         /* enable the write to the equivalent lower bits */
1425         data = BIT(bit + 16) | (enable << bit);
1426         rmask = BIT(bit + 16) | BIT(bit);
1427
1428         ret = regmap_update_bits(regmap, reg, rmask, data);
1429         spin_unlock_irqrestore(&bank->slock, flags);
1430
1431         return ret;
1432 }
1433
1434 /*
1435  * Pinmux_ops handling
1436  */
1437
1438 static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
1439 {
1440         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1441
1442         return info->nfunctions;
1443 }
1444
1445 static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev,
1446                                           unsigned selector)
1447 {
1448         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1449
1450         return info->functions[selector].name;
1451 }
1452
1453 static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
1454                                 unsigned selector, const char * const **groups,
1455                                 unsigned * const num_groups)
1456 {
1457         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1458
1459         *groups = info->functions[selector].groups;
1460         *num_groups = info->functions[selector].ngroups;
1461
1462         return 0;
1463 }
1464
1465 static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
1466                             unsigned group)
1467 {
1468         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1469         const unsigned int *pins = info->groups[group].pins;
1470         const struct rockchip_pin_config *data = info->groups[group].data;
1471         struct rockchip_pin_bank *bank;
1472         int cnt, ret = 0;
1473
1474         dev_dbg(info->dev, "enable function %s group %s\n",
1475                 info->functions[selector].name, info->groups[group].name);
1476
1477         /*
1478          * for each pin in the pin group selected, program the correspoding pin
1479          * pin function number in the config register.
1480          */
1481         for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
1482                 bank = pin_to_bank(info, pins[cnt]);
1483                 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
1484                                        data[cnt].func);
1485                 if (ret)
1486                         break;
1487         }
1488
1489         if (ret) {
1490                 /* revert the already done pin settings */
1491                 for (cnt--; cnt >= 0; cnt--)
1492                         rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
1493
1494                 return ret;
1495         }
1496
1497         return 0;
1498 }
1499
1500 static int rockchip_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
1501 {
1502         struct rockchip_pin_bank *bank = gpiochip_get_data(chip);
1503         u32 data;
1504
1505         data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
1506
1507         return !(data & BIT(offset));
1508 }
1509
1510 /*
1511  * The calls to gpio_direction_output() and gpio_direction_input()
1512  * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
1513  * function called from the gpiolib interface).
1514  */
1515 static int _rockchip_pmx_gpio_set_direction(struct gpio_chip *chip,
1516                                             int pin, bool input)
1517 {
1518         struct rockchip_pin_bank *bank;
1519         int ret;
1520         unsigned long flags;
1521         u32 data;
1522
1523         bank = gpiochip_get_data(chip);
1524
1525         ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO);
1526         if (ret < 0)
1527                 return ret;
1528
1529         clk_enable(bank->clk);
1530         spin_lock_irqsave(&bank->slock, flags);
1531
1532         data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
1533         /* set bit to 1 for output, 0 for input */
1534         if (!input)
1535                 data |= BIT(pin);
1536         else
1537                 data &= ~BIT(pin);
1538         writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
1539
1540         spin_unlock_irqrestore(&bank->slock, flags);
1541         clk_disable(bank->clk);
1542
1543         return 0;
1544 }
1545
1546 static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
1547                                               struct pinctrl_gpio_range *range,
1548                                               unsigned offset, bool input)
1549 {
1550         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1551         struct gpio_chip *chip;
1552         int pin;
1553
1554         chip = range->gc;
1555         pin = offset - chip->base;
1556         dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
1557                  offset, range->name, pin, input ? "input" : "output");
1558
1559         return _rockchip_pmx_gpio_set_direction(chip, offset - chip->base,
1560                                                 input);
1561 }
1562
1563 static const struct pinmux_ops rockchip_pmx_ops = {
1564         .get_functions_count    = rockchip_pmx_get_funcs_count,
1565         .get_function_name      = rockchip_pmx_get_func_name,
1566         .get_function_groups    = rockchip_pmx_get_groups,
1567         .set_mux                = rockchip_pmx_set,
1568         .gpio_set_direction     = rockchip_pmx_gpio_set_direction,
1569 };
1570
1571 /*
1572  * Pinconf_ops handling
1573  */
1574
1575 static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
1576                                         enum pin_config_param pull)
1577 {
1578         switch (ctrl->type) {
1579         case RK2928:
1580                 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
1581                                         pull == PIN_CONFIG_BIAS_DISABLE);
1582         case RK3066B:
1583                 return pull ? false : true;
1584         case RV1108:
1585         case RK3188:
1586         case RK3288:
1587         case RK3368:
1588         case RK3399:
1589                 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
1590         }
1591
1592         return false;
1593 }
1594
1595 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value);
1596 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset);
1597
1598 /* set the pin config settings for a specified pin */
1599 static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
1600                                 unsigned long *configs, unsigned num_configs)
1601 {
1602         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1603         struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
1604         enum pin_config_param param;
1605         u32 arg;
1606         int i;
1607         int rc;
1608
1609         for (i = 0; i < num_configs; i++) {
1610                 param = pinconf_to_config_param(configs[i]);
1611                 arg = pinconf_to_config_argument(configs[i]);
1612
1613                 switch (param) {
1614                 case PIN_CONFIG_BIAS_DISABLE:
1615                         rc =  rockchip_set_pull(bank, pin - bank->pin_base,
1616                                 param);
1617                         if (rc)
1618                                 return rc;
1619                         break;
1620                 case PIN_CONFIG_BIAS_PULL_UP:
1621                 case PIN_CONFIG_BIAS_PULL_DOWN:
1622                 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
1623                 case PIN_CONFIG_BIAS_BUS_HOLD:
1624                         if (!rockchip_pinconf_pull_valid(info->ctrl, param))
1625                                 return -ENOTSUPP;
1626
1627                         if (!arg)
1628                                 return -EINVAL;
1629
1630                         rc = rockchip_set_pull(bank, pin - bank->pin_base,
1631                                 param);
1632                         if (rc)
1633                                 return rc;
1634                         break;
1635                 case PIN_CONFIG_OUTPUT:
1636                         rockchip_gpio_set(&bank->gpio_chip,
1637                                           pin - bank->pin_base, arg);
1638                         rc = _rockchip_pmx_gpio_set_direction(&bank->gpio_chip,
1639                                           pin - bank->pin_base, false);
1640                         if (rc)
1641                                 return rc;
1642                         break;
1643                 case PIN_CONFIG_DRIVE_STRENGTH:
1644                         /* rk3288 is the first with per-pin drive-strength */
1645                         if (!info->ctrl->drv_calc_reg)
1646                                 return -ENOTSUPP;
1647
1648                         rc = rockchip_set_drive_perpin(bank,
1649                                                 pin - bank->pin_base, arg);
1650                         if (rc < 0)
1651                                 return rc;
1652                         break;
1653                 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
1654                         if (!info->ctrl->schmitt_calc_reg)
1655                                 return -ENOTSUPP;
1656
1657                         rc = rockchip_set_schmitt(bank,
1658                                                   pin - bank->pin_base, arg);
1659                         if (rc < 0)
1660                                 return rc;
1661                         break;
1662                 default:
1663                         return -ENOTSUPP;
1664                         break;
1665                 }
1666         } /* for each config */
1667
1668         return 0;
1669 }
1670
1671 /* get the pin config settings for a specified pin */
1672 static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
1673                                                         unsigned long *config)
1674 {
1675         struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1676         struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
1677         enum pin_config_param param = pinconf_to_config_param(*config);
1678         u16 arg;
1679         int rc;
1680
1681         switch (param) {
1682         case PIN_CONFIG_BIAS_DISABLE:
1683                 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
1684                         return -EINVAL;
1685
1686                 arg = 0;
1687                 break;
1688         case PIN_CONFIG_BIAS_PULL_UP:
1689         case PIN_CONFIG_BIAS_PULL_DOWN:
1690         case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
1691         case PIN_CONFIG_BIAS_BUS_HOLD:
1692                 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
1693                         return -ENOTSUPP;
1694
1695                 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
1696                         return -EINVAL;
1697
1698                 arg = 1;
1699                 break;
1700         case PIN_CONFIG_OUTPUT:
1701                 rc = rockchip_get_mux(bank, pin - bank->pin_base);
1702                 if (rc != RK_FUNC_GPIO)
1703                         return -EINVAL;
1704
1705                 rc = rockchip_gpio_get(&bank->gpio_chip, pin - bank->pin_base);
1706                 if (rc < 0)
1707                         return rc;
1708
1709                 arg = rc ? 1 : 0;
1710                 break;
1711         case PIN_CONFIG_DRIVE_STRENGTH:
1712                 /* rk3288 is the first with per-pin drive-strength */
1713                 if (!info->ctrl->drv_calc_reg)
1714                         return -ENOTSUPP;
1715
1716                 rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base);
1717                 if (rc < 0)
1718                         return rc;
1719
1720                 arg = rc;
1721                 break;
1722         case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
1723                 if (!info->ctrl->schmitt_calc_reg)
1724                         return -ENOTSUPP;
1725
1726                 rc = rockchip_get_schmitt(bank, pin - bank->pin_base);
1727                 if (rc < 0)
1728                         return rc;
1729
1730                 arg = rc;
1731                 break;
1732         default:
1733                 return -ENOTSUPP;
1734                 break;
1735         }
1736
1737         *config = pinconf_to_config_packed(param, arg);
1738
1739         return 0;
1740 }
1741
1742 static const struct pinconf_ops rockchip_pinconf_ops = {
1743         .pin_config_get                 = rockchip_pinconf_get,
1744         .pin_config_set                 = rockchip_pinconf_set,
1745         .is_generic                     = true,
1746 };
1747
1748 static const struct of_device_id rockchip_bank_match[] = {
1749         { .compatible = "rockchip,gpio-bank" },
1750         { .compatible = "rockchip,rk3188-gpio-bank0" },
1751         {},
1752 };
1753
1754 static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
1755                                                 struct device_node *np)
1756 {
1757         struct device_node *child;
1758
1759         for_each_child_of_node(np, child) {
1760                 if (of_match_node(rockchip_bank_match, child))
1761                         continue;
1762
1763                 info->nfunctions++;
1764                 info->ngroups += of_get_child_count(child);
1765         }
1766 }
1767
1768 static int rockchip_pinctrl_parse_groups(struct device_node *np,
1769                                               struct rockchip_pin_group *grp,
1770                                               struct rockchip_pinctrl *info,
1771                                               u32 index)
1772 {
1773         struct rockchip_pin_bank *bank;
1774         int size;
1775         const __be32 *list;
1776         int num;
1777         int i, j;
1778         int ret;
1779
1780         dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
1781
1782         /* Initialise group */
1783         grp->name = np->name;
1784
1785         /*
1786          * the binding format is rockchip,pins = <bank pin mux CONFIG>,
1787          * do sanity check and calculate pins number
1788          */
1789         list = of_get_property(np, "rockchip,pins", &size);
1790         /* we do not check return since it's safe node passed down */
1791         size /= sizeof(*list);
1792         if (!size || size % 4) {
1793                 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
1794                 return -EINVAL;
1795         }
1796
1797         grp->npins = size / 4;
1798
1799         grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
1800                                                 GFP_KERNEL);
1801         grp->data = devm_kzalloc(info->dev, grp->npins *
1802                                           sizeof(struct rockchip_pin_config),
1803                                         GFP_KERNEL);
1804         if (!grp->pins || !grp->data)
1805                 return -ENOMEM;
1806
1807         for (i = 0, j = 0; i < size; i += 4, j++) {
1808                 const __be32 *phandle;
1809                 struct device_node *np_config;
1810
1811                 num = be32_to_cpu(*list++);
1812                 bank = bank_num_to_bank(info, num);
1813                 if (IS_ERR(bank))
1814                         return PTR_ERR(bank);
1815
1816                 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++);
1817                 grp->data[j].func = be32_to_cpu(*list++);
1818
1819                 phandle = list++;
1820                 if (!phandle)
1821                         return -EINVAL;
1822
1823                 np_config = of_find_node_by_phandle(be32_to_cpup(phandle));
1824                 ret = pinconf_generic_parse_dt_config(np_config, NULL,
1825                                 &grp->data[j].configs, &grp->data[j].nconfigs);
1826                 if (ret)
1827                         return ret;
1828         }
1829
1830         return 0;
1831 }
1832
1833 static int rockchip_pinctrl_parse_functions(struct device_node *np,
1834                                                 struct rockchip_pinctrl *info,
1835                                                 u32 index)
1836 {
1837         struct device_node *child;
1838         struct rockchip_pmx_func *func;
1839         struct rockchip_pin_group *grp;
1840         int ret;
1841         static u32 grp_index;
1842         u32 i = 0;
1843
1844         dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
1845
1846         func = &info->functions[index];
1847
1848         /* Initialise function */
1849         func->name = np->name;
1850         func->ngroups = of_get_child_count(np);
1851         if (func->ngroups <= 0)
1852                 return 0;
1853
1854         func->groups = devm_kzalloc(info->dev,
1855                         func->ngroups * sizeof(char *), GFP_KERNEL);
1856         if (!func->groups)
1857                 return -ENOMEM;
1858
1859         for_each_child_of_node(np, child) {
1860                 func->groups[i] = child->name;
1861                 grp = &info->groups[grp_index++];
1862                 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++);
1863                 if (ret) {
1864                         of_node_put(child);
1865                         return ret;
1866                 }
1867         }
1868
1869         return 0;
1870 }
1871
1872 static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
1873                                               struct rockchip_pinctrl *info)
1874 {
1875         struct device *dev = &pdev->dev;
1876         struct device_node *np = dev->of_node;
1877         struct device_node *child;
1878         int ret;
1879         int i;
1880
1881         rockchip_pinctrl_child_count(info, np);
1882
1883         dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
1884         dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
1885
1886         info->functions = devm_kzalloc(dev, info->nfunctions *
1887                                               sizeof(struct rockchip_pmx_func),
1888                                               GFP_KERNEL);
1889         if (!info->functions) {
1890                 dev_err(dev, "failed to allocate memory for function list\n");
1891                 return -EINVAL;
1892         }
1893
1894         info->groups = devm_kzalloc(dev, info->ngroups *
1895                                             sizeof(struct rockchip_pin_group),
1896                                             GFP_KERNEL);
1897         if (!info->groups) {
1898                 dev_err(dev, "failed allocate memory for ping group list\n");
1899                 return -EINVAL;
1900         }
1901
1902         i = 0;
1903
1904         for_each_child_of_node(np, child) {
1905                 if (of_match_node(rockchip_bank_match, child))
1906                         continue;
1907
1908                 ret = rockchip_pinctrl_parse_functions(child, info, i++);
1909                 if (ret) {
1910                         dev_err(&pdev->dev, "failed to parse function\n");
1911                         of_node_put(child);
1912                         return ret;
1913                 }
1914         }
1915
1916         return 0;
1917 }
1918
1919 static int rockchip_pinctrl_register(struct platform_device *pdev,
1920                                         struct rockchip_pinctrl *info)
1921 {
1922         struct pinctrl_desc *ctrldesc = &info->pctl;
1923         struct pinctrl_pin_desc *pindesc, *pdesc;
1924         struct rockchip_pin_bank *pin_bank;
1925         int pin, bank, ret;
1926         int k;
1927
1928         ctrldesc->name = "rockchip-pinctrl";
1929         ctrldesc->owner = THIS_MODULE;
1930         ctrldesc->pctlops = &rockchip_pctrl_ops;
1931         ctrldesc->pmxops = &rockchip_pmx_ops;
1932         ctrldesc->confops = &rockchip_pinconf_ops;
1933
1934         pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) *
1935                         info->ctrl->nr_pins, GFP_KERNEL);
1936         if (!pindesc) {
1937                 dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n");
1938                 return -ENOMEM;
1939         }
1940         ctrldesc->pins = pindesc;
1941         ctrldesc->npins = info->ctrl->nr_pins;
1942
1943         pdesc = pindesc;
1944         for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) {
1945                 pin_bank = &info->ctrl->pin_banks[bank];
1946                 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
1947                         pdesc->number = k;
1948                         pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
1949                                                 pin_bank->name, pin);
1950                         pdesc++;
1951                 }
1952         }
1953
1954         ret = rockchip_pinctrl_parse_dt(pdev, info);
1955         if (ret)
1956                 return ret;
1957
1958         info->pctl_dev = devm_pinctrl_register(&pdev->dev, ctrldesc, info);
1959         if (IS_ERR(info->pctl_dev)) {
1960                 dev_err(&pdev->dev, "could not register pinctrl driver\n");
1961                 return PTR_ERR(info->pctl_dev);
1962         }
1963
1964         for (bank = 0; bank < info->ctrl->nr_banks; ++bank) {
1965                 pin_bank = &info->ctrl->pin_banks[bank];
1966                 pin_bank->grange.name = pin_bank->name;
1967                 pin_bank->grange.id = bank;
1968                 pin_bank->grange.pin_base = pin_bank->pin_base;
1969                 pin_bank->grange.base = pin_bank->gpio_chip.base;
1970                 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio;
1971                 pin_bank->grange.gc = &pin_bank->gpio_chip;
1972                 pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange);
1973         }
1974
1975         return 0;
1976 }
1977
1978 /*
1979  * GPIO handling
1980  */
1981
1982 static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
1983 {
1984         struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
1985         void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR;
1986         unsigned long flags;
1987         u32 data;
1988
1989         clk_enable(bank->clk);
1990         spin_lock_irqsave(&bank->slock, flags);
1991
1992         data = readl(reg);
1993         data &= ~BIT(offset);
1994         if (value)
1995                 data |= BIT(offset);
1996         writel(data, reg);
1997
1998         spin_unlock_irqrestore(&bank->slock, flags);
1999         clk_disable(bank->clk);
2000 }
2001
2002 /*
2003  * Returns the level of the pin for input direction and setting of the DR
2004  * register for output gpios.
2005  */
2006 static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset)
2007 {
2008         struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
2009         u32 data;
2010
2011         clk_enable(bank->clk);
2012         data = readl(bank->reg_base + GPIO_EXT_PORT);
2013         clk_disable(bank->clk);
2014         data >>= offset;
2015         data &= 1;
2016         return data;
2017 }
2018
2019 /*
2020  * gpiolib gpio_direction_input callback function. The setting of the pin
2021  * mux function as 'gpio input' will be handled by the pinctrl susbsystem
2022  * interface.
2023  */
2024 static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
2025 {
2026         return pinctrl_gpio_direction_input(gc->base + offset);
2027 }
2028
2029 /*
2030  * gpiolib gpio_direction_output callback function. The setting of the pin
2031  * mux function as 'gpio output' will be handled by the pinctrl susbsystem
2032  * interface.
2033  */
2034 static int rockchip_gpio_direction_output(struct gpio_chip *gc,
2035                                           unsigned offset, int value)
2036 {
2037         rockchip_gpio_set(gc, offset, value);
2038         return pinctrl_gpio_direction_output(gc->base + offset);
2039 }
2040
2041 /*
2042  * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
2043  * and a virtual IRQ, if not already present.
2044  */
2045 static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
2046 {
2047         struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
2048         unsigned int virq;
2049
2050         if (!bank->domain)
2051                 return -ENXIO;
2052
2053         virq = irq_create_mapping(bank->domain, offset);
2054
2055         return (virq) ? : -ENXIO;
2056 }
2057
2058 static const struct gpio_chip rockchip_gpiolib_chip = {
2059         .request = gpiochip_generic_request,
2060         .free = gpiochip_generic_free,
2061         .set = rockchip_gpio_set,
2062         .get = rockchip_gpio_get,
2063         .get_direction  = rockchip_gpio_get_direction,
2064         .direction_input = rockchip_gpio_direction_input,
2065         .direction_output = rockchip_gpio_direction_output,
2066         .to_irq = rockchip_gpio_to_irq,
2067         .owner = THIS_MODULE,
2068 };
2069
2070 /*
2071  * Interrupt handling
2072  */
2073
2074 static void rockchip_irq_demux(struct irq_desc *desc)
2075 {
2076         struct irq_chip *chip = irq_desc_get_chip(desc);
2077         struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc);
2078         u32 pend;
2079
2080         dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name);
2081
2082         chained_irq_enter(chip, desc);
2083
2084         pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS);
2085
2086         while (pend) {
2087                 unsigned int irq, virq;
2088
2089                 irq = __ffs(pend);
2090                 pend &= ~BIT(irq);
2091                 virq = irq_linear_revmap(bank->domain, irq);
2092
2093                 if (!virq) {
2094                         dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq);
2095                         continue;
2096                 }
2097
2098                 dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq);
2099
2100                 /*
2101                  * Triggering IRQ on both rising and falling edge
2102                  * needs manual intervention.
2103                  */
2104                 if (bank->toggle_edge_mode & BIT(irq)) {
2105                         u32 data, data_old, polarity;
2106                         unsigned long flags;
2107
2108                         data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT);
2109                         do {
2110                                 spin_lock_irqsave(&bank->slock, flags);
2111
2112                                 polarity = readl_relaxed(bank->reg_base +
2113                                                          GPIO_INT_POLARITY);
2114                                 if (data & BIT(irq))
2115                                         polarity &= ~BIT(irq);
2116                                 else
2117                                         polarity |= BIT(irq);
2118                                 writel(polarity,
2119                                        bank->reg_base + GPIO_INT_POLARITY);
2120
2121                                 spin_unlock_irqrestore(&bank->slock, flags);
2122
2123                                 data_old = data;
2124                                 data = readl_relaxed(bank->reg_base +
2125                                                      GPIO_EXT_PORT);
2126                         } while ((data & BIT(irq)) != (data_old & BIT(irq)));
2127                 }
2128
2129                 generic_handle_irq(virq);
2130         }
2131
2132         chained_irq_exit(chip, desc);
2133 }
2134
2135 static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
2136 {
2137         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2138         struct rockchip_pin_bank *bank = gc->private;
2139         u32 mask = BIT(d->hwirq);
2140         u32 polarity;
2141         u32 level;
2142         u32 data;
2143         unsigned long flags;
2144         int ret;
2145
2146         /* make sure the pin is configured as gpio input */
2147         ret = rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO);
2148         if (ret < 0)
2149                 return ret;
2150
2151         clk_enable(bank->clk);
2152         spin_lock_irqsave(&bank->slock, flags);
2153
2154         data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
2155         data &= ~mask;
2156         writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
2157
2158         spin_unlock_irqrestore(&bank->slock, flags);
2159
2160         if (type & IRQ_TYPE_EDGE_BOTH)
2161                 irq_set_handler_locked(d, handle_edge_irq);
2162         else
2163                 irq_set_handler_locked(d, handle_level_irq);
2164
2165         spin_lock_irqsave(&bank->slock, flags);
2166         irq_gc_lock(gc);
2167
2168         level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL);
2169         polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY);
2170
2171         switch (type) {
2172         case IRQ_TYPE_EDGE_BOTH:
2173                 bank->toggle_edge_mode |= mask;
2174                 level |= mask;
2175
2176                 /*
2177                  * Determine gpio state. If 1 next interrupt should be falling
2178                  * otherwise rising.
2179                  */
2180                 data = readl(bank->reg_base + GPIO_EXT_PORT);
2181                 if (data & mask)
2182                         polarity &= ~mask;
2183                 else
2184                         polarity |= mask;
2185                 break;
2186         case IRQ_TYPE_EDGE_RISING:
2187                 bank->toggle_edge_mode &= ~mask;
2188                 level |= mask;
2189                 polarity |= mask;
2190                 break;
2191         case IRQ_TYPE_EDGE_FALLING:
2192                 bank->toggle_edge_mode &= ~mask;
2193                 level |= mask;
2194                 polarity &= ~mask;
2195                 break;
2196         case IRQ_TYPE_LEVEL_HIGH:
2197                 bank->toggle_edge_mode &= ~mask;
2198                 level &= ~mask;
2199                 polarity |= mask;
2200                 break;
2201         case IRQ_TYPE_LEVEL_LOW:
2202                 bank->toggle_edge_mode &= ~mask;
2203                 level &= ~mask;
2204                 polarity &= ~mask;
2205                 break;
2206         default:
2207                 irq_gc_unlock(gc);
2208                 spin_unlock_irqrestore(&bank->slock, flags);
2209                 clk_disable(bank->clk);
2210                 return -EINVAL;
2211         }
2212
2213         writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL);
2214         writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY);
2215
2216         irq_gc_unlock(gc);
2217         spin_unlock_irqrestore(&bank->slock, flags);
2218         clk_disable(bank->clk);
2219
2220         return 0;
2221 }
2222
2223 static void rockchip_irq_suspend(struct irq_data *d)
2224 {
2225         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2226         struct rockchip_pin_bank *bank = gc->private;
2227
2228         clk_enable(bank->clk);
2229         bank->saved_masks = irq_reg_readl(gc, GPIO_INTMASK);
2230         irq_reg_writel(gc, ~gc->wake_active, GPIO_INTMASK);
2231         clk_disable(bank->clk);
2232 }
2233
2234 static void rockchip_irq_resume(struct irq_data *d)
2235 {
2236         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2237         struct rockchip_pin_bank *bank = gc->private;
2238
2239         clk_enable(bank->clk);
2240         irq_reg_writel(gc, bank->saved_masks, GPIO_INTMASK);
2241         clk_disable(bank->clk);
2242 }
2243
2244 static void rockchip_irq_enable(struct irq_data *d)
2245 {
2246         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2247         struct rockchip_pin_bank *bank = gc->private;
2248
2249         clk_enable(bank->clk);
2250         irq_gc_mask_clr_bit(d);
2251 }
2252
2253 static void rockchip_irq_disable(struct irq_data *d)
2254 {
2255         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2256         struct rockchip_pin_bank *bank = gc->private;
2257
2258         irq_gc_mask_set_bit(d);
2259         clk_disable(bank->clk);
2260 }
2261
2262 static int rockchip_interrupts_register(struct platform_device *pdev,
2263                                                 struct rockchip_pinctrl *info)
2264 {
2265         struct rockchip_pin_ctrl *ctrl = info->ctrl;
2266         struct rockchip_pin_bank *bank = ctrl->pin_banks;
2267         unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
2268         struct irq_chip_generic *gc;
2269         int ret;
2270         int i, j;
2271
2272         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2273                 if (!bank->valid) {
2274                         dev_warn(&pdev->dev, "bank %s is not valid\n",
2275                                  bank->name);
2276                         continue;
2277                 }
2278
2279                 ret = clk_enable(bank->clk);
2280                 if (ret) {
2281                         dev_err(&pdev->dev, "failed to enable clock for bank %s\n",
2282                                 bank->name);
2283                         continue;
2284                 }
2285
2286                 bank->domain = irq_domain_add_linear(bank->of_node, 32,
2287                                                 &irq_generic_chip_ops, NULL);
2288                 if (!bank->domain) {
2289                         dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n",
2290                                  bank->name);
2291                         clk_disable(bank->clk);
2292                         continue;
2293                 }
2294
2295                 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
2296                                          "rockchip_gpio_irq", handle_level_irq,
2297                                          clr, 0, IRQ_GC_INIT_MASK_CACHE);
2298                 if (ret) {
2299                         dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n",
2300                                 bank->name);
2301                         irq_domain_remove(bank->domain);
2302                         clk_disable(bank->clk);
2303                         continue;
2304                 }
2305
2306                 /*
2307                  * Linux assumes that all interrupts start out disabled/masked.
2308                  * Our driver only uses the concept of masked and always keeps
2309                  * things enabled, so for us that's all masked and all enabled.
2310                  */
2311                 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTMASK);
2312                 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTEN);
2313
2314                 gc = irq_get_domain_generic_chip(bank->domain, 0);
2315                 gc->reg_base = bank->reg_base;
2316                 gc->private = bank;
2317                 gc->chip_types[0].regs.mask = GPIO_INTMASK;
2318                 gc->chip_types[0].regs.ack = GPIO_PORTS_EOI;
2319                 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
2320                 gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit;
2321                 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit;
2322                 gc->chip_types[0].chip.irq_enable = rockchip_irq_enable;
2323                 gc->chip_types[0].chip.irq_disable = rockchip_irq_disable;
2324                 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
2325                 gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend;
2326                 gc->chip_types[0].chip.irq_resume = rockchip_irq_resume;
2327                 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
2328                 gc->wake_enabled = IRQ_MSK(bank->nr_pins);
2329
2330                 irq_set_chained_handler_and_data(bank->irq,
2331                                                  rockchip_irq_demux, bank);
2332
2333                 /* map the gpio irqs here, when the clock is still running */
2334                 for (j = 0 ; j < 32 ; j++)
2335                         irq_create_mapping(bank->domain, j);
2336
2337                 clk_disable(bank->clk);
2338         }
2339
2340         return 0;
2341 }
2342
2343 static int rockchip_gpiolib_register(struct platform_device *pdev,
2344                                                 struct rockchip_pinctrl *info)
2345 {
2346         struct rockchip_pin_ctrl *ctrl = info->ctrl;
2347         struct rockchip_pin_bank *bank = ctrl->pin_banks;
2348         struct gpio_chip *gc;
2349         int ret;
2350         int i;
2351
2352         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2353                 if (!bank->valid) {
2354                         dev_warn(&pdev->dev, "bank %s is not valid\n",
2355                                  bank->name);
2356                         continue;
2357                 }
2358
2359                 bank->gpio_chip = rockchip_gpiolib_chip;
2360
2361                 gc = &bank->gpio_chip;
2362                 gc->base = bank->pin_base;
2363                 gc->ngpio = bank->nr_pins;
2364                 gc->parent = &pdev->dev;
2365                 gc->of_node = bank->of_node;
2366                 gc->label = bank->name;
2367
2368                 ret = gpiochip_add_data(gc, bank);
2369                 if (ret) {
2370                         dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n",
2371                                                         gc->label, ret);
2372                         goto fail;
2373                 }
2374         }
2375
2376         rockchip_interrupts_register(pdev, info);
2377
2378         return 0;
2379
2380 fail:
2381         for (--i, --bank; i >= 0; --i, --bank) {
2382                 if (!bank->valid)
2383                         continue;
2384                 gpiochip_remove(&bank->gpio_chip);
2385         }
2386         return ret;
2387 }
2388
2389 static int rockchip_gpiolib_unregister(struct platform_device *pdev,
2390                                                 struct rockchip_pinctrl *info)
2391 {
2392         struct rockchip_pin_ctrl *ctrl = info->ctrl;
2393         struct rockchip_pin_bank *bank = ctrl->pin_banks;
2394         int i;
2395
2396         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2397                 if (!bank->valid)
2398                         continue;
2399                 gpiochip_remove(&bank->gpio_chip);
2400         }
2401
2402         return 0;
2403 }
2404
2405 static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
2406                                   struct rockchip_pinctrl *info)
2407 {
2408         struct resource res;
2409         void __iomem *base;
2410
2411         if (of_address_to_resource(bank->of_node, 0, &res)) {
2412                 dev_err(info->dev, "cannot find IO resource for bank\n");
2413                 return -ENOENT;
2414         }
2415
2416         bank->reg_base = devm_ioremap_resource(info->dev, &res);
2417         if (IS_ERR(bank->reg_base))
2418                 return PTR_ERR(bank->reg_base);
2419
2420         /*
2421          * special case, where parts of the pull setting-registers are
2422          * part of the PMU register space
2423          */
2424         if (of_device_is_compatible(bank->of_node,
2425                                     "rockchip,rk3188-gpio-bank0")) {
2426                 struct device_node *node;
2427
2428                 node = of_parse_phandle(bank->of_node->parent,
2429                                         "rockchip,pmu", 0);
2430                 if (!node) {
2431                         if (of_address_to_resource(bank->of_node, 1, &res)) {
2432                                 dev_err(info->dev, "cannot find IO resource for bank\n");
2433                                 return -ENOENT;
2434                         }
2435
2436                         base = devm_ioremap_resource(info->dev, &res);
2437                         if (IS_ERR(base))
2438                                 return PTR_ERR(base);
2439                         rockchip_regmap_config.max_register =
2440                                                     resource_size(&res) - 4;
2441                         rockchip_regmap_config.name =
2442                                             "rockchip,rk3188-gpio-bank0-pull";
2443                         bank->regmap_pull = devm_regmap_init_mmio(info->dev,
2444                                                     base,
2445                                                     &rockchip_regmap_config);
2446                 }
2447         }
2448
2449         bank->irq = irq_of_parse_and_map(bank->of_node, 0);
2450
2451         bank->clk = of_clk_get(bank->of_node, 0);
2452         if (IS_ERR(bank->clk))
2453                 return PTR_ERR(bank->clk);
2454
2455         return clk_prepare(bank->clk);
2456 }
2457
2458 static const struct of_device_id rockchip_pinctrl_dt_match[];
2459
2460 /* retrieve the soc specific data */
2461 static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
2462                                                 struct rockchip_pinctrl *d,
2463                                                 struct platform_device *pdev)
2464 {
2465         const struct of_device_id *match;
2466         struct device_node *node = pdev->dev.of_node;
2467         struct device_node *np;
2468         struct rockchip_pin_ctrl *ctrl;
2469         struct rockchip_pin_bank *bank;
2470         int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j;
2471
2472         match = of_match_node(rockchip_pinctrl_dt_match, node);
2473         ctrl = (struct rockchip_pin_ctrl *)match->data;
2474
2475         for_each_child_of_node(node, np) {
2476                 if (!of_find_property(np, "gpio-controller", NULL))
2477                         continue;
2478
2479                 bank = ctrl->pin_banks;
2480                 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2481                         if (!strcmp(bank->name, np->name)) {
2482                                 bank->of_node = np;
2483
2484                                 if (!rockchip_get_bank_data(bank, d))
2485                                         bank->valid = true;
2486
2487                                 break;
2488                         }
2489                 }
2490         }
2491
2492         grf_offs = ctrl->grf_mux_offset;
2493         pmu_offs = ctrl->pmu_mux_offset;
2494         drv_pmu_offs = ctrl->pmu_drv_offset;
2495         drv_grf_offs = ctrl->grf_drv_offset;
2496         bank = ctrl->pin_banks;
2497         for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2498                 int bank_pins = 0;
2499
2500                 spin_lock_init(&bank->slock);
2501                 bank->drvdata = d;
2502                 bank->pin_base = ctrl->nr_pins;
2503                 ctrl->nr_pins += bank->nr_pins;
2504
2505                 /* calculate iomux and drv offsets */
2506                 for (j = 0; j < 4; j++) {
2507                         struct rockchip_iomux *iom = &bank->iomux[j];
2508                         struct rockchip_drv *drv = &bank->drv[j];
2509                         int inc;
2510
2511                         if (bank_pins >= bank->nr_pins)
2512                                 break;
2513
2514                         /* preset iomux offset value, set new start value */
2515                         if (iom->offset >= 0) {
2516                                 if (iom->type & IOMUX_SOURCE_PMU)
2517                                         pmu_offs = iom->offset;
2518                                 else
2519                                         grf_offs = iom->offset;
2520                         } else { /* set current iomux offset */
2521                                 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ?
2522                                                         pmu_offs : grf_offs;
2523                         }
2524
2525                         /* preset drv offset value, set new start value */
2526                         if (drv->offset >= 0) {
2527                                 if (iom->type & IOMUX_SOURCE_PMU)
2528                                         drv_pmu_offs = drv->offset;
2529                                 else
2530                                         drv_grf_offs = drv->offset;
2531                         } else { /* set current drv offset */
2532                                 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ?
2533                                                 drv_pmu_offs : drv_grf_offs;
2534                         }
2535
2536                         dev_dbg(d->dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n",
2537                                 i, j, iom->offset, drv->offset);
2538
2539                         /*
2540                          * Increase offset according to iomux width.
2541                          * 4bit iomux'es are spread over two registers.
2542                          */
2543                         inc = (iom->type & (IOMUX_WIDTH_4BIT |
2544                                             IOMUX_WIDTH_3BIT)) ? 8 : 4;
2545                         if (iom->type & IOMUX_SOURCE_PMU)
2546                                 pmu_offs += inc;
2547                         else
2548                                 grf_offs += inc;
2549
2550                         /*
2551                          * Increase offset according to drv width.
2552                          * 3bit drive-strenth'es are spread over two registers.
2553                          */
2554                         if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
2555                             (drv->drv_type == DRV_TYPE_IO_3V3_ONLY))
2556                                 inc = 8;
2557                         else
2558                                 inc = 4;
2559
2560                         if (iom->type & IOMUX_SOURCE_PMU)
2561                                 drv_pmu_offs += inc;
2562                         else
2563                                 drv_grf_offs += inc;
2564
2565                         bank_pins += 8;
2566                 }
2567         }
2568
2569         return ctrl;
2570 }
2571
2572 #define RK3288_GRF_GPIO6C_IOMUX         0x64
2573 #define GPIO6C6_SEL_WRITE_ENABLE        BIT(28)
2574
2575 static u32 rk3288_grf_gpio6c_iomux;
2576
2577 static int __maybe_unused rockchip_pinctrl_suspend(struct device *dev)
2578 {
2579         struct rockchip_pinctrl *info = dev_get_drvdata(dev);
2580         int ret = pinctrl_force_sleep(info->pctl_dev);
2581
2582         if (ret)
2583                 return ret;
2584
2585         /*
2586          * RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save
2587          * the setting here, and restore it at resume.
2588          */
2589         if (info->ctrl->type == RK3288) {
2590                 ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
2591                                   &rk3288_grf_gpio6c_iomux);
2592                 if (ret) {
2593                         pinctrl_force_default(info->pctl_dev);
2594                         return ret;
2595                 }
2596         }
2597
2598         return 0;
2599 }
2600
2601 static int __maybe_unused rockchip_pinctrl_resume(struct device *dev)
2602 {
2603         struct rockchip_pinctrl *info = dev_get_drvdata(dev);
2604         int ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
2605                                rk3288_grf_gpio6c_iomux |
2606                                GPIO6C6_SEL_WRITE_ENABLE);
2607
2608         if (ret)
2609                 return ret;
2610
2611         return pinctrl_force_default(info->pctl_dev);
2612 }
2613
2614 static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend,
2615                          rockchip_pinctrl_resume);
2616
2617 static int rockchip_pinctrl_probe(struct platform_device *pdev)
2618 {
2619         struct rockchip_pinctrl *info;
2620         struct device *dev = &pdev->dev;
2621         struct rockchip_pin_ctrl *ctrl;
2622         struct device_node *np = pdev->dev.of_node, *node;
2623         struct resource *res;
2624         void __iomem *base;
2625         int ret;
2626
2627         if (!dev->of_node) {
2628                 dev_err(dev, "device tree node not found\n");
2629                 return -ENODEV;
2630         }
2631
2632         info = devm_kzalloc(dev, sizeof(struct rockchip_pinctrl), GFP_KERNEL);
2633         if (!info)
2634                 return -ENOMEM;
2635
2636         info->dev = dev;
2637
2638         ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
2639         if (!ctrl) {
2640                 dev_err(dev, "driver data not available\n");
2641                 return -EINVAL;
2642         }
2643         info->ctrl = ctrl;
2644
2645         node = of_parse_phandle(np, "rockchip,grf", 0);
2646         if (node) {
2647                 info->regmap_base = syscon_node_to_regmap(node);
2648                 if (IS_ERR(info->regmap_base))
2649                         return PTR_ERR(info->regmap_base);
2650         } else {
2651                 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2652                 base = devm_ioremap_resource(&pdev->dev, res);
2653                 if (IS_ERR(base))
2654                         return PTR_ERR(base);
2655
2656                 rockchip_regmap_config.max_register = resource_size(res) - 4;
2657                 rockchip_regmap_config.name = "rockchip,pinctrl";
2658                 info->regmap_base = devm_regmap_init_mmio(&pdev->dev, base,
2659                                                     &rockchip_regmap_config);
2660
2661                 /* to check for the old dt-bindings */
2662                 info->reg_size = resource_size(res);
2663
2664                 /* Honor the old binding, with pull registers as 2nd resource */
2665                 if (ctrl->type == RK3188 && info->reg_size < 0x200) {
2666                         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2667                         base = devm_ioremap_resource(&pdev->dev, res);
2668                         if (IS_ERR(base))
2669                                 return PTR_ERR(base);
2670
2671                         rockchip_regmap_config.max_register =
2672                                                         resource_size(res) - 4;
2673                         rockchip_regmap_config.name = "rockchip,pinctrl-pull";
2674                         info->regmap_pull = devm_regmap_init_mmio(&pdev->dev,
2675                                                     base,
2676                                                     &rockchip_regmap_config);
2677                 }
2678         }
2679
2680         /* try to find the optional reference to the pmu syscon */
2681         node = of_parse_phandle(np, "rockchip,pmu", 0);
2682         if (node) {
2683                 info->regmap_pmu = syscon_node_to_regmap(node);
2684                 if (IS_ERR(info->regmap_pmu))
2685                         return PTR_ERR(info->regmap_pmu);
2686         }
2687
2688         ret = rockchip_gpiolib_register(pdev, info);
2689         if (ret)
2690                 return ret;
2691
2692         ret = rockchip_pinctrl_register(pdev, info);
2693         if (ret) {
2694                 rockchip_gpiolib_unregister(pdev, info);
2695                 return ret;
2696         }
2697
2698         platform_set_drvdata(pdev, info);
2699
2700         return 0;
2701 }
2702
2703 static struct rockchip_pin_bank rv1108_pin_banks[] = {
2704         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
2705                                              IOMUX_SOURCE_PMU,
2706                                              IOMUX_SOURCE_PMU,
2707                                              IOMUX_SOURCE_PMU),
2708         PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
2709         PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0),
2710         PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0),
2711 };
2712
2713 static struct rockchip_pin_ctrl rv1108_pin_ctrl = {
2714         .pin_banks              = rv1108_pin_banks,
2715         .nr_banks               = ARRAY_SIZE(rv1108_pin_banks),
2716         .label                  = "RV1108-GPIO",
2717         .type                   = RV1108,
2718         .grf_mux_offset         = 0x10,
2719         .pmu_mux_offset         = 0x0,
2720         .pull_calc_reg          = rv1108_calc_pull_reg_and_bit,
2721         .drv_calc_reg           = rv1108_calc_drv_reg_and_bit,
2722 };
2723
2724 static struct rockchip_pin_bank rk2928_pin_banks[] = {
2725         PIN_BANK(0, 32, "gpio0"),
2726         PIN_BANK(1, 32, "gpio1"),
2727         PIN_BANK(2, 32, "gpio2"),
2728         PIN_BANK(3, 32, "gpio3"),
2729 };
2730
2731 static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
2732                 .pin_banks              = rk2928_pin_banks,
2733                 .nr_banks               = ARRAY_SIZE(rk2928_pin_banks),
2734                 .label                  = "RK2928-GPIO",
2735                 .type                   = RK2928,
2736                 .grf_mux_offset         = 0xa8,
2737                 .pull_calc_reg          = rk2928_calc_pull_reg_and_bit,
2738 };
2739
2740 static struct rockchip_pin_bank rk3036_pin_banks[] = {
2741         PIN_BANK(0, 32, "gpio0"),
2742         PIN_BANK(1, 32, "gpio1"),
2743         PIN_BANK(2, 32, "gpio2"),
2744 };
2745
2746 static struct rockchip_pin_ctrl rk3036_pin_ctrl = {
2747                 .pin_banks              = rk3036_pin_banks,
2748                 .nr_banks               = ARRAY_SIZE(rk3036_pin_banks),
2749                 .label                  = "RK3036-GPIO",
2750                 .type                   = RK2928,
2751                 .grf_mux_offset         = 0xa8,
2752                 .pull_calc_reg          = rk2928_calc_pull_reg_and_bit,
2753 };
2754
2755 static struct rockchip_pin_bank rk3066a_pin_banks[] = {
2756         PIN_BANK(0, 32, "gpio0"),
2757         PIN_BANK(1, 32, "gpio1"),
2758         PIN_BANK(2, 32, "gpio2"),
2759         PIN_BANK(3, 32, "gpio3"),
2760         PIN_BANK(4, 32, "gpio4"),
2761         PIN_BANK(6, 16, "gpio6"),
2762 };
2763
2764 static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
2765                 .pin_banks              = rk3066a_pin_banks,
2766                 .nr_banks               = ARRAY_SIZE(rk3066a_pin_banks),
2767                 .label                  = "RK3066a-GPIO",
2768                 .type                   = RK2928,
2769                 .grf_mux_offset         = 0xa8,
2770                 .pull_calc_reg          = rk2928_calc_pull_reg_and_bit,
2771 };
2772
2773 static struct rockchip_pin_bank rk3066b_pin_banks[] = {
2774         PIN_BANK(0, 32, "gpio0"),
2775         PIN_BANK(1, 32, "gpio1"),
2776         PIN_BANK(2, 32, "gpio2"),
2777         PIN_BANK(3, 32, "gpio3"),
2778 };
2779
2780 static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
2781                 .pin_banks      = rk3066b_pin_banks,
2782                 .nr_banks       = ARRAY_SIZE(rk3066b_pin_banks),
2783                 .label          = "RK3066b-GPIO",
2784                 .type           = RK3066B,
2785                 .grf_mux_offset = 0x60,
2786 };
2787
2788 static struct rockchip_pin_bank rk3188_pin_banks[] = {
2789         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
2790         PIN_BANK(1, 32, "gpio1"),
2791         PIN_BANK(2, 32, "gpio2"),
2792         PIN_BANK(3, 32, "gpio3"),
2793 };
2794
2795 static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
2796                 .pin_banks              = rk3188_pin_banks,
2797                 .nr_banks               = ARRAY_SIZE(rk3188_pin_banks),
2798                 .label                  = "RK3188-GPIO",
2799                 .type                   = RK3188,
2800                 .grf_mux_offset         = 0x60,
2801                 .pull_calc_reg          = rk3188_calc_pull_reg_and_bit,
2802 };
2803
2804 static struct rockchip_pin_bank rk3228_pin_banks[] = {
2805         PIN_BANK(0, 32, "gpio0"),
2806         PIN_BANK(1, 32, "gpio1"),
2807         PIN_BANK(2, 32, "gpio2"),
2808         PIN_BANK(3, 32, "gpio3"),
2809 };
2810
2811 static struct rockchip_pin_ctrl rk3228_pin_ctrl = {
2812                 .pin_banks              = rk3228_pin_banks,
2813                 .nr_banks               = ARRAY_SIZE(rk3228_pin_banks),
2814                 .label                  = "RK3228-GPIO",
2815                 .type                   = RK3288,
2816                 .grf_mux_offset         = 0x0,
2817                 .pull_calc_reg          = rk3228_calc_pull_reg_and_bit,
2818                 .drv_calc_reg           = rk3228_calc_drv_reg_and_bit,
2819 };
2820
2821 static struct rockchip_pin_bank rk3288_pin_banks[] = {
2822         PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU,
2823                                              IOMUX_SOURCE_PMU,
2824                                              IOMUX_SOURCE_PMU,
2825                                              IOMUX_UNROUTED
2826                             ),
2827         PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED,
2828                                              IOMUX_UNROUTED,
2829                                              IOMUX_UNROUTED,
2830                                              0
2831                             ),
2832         PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED),
2833         PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT),
2834         PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
2835                                              IOMUX_WIDTH_4BIT,
2836                                              0,
2837                                              0
2838                             ),
2839         PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED,
2840                                              0,
2841                                              0,
2842                                              IOMUX_UNROUTED
2843                             ),
2844         PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED),
2845         PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0,
2846                                              0,
2847                                              IOMUX_WIDTH_4BIT,
2848                                              IOMUX_UNROUTED
2849                             ),
2850         PIN_BANK(8, 16, "gpio8"),
2851 };
2852
2853 static struct rockchip_pin_ctrl rk3288_pin_ctrl = {
2854                 .pin_banks              = rk3288_pin_banks,
2855                 .nr_banks               = ARRAY_SIZE(rk3288_pin_banks),
2856                 .label                  = "RK3288-GPIO",
2857                 .type                   = RK3288,
2858                 .grf_mux_offset         = 0x0,
2859                 .pmu_mux_offset         = 0x84,
2860                 .pull_calc_reg          = rk3288_calc_pull_reg_and_bit,
2861                 .drv_calc_reg           = rk3288_calc_drv_reg_and_bit,
2862 };
2863
2864 static struct rockchip_pin_bank rk3328_pin_banks[] = {
2865         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0),
2866         PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
2867         PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0,
2868                              IOMUX_WIDTH_3BIT | IOMUX_RECALCED,
2869                              IOMUX_WIDTH_3BIT | IOMUX_RECALCED,
2870                              0),
2871         PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
2872                              IOMUX_WIDTH_3BIT,
2873                              IOMUX_WIDTH_3BIT | IOMUX_RECALCED,
2874                              0,
2875                              0),
2876 };
2877
2878 static struct rockchip_pin_ctrl rk3328_pin_ctrl = {
2879                 .pin_banks              = rk3328_pin_banks,
2880                 .nr_banks               = ARRAY_SIZE(rk3328_pin_banks),
2881                 .label                  = "RK3328-GPIO",
2882                 .type                   = RK3288,
2883                 .grf_mux_offset         = 0x0,
2884                 .pull_calc_reg          = rk3228_calc_pull_reg_and_bit,
2885                 .drv_calc_reg           = rk3228_calc_drv_reg_and_bit,
2886                 .iomux_recalc           = rk3328_recalc_mux,
2887                 .schmitt_calc_reg       = rk3328_calc_schmitt_reg_and_bit,
2888 };
2889
2890 static struct rockchip_pin_bank rk3368_pin_banks[] = {
2891         PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
2892                                              IOMUX_SOURCE_PMU,
2893                                              IOMUX_SOURCE_PMU,
2894                                              IOMUX_SOURCE_PMU
2895                             ),
2896         PIN_BANK(1, 32, "gpio1"),
2897         PIN_BANK(2, 32, "gpio2"),
2898         PIN_BANK(3, 32, "gpio3"),
2899 };
2900
2901 static struct rockchip_pin_ctrl rk3368_pin_ctrl = {
2902                 .pin_banks              = rk3368_pin_banks,
2903                 .nr_banks               = ARRAY_SIZE(rk3368_pin_banks),
2904                 .label                  = "RK3368-GPIO",
2905                 .type                   = RK3368,
2906                 .grf_mux_offset         = 0x0,
2907                 .pmu_mux_offset         = 0x0,
2908                 .pull_calc_reg          = rk3368_calc_pull_reg_and_bit,
2909                 .drv_calc_reg           = rk3368_calc_drv_reg_and_bit,
2910 };
2911
2912 static struct rockchip_pin_bank rk3399_pin_banks[] = {
2913         PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0",
2914                                                          IOMUX_SOURCE_PMU,
2915                                                          IOMUX_SOURCE_PMU,
2916                                                          IOMUX_SOURCE_PMU,
2917                                                          IOMUX_SOURCE_PMU,
2918                                                          DRV_TYPE_IO_1V8_ONLY,
2919                                                          DRV_TYPE_IO_1V8_ONLY,
2920                                                          DRV_TYPE_IO_DEFAULT,
2921                                                          DRV_TYPE_IO_DEFAULT,
2922                                                          0x0,
2923                                                          0x8,
2924                                                          -1,
2925                                                          -1,
2926                                                          PULL_TYPE_IO_1V8_ONLY,
2927                                                          PULL_TYPE_IO_1V8_ONLY,
2928                                                          PULL_TYPE_IO_DEFAULT,
2929                                                          PULL_TYPE_IO_DEFAULT
2930                                                         ),
2931         PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU,
2932                                         IOMUX_SOURCE_PMU,
2933                                         IOMUX_SOURCE_PMU,
2934                                         IOMUX_SOURCE_PMU,
2935                                         DRV_TYPE_IO_1V8_OR_3V0,
2936                                         DRV_TYPE_IO_1V8_OR_3V0,
2937                                         DRV_TYPE_IO_1V8_OR_3V0,
2938                                         DRV_TYPE_IO_1V8_OR_3V0,
2939                                         0x20,
2940                                         0x28,
2941                                         0x30,
2942                                         0x38
2943                                         ),
2944         PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0,
2945                                       DRV_TYPE_IO_1V8_OR_3V0,
2946                                       DRV_TYPE_IO_1V8_ONLY,
2947                                       DRV_TYPE_IO_1V8_ONLY,
2948                                       PULL_TYPE_IO_DEFAULT,
2949                                       PULL_TYPE_IO_DEFAULT,
2950                                       PULL_TYPE_IO_1V8_ONLY,
2951                                       PULL_TYPE_IO_1V8_ONLY
2952                                       ),
2953         PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY,
2954                            DRV_TYPE_IO_3V3_ONLY,
2955                            DRV_TYPE_IO_3V3_ONLY,
2956                            DRV_TYPE_IO_1V8_OR_3V0
2957                            ),
2958         PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0,
2959                            DRV_TYPE_IO_1V8_3V0_AUTO,
2960                            DRV_TYPE_IO_1V8_OR_3V0,
2961                            DRV_TYPE_IO_1V8_OR_3V0
2962                            ),
2963 };
2964
2965 static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
2966                 .pin_banks              = rk3399_pin_banks,
2967                 .nr_banks               = ARRAY_SIZE(rk3399_pin_banks),
2968                 .label                  = "RK3399-GPIO",
2969                 .type                   = RK3399,
2970                 .grf_mux_offset         = 0xe000,
2971                 .pmu_mux_offset         = 0x0,
2972                 .grf_drv_offset         = 0xe100,
2973                 .pmu_drv_offset         = 0x80,
2974                 .pull_calc_reg          = rk3399_calc_pull_reg_and_bit,
2975                 .drv_calc_reg           = rk3399_calc_drv_reg_and_bit,
2976 };
2977
2978 static const struct of_device_id rockchip_pinctrl_dt_match[] = {
2979         { .compatible = "rockchip,rv1108-pinctrl",
2980                 .data = (void *)&rv1108_pin_ctrl },
2981         { .compatible = "rockchip,rk2928-pinctrl",
2982                 .data = (void *)&rk2928_pin_ctrl },
2983         { .compatible = "rockchip,rk3036-pinctrl",
2984                 .data = (void *)&rk3036_pin_ctrl },
2985         { .compatible = "rockchip,rk3066a-pinctrl",
2986                 .data = (void *)&rk3066a_pin_ctrl },
2987         { .compatible = "rockchip,rk3066b-pinctrl",
2988                 .data = (void *)&rk3066b_pin_ctrl },
2989         { .compatible = "rockchip,rk3188-pinctrl",
2990                 .data = (void *)&rk3188_pin_ctrl },
2991         { .compatible = "rockchip,rk3228-pinctrl",
2992                 .data = (void *)&rk3228_pin_ctrl },
2993         { .compatible = "rockchip,rk3288-pinctrl",
2994                 .data = (void *)&rk3288_pin_ctrl },
2995         { .compatible = "rockchip,rk3328-pinctrl",
2996                 .data = (void *)&rk3328_pin_ctrl },
2997         { .compatible = "rockchip,rk3368-pinctrl",
2998                 .data = (void *)&rk3368_pin_ctrl },
2999         { .compatible = "rockchip,rk3399-pinctrl",
3000                 .data = (void *)&rk3399_pin_ctrl },
3001         {},
3002 };
3003
3004 static struct platform_driver rockchip_pinctrl_driver = {
3005         .probe          = rockchip_pinctrl_probe,
3006         .driver = {
3007                 .name   = "rockchip-pinctrl",
3008                 .pm = &rockchip_pinctrl_dev_pm_ops,
3009                 .of_match_table = rockchip_pinctrl_dt_match,
3010         },
3011 };
3012
3013 static int __init rockchip_pinctrl_drv_register(void)
3014 {
3015         return platform_driver_register(&rockchip_pinctrl_driver);
3016 }
3017 postcore_initcall(rockchip_pinctrl_drv_register);