2 * Generic device tree based pinctrl driver for one register per pin
3 * type pinmux controllers
5 * Copyright (C) 2012 Texas Instruments, Inc.
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
12 #include <linux/init.h>
13 #include <linux/module.h>
15 #include <linux/slab.h>
16 #include <linux/err.h>
17 #include <linux/list.h>
18 #include <linux/interrupt.h>
20 #include <linux/irqchip/chained_irq.h>
23 #include <linux/of_device.h>
24 #include <linux/of_address.h>
25 #include <linux/of_irq.h>
27 #include <linux/pinctrl/pinctrl.h>
28 #include <linux/pinctrl/pinmux.h>
29 #include <linux/pinctrl/pinconf-generic.h>
31 #include <linux/platform_data/pinctrl-single.h>
36 #define DRIVER_NAME "pinctrl-single"
37 #define PCS_MUX_PINS_NAME "pinctrl-single,pins"
38 #define PCS_MUX_BITS_NAME "pinctrl-single,bits"
39 #define PCS_REG_NAME_LEN ((sizeof(unsigned long) * 2) + 3)
40 #define PCS_OFF_DISABLED ~0U
43 * struct pcs_pingroup - pingroups for a function
44 * @np: pingroup device node pointer
45 * @name: pingroup name
46 * @gpins: array of the pins in the group
47 * @ngpins: number of pins in the group
51 struct device_node *np;
55 struct list_head node;
59 * struct pcs_func_vals - mux function register offset and value pair
60 * @reg: register virtual address
61 * @val: register value
63 struct pcs_func_vals {
70 * struct pcs_conf_vals - pinconf parameter, pinconf register offset
71 * and value, enable, disable, mask
72 * @param: config parameter
73 * @val: user input bits in the pinconf register
74 * @enable: enable bits in the pinconf register
75 * @disable: disable bits in the pinconf register
76 * @mask: mask bits in the register value
78 struct pcs_conf_vals {
79 enum pin_config_param param;
87 * struct pcs_conf_type - pinconf property name, pinconf param pair
88 * @name: property name in DTS file
89 * @param: config parameter
91 struct pcs_conf_type {
93 enum pin_config_param param;
97 * struct pcs_function - pinctrl function
98 * @name: pinctrl function name
99 * @vals: register and vals array
100 * @nvals: number of entries in vals array
101 * @pgnames: array of pingroup names the function uses
102 * @npgnames: number of pingroup names the function uses
105 struct pcs_function {
107 struct pcs_func_vals *vals;
109 const char **pgnames;
111 struct pcs_conf_vals *conf;
113 struct list_head node;
117 * struct pcs_gpiofunc_range - pin ranges with same mux value of gpio function
118 * @offset: offset base of pins
119 * @npins: number pins with the same mux value of gpio function
120 * @gpiofunc: mux value of gpio function
123 struct pcs_gpiofunc_range {
127 struct list_head node;
131 * struct pcs_data - wrapper for data needed by pinctrl framework
133 * @cur: index to current element
135 * REVISIT: We should be able to drop this eventually by adding
136 * support for registering pins individually in the pinctrl
137 * framework for those drivers that don't need a static array.
140 struct pinctrl_pin_desc *pa;
145 * struct pcs_name - register name for a pin
146 * @name: name of the pinctrl register
148 * REVISIT: We may want to make names optional in the pinctrl
149 * framework as some drivers may not care about pin names to
150 * avoid kernel bloat. The pin names can be deciphered by user
151 * space tools using debugfs based on the register address and
152 * SoC packaging information.
155 char name[PCS_REG_NAME_LEN];
159 * struct pcs_soc_data - SoC specific settings
160 * @flags: initial SoC specific PCS_FEAT_xxx values
161 * @irq: optional interrupt for the controller
162 * @irq_enable_mask: optional SoC specific interrupt enable mask
163 * @irq_status_mask: optional SoC specific interrupt status mask
164 * @rearm: optional SoC specific wake-up rearm function
166 struct pcs_soc_data {
169 unsigned irq_enable_mask;
170 unsigned irq_status_mask;
175 * struct pcs_device - pinctrl device instance
177 * @base: virtual address of the controller
178 * @size: size of the ioremapped area
180 * @pctl: pin controller device
181 * @flags: mask of PCS_FEAT_xxx values
182 * @lock: spinlock for register access
183 * @mutex: mutex protecting the lists
184 * @width: bits per mux register
185 * @fmask: function register mask
186 * @fshift: function register shift
187 * @foff: value to turn mux off
188 * @fmax: max number of functions in fmask
189 * @bits_per_pin:number of bits per pin
190 * @names: array of register names for pins
191 * @pins: physical pins on the SoC
192 * @pgtree: pingroup index radix tree
193 * @ftree: function index radix tree
194 * @pingroups: list of pingroups
195 * @functions: list of functions
196 * @gpiofuncs: list of gpio functions
197 * @irqs: list of interrupt registers
198 * @chip: chip container for this instance
199 * @domain: IRQ domain for this instance
200 * @ngroups: number of pingroups
201 * @nfuncs: number of functions
202 * @desc: pin controller descriptor
203 * @read: register read function to use
204 * @write: register write function to use
207 struct resource *res;
211 struct pinctrl_dev *pctl;
213 #define PCS_QUIRK_SHARED_IRQ (1 << 2)
214 #define PCS_FEAT_IRQ (1 << 1)
215 #define PCS_FEAT_PINCONF (1 << 0)
216 struct pcs_soc_data socdata;
225 unsigned bits_per_pin;
226 struct pcs_name *names;
227 struct pcs_data pins;
228 struct radix_tree_root pgtree;
229 struct radix_tree_root ftree;
230 struct list_head pingroups;
231 struct list_head functions;
232 struct list_head gpiofuncs;
233 struct list_head irqs;
234 struct irq_chip chip;
235 struct irq_domain *domain;
238 struct pinctrl_desc desc;
239 unsigned (*read)(void __iomem *reg);
240 void (*write)(unsigned val, void __iomem *reg);
243 #define PCS_QUIRK_HAS_SHARED_IRQ (pcs->flags & PCS_QUIRK_SHARED_IRQ)
244 #define PCS_HAS_IRQ (pcs->flags & PCS_FEAT_IRQ)
245 #define PCS_HAS_PINCONF (pcs->flags & PCS_FEAT_PINCONF)
247 static int pcs_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin,
248 unsigned long *config);
249 static int pcs_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin,
250 unsigned long *configs, unsigned num_configs);
252 static enum pin_config_param pcs_bias[] = {
253 PIN_CONFIG_BIAS_PULL_DOWN,
254 PIN_CONFIG_BIAS_PULL_UP,
258 * This lock class tells lockdep that irqchip core that this single
259 * pinctrl can be in a different category than its parents, so it won't
260 * report false recursion.
262 static struct lock_class_key pcs_lock_class;
265 * REVISIT: Reads and writes could eventually use regmap or something
266 * generic. But at least on omaps, some mux registers are performance
267 * critical as they may need to be remuxed every time before and after
268 * idle. Adding tests for register access width for every read and
269 * write like regmap is doing is not desired, and caching the registers
270 * does not help in this case.
273 static unsigned __maybe_unused pcs_readb(void __iomem *reg)
278 static unsigned __maybe_unused pcs_readw(void __iomem *reg)
283 static unsigned __maybe_unused pcs_readl(void __iomem *reg)
288 static void __maybe_unused pcs_writeb(unsigned val, void __iomem *reg)
293 static void __maybe_unused pcs_writew(unsigned val, void __iomem *reg)
298 static void __maybe_unused pcs_writel(unsigned val, void __iomem *reg)
303 static int pcs_get_groups_count(struct pinctrl_dev *pctldev)
305 struct pcs_device *pcs;
307 pcs = pinctrl_dev_get_drvdata(pctldev);
312 static const char *pcs_get_group_name(struct pinctrl_dev *pctldev,
315 struct pcs_device *pcs;
316 struct pcs_pingroup *group;
318 pcs = pinctrl_dev_get_drvdata(pctldev);
319 group = radix_tree_lookup(&pcs->pgtree, gselector);
321 dev_err(pcs->dev, "%s could not find pingroup%i\n",
322 __func__, gselector);
329 static int pcs_get_group_pins(struct pinctrl_dev *pctldev,
331 const unsigned **pins,
334 struct pcs_device *pcs;
335 struct pcs_pingroup *group;
337 pcs = pinctrl_dev_get_drvdata(pctldev);
338 group = radix_tree_lookup(&pcs->pgtree, gselector);
340 dev_err(pcs->dev, "%s could not find pingroup%i\n",
341 __func__, gselector);
345 *pins = group->gpins;
346 *npins = group->ngpins;
351 static void pcs_pin_dbg_show(struct pinctrl_dev *pctldev,
355 struct pcs_device *pcs;
356 unsigned val, mux_bytes;
358 pcs = pinctrl_dev_get_drvdata(pctldev);
360 mux_bytes = pcs->width / BITS_PER_BYTE;
361 val = pcs->read(pcs->base + pin * mux_bytes);
363 seq_printf(s, "%08x %s " , val, DRIVER_NAME);
366 static void pcs_dt_free_map(struct pinctrl_dev *pctldev,
367 struct pinctrl_map *map, unsigned num_maps)
369 struct pcs_device *pcs;
371 pcs = pinctrl_dev_get_drvdata(pctldev);
372 devm_kfree(pcs->dev, map);
375 static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
376 struct device_node *np_config,
377 struct pinctrl_map **map, unsigned *num_maps);
379 static const struct pinctrl_ops pcs_pinctrl_ops = {
380 .get_groups_count = pcs_get_groups_count,
381 .get_group_name = pcs_get_group_name,
382 .get_group_pins = pcs_get_group_pins,
383 .pin_dbg_show = pcs_pin_dbg_show,
384 .dt_node_to_map = pcs_dt_node_to_map,
385 .dt_free_map = pcs_dt_free_map,
388 static int pcs_get_functions_count(struct pinctrl_dev *pctldev)
390 struct pcs_device *pcs;
392 pcs = pinctrl_dev_get_drvdata(pctldev);
397 static const char *pcs_get_function_name(struct pinctrl_dev *pctldev,
400 struct pcs_device *pcs;
401 struct pcs_function *func;
403 pcs = pinctrl_dev_get_drvdata(pctldev);
404 func = radix_tree_lookup(&pcs->ftree, fselector);
406 dev_err(pcs->dev, "%s could not find function%i\n",
407 __func__, fselector);
414 static int pcs_get_function_groups(struct pinctrl_dev *pctldev,
416 const char * const **groups,
417 unsigned * const ngroups)
419 struct pcs_device *pcs;
420 struct pcs_function *func;
422 pcs = pinctrl_dev_get_drvdata(pctldev);
423 func = radix_tree_lookup(&pcs->ftree, fselector);
425 dev_err(pcs->dev, "%s could not find function%i\n",
426 __func__, fselector);
429 *groups = func->pgnames;
430 *ngroups = func->npgnames;
435 static int pcs_get_function(struct pinctrl_dev *pctldev, unsigned pin,
436 struct pcs_function **func)
438 struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
439 struct pin_desc *pdesc = pin_desc_get(pctldev, pin);
440 const struct pinctrl_setting_mux *setting;
443 /* If pin is not described in DTS & enabled, mux_setting is NULL. */
444 setting = pdesc->mux_setting;
447 fselector = setting->func;
448 *func = radix_tree_lookup(&pcs->ftree, fselector);
450 dev_err(pcs->dev, "%s could not find function%i\n",
451 __func__, fselector);
457 static int pcs_set_mux(struct pinctrl_dev *pctldev, unsigned fselector,
460 struct pcs_device *pcs;
461 struct pcs_function *func;
464 pcs = pinctrl_dev_get_drvdata(pctldev);
465 /* If function mask is null, needn't enable it. */
468 func = radix_tree_lookup(&pcs->ftree, fselector);
472 dev_dbg(pcs->dev, "enabling %s function%i\n",
473 func->name, fselector);
475 for (i = 0; i < func->nvals; i++) {
476 struct pcs_func_vals *vals;
480 vals = &func->vals[i];
481 raw_spin_lock_irqsave(&pcs->lock, flags);
482 val = pcs->read(vals->reg);
484 if (pcs->bits_per_mux)
490 val |= (vals->val & mask);
491 pcs->write(val, vals->reg);
492 raw_spin_unlock_irqrestore(&pcs->lock, flags);
498 static int pcs_request_gpio(struct pinctrl_dev *pctldev,
499 struct pinctrl_gpio_range *range, unsigned pin)
501 struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
502 struct pcs_gpiofunc_range *frange = NULL;
503 struct list_head *pos, *tmp;
507 /* If function mask is null, return directly. */
511 list_for_each_safe(pos, tmp, &pcs->gpiofuncs) {
512 frange = list_entry(pos, struct pcs_gpiofunc_range, node);
513 if (pin >= frange->offset + frange->npins
514 || pin < frange->offset)
516 mux_bytes = pcs->width / BITS_PER_BYTE;
517 data = pcs->read(pcs->base + pin * mux_bytes) & ~pcs->fmask;
518 data |= frange->gpiofunc;
519 pcs->write(data, pcs->base + pin * mux_bytes);
525 static const struct pinmux_ops pcs_pinmux_ops = {
526 .get_functions_count = pcs_get_functions_count,
527 .get_function_name = pcs_get_function_name,
528 .get_function_groups = pcs_get_function_groups,
529 .set_mux = pcs_set_mux,
530 .gpio_request_enable = pcs_request_gpio,
533 /* Clear BIAS value */
534 static void pcs_pinconf_clear_bias(struct pinctrl_dev *pctldev, unsigned pin)
536 unsigned long config;
538 for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) {
539 config = pinconf_to_config_packed(pcs_bias[i], 0);
540 pcs_pinconf_set(pctldev, pin, &config, 1);
545 * Check whether PIN_CONFIG_BIAS_DISABLE is valid.
546 * It's depend on that PULL_DOWN & PULL_UP configs are all invalid.
548 static bool pcs_pinconf_bias_disable(struct pinctrl_dev *pctldev, unsigned pin)
550 unsigned long config;
553 for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) {
554 config = pinconf_to_config_packed(pcs_bias[i], 0);
555 if (!pcs_pinconf_get(pctldev, pin, &config))
563 static int pcs_pinconf_get(struct pinctrl_dev *pctldev,
564 unsigned pin, unsigned long *config)
566 struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
567 struct pcs_function *func;
568 enum pin_config_param param;
569 unsigned offset = 0, data = 0, i, j, ret;
571 ret = pcs_get_function(pctldev, pin, &func);
575 for (i = 0; i < func->nconfs; i++) {
576 param = pinconf_to_config_param(*config);
577 if (param == PIN_CONFIG_BIAS_DISABLE) {
578 if (pcs_pinconf_bias_disable(pctldev, pin)) {
584 } else if (param != func->conf[i].param) {
588 offset = pin * (pcs->width / BITS_PER_BYTE);
589 data = pcs->read(pcs->base + offset) & func->conf[i].mask;
590 switch (func->conf[i].param) {
592 case PIN_CONFIG_BIAS_PULL_DOWN:
593 case PIN_CONFIG_BIAS_PULL_UP:
594 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
595 if ((data != func->conf[i].enable) ||
596 (data == func->conf[i].disable))
601 case PIN_CONFIG_INPUT_SCHMITT:
602 for (j = 0; j < func->nconfs; j++) {
603 switch (func->conf[j].param) {
604 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
605 if (data != func->conf[j].enable)
614 case PIN_CONFIG_DRIVE_STRENGTH:
615 case PIN_CONFIG_SLEW_RATE:
616 case PIN_CONFIG_LOW_POWER_MODE:
626 static int pcs_pinconf_set(struct pinctrl_dev *pctldev,
627 unsigned pin, unsigned long *configs,
628 unsigned num_configs)
630 struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
631 struct pcs_function *func;
632 unsigned offset = 0, shift = 0, i, data, ret;
636 ret = pcs_get_function(pctldev, pin, &func);
640 for (j = 0; j < num_configs; j++) {
641 for (i = 0; i < func->nconfs; i++) {
642 if (pinconf_to_config_param(configs[j])
643 != func->conf[i].param)
646 offset = pin * (pcs->width / BITS_PER_BYTE);
647 data = pcs->read(pcs->base + offset);
648 arg = pinconf_to_config_argument(configs[j]);
649 switch (func->conf[i].param) {
651 case PIN_CONFIG_INPUT_SCHMITT:
652 case PIN_CONFIG_DRIVE_STRENGTH:
653 case PIN_CONFIG_SLEW_RATE:
654 case PIN_CONFIG_LOW_POWER_MODE:
655 shift = ffs(func->conf[i].mask) - 1;
656 data &= ~func->conf[i].mask;
657 data |= (arg << shift) & func->conf[i].mask;
660 case PIN_CONFIG_BIAS_DISABLE:
661 pcs_pinconf_clear_bias(pctldev, pin);
663 case PIN_CONFIG_BIAS_PULL_DOWN:
664 case PIN_CONFIG_BIAS_PULL_UP:
666 pcs_pinconf_clear_bias(pctldev, pin);
668 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
669 data &= ~func->conf[i].mask;
671 data |= func->conf[i].enable;
673 data |= func->conf[i].disable;
678 pcs->write(data, pcs->base + offset);
682 if (i >= func->nconfs)
684 } /* for each config */
689 static int pcs_pinconf_group_get(struct pinctrl_dev *pctldev,
690 unsigned group, unsigned long *config)
692 const unsigned *pins;
693 unsigned npins, old = 0;
696 ret = pcs_get_group_pins(pctldev, group, &pins, &npins);
699 for (i = 0; i < npins; i++) {
700 if (pcs_pinconf_get(pctldev, pins[i], config))
702 /* configs do not match between two pins */
703 if (i && (old != *config))
710 static int pcs_pinconf_group_set(struct pinctrl_dev *pctldev,
711 unsigned group, unsigned long *configs,
712 unsigned num_configs)
714 const unsigned *pins;
718 ret = pcs_get_group_pins(pctldev, group, &pins, &npins);
721 for (i = 0; i < npins; i++) {
722 if (pcs_pinconf_set(pctldev, pins[i], configs, num_configs))
728 static void pcs_pinconf_dbg_show(struct pinctrl_dev *pctldev,
729 struct seq_file *s, unsigned pin)
733 static void pcs_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
734 struct seq_file *s, unsigned selector)
738 static void pcs_pinconf_config_dbg_show(struct pinctrl_dev *pctldev,
740 unsigned long config)
742 pinconf_generic_dump_config(pctldev, s, config);
745 static const struct pinconf_ops pcs_pinconf_ops = {
746 .pin_config_get = pcs_pinconf_get,
747 .pin_config_set = pcs_pinconf_set,
748 .pin_config_group_get = pcs_pinconf_group_get,
749 .pin_config_group_set = pcs_pinconf_group_set,
750 .pin_config_dbg_show = pcs_pinconf_dbg_show,
751 .pin_config_group_dbg_show = pcs_pinconf_group_dbg_show,
752 .pin_config_config_dbg_show = pcs_pinconf_config_dbg_show,
757 * pcs_add_pin() - add a pin to the static per controller pin array
758 * @pcs: pcs driver instance
759 * @offset: register offset from base
761 static int pcs_add_pin(struct pcs_device *pcs, unsigned offset,
764 struct pcs_soc_data *pcs_soc = &pcs->socdata;
765 struct pinctrl_pin_desc *pin;
770 if (i >= pcs->desc.npins) {
771 dev_err(pcs->dev, "too many pins, max %i\n",
776 if (pcs_soc->irq_enable_mask) {
779 val = pcs->read(pcs->base + offset);
780 if (val & pcs_soc->irq_enable_mask) {
781 dev_dbg(pcs->dev, "irq enabled at boot for pin at %lx (%x), clearing\n",
782 (unsigned long)pcs->res->start + offset, val);
783 val &= ~pcs_soc->irq_enable_mask;
784 pcs->write(val, pcs->base + offset);
788 pin = &pcs->pins.pa[i];
790 sprintf(pn->name, "%lx.%u",
791 (unsigned long)pcs->res->start + offset, pin_pos);
792 pin->name = pn->name;
800 * pcs_allocate_pin_table() - adds all the pins for the pinctrl driver
801 * @pcs: pcs driver instance
803 * In case of errors, resources are freed in pcs_free_resources.
805 * If your hardware needs holes in the address space, then just set
806 * up multiple driver instances.
808 static int pcs_allocate_pin_table(struct pcs_device *pcs)
810 int mux_bytes, nr_pins, i;
811 int num_pins_in_register = 0;
813 mux_bytes = pcs->width / BITS_PER_BYTE;
815 if (pcs->bits_per_mux) {
816 pcs->bits_per_pin = fls(pcs->fmask);
817 nr_pins = (pcs->size * BITS_PER_BYTE) / pcs->bits_per_pin;
818 num_pins_in_register = pcs->width / pcs->bits_per_pin;
820 nr_pins = pcs->size / mux_bytes;
823 dev_dbg(pcs->dev, "allocating %i pins\n", nr_pins);
824 pcs->pins.pa = devm_kzalloc(pcs->dev,
825 sizeof(*pcs->pins.pa) * nr_pins,
830 pcs->names = devm_kzalloc(pcs->dev,
831 sizeof(struct pcs_name) * nr_pins,
836 pcs->desc.pins = pcs->pins.pa;
837 pcs->desc.npins = nr_pins;
839 for (i = 0; i < pcs->desc.npins; i++) {
845 if (pcs->bits_per_mux) {
846 byte_num = (pcs->bits_per_pin * i) / BITS_PER_BYTE;
847 offset = (byte_num / mux_bytes) * mux_bytes;
848 pin_pos = i % num_pins_in_register;
850 offset = i * mux_bytes;
852 res = pcs_add_pin(pcs, offset, pin_pos);
854 dev_err(pcs->dev, "error adding pins: %i\n", res);
863 * pcs_add_function() - adds a new function to the function list
864 * @pcs: pcs driver instance
865 * @np: device node of the mux entry
866 * @name: name of the function
867 * @vals: array of mux register value pairs used by the function
868 * @nvals: number of mux register value pairs
869 * @pgnames: array of pingroup names for the function
870 * @npgnames: number of pingroup names
872 static struct pcs_function *pcs_add_function(struct pcs_device *pcs,
873 struct device_node *np,
875 struct pcs_func_vals *vals,
877 const char **pgnames,
880 struct pcs_function *function;
882 function = devm_kzalloc(pcs->dev, sizeof(*function), GFP_KERNEL);
886 function->name = name;
887 function->vals = vals;
888 function->nvals = nvals;
889 function->pgnames = pgnames;
890 function->npgnames = npgnames;
892 mutex_lock(&pcs->mutex);
893 list_add_tail(&function->node, &pcs->functions);
894 radix_tree_insert(&pcs->ftree, pcs->nfuncs, function);
896 mutex_unlock(&pcs->mutex);
901 static void pcs_remove_function(struct pcs_device *pcs,
902 struct pcs_function *function)
906 mutex_lock(&pcs->mutex);
907 for (i = 0; i < pcs->nfuncs; i++) {
908 struct pcs_function *found;
910 found = radix_tree_lookup(&pcs->ftree, i);
911 if (found == function)
912 radix_tree_delete(&pcs->ftree, i);
914 list_del(&function->node);
915 mutex_unlock(&pcs->mutex);
919 * pcs_add_pingroup() - add a pingroup to the pingroup list
920 * @pcs: pcs driver instance
921 * @np: device node of the mux entry
922 * @name: name of the pingroup
923 * @gpins: array of the pins that belong to the group
924 * @ngpins: number of pins in the group
926 static int pcs_add_pingroup(struct pcs_device *pcs,
927 struct device_node *np,
932 struct pcs_pingroup *pingroup;
934 pingroup = devm_kzalloc(pcs->dev, sizeof(*pingroup), GFP_KERNEL);
938 pingroup->name = name;
940 pingroup->gpins = gpins;
941 pingroup->ngpins = ngpins;
943 mutex_lock(&pcs->mutex);
944 list_add_tail(&pingroup->node, &pcs->pingroups);
945 radix_tree_insert(&pcs->pgtree, pcs->ngroups, pingroup);
947 mutex_unlock(&pcs->mutex);
953 * pcs_get_pin_by_offset() - get a pin index based on the register offset
954 * @pcs: pcs driver instance
955 * @offset: register offset from the base
957 * Note that this is OK as long as the pins are in a static array.
959 static int pcs_get_pin_by_offset(struct pcs_device *pcs, unsigned offset)
963 if (offset >= pcs->size) {
964 dev_err(pcs->dev, "mux offset out of range: 0x%x (0x%x)\n",
969 if (pcs->bits_per_mux)
970 index = (offset * BITS_PER_BYTE) / pcs->bits_per_pin;
972 index = offset / (pcs->width / BITS_PER_BYTE);
978 * check whether data matches enable bits or disable bits
979 * Return value: 1 for matching enable bits, 0 for matching disable bits,
980 * and negative value for matching failure.
982 static int pcs_config_match(unsigned data, unsigned enable, unsigned disable)
988 else if (data == disable)
993 static void add_config(struct pcs_conf_vals **conf, enum pin_config_param param,
994 unsigned value, unsigned enable, unsigned disable,
997 (*conf)->param = param;
998 (*conf)->val = value;
999 (*conf)->enable = enable;
1000 (*conf)->disable = disable;
1001 (*conf)->mask = mask;
1005 static void add_setting(unsigned long **setting, enum pin_config_param param,
1008 **setting = pinconf_to_config_packed(param, arg);
1012 /* add pinconf setting with 2 parameters */
1013 static void pcs_add_conf2(struct pcs_device *pcs, struct device_node *np,
1014 const char *name, enum pin_config_param param,
1015 struct pcs_conf_vals **conf, unsigned long **settings)
1017 unsigned value[2], shift;
1020 ret = of_property_read_u32_array(np, name, value, 2);
1023 /* set value & mask */
1024 value[0] &= value[1];
1025 shift = ffs(value[1]) - 1;
1026 /* skip enable & disable */
1027 add_config(conf, param, value[0], 0, 0, value[1]);
1028 add_setting(settings, param, value[0] >> shift);
1031 /* add pinconf setting with 4 parameters */
1032 static void pcs_add_conf4(struct pcs_device *pcs, struct device_node *np,
1033 const char *name, enum pin_config_param param,
1034 struct pcs_conf_vals **conf, unsigned long **settings)
1039 /* value to set, enable, disable, mask */
1040 ret = of_property_read_u32_array(np, name, value, 4);
1044 dev_err(pcs->dev, "mask field of the property can't be 0\n");
1047 value[0] &= value[3];
1048 value[1] &= value[3];
1049 value[2] &= value[3];
1050 ret = pcs_config_match(value[0], value[1], value[2]);
1052 dev_dbg(pcs->dev, "failed to match enable or disable bits\n");
1053 add_config(conf, param, value[0], value[1], value[2], value[3]);
1054 add_setting(settings, param, ret);
1057 static int pcs_parse_pinconf(struct pcs_device *pcs, struct device_node *np,
1058 struct pcs_function *func,
1059 struct pinctrl_map **map)
1062 struct pinctrl_map *m = *map;
1063 int i = 0, nconfs = 0;
1064 unsigned long *settings = NULL, *s = NULL;
1065 struct pcs_conf_vals *conf = NULL;
1066 struct pcs_conf_type prop2[] = {
1067 { "pinctrl-single,drive-strength", PIN_CONFIG_DRIVE_STRENGTH, },
1068 { "pinctrl-single,slew-rate", PIN_CONFIG_SLEW_RATE, },
1069 { "pinctrl-single,input-schmitt", PIN_CONFIG_INPUT_SCHMITT, },
1070 { "pinctrl-single,low-power-mode", PIN_CONFIG_LOW_POWER_MODE, },
1072 struct pcs_conf_type prop4[] = {
1073 { "pinctrl-single,bias-pullup", PIN_CONFIG_BIAS_PULL_UP, },
1074 { "pinctrl-single,bias-pulldown", PIN_CONFIG_BIAS_PULL_DOWN, },
1075 { "pinctrl-single,input-schmitt-enable",
1076 PIN_CONFIG_INPUT_SCHMITT_ENABLE, },
1079 /* If pinconf isn't supported, don't parse properties in below. */
1080 if (!PCS_HAS_PINCONF)
1083 /* cacluate how much properties are supported in current node */
1084 for (i = 0; i < ARRAY_SIZE(prop2); i++) {
1085 if (of_find_property(np, prop2[i].name, NULL))
1088 for (i = 0; i < ARRAY_SIZE(prop4); i++) {
1089 if (of_find_property(np, prop4[i].name, NULL))
1095 func->conf = devm_kzalloc(pcs->dev,
1096 sizeof(struct pcs_conf_vals) * nconfs,
1100 func->nconfs = nconfs;
1101 conf = &(func->conf[0]);
1103 settings = devm_kzalloc(pcs->dev, sizeof(unsigned long) * nconfs,
1109 for (i = 0; i < ARRAY_SIZE(prop2); i++)
1110 pcs_add_conf2(pcs, np, prop2[i].name, prop2[i].param,
1112 for (i = 0; i < ARRAY_SIZE(prop4); i++)
1113 pcs_add_conf4(pcs, np, prop4[i].name, prop4[i].param,
1115 m->type = PIN_MAP_TYPE_CONFIGS_GROUP;
1116 m->data.configs.group_or_pin = np->name;
1117 m->data.configs.configs = settings;
1118 m->data.configs.num_configs = nconfs;
1122 static void pcs_free_pingroups(struct pcs_device *pcs);
1125 * smux_parse_one_pinctrl_entry() - parses a device tree mux entry
1126 * @pcs: pinctrl driver instance
1127 * @np: device node of the mux entry
1129 * @num_maps: number of map
1130 * @pgnames: pingroup names
1132 * Note that this binding currently supports only sets of one register + value.
1134 * Also note that this driver tries to avoid understanding pin and function
1135 * names because of the extra bloat they would cause especially in the case of
1136 * a large number of pins. This driver just sets what is specified for the board
1137 * in the .dts file. Further user space debugging tools can be developed to
1138 * decipher the pin and function names using debugfs.
1140 * If you are concerned about the boot time, set up the static pins in
1141 * the bootloader, and only set up selected pins as device tree entries.
1143 static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs,
1144 struct device_node *np,
1145 struct pinctrl_map **map,
1147 const char **pgnames)
1149 struct pcs_func_vals *vals;
1151 int size, rows, *pins, index = 0, found = 0, res = -ENOMEM;
1152 struct pcs_function *function;
1154 mux = of_get_property(np, PCS_MUX_PINS_NAME, &size);
1155 if ((!mux) || (size < sizeof(*mux) * 2)) {
1156 dev_err(pcs->dev, "bad data for mux %s\n",
1161 size /= sizeof(*mux); /* Number of elements in array */
1164 vals = devm_kzalloc(pcs->dev, sizeof(*vals) * rows, GFP_KERNEL);
1168 pins = devm_kzalloc(pcs->dev, sizeof(*pins) * rows, GFP_KERNEL);
1172 while (index < size) {
1173 unsigned offset, val;
1176 offset = be32_to_cpup(mux + index++);
1177 val = be32_to_cpup(mux + index++);
1178 vals[found].reg = pcs->base + offset;
1179 vals[found].val = val;
1181 pin = pcs_get_pin_by_offset(pcs, offset);
1184 "could not add functions for %s %ux\n",
1188 pins[found++] = pin;
1191 pgnames[0] = np->name;
1192 function = pcs_add_function(pcs, np, np->name, vals, found, pgnames, 1);
1196 res = pcs_add_pingroup(pcs, np, np->name, pins, found);
1200 (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
1201 (*map)->data.mux.group = np->name;
1202 (*map)->data.mux.function = np->name;
1204 if (PCS_HAS_PINCONF) {
1205 res = pcs_parse_pinconf(pcs, np, function, map);
1207 goto free_pingroups;
1215 pcs_free_pingroups(pcs);
1218 pcs_remove_function(pcs, function);
1221 devm_kfree(pcs->dev, pins);
1224 devm_kfree(pcs->dev, vals);
1229 #define PARAMS_FOR_BITS_PER_MUX 3
1231 static int pcs_parse_bits_in_pinctrl_entry(struct pcs_device *pcs,
1232 struct device_node *np,
1233 struct pinctrl_map **map,
1235 const char **pgnames)
1237 struct pcs_func_vals *vals;
1239 int size, rows, *pins, index = 0, found = 0, res = -ENOMEM;
1241 struct pcs_function *function;
1243 mux = of_get_property(np, PCS_MUX_BITS_NAME, &size);
1246 dev_err(pcs->dev, "no valid property for %s\n", np->name);
1250 if (size < (sizeof(*mux) * PARAMS_FOR_BITS_PER_MUX)) {
1251 dev_err(pcs->dev, "bad data for %s\n", np->name);
1255 /* Number of elements in array */
1256 size /= sizeof(*mux);
1258 rows = size / PARAMS_FOR_BITS_PER_MUX;
1259 npins_in_row = pcs->width / pcs->bits_per_pin;
1261 vals = devm_kzalloc(pcs->dev, sizeof(*vals) * rows * npins_in_row,
1266 pins = devm_kzalloc(pcs->dev, sizeof(*pins) * rows * npins_in_row,
1271 while (index < size) {
1272 unsigned offset, val;
1273 unsigned mask, bit_pos, val_pos, mask_pos, submask;
1274 unsigned pin_num_from_lsb;
1277 offset = be32_to_cpup(mux + index++);
1278 val = be32_to_cpup(mux + index++);
1279 mask = be32_to_cpup(mux + index++);
1281 /* Parse pins in each row from LSB */
1283 bit_pos = __ffs(mask);
1284 pin_num_from_lsb = bit_pos / pcs->bits_per_pin;
1285 mask_pos = ((pcs->fmask) << bit_pos);
1286 val_pos = val & mask_pos;
1287 submask = mask & mask_pos;
1289 if ((mask & mask_pos) == 0) {
1291 "Invalid mask for %s at 0x%x\n",
1298 if (submask != mask_pos) {
1300 "Invalid submask 0x%x for %s at 0x%x\n",
1301 submask, np->name, offset);
1305 vals[found].mask = submask;
1306 vals[found].reg = pcs->base + offset;
1307 vals[found].val = val_pos;
1309 pin = pcs_get_pin_by_offset(pcs, offset);
1312 "could not add functions for %s %ux\n",
1316 pins[found++] = pin + pin_num_from_lsb;
1320 pgnames[0] = np->name;
1321 function = pcs_add_function(pcs, np, np->name, vals, found, pgnames, 1);
1325 res = pcs_add_pingroup(pcs, np, np->name, pins, found);
1329 (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
1330 (*map)->data.mux.group = np->name;
1331 (*map)->data.mux.function = np->name;
1333 if (PCS_HAS_PINCONF) {
1334 dev_err(pcs->dev, "pinconf not supported\n");
1335 goto free_pingroups;
1342 pcs_free_pingroups(pcs);
1345 pcs_remove_function(pcs, function);
1348 devm_kfree(pcs->dev, pins);
1351 devm_kfree(pcs->dev, vals);
1356 * pcs_dt_node_to_map() - allocates and parses pinctrl maps
1357 * @pctldev: pinctrl instance
1358 * @np_config: device tree pinmux entry
1359 * @map: array of map entries
1360 * @num_maps: number of maps
1362 static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
1363 struct device_node *np_config,
1364 struct pinctrl_map **map, unsigned *num_maps)
1366 struct pcs_device *pcs;
1367 const char **pgnames;
1370 pcs = pinctrl_dev_get_drvdata(pctldev);
1372 /* create 2 maps. One is for pinmux, and the other is for pinconf. */
1373 *map = devm_kzalloc(pcs->dev, sizeof(**map) * 2, GFP_KERNEL);
1379 pgnames = devm_kzalloc(pcs->dev, sizeof(*pgnames), GFP_KERNEL);
1385 if (pcs->bits_per_mux) {
1386 ret = pcs_parse_bits_in_pinctrl_entry(pcs, np_config, map,
1389 dev_err(pcs->dev, "no pins entries for %s\n",
1394 ret = pcs_parse_one_pinctrl_entry(pcs, np_config, map,
1397 dev_err(pcs->dev, "no pins entries for %s\n",
1406 devm_kfree(pcs->dev, pgnames);
1408 devm_kfree(pcs->dev, *map);
1414 * pcs_free_funcs() - free memory used by functions
1415 * @pcs: pcs driver instance
1417 static void pcs_free_funcs(struct pcs_device *pcs)
1419 struct list_head *pos, *tmp;
1422 mutex_lock(&pcs->mutex);
1423 for (i = 0; i < pcs->nfuncs; i++) {
1424 struct pcs_function *func;
1426 func = radix_tree_lookup(&pcs->ftree, i);
1429 radix_tree_delete(&pcs->ftree, i);
1431 list_for_each_safe(pos, tmp, &pcs->functions) {
1432 struct pcs_function *function;
1434 function = list_entry(pos, struct pcs_function, node);
1435 list_del(&function->node);
1437 mutex_unlock(&pcs->mutex);
1441 * pcs_free_pingroups() - free memory used by pingroups
1442 * @pcs: pcs driver instance
1444 static void pcs_free_pingroups(struct pcs_device *pcs)
1446 struct list_head *pos, *tmp;
1449 mutex_lock(&pcs->mutex);
1450 for (i = 0; i < pcs->ngroups; i++) {
1451 struct pcs_pingroup *pingroup;
1453 pingroup = radix_tree_lookup(&pcs->pgtree, i);
1456 radix_tree_delete(&pcs->pgtree, i);
1458 list_for_each_safe(pos, tmp, &pcs->pingroups) {
1459 struct pcs_pingroup *pingroup;
1461 pingroup = list_entry(pos, struct pcs_pingroup, node);
1462 list_del(&pingroup->node);
1464 mutex_unlock(&pcs->mutex);
1468 * pcs_irq_free() - free interrupt
1469 * @pcs: pcs driver instance
1471 static void pcs_irq_free(struct pcs_device *pcs)
1473 struct pcs_soc_data *pcs_soc = &pcs->socdata;
1475 if (pcs_soc->irq < 0)
1479 irq_domain_remove(pcs->domain);
1481 if (PCS_QUIRK_HAS_SHARED_IRQ)
1482 free_irq(pcs_soc->irq, pcs_soc);
1484 irq_set_chained_handler(pcs_soc->irq, NULL);
1488 * pcs_free_resources() - free memory used by this driver
1489 * @pcs: pcs driver instance
1491 static void pcs_free_resources(struct pcs_device *pcs)
1494 pinctrl_unregister(pcs->pctl);
1495 pcs_free_funcs(pcs);
1496 pcs_free_pingroups(pcs);
1499 #define PCS_GET_PROP_U32(name, reg, err) \
1501 ret = of_property_read_u32(np, name, reg); \
1503 dev_err(pcs->dev, err); \
1508 static const struct of_device_id pcs_of_match[];
1510 static int pcs_add_gpio_func(struct device_node *node, struct pcs_device *pcs)
1512 const char *propname = "pinctrl-single,gpio-range";
1513 const char *cellname = "#pinctrl-single,gpio-range-cells";
1514 struct of_phandle_args gpiospec;
1515 struct pcs_gpiofunc_range *range;
1518 for (i = 0; ; i++) {
1519 ret = of_parse_phandle_with_args(node, propname, cellname,
1521 /* Do not treat it as error. Only treat it as end condition. */
1526 range = devm_kzalloc(pcs->dev, sizeof(*range), GFP_KERNEL);
1531 range->offset = gpiospec.args[0];
1532 range->npins = gpiospec.args[1];
1533 range->gpiofunc = gpiospec.args[2];
1534 mutex_lock(&pcs->mutex);
1535 list_add_tail(&range->node, &pcs->gpiofuncs);
1536 mutex_unlock(&pcs->mutex);
1541 * @reg: virtual address of interrupt register
1542 * @hwirq: hardware irq number
1543 * @irq: virtual irq number
1546 struct pcs_interrupt {
1548 irq_hw_number_t hwirq;
1550 struct list_head node;
1554 * pcs_irq_set() - enables or disables an interrupt
1556 * Note that this currently assumes one interrupt per pinctrl
1557 * register that is typically used for wake-up events.
1559 static inline void pcs_irq_set(struct pcs_soc_data *pcs_soc,
1560 int irq, const bool enable)
1562 struct pcs_device *pcs;
1563 struct list_head *pos;
1566 pcs = container_of(pcs_soc, struct pcs_device, socdata);
1567 list_for_each(pos, &pcs->irqs) {
1568 struct pcs_interrupt *pcswi;
1571 pcswi = list_entry(pos, struct pcs_interrupt, node);
1572 if (irq != pcswi->irq)
1575 soc_mask = pcs_soc->irq_enable_mask;
1576 raw_spin_lock(&pcs->lock);
1577 mask = pcs->read(pcswi->reg);
1582 pcs->write(mask, pcswi->reg);
1584 /* flush posted write */
1585 mask = pcs->read(pcswi->reg);
1586 raw_spin_unlock(&pcs->lock);
1594 * pcs_irq_mask() - mask pinctrl interrupt
1595 * @d: interrupt data
1597 static void pcs_irq_mask(struct irq_data *d)
1599 struct pcs_soc_data *pcs_soc = irq_data_get_irq_chip_data(d);
1601 pcs_irq_set(pcs_soc, d->irq, false);
1605 * pcs_irq_unmask() - unmask pinctrl interrupt
1606 * @d: interrupt data
1608 static void pcs_irq_unmask(struct irq_data *d)
1610 struct pcs_soc_data *pcs_soc = irq_data_get_irq_chip_data(d);
1612 pcs_irq_set(pcs_soc, d->irq, true);
1616 * pcs_irq_set_wake() - toggle the suspend and resume wake up
1617 * @d: interrupt data
1618 * @state: wake-up state
1620 * Note that this should be called only for suspend and resume.
1621 * For runtime PM, the wake-up events should be enabled by default.
1623 static int pcs_irq_set_wake(struct irq_data *d, unsigned int state)
1634 * pcs_irq_handle() - common interrupt handler
1635 * @pcs_irq: interrupt data
1637 * Note that this currently assumes we have one interrupt bit per
1638 * mux register. This interrupt is typically used for wake-up events.
1639 * For more complex interrupts different handlers can be specified.
1641 static int pcs_irq_handle(struct pcs_soc_data *pcs_soc)
1643 struct pcs_device *pcs;
1644 struct list_head *pos;
1647 pcs = container_of(pcs_soc, struct pcs_device, socdata);
1648 list_for_each(pos, &pcs->irqs) {
1649 struct pcs_interrupt *pcswi;
1652 pcswi = list_entry(pos, struct pcs_interrupt, node);
1653 raw_spin_lock(&pcs->lock);
1654 mask = pcs->read(pcswi->reg);
1655 raw_spin_unlock(&pcs->lock);
1656 if (mask & pcs_soc->irq_status_mask) {
1657 generic_handle_irq(irq_find_mapping(pcs->domain,
1667 * pcs_irq_handler() - handler for the shared interrupt case
1671 * Use this for cases where multiple instances of
1672 * pinctrl-single share a single interrupt like on omaps.
1674 static irqreturn_t pcs_irq_handler(int irq, void *d)
1676 struct pcs_soc_data *pcs_soc = d;
1678 return pcs_irq_handle(pcs_soc) ? IRQ_HANDLED : IRQ_NONE;
1682 * pcs_irq_handle() - handler for the dedicated chained interrupt case
1684 * @desc: interrupt descriptor
1686 * Use this if you have a separate interrupt for each
1687 * pinctrl-single instance.
1689 static void pcs_irq_chain_handler(struct irq_desc *desc)
1691 struct pcs_soc_data *pcs_soc = irq_desc_get_handler_data(desc);
1692 struct irq_chip *chip;
1694 chip = irq_desc_get_chip(desc);
1695 chained_irq_enter(chip, desc);
1696 pcs_irq_handle(pcs_soc);
1697 /* REVISIT: export and add handle_bad_irq(irq, desc)? */
1698 chained_irq_exit(chip, desc);
1703 static int pcs_irqdomain_map(struct irq_domain *d, unsigned int irq,
1704 irq_hw_number_t hwirq)
1706 struct pcs_soc_data *pcs_soc = d->host_data;
1707 struct pcs_device *pcs;
1708 struct pcs_interrupt *pcswi;
1710 pcs = container_of(pcs_soc, struct pcs_device, socdata);
1711 pcswi = devm_kzalloc(pcs->dev, sizeof(*pcswi), GFP_KERNEL);
1715 pcswi->reg = pcs->base + hwirq;
1716 pcswi->hwirq = hwirq;
1719 mutex_lock(&pcs->mutex);
1720 list_add_tail(&pcswi->node, &pcs->irqs);
1721 mutex_unlock(&pcs->mutex);
1723 irq_set_chip_data(irq, pcs_soc);
1724 irq_set_chip_and_handler(irq, &pcs->chip,
1726 irq_set_lockdep_class(irq, &pcs_lock_class);
1727 irq_set_noprobe(irq);
1732 static const struct irq_domain_ops pcs_irqdomain_ops = {
1733 .map = pcs_irqdomain_map,
1734 .xlate = irq_domain_xlate_onecell,
1738 * pcs_irq_init_chained_handler() - set up a chained interrupt handler
1739 * @pcs: pcs driver instance
1740 * @np: device node pointer
1742 static int pcs_irq_init_chained_handler(struct pcs_device *pcs,
1743 struct device_node *np)
1745 struct pcs_soc_data *pcs_soc = &pcs->socdata;
1746 const char *name = "pinctrl";
1749 if (!pcs_soc->irq_enable_mask ||
1750 !pcs_soc->irq_status_mask) {
1755 INIT_LIST_HEAD(&pcs->irqs);
1756 pcs->chip.name = name;
1757 pcs->chip.irq_ack = pcs_irq_mask;
1758 pcs->chip.irq_mask = pcs_irq_mask;
1759 pcs->chip.irq_unmask = pcs_irq_unmask;
1760 pcs->chip.irq_set_wake = pcs_irq_set_wake;
1762 if (PCS_QUIRK_HAS_SHARED_IRQ) {
1765 res = request_irq(pcs_soc->irq, pcs_irq_handler,
1766 IRQF_SHARED | IRQF_NO_SUSPEND |
1774 irq_set_chained_handler_and_data(pcs_soc->irq,
1775 pcs_irq_chain_handler,
1780 * We can use the register offset as the hardirq
1781 * number as irq_domain_add_simple maps them lazily.
1782 * This way we can easily support more than one
1783 * interrupt per function if needed.
1785 num_irqs = pcs->size;
1787 pcs->domain = irq_domain_add_simple(np, num_irqs, 0,
1791 irq_set_chained_handler(pcs_soc->irq, NULL);
1799 static int pinctrl_single_suspend(struct platform_device *pdev,
1802 struct pcs_device *pcs;
1804 pcs = platform_get_drvdata(pdev);
1808 return pinctrl_force_sleep(pcs->pctl);
1811 static int pinctrl_single_resume(struct platform_device *pdev)
1813 struct pcs_device *pcs;
1815 pcs = platform_get_drvdata(pdev);
1819 return pinctrl_force_default(pcs->pctl);
1823 static int pcs_probe(struct platform_device *pdev)
1825 struct device_node *np = pdev->dev.of_node;
1826 const struct of_device_id *match;
1827 struct pcs_pdata *pdata;
1828 struct resource *res;
1829 struct pcs_device *pcs;
1830 const struct pcs_soc_data *soc;
1833 match = of_match_device(pcs_of_match, &pdev->dev);
1837 pcs = devm_kzalloc(&pdev->dev, sizeof(*pcs), GFP_KERNEL);
1839 dev_err(&pdev->dev, "could not allocate\n");
1842 pcs->dev = &pdev->dev;
1843 raw_spin_lock_init(&pcs->lock);
1844 mutex_init(&pcs->mutex);
1845 INIT_LIST_HEAD(&pcs->pingroups);
1846 INIT_LIST_HEAD(&pcs->functions);
1847 INIT_LIST_HEAD(&pcs->gpiofuncs);
1849 pcs->flags = soc->flags;
1850 memcpy(&pcs->socdata, soc, sizeof(*soc));
1852 PCS_GET_PROP_U32("pinctrl-single,register-width", &pcs->width,
1853 "register width not specified\n");
1855 ret = of_property_read_u32(np, "pinctrl-single,function-mask",
1858 pcs->fshift = __ffs(pcs->fmask);
1859 pcs->fmax = pcs->fmask >> pcs->fshift;
1861 /* If mask property doesn't exist, function mux is invalid. */
1867 ret = of_property_read_u32(np, "pinctrl-single,function-off",
1870 pcs->foff = PCS_OFF_DISABLED;
1872 pcs->bits_per_mux = of_property_read_bool(np,
1873 "pinctrl-single,bit-per-mux");
1875 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1877 dev_err(pcs->dev, "could not get resource\n");
1881 pcs->res = devm_request_mem_region(pcs->dev, res->start,
1882 resource_size(res), DRIVER_NAME);
1884 dev_err(pcs->dev, "could not get mem_region\n");
1888 pcs->size = resource_size(pcs->res);
1889 pcs->base = devm_ioremap(pcs->dev, pcs->res->start, pcs->size);
1891 dev_err(pcs->dev, "could not ioremap\n");
1895 INIT_RADIX_TREE(&pcs->pgtree, GFP_KERNEL);
1896 INIT_RADIX_TREE(&pcs->ftree, GFP_KERNEL);
1897 platform_set_drvdata(pdev, pcs);
1899 switch (pcs->width) {
1901 pcs->read = pcs_readb;
1902 pcs->write = pcs_writeb;
1905 pcs->read = pcs_readw;
1906 pcs->write = pcs_writew;
1909 pcs->read = pcs_readl;
1910 pcs->write = pcs_writel;
1916 pcs->desc.name = DRIVER_NAME;
1917 pcs->desc.pctlops = &pcs_pinctrl_ops;
1918 pcs->desc.pmxops = &pcs_pinmux_ops;
1919 if (PCS_HAS_PINCONF)
1920 pcs->desc.confops = &pcs_pinconf_ops;
1921 pcs->desc.owner = THIS_MODULE;
1923 ret = pcs_allocate_pin_table(pcs);
1927 pcs->pctl = pinctrl_register(&pcs->desc, pcs->dev, pcs);
1928 if (IS_ERR(pcs->pctl)) {
1929 dev_err(pcs->dev, "could not register single pinctrl driver\n");
1930 ret = PTR_ERR(pcs->pctl);
1934 ret = pcs_add_gpio_func(np, pcs);
1938 pcs->socdata.irq = irq_of_parse_and_map(np, 0);
1939 if (pcs->socdata.irq)
1940 pcs->flags |= PCS_FEAT_IRQ;
1942 /* We still need auxdata for some omaps for PRM interrupts */
1943 pdata = dev_get_platdata(&pdev->dev);
1946 pcs->socdata.rearm = pdata->rearm;
1948 pcs->socdata.irq = pdata->irq;
1949 pcs->flags |= PCS_FEAT_IRQ;
1954 ret = pcs_irq_init_chained_handler(pcs, np);
1956 dev_warn(pcs->dev, "initialized with no interrupts\n");
1959 dev_info(pcs->dev, "%i pins at pa %p size %u\n",
1960 pcs->desc.npins, pcs->base, pcs->size);
1965 pcs_free_resources(pcs);
1970 static int pcs_remove(struct platform_device *pdev)
1972 struct pcs_device *pcs = platform_get_drvdata(pdev);
1977 pcs_free_resources(pcs);
1982 static const struct pcs_soc_data pinctrl_single_omap_wkup = {
1983 .flags = PCS_QUIRK_SHARED_IRQ,
1984 .irq_enable_mask = (1 << 14), /* OMAP_WAKEUP_EN */
1985 .irq_status_mask = (1 << 15), /* OMAP_WAKEUP_EVENT */
1988 static const struct pcs_soc_data pinctrl_single_dra7 = {
1989 .irq_enable_mask = (1 << 24), /* WAKEUPENABLE */
1990 .irq_status_mask = (1 << 25), /* WAKEUPEVENT */
1993 static const struct pcs_soc_data pinctrl_single_am437x = {
1994 .flags = PCS_QUIRK_SHARED_IRQ,
1995 .irq_enable_mask = (1 << 29), /* OMAP_WAKEUP_EN */
1996 .irq_status_mask = (1 << 30), /* OMAP_WAKEUP_EVENT */
1999 static const struct pcs_soc_data pinctrl_single = {
2002 static const struct pcs_soc_data pinconf_single = {
2003 .flags = PCS_FEAT_PINCONF,
2006 static const struct of_device_id pcs_of_match[] = {
2007 { .compatible = "ti,omap3-padconf", .data = &pinctrl_single_omap_wkup },
2008 { .compatible = "ti,omap4-padconf", .data = &pinctrl_single_omap_wkup },
2009 { .compatible = "ti,omap5-padconf", .data = &pinctrl_single_omap_wkup },
2010 { .compatible = "ti,dra7-padconf", .data = &pinctrl_single_dra7 },
2011 { .compatible = "ti,am437-padconf", .data = &pinctrl_single_am437x },
2012 { .compatible = "pinctrl-single", .data = &pinctrl_single },
2013 { .compatible = "pinconf-single", .data = &pinconf_single },
2016 MODULE_DEVICE_TABLE(of, pcs_of_match);
2018 static struct platform_driver pcs_driver = {
2020 .remove = pcs_remove,
2022 .name = DRIVER_NAME,
2023 .of_match_table = pcs_of_match,
2026 .suspend = pinctrl_single_suspend,
2027 .resume = pinctrl_single_resume,
2031 module_platform_driver(pcs_driver);
2033 MODULE_AUTHOR("Tony Lindgren <tony@atomide.com>");
2034 MODULE_DESCRIPTION("One-register-per-pin type device tree based pinctrl driver");
2035 MODULE_LICENSE("GPL v2");