2 * Allwinner A1X SoCs pinctrl driver.
4 * Copyright (C) 2012 Maxime Ripard
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
14 #include <linux/clk.h>
15 #include <linux/gpio.h>
16 #include <linux/irqdomain.h>
17 #include <linux/module.h>
19 #include <linux/of_address.h>
20 #include <linux/of_device.h>
21 #include <linux/of_irq.h>
22 #include <linux/pinctrl/consumer.h>
23 #include <linux/pinctrl/machine.h>
24 #include <linux/pinctrl/pinctrl.h>
25 #include <linux/pinctrl/pinconf-generic.h>
26 #include <linux/pinctrl/pinmux.h>
27 #include <linux/platform_device.h>
28 #include <linux/slab.h>
31 #include "pinctrl-sunxi.h"
32 #include "pinctrl-sunxi-pins.h"
34 static struct sunxi_pinctrl_group *
35 sunxi_pinctrl_find_group_by_name(struct sunxi_pinctrl *pctl, const char *group)
39 for (i = 0; i < pctl->ngroups; i++) {
40 struct sunxi_pinctrl_group *grp = pctl->groups + i;
42 if (!strcmp(grp->name, group))
49 static struct sunxi_pinctrl_function *
50 sunxi_pinctrl_find_function_by_name(struct sunxi_pinctrl *pctl,
53 struct sunxi_pinctrl_function *func = pctl->functions;
56 for (i = 0; i < pctl->nfunctions; i++) {
60 if (!strcmp(func[i].name, name))
67 static struct sunxi_desc_function *
68 sunxi_pinctrl_desc_find_function_by_name(struct sunxi_pinctrl *pctl,
70 const char *func_name)
74 for (i = 0; i < pctl->desc->npins; i++) {
75 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
77 if (!strcmp(pin->pin.name, pin_name)) {
78 struct sunxi_desc_function *func = pin->functions;
81 if (!strcmp(func->name, func_name))
92 static struct sunxi_desc_function *
93 sunxi_pinctrl_desc_find_function_by_pin(struct sunxi_pinctrl *pctl,
95 const char *func_name)
99 for (i = 0; i < pctl->desc->npins; i++) {
100 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
102 if (pin->pin.number == pin_num) {
103 struct sunxi_desc_function *func = pin->functions;
106 if (!strcmp(func->name, func_name))
117 static int sunxi_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
119 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
121 return pctl->ngroups;
124 static const char *sunxi_pctrl_get_group_name(struct pinctrl_dev *pctldev,
127 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
129 return pctl->groups[group].name;
132 static int sunxi_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
134 const unsigned **pins,
137 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
139 *pins = (unsigned *)&pctl->groups[group].pin;
145 static int sunxi_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
146 struct device_node *node,
147 struct pinctrl_map **map,
150 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
151 unsigned long *pinconfig;
152 struct property *prop;
153 const char *function;
155 int ret, nmaps, i = 0;
161 ret = of_property_read_string(node, "allwinner,function", &function);
164 "missing allwinner,function property in node %s\n",
169 nmaps = of_property_count_strings(node, "allwinner,pins") * 2;
172 "missing allwinner,pins property in node %s\n",
177 *map = kmalloc(nmaps * sizeof(struct pinctrl_map), GFP_KERNEL);
181 of_property_for_each_string(node, "allwinner,pins", prop, group) {
182 struct sunxi_pinctrl_group *grp =
183 sunxi_pinctrl_find_group_by_name(pctl, group);
184 int j = 0, configlen = 0;
187 dev_err(pctl->dev, "unknown pin %s", group);
191 if (!sunxi_pinctrl_desc_find_function_by_name(pctl,
194 dev_err(pctl->dev, "unsupported function %s on pin %s",
199 (*map)[i].type = PIN_MAP_TYPE_MUX_GROUP;
200 (*map)[i].data.mux.group = group;
201 (*map)[i].data.mux.function = function;
205 (*map)[i].type = PIN_MAP_TYPE_CONFIGS_GROUP;
206 (*map)[i].data.configs.group_or_pin = group;
208 if (of_find_property(node, "allwinner,drive", NULL))
210 if (of_find_property(node, "allwinner,pull", NULL))
213 pinconfig = kzalloc(configlen * sizeof(*pinconfig), GFP_KERNEL);
215 if (!of_property_read_u32(node, "allwinner,drive", &val)) {
216 u16 strength = (val + 1) * 10;
218 pinconf_to_config_packed(PIN_CONFIG_DRIVE_STRENGTH,
222 if (!of_property_read_u32(node, "allwinner,pull", &val)) {
223 enum pin_config_param pull = PIN_CONFIG_END;
225 pull = PIN_CONFIG_BIAS_PULL_UP;
227 pull = PIN_CONFIG_BIAS_PULL_DOWN;
228 pinconfig[j++] = pinconf_to_config_packed(pull, 0);
231 (*map)[i].data.configs.configs = pinconfig;
232 (*map)[i].data.configs.num_configs = configlen;
242 static void sunxi_pctrl_dt_free_map(struct pinctrl_dev *pctldev,
243 struct pinctrl_map *map,
248 for (i = 0; i < num_maps; i++) {
249 if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP)
250 kfree(map[i].data.configs.configs);
256 static const struct pinctrl_ops sunxi_pctrl_ops = {
257 .dt_node_to_map = sunxi_pctrl_dt_node_to_map,
258 .dt_free_map = sunxi_pctrl_dt_free_map,
259 .get_groups_count = sunxi_pctrl_get_groups_count,
260 .get_group_name = sunxi_pctrl_get_group_name,
261 .get_group_pins = sunxi_pctrl_get_group_pins,
264 static int sunxi_pconf_group_get(struct pinctrl_dev *pctldev,
266 unsigned long *config)
268 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
270 *config = pctl->groups[group].config;
275 static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev,
277 unsigned long *configs,
278 unsigned num_configs)
280 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
281 struct sunxi_pinctrl_group *g = &pctl->groups[group];
288 spin_lock_irqsave(&pctl->lock, flags);
290 for (i = 0; i < num_configs; i++) {
291 switch (pinconf_to_config_param(configs[i])) {
292 case PIN_CONFIG_DRIVE_STRENGTH:
293 strength = pinconf_to_config_argument(configs[i]);
295 spin_unlock_irqrestore(&pctl->lock, flags);
299 * We convert from mA to what the register expects:
305 dlevel = strength / 10 - 1;
306 val = readl(pctl->membase + sunxi_dlevel_reg(g->pin));
307 mask = DLEVEL_PINS_MASK << sunxi_dlevel_offset(g->pin);
309 | dlevel << sunxi_dlevel_offset(g->pin),
310 pctl->membase + sunxi_dlevel_reg(g->pin));
312 case PIN_CONFIG_BIAS_PULL_UP:
313 val = readl(pctl->membase + sunxi_pull_reg(g->pin));
314 mask = PULL_PINS_MASK << sunxi_pull_offset(g->pin);
315 writel((val & ~mask) | 1 << sunxi_pull_offset(g->pin),
316 pctl->membase + sunxi_pull_reg(g->pin));
318 case PIN_CONFIG_BIAS_PULL_DOWN:
319 val = readl(pctl->membase + sunxi_pull_reg(g->pin));
320 mask = PULL_PINS_MASK << sunxi_pull_offset(g->pin);
321 writel((val & ~mask) | 2 << sunxi_pull_offset(g->pin),
322 pctl->membase + sunxi_pull_reg(g->pin));
327 /* cache the config value */
328 g->config = configs[i];
329 } /* for each config */
331 spin_unlock_irqrestore(&pctl->lock, flags);
336 static const struct pinconf_ops sunxi_pconf_ops = {
337 .pin_config_group_get = sunxi_pconf_group_get,
338 .pin_config_group_set = sunxi_pconf_group_set,
341 static int sunxi_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
343 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
345 return pctl->nfunctions;
348 static const char *sunxi_pmx_get_func_name(struct pinctrl_dev *pctldev,
351 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
353 return pctl->functions[function].name;
356 static int sunxi_pmx_get_func_groups(struct pinctrl_dev *pctldev,
358 const char * const **groups,
359 unsigned * const num_groups)
361 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
363 *groups = pctl->functions[function].groups;
364 *num_groups = pctl->functions[function].ngroups;
369 static void sunxi_pmx_set(struct pinctrl_dev *pctldev,
373 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
377 spin_lock_irqsave(&pctl->lock, flags);
379 val = readl(pctl->membase + sunxi_mux_reg(pin));
380 mask = MUX_PINS_MASK << sunxi_mux_offset(pin);
381 writel((val & ~mask) | config << sunxi_mux_offset(pin),
382 pctl->membase + sunxi_mux_reg(pin));
384 spin_unlock_irqrestore(&pctl->lock, flags);
387 static int sunxi_pmx_enable(struct pinctrl_dev *pctldev,
391 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
392 struct sunxi_pinctrl_group *g = pctl->groups + group;
393 struct sunxi_pinctrl_function *func = pctl->functions + function;
394 struct sunxi_desc_function *desc =
395 sunxi_pinctrl_desc_find_function_by_name(pctl,
402 sunxi_pmx_set(pctldev, g->pin, desc->muxval);
408 sunxi_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
409 struct pinctrl_gpio_range *range,
413 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
414 struct sunxi_desc_function *desc;
422 desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, offset, func);
426 sunxi_pmx_set(pctldev, offset, desc->muxval);
431 static const struct pinmux_ops sunxi_pmx_ops = {
432 .get_functions_count = sunxi_pmx_get_funcs_cnt,
433 .get_function_name = sunxi_pmx_get_func_name,
434 .get_function_groups = sunxi_pmx_get_func_groups,
435 .enable = sunxi_pmx_enable,
436 .gpio_set_direction = sunxi_pmx_gpio_set_direction,
439 static struct pinctrl_desc sunxi_pctrl_desc = {
440 .confops = &sunxi_pconf_ops,
441 .pctlops = &sunxi_pctrl_ops,
442 .pmxops = &sunxi_pmx_ops,
445 static int sunxi_pinctrl_gpio_request(struct gpio_chip *chip, unsigned offset)
447 return pinctrl_request_gpio(chip->base + offset);
450 static void sunxi_pinctrl_gpio_free(struct gpio_chip *chip, unsigned offset)
452 pinctrl_free_gpio(chip->base + offset);
455 static int sunxi_pinctrl_gpio_direction_input(struct gpio_chip *chip,
458 return pinctrl_gpio_direction_input(chip->base + offset);
461 static int sunxi_pinctrl_gpio_get(struct gpio_chip *chip, unsigned offset)
463 struct sunxi_pinctrl *pctl = dev_get_drvdata(chip->dev);
465 u32 reg = sunxi_data_reg(offset);
466 u8 index = sunxi_data_offset(offset);
467 u32 val = (readl(pctl->membase + reg) >> index) & DATA_PINS_MASK;
472 static void sunxi_pinctrl_gpio_set(struct gpio_chip *chip,
473 unsigned offset, int value)
475 struct sunxi_pinctrl *pctl = dev_get_drvdata(chip->dev);
476 u32 reg = sunxi_data_reg(offset);
477 u8 index = sunxi_data_offset(offset);
481 spin_lock_irqsave(&pctl->lock, flags);
483 regval = readl(pctl->membase + reg);
486 regval |= BIT(index);
488 regval &= ~(BIT(index));
490 writel(regval, pctl->membase + reg);
492 spin_unlock_irqrestore(&pctl->lock, flags);
495 static int sunxi_pinctrl_gpio_direction_output(struct gpio_chip *chip,
496 unsigned offset, int value)
498 sunxi_pinctrl_gpio_set(chip, offset, value);
499 return pinctrl_gpio_direction_output(chip->base + offset);
502 static int sunxi_pinctrl_gpio_of_xlate(struct gpio_chip *gc,
503 const struct of_phandle_args *gpiospec,
508 base = PINS_PER_BANK * gpiospec->args[0];
509 pin = base + gpiospec->args[1];
511 if (pin > (gc->base + gc->ngpio))
515 *flags = gpiospec->args[2];
520 static int sunxi_pinctrl_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
522 struct sunxi_pinctrl *pctl = dev_get_drvdata(chip->dev);
523 struct sunxi_desc_function *desc;
525 if (offset >= chip->ngpio)
528 desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, offset, "irq");
532 pctl->irq_array[desc->irqnum] = offset;
534 dev_dbg(chip->dev, "%s: request IRQ for GPIO %d, return %d\n",
535 chip->label, offset + chip->base, desc->irqnum);
537 return irq_find_mapping(pctl->domain, desc->irqnum);
540 static struct gpio_chip sunxi_pinctrl_gpio_chip = {
541 .owner = THIS_MODULE,
542 .request = sunxi_pinctrl_gpio_request,
543 .free = sunxi_pinctrl_gpio_free,
544 .direction_input = sunxi_pinctrl_gpio_direction_input,
545 .direction_output = sunxi_pinctrl_gpio_direction_output,
546 .get = sunxi_pinctrl_gpio_get,
547 .set = sunxi_pinctrl_gpio_set,
548 .of_xlate = sunxi_pinctrl_gpio_of_xlate,
549 .to_irq = sunxi_pinctrl_gpio_to_irq,
550 .of_gpio_n_cells = 3,
554 static int sunxi_pinctrl_irq_set_type(struct irq_data *d,
557 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
558 u32 reg = sunxi_irq_cfg_reg(d->hwirq);
559 u8 index = sunxi_irq_cfg_offset(d->hwirq);
565 case IRQ_TYPE_EDGE_RISING:
566 mode = IRQ_EDGE_RISING;
568 case IRQ_TYPE_EDGE_FALLING:
569 mode = IRQ_EDGE_FALLING;
571 case IRQ_TYPE_EDGE_BOTH:
572 mode = IRQ_EDGE_BOTH;
574 case IRQ_TYPE_LEVEL_HIGH:
575 mode = IRQ_LEVEL_HIGH;
577 case IRQ_TYPE_LEVEL_LOW:
578 mode = IRQ_LEVEL_LOW;
584 spin_lock_irqsave(&pctl->lock, flags);
586 regval = readl(pctl->membase + reg);
587 regval &= ~IRQ_CFG_IRQ_MASK;
588 writel(regval | (mode << index), pctl->membase + reg);
590 spin_unlock_irqrestore(&pctl->lock, flags);
595 static void sunxi_pinctrl_irq_mask_ack(struct irq_data *d)
597 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
598 u32 ctrl_reg = sunxi_irq_ctrl_reg(d->hwirq);
599 u8 ctrl_idx = sunxi_irq_ctrl_offset(d->hwirq);
600 u32 status_reg = sunxi_irq_status_reg(d->hwirq);
601 u8 status_idx = sunxi_irq_status_offset(d->hwirq);
605 spin_lock_irqsave(&pctl->lock, flags);
608 val = readl(pctl->membase + ctrl_reg);
609 writel(val & ~(1 << ctrl_idx), pctl->membase + ctrl_reg);
612 writel(1 << status_idx, pctl->membase + status_reg);
614 spin_unlock_irqrestore(&pctl->lock, flags);
617 static void sunxi_pinctrl_irq_mask(struct irq_data *d)
619 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
620 u32 reg = sunxi_irq_ctrl_reg(d->hwirq);
621 u8 idx = sunxi_irq_ctrl_offset(d->hwirq);
625 spin_lock_irqsave(&pctl->lock, flags);
628 val = readl(pctl->membase + reg);
629 writel(val & ~(1 << idx), pctl->membase + reg);
631 spin_unlock_irqrestore(&pctl->lock, flags);
634 static void sunxi_pinctrl_irq_unmask(struct irq_data *d)
636 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
637 struct sunxi_desc_function *func;
638 u32 reg = sunxi_irq_ctrl_reg(d->hwirq);
639 u8 idx = sunxi_irq_ctrl_offset(d->hwirq);
643 func = sunxi_pinctrl_desc_find_function_by_pin(pctl,
644 pctl->irq_array[d->hwirq],
647 /* Change muxing to INT mode */
648 sunxi_pmx_set(pctl->pctl_dev, pctl->irq_array[d->hwirq], func->muxval);
650 spin_lock_irqsave(&pctl->lock, flags);
653 val = readl(pctl->membase + reg);
654 writel(val | (1 << idx), pctl->membase + reg);
656 spin_unlock_irqrestore(&pctl->lock, flags);
659 static struct irq_chip sunxi_pinctrl_irq_chip = {
660 .irq_mask = sunxi_pinctrl_irq_mask,
661 .irq_mask_ack = sunxi_pinctrl_irq_mask_ack,
662 .irq_unmask = sunxi_pinctrl_irq_unmask,
663 .irq_set_type = sunxi_pinctrl_irq_set_type,
666 static void sunxi_pinctrl_irq_handler(unsigned irq, struct irq_desc *desc)
668 struct sunxi_pinctrl *pctl = irq_get_handler_data(irq);
669 const unsigned long reg = readl(pctl->membase + IRQ_STATUS_REG);
671 /* Clear all interrupts */
672 writel(reg, pctl->membase + IRQ_STATUS_REG);
677 for_each_set_bit(irqoffset, ®, SUNXI_IRQ_NUMBER) {
678 int pin_irq = irq_find_mapping(pctl->domain, irqoffset);
679 generic_handle_irq(pin_irq);
684 static struct of_device_id sunxi_pinctrl_match[] = {
685 { .compatible = "allwinner,sun4i-a10-pinctrl", .data = (void *)&sun4i_a10_pinctrl_data },
686 { .compatible = "allwinner,sun5i-a10s-pinctrl", .data = (void *)&sun5i_a10s_pinctrl_data },
687 { .compatible = "allwinner,sun5i-a13-pinctrl", .data = (void *)&sun5i_a13_pinctrl_data },
688 { .compatible = "allwinner,sun6i-a31-pinctrl", .data = (void *)&sun6i_a31_pinctrl_data },
689 { .compatible = "allwinner,sun7i-a20-pinctrl", .data = (void *)&sun7i_a20_pinctrl_data },
692 MODULE_DEVICE_TABLE(of, sunxi_pinctrl_match);
694 static int sunxi_pinctrl_add_function(struct sunxi_pinctrl *pctl,
697 struct sunxi_pinctrl_function *func = pctl->functions;
700 /* function already there */
701 if (strcmp(func->name, name) == 0) {
716 static int sunxi_pinctrl_build_state(struct platform_device *pdev)
718 struct sunxi_pinctrl *pctl = platform_get_drvdata(pdev);
721 pctl->ngroups = pctl->desc->npins;
723 /* Allocate groups */
724 pctl->groups = devm_kzalloc(&pdev->dev,
725 pctl->ngroups * sizeof(*pctl->groups),
730 for (i = 0; i < pctl->desc->npins; i++) {
731 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
732 struct sunxi_pinctrl_group *group = pctl->groups + i;
734 group->name = pin->pin.name;
735 group->pin = pin->pin.number;
739 * We suppose that we won't have any more functions than pins,
740 * we'll reallocate that later anyway
742 pctl->functions = devm_kzalloc(&pdev->dev,
743 pctl->desc->npins * sizeof(*pctl->functions),
745 if (!pctl->functions)
748 /* Count functions and their associated groups */
749 for (i = 0; i < pctl->desc->npins; i++) {
750 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
751 struct sunxi_desc_function *func = pin->functions;
754 sunxi_pinctrl_add_function(pctl, func->name);
759 pctl->functions = krealloc(pctl->functions,
760 pctl->nfunctions * sizeof(*pctl->functions),
763 for (i = 0; i < pctl->desc->npins; i++) {
764 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
765 struct sunxi_desc_function *func = pin->functions;
768 struct sunxi_pinctrl_function *func_item;
769 const char **func_grp;
771 func_item = sunxi_pinctrl_find_function_by_name(pctl,
776 if (!func_item->groups) {
778 devm_kzalloc(&pdev->dev,
779 func_item->ngroups * sizeof(*func_item->groups),
781 if (!func_item->groups)
785 func_grp = func_item->groups;
789 *func_grp = pin->pin.name;
797 static int sunxi_pinctrl_probe(struct platform_device *pdev)
799 struct device_node *node = pdev->dev.of_node;
800 const struct of_device_id *device;
801 struct pinctrl_pin_desc *pins;
802 struct sunxi_pinctrl *pctl;
803 int i, ret, last_pin;
806 pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
809 platform_set_drvdata(pdev, pctl);
811 spin_lock_init(&pctl->lock);
813 pctl->membase = of_iomap(node, 0);
817 device = of_match_device(sunxi_pinctrl_match, &pdev->dev);
821 pctl->desc = (struct sunxi_pinctrl_desc *)device->data;
823 ret = sunxi_pinctrl_build_state(pdev);
825 dev_err(&pdev->dev, "dt probe failed: %d\n", ret);
829 pins = devm_kzalloc(&pdev->dev,
830 pctl->desc->npins * sizeof(*pins),
835 for (i = 0; i < pctl->desc->npins; i++)
836 pins[i] = pctl->desc->pins[i].pin;
838 sunxi_pctrl_desc.name = dev_name(&pdev->dev);
839 sunxi_pctrl_desc.owner = THIS_MODULE;
840 sunxi_pctrl_desc.pins = pins;
841 sunxi_pctrl_desc.npins = pctl->desc->npins;
842 pctl->dev = &pdev->dev;
843 pctl->pctl_dev = pinctrl_register(&sunxi_pctrl_desc,
845 if (!pctl->pctl_dev) {
846 dev_err(&pdev->dev, "couldn't register pinctrl driver\n");
850 pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL);
856 last_pin = pctl->desc->pins[pctl->desc->npins - 1].pin.number;
857 pctl->chip = &sunxi_pinctrl_gpio_chip;
858 pctl->chip->ngpio = round_up(last_pin, PINS_PER_BANK);
859 pctl->chip->label = dev_name(&pdev->dev);
860 pctl->chip->dev = &pdev->dev;
861 pctl->chip->base = 0;
863 ret = gpiochip_add(pctl->chip);
867 for (i = 0; i < pctl->desc->npins; i++) {
868 const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
870 ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev),
877 clk = devm_clk_get(&pdev->dev, NULL);
883 clk_prepare_enable(clk);
885 pctl->irq = irq_of_parse_and_map(node, 0);
891 pctl->domain = irq_domain_add_linear(node, SUNXI_IRQ_NUMBER,
892 &irq_domain_simple_ops, NULL);
894 dev_err(&pdev->dev, "Couldn't register IRQ domain\n");
899 for (i = 0; i < SUNXI_IRQ_NUMBER; i++) {
900 int irqno = irq_create_mapping(pctl->domain, i);
902 irq_set_chip_and_handler(irqno, &sunxi_pinctrl_irq_chip,
904 irq_set_chip_data(irqno, pctl);
907 irq_set_chained_handler(pctl->irq, sunxi_pinctrl_irq_handler);
908 irq_set_handler_data(pctl->irq, pctl);
910 dev_info(&pdev->dev, "initialized sunXi PIO driver\n");
915 if (gpiochip_remove(pctl->chip))
916 dev_err(&pdev->dev, "failed to remove gpio chip\n");
918 pinctrl_unregister(pctl->pctl_dev);
922 static struct platform_driver sunxi_pinctrl_driver = {
923 .probe = sunxi_pinctrl_probe,
925 .name = "sunxi-pinctrl",
926 .owner = THIS_MODULE,
927 .of_match_table = sunxi_pinctrl_match,
930 module_platform_driver(sunxi_pinctrl_driver);
932 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com");
933 MODULE_DESCRIPTION("Allwinner A1X pinctrl driver");
934 MODULE_LICENSE("GPL");