2 * R8A7790 processor support
4 * Copyright (C) 2013 Renesas Electronics Corporation
5 * Copyright (C) 2013 Magnus Damm
6 * Copyright (C) 2012 Renesas Solutions Corp.
7 * Copyright (C) 2012 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; version 2 of the
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
24 #include <linux/kernel.h>
25 #include <linux/platform_data/gpio-rcar.h>
30 #define CPU_ALL_PORT(fn, sfx) \
31 PORT_GP_32(0, fn, sfx), \
32 PORT_GP_32(1, fn, sfx), \
33 PORT_GP_32(2, fn, sfx), \
34 PORT_GP_32(3, fn, sfx), \
35 PORT_GP_32(4, fn, sfx), \
36 PORT_GP_32(5, fn, sfx)
45 PINMUX_FUNCTION_BEGIN,
49 FN_IP0_2_0, FN_IP0_5_3, FN_IP0_8_6, FN_IP0_11_9, FN_IP0_15_12,
50 FN_IP0_19_16, FN_IP0_22_20, FN_IP0_26_23, FN_IP0_30_27,
51 FN_IP1_3_0, FN_IP1_7_4, FN_IP1_11_8, FN_IP1_14_12,
52 FN_IP1_17_15, FN_IP1_21_18, FN_IP1_25_22, FN_IP1_27_26,
53 FN_IP1_29_28, FN_IP2_2_0, FN_IP2_5_3, FN_IP2_8_6, FN_IP2_11_9,
54 FN_IP2_14_12, FN_IP2_17_15, FN_IP2_21_18, FN_IP2_25_22,
55 FN_IP2_28_26, FN_IP3_3_0, FN_IP3_7_4, FN_IP3_11_8,
56 FN_IP3_14_12, FN_IP3_17_15,
59 FN_IP3_19_18, FN_IP3_22_20, FN_IP3_25_23, FN_IP3_28_26,
60 FN_IP3_31_29, FN_IP4_2_0, FN_IP4_5_3, FN_IP4_8_6, FN_IP4_11_9,
61 FN_IP4_14_12, FN_IP4_17_15, FN_IP4_20_18, FN_IP4_23_21,
62 FN_IP4_26_24, FN_IP4_29_27, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_9_6,
63 FN_IP5_12_10, FN_IP5_14_13, FN_IP5_17_15, FN_IP5_20_18,
64 FN_IP5_23_21, FN_IP5_26_24, FN_IP5_29_27, FN_IP6_2_0,
65 FN_IP6_5_3, FN_IP6_8_6, FN_IP6_10_9, FN_IP6_13_11,
68 FN_IP7_28_27, FN_IP7_30_29, FN_IP8_1_0, FN_IP8_3_2, FN_IP8_5_4,
69 FN_IP8_7_6, FN_IP8_9_8, FN_IP8_11_10, FN_IP8_13_12, FN_IP8_15_14,
70 FN_IP8_17_16, FN_IP8_19_18, FN_IP8_21_20, FN_IP8_23_22,
71 FN_IP8_25_24, FN_IP8_26, FN_IP8_27, FN_VI1_DATA7_VI1_B7,
72 FN_IP6_16_14, FN_IP6_19_17, FN_IP6_22_20, FN_IP6_25_23,
73 FN_IP6_28_26, FN_IP6_31_29, FN_IP7_2_0, FN_IP7_5_3, FN_IP7_7_6,
74 FN_IP7_9_8, FN_IP7_12_10, FN_IP7_15_13,
77 FN_IP8_28, FN_IP8_30_29, FN_IP9_1_0, FN_IP9_3_2, FN_IP9_5_4,
78 FN_IP9_7_6, FN_IP9_11_8, FN_IP9_15_12, FN_IP9_17_16, FN_IP9_19_18,
79 FN_IP9_21_20, FN_IP9_23_22, FN_IP9_25_24, FN_IP9_27_26,
80 FN_IP9_31_28, FN_IP10_3_0, FN_IP10_6_4, FN_IP10_10_7, FN_IP10_14_11,
81 FN_IP10_18_15, FN_IP10_22_19, FN_IP10_25_23, FN_IP10_29_26,
82 FN_IP11_3_0, FN_IP11_4, FN_IP11_6_5, FN_IP11_8_7, FN_IP11_10_9,
83 FN_IP11_12_11, FN_IP11_14_13, FN_IP11_17_15, FN_IP11_21_18,
86 FN_IP11_23_22, FN_IP11_26_24, FN_IP11_29_27, FN_IP11_31_30,
87 FN_IP12_1_0, FN_IP12_3_2, FN_IP12_5_4, FN_IP12_7_6, FN_IP12_10_8,
88 FN_IP12_13_11, FN_IP12_16_14, FN_IP12_19_17, FN_IP12_22_20,
89 FN_IP12_24_23, FN_IP12_27_25, FN_IP12_30_28, FN_IP13_2_0,
90 FN_IP13_6_3, FN_IP13_9_7, FN_IP13_12_10, FN_IP13_15_13,
91 FN_IP13_18_16, FN_IP13_22_19, FN_IP13_25_23, FN_IP13_28_26,
92 FN_IP13_30_29, FN_IP14_2_0, FN_IP14_5_3, FN_IP14_8_6, FN_IP14_11_9,
93 FN_IP14_15_12, FN_IP14_18_16,
96 FN_IP14_21_19, FN_IP14_24_22, FN_IP14_27_25, FN_IP14_30_28,
97 FN_IP15_2_0, FN_IP15_5_3, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_13_12,
98 FN_IP15_15_14, FN_IP15_17_16, FN_IP15_19_18, FN_IP15_22_20,
99 FN_IP15_25_23, FN_IP15_27_26, FN_IP15_29_28, FN_IP16_2_0,
100 FN_IP16_5_3, FN_USB0_PWEN, FN_USB0_OVC_VBUS, FN_IP16_6, FN_IP16_7,
101 FN_USB2_PWEN, FN_USB2_OVC, FN_AVS1, FN_AVS2, FN_DU_DOTCLKIN0,
102 FN_IP7_26_25, FN_DU_DOTCLKIN2, FN_IP7_18_16, FN_IP7_21_19, FN_IP7_24_22,
105 FN_D0, FN_MSIOF3_SCK_B, FN_VI3_DATA0, FN_VI0_G4, FN_VI0_G4_B,
106 FN_D1, FN_MSIOF3_SYNC_B, FN_VI3_DATA1, FN_VI0_G5,
107 FN_VI0_G5_B, FN_D2, FN_MSIOF3_RXD_B, FN_VI3_DATA2,
108 FN_VI0_G6, FN_VI0_G6_B, FN_D3, FN_MSIOF3_TXD_B,
109 FN_VI3_DATA3, FN_VI0_G7, FN_VI0_G7_B, FN_D4,
110 FN_SCIFB1_RXD_F, FN_SCIFB0_RXD_C, FN_VI3_DATA4,
111 FN_VI0_R0, FN_VI0_R0_B, FN_RX0_B, FN_D5,
112 FN_SCIFB1_TXD_F, FN_SCIFB0_TXD_C, FN_VI3_DATA5,
113 FN_VI0_R1, FN_VI0_R1_B, FN_TX0_B, FN_D6,
114 FN_IIC2_SCL_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B,
115 FN_I2C2_SCL_C, FN_D7, FN_AD_DI_B, FN_IIC2_SDA_C,
116 FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_I2C2_SDA_C, FN_TCLK1,
117 FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0,
118 FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0,
121 FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1,
122 FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1, FN_D10,
123 FN_SCIFA1_TXD_C, FN_AVB_TXD2,
124 FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2, FN_D11,
125 FN_SCIFA1_CTS_N_C, FN_AVB_TXD3,
126 FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3,
127 FN_D12, FN_SCIFA1_RTS_N_C, FN_AVB_TXD4,
128 FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4,
129 FN_D13, FN_AVB_TXD5, FN_VI0_VSYNC_N,
130 FN_VI0_VSYNC_N_B, FN_VI2_DATA5_VI2_B5, FN_D14,
131 FN_SCIFB1_RXD_C, FN_AVB_TXD6, FN_RX1_B,
132 FN_VI0_CLKENB, FN_VI0_CLKENB_B, FN_VI2_DATA6_VI2_B6,
133 FN_D15, FN_SCIFB1_TXD_C, FN_AVB_TXD7, FN_TX1_B,
134 FN_VI0_FIELD, FN_VI0_FIELD_B, FN_VI2_DATA7_VI2_B7,
135 FN_A0, FN_PWM3, FN_A1, FN_PWM4,
138 FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, FN_A3,
139 FN_PWM6, FN_MSIOF1_SS2_B, FN_A4, FN_MSIOF1_TXD_B,
140 FN_TPU0TO0, FN_A5, FN_SCIFA1_TXD_B, FN_TPU0TO1,
141 FN_A6, FN_SCIFA1_RTS_N_B, FN_TPU0TO2, FN_A7,
142 FN_SCIFA1_SCK_B, FN_AUDIO_CLKOUT_B, FN_TPU0TO3,
143 FN_A8, FN_SCIFA1_RXD_B, FN_SSI_SCK5_B, FN_VI0_R4,
144 FN_VI0_R4_B, FN_SCIFB2_RXD_C, FN_RX2_B, FN_VI2_DATA0_VI2_B0_B,
145 FN_A9, FN_SCIFA1_CTS_N_B, FN_SSI_WS5_B, FN_VI0_R5,
146 FN_VI0_R5_B, FN_SCIFB2_TXD_C, FN_TX2_B, FN_VI2_DATA1_VI2_B1_B,
147 FN_A10, FN_SSI_SDATA5_B, FN_MSIOF2_SYNC, FN_VI0_R6,
148 FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B,
151 FN_A11, FN_SCIFB2_CTS_N_B, FN_MSIOF2_SCK, FN_VI1_R0,
152 FN_VI1_R0_B, FN_VI2_G0, FN_VI2_DATA3_VI2_B3_B,
153 FN_A12, FN_SCIFB2_RXD_B, FN_MSIOF2_TXD, FN_VI1_R1,
154 FN_VI1_R1_B, FN_VI2_G1, FN_VI2_DATA4_VI2_B4_B,
155 FN_A13, FN_SCIFB2_RTS_N_B, FN_EX_WAIT2,
156 FN_MSIOF2_RXD, FN_VI1_R2, FN_VI1_R2_B, FN_VI2_G2,
157 FN_VI2_DATA5_VI2_B5_B, FN_A14, FN_SCIFB2_TXD_B,
158 FN_ATACS11_N, FN_MSIOF2_SS1, FN_A15, FN_SCIFB2_SCK_B,
159 FN_ATARD1_N, FN_MSIOF2_SS2, FN_A16, FN_ATAWR1_N,
160 FN_A17, FN_AD_DO_B, FN_ATADIR1_N, FN_A18,
161 FN_AD_CLK_B, FN_ATAG1_N, FN_A19, FN_AD_NCS_N_B,
162 FN_ATACS01_N, FN_EX_WAIT0_B, FN_A20, FN_SPCLK,
163 FN_VI1_R3, FN_VI1_R3_B, FN_VI2_G4,
166 FN_A21, FN_MOSI_IO0, FN_VI1_R4, FN_VI1_R4_B, FN_VI2_G5,
167 FN_A22, FN_MISO_IO1, FN_VI1_R5, FN_VI1_R5_B,
168 FN_VI2_G6, FN_A23, FN_IO2, FN_VI1_G7,
169 FN_VI1_G7_B, FN_VI2_G7, FN_A24, FN_IO3,
170 FN_VI1_R7, FN_VI1_R7_B, FN_VI2_CLKENB,
171 FN_VI2_CLKENB_B, FN_A25, FN_SSL, FN_VI1_G6,
172 FN_VI1_G6_B, FN_VI2_FIELD, FN_VI2_FIELD_B, FN_CS0_N,
173 FN_VI1_R6, FN_VI1_R6_B, FN_VI2_G3, FN_MSIOF0_SS2_B,
174 FN_CS1_N_A26, FN_SPEEDIN, FN_VI0_R7, FN_VI0_R7_B,
175 FN_VI2_CLK, FN_VI2_CLK_B, FN_EX_CS0_N, FN_HRX1_B,
176 FN_VI1_G5, FN_VI1_G5_B, FN_VI2_R0, FN_HTX0_B,
177 FN_MSIOF0_SS1_B, FN_EX_CS1_N, FN_GPS_CLK,
178 FN_HCTS1_N_B, FN_VI1_FIELD, FN_VI1_FIELD_B,
179 FN_VI2_R1, FN_EX_CS2_N, FN_GPS_SIGN, FN_HRTS1_N_B,
180 FN_VI3_CLKENB, FN_VI1_G0, FN_VI1_G0_B, FN_VI2_R2,
183 FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B,
184 FN_VI2_R3, FN_EX_CS4_N, FN_MSIOF1_SCK_B, FN_VI3_HSYNC_N,
185 FN_VI2_HSYNC_N, FN_IIC1_SCL, FN_VI2_HSYNC_N_B,
186 FN_INTC_EN0_N, FN_I2C1_SCL, FN_EX_CS5_N, FN_CAN0_RX,
187 FN_MSIOF1_RXD_B, FN_VI3_VSYNC_N, FN_VI1_G2,
188 FN_VI1_G2_B, FN_VI2_R4, FN_IIC1_SDA, FN_INTC_EN1_N,
189 FN_I2C1_SDA, FN_BS_N, FN_IETX, FN_HTX1_B,
190 FN_CAN1_TX, FN_DRACK0, FN_IETX_C, FN_RD_N,
191 FN_CAN0_TX, FN_SCIFA0_SCK_B, FN_RD_WR_N, FN_VI1_G3,
192 FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B,
193 FN_INTC_IRQ4_N, FN_WE0_N, FN_IECLK, FN_CAN_CLK,
194 FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B,
195 FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4,
196 FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B,
197 FN_IERX_C, FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N,
198 FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B,
199 FN_MSIOF0_SCK_B, FN_DREQ0_N, FN_VI1_HSYNC_N,
200 FN_VI1_HSYNC_N_B, FN_VI2_R7, FN_SSI_SCK78_C,
204 FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B,
205 FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C,
206 FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B,
207 FN_SSI_SDATA7_C, FN_SSI_SCK78_B, FN_DACK1, FN_IRQ1,
208 FN_INTC_IRQ1_N, FN_SSI_WS6_B, FN_SSI_SDATA8_C,
209 FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B,
210 FN_MSIOF0_TXD_B, FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N,
211 FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B,
212 FN_ETH_CRS_DV, FN_STP_ISCLK_0_B,
213 FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E,
214 FN_I2C2_SCL_E, FN_ETH_RX_ER,
215 FN_STP_ISD_0_B, FN_TS_SPSYNC0_D, FN_GLO_Q1_C,
216 FN_IIC2_SDA_E, FN_I2C2_SDA_E, FN_ETH_RXD0,
217 FN_STP_ISEN_0_B, FN_TS_SDAT0_D, FN_GLO_I0_C,
218 FN_SCIFB1_SCK_G, FN_SCK1_E, FN_ETH_RXD1,
219 FN_HRX0_E, FN_STP_ISSYNC_0_B,
220 FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G,
221 FN_RX1_E, FN_ETH_LINK, FN_HTX0_E,
222 FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E,
223 FN_ETH_REF_CLK, FN_HCTS0_N_E,
224 FN_STP_IVCXO27_1_B, FN_HRX0_F,
227 FN_ETH_MDIO, FN_HRTS0_N_E,
228 FN_SIM0_D_C, FN_HCTS0_N_F, FN_ETH_TXD1,
229 FN_HTX0_F, FN_BPFCLK_G,
230 FN_ETH_TX_EN, FN_SIM0_CLK_C,
231 FN_HRTS0_N_F, FN_ETH_MAGIC,
232 FN_SIM0_RST_C, FN_ETH_TXD0,
233 FN_STP_ISCLK_1_B, FN_TS_SDEN1_C, FN_GLO_SCLK_C,
234 FN_ETH_MDC, FN_STP_ISD_1_B,
235 FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, FN_PWM0,
236 FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C,
237 FN_GLO_SS_C, FN_PWM1, FN_SCIFA2_TXD_C,
238 FN_STP_ISSYNC_1_B, FN_TS_SCK1_C, FN_GLO_RFON_C,
239 FN_PCMOE_N, FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C,
240 FN_PCMWE_N, FN_IECLK_C, FN_DU_DOTCLKIN1,
241 FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, FN_VI0_CLK,
242 FN_ATACS00_N, FN_AVB_RXD1,
243 FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2,
246 FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3,
247 FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N,
248 FN_AVB_RXD4, FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N,
249 FN_AVB_RXD5, FN_VI0_DATA4_VI0_B4, FN_ATAG0_N,
250 FN_AVB_RXD6, FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1,
251 FN_AVB_RXD7, FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER,
252 FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK,
253 FN_VI1_CLK, FN_AVB_RX_DV,
254 FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D,
255 FN_AVB_CRS, FN_VI1_DATA1_VI1_B1,
256 FN_SCIFA1_RXD_D, FN_AVB_MDC,
257 FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO,
258 FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D,
259 FN_AVB_GTX_CLK, FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D,
260 FN_AVB_MAGIC, FN_VI1_DATA5_VI1_B5,
261 FN_AVB_PHY_INT, FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK,
262 FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B, FN_SD0_CMD,
263 FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B,
266 FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B,
267 FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B,
268 FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B,
269 FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B,
270 FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP,
271 FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_IIC1_SCL_B,
272 FN_I2C1_SCL_B, FN_VI2_DATA6_VI2_B6_B, FN_SD0_WP,
273 FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN,
274 FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_IIC1_SDA_B,
275 FN_I2C1_SDA_B, FN_VI2_DATA7_VI2_B7_B, FN_SD1_CLK,
276 FN_AVB_TX_EN, FN_SD1_CMD,
277 FN_AVB_TX_ER, FN_SCIFB0_SCK_B,
278 FN_SD1_DAT0, FN_AVB_TX_CLK,
279 FN_SCIFB0_RXD_B, FN_SD1_DAT1, FN_AVB_LINK,
280 FN_SCIFB0_TXD_B, FN_SD1_DAT2,
281 FN_AVB_COL, FN_SCIFB0_CTS_N_B,
282 FN_SD1_DAT3, FN_AVB_RXD0,
283 FN_SCIFB0_RTS_N_B, FN_SD1_CD, FN_MMC1_D6,
284 FN_TS_SDEN1, FN_USB1_EXTP, FN_GLO_SS, FN_VI0_CLK_B,
285 FN_IIC2_SCL_D, FN_I2C2_SCL_D, FN_SIM0_CLK_B,
289 FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN,
290 FN_GLO_RFON, FN_VI1_CLK_B, FN_IIC2_SDA_D, FN_I2C2_SDA_D,
291 FN_SIM0_D_B, FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK,
292 FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B,
293 FN_VI3_DATA0_B, FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D,
294 FN_VI0_DATA1_VI0_B1_B, FN_SCIFB1_SCK_E, FN_SCK1_D,
295 FN_TS_SPSYNC0_C, FN_GLO_SDATA_B, FN_VI3_DATA1_B,
296 FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B,
297 FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D,
298 FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B,
299 FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B,
300 FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D,
301 FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B,
302 FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B,
303 FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B,
304 FN_GLO_Q0_B, FN_VI3_DATA4_B, FN_SD2_DAT3,
305 FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B,
306 FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B,
307 FN_VI3_DATA5_B, FN_SD2_CD, FN_MMC0_D4,
308 FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0,
309 FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B,
310 FN_GLO_I0_B, FN_VI3_DATA6_B,
313 FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN,
314 FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D,
315 FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B,
316 FN_SD3_CLK, FN_MMC1_CLK, FN_SD3_CMD, FN_MMC1_CMD,
317 FN_MTS_N, FN_SD3_DAT0, FN_MMC1_D0, FN_STM_N,
318 FN_SD3_DAT1, FN_MMC1_D1, FN_MDATA, FN_SD3_DAT2,
319 FN_MMC1_D2, FN_SDATA, FN_SD3_DAT3, FN_MMC1_D3,
320 FN_SCKZ, FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1,
321 FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, FN_SD3_WP,
322 FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C,
323 FN_FMIN_E, FN_FMIN_F,
324 FN_MLB_CLK, FN_IIC2_SCL_B, FN_I2C2_SCL_B,
325 FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_IIC2_SDA_B,
326 FN_I2C2_SDA_B, FN_MLB_DAT,
327 FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C,
328 FN_SSI_SCK0129, FN_CAN_CLK_B,
332 FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1,
333 FN_SSI_SDATA0, FN_CAN0_RX_B, FN_MOUT2,
334 FN_SSI_SDATA1, FN_CAN1_TX_B, FN_MOUT5,
335 FN_SSI_SDATA2, FN_CAN1_RX_B, FN_SSI_SCK1, FN_MOUT6,
336 FN_SSI_SCK34, FN_STP_OPWM_0, FN_SCIFB0_SCK,
337 FN_MSIOF1_SCK, FN_CAN_DEBUG_HW_TRIGGER, FN_SSI_WS34,
338 FN_STP_IVCXO27_0, FN_SCIFB0_RXD, FN_MSIOF1_SYNC,
339 FN_CAN_STEP0, FN_SSI_SDATA3, FN_STP_ISCLK_0,
340 FN_SCIFB0_TXD, FN_MSIOF1_SS1, FN_CAN_TXCLK,
341 FN_SSI_SCK4, FN_STP_ISD_0, FN_SCIFB0_CTS_N,
342 FN_MSIOF1_SS2, FN_SSI_SCK5_C, FN_CAN_DEBUGOUT0,
343 FN_SSI_WS4, FN_STP_ISEN_0, FN_SCIFB0_RTS_N,
344 FN_MSIOF1_TXD, FN_SSI_WS5_C, FN_CAN_DEBUGOUT1,
345 FN_SSI_SDATA4, FN_STP_ISSYNC_0, FN_MSIOF1_RXD,
346 FN_CAN_DEBUGOUT2, FN_SSI_SCK5, FN_SCIFB1_SCK,
347 FN_IERX_B, FN_DU2_EXHSYNC_DU2_HSYNC, FN_QSTH_QHS,
348 FN_CAN_DEBUGOUT3, FN_SSI_WS5, FN_SCIFB1_RXD,
349 FN_IECLK_B, FN_DU2_EXVSYNC_DU2_VSYNC, FN_QSTB_QHE,
353 FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2,
354 FN_LCDOUT2, FN_CAN_DEBUGOUT5, FN_SSI_SCK6,
355 FN_SCIFB1_CTS_N, FN_BPFCLK_D,
356 FN_DU2_DR3, FN_LCDOUT3, FN_CAN_DEBUGOUT6,
357 FN_BPFCLK_F, FN_SSI_WS6,
358 FN_SCIFB1_RTS_N, FN_CAN0_TX_D, FN_DU2_DR4,
359 FN_LCDOUT4, FN_CAN_DEBUGOUT7, FN_SSI_SDATA6,
360 FN_FMIN_D, FN_DU2_DR5, FN_LCDOUT5,
361 FN_CAN_DEBUGOUT8, FN_SSI_SCK78, FN_STP_IVCXO27_1,
362 FN_SCK1, FN_SCIFA1_SCK, FN_DU2_DR6, FN_LCDOUT6,
363 FN_CAN_DEBUGOUT9, FN_SSI_WS78, FN_STP_ISCLK_1,
364 FN_SCIFB2_SCK, FN_SCIFA2_CTS_N, FN_DU2_DR7,
365 FN_LCDOUT7, FN_CAN_DEBUGOUT10, FN_SSI_SDATA7,
366 FN_STP_ISD_1, FN_SCIFB2_RXD, FN_SCIFA2_RTS_N,
367 FN_TCLK2, FN_QSTVA_QVS, FN_CAN_DEBUGOUT11,
368 FN_BPFCLK_E, FN_SSI_SDATA7_B,
369 FN_FMIN_G, FN_SSI_SDATA8,
370 FN_STP_ISEN_1, FN_SCIFB2_TXD, FN_CAN0_TX_C,
371 FN_CAN_DEBUGOUT12, FN_SSI_SDATA8_B, FN_SSI_SDATA9,
372 FN_STP_ISSYNC_1, FN_SCIFB2_CTS_N, FN_SSI_WS1,
373 FN_SSI_SDATA5_C, FN_CAN_DEBUGOUT13, FN_AUDIO_CLKA,
374 FN_SCIFB2_RTS_N, FN_CAN_DEBUGOUT14,
377 FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D,
378 FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15,
379 FN_REMOCON, FN_SCIFA0_SCK, FN_HSCK1, FN_SCK0,
380 FN_MSIOF3_SS2, FN_DU2_DG2, FN_LCDOUT10, FN_IIC1_SDA_C,
381 FN_I2C1_SDA_C, FN_SCIFA0_RXD, FN_HRX1, FN_RX0,
382 FN_DU2_DR0, FN_LCDOUT0, FN_SCIFA0_TXD, FN_HTX1,
383 FN_TX0, FN_DU2_DR1, FN_LCDOUT1, FN_SCIFA0_CTS_N,
384 FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC, FN_DU2_DG3,
385 FN_LCDOUT11, FN_PWM0_B, FN_IIC1_SCL_C, FN_I2C1_SCL_C,
386 FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N,
387 FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B,
388 FN_SCIFA1_RXD, FN_AD_DI, FN_RX1,
389 FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, FN_QCPV_QDE,
390 FN_SCIFA1_TXD, FN_AD_DO, FN_TX1, FN_DU2_DG1,
391 FN_LCDOUT9, FN_SCIFA1_CTS_N, FN_AD_CLK,
392 FN_CTS1_N, FN_MSIOF3_RXD, FN_DU0_DOTCLKOUT, FN_QCLK,
393 FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N,
394 FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE,
398 FN_SCIFA2_SCK, FN_FMCLK, FN_SCK2, FN_MSIOF3_SCK, FN_DU2_DG7,
399 FN_LCDOUT15, FN_SCIF_CLK_B, FN_SCIFA2_RXD, FN_FMIN,
400 FN_TX2, FN_DU2_DB0, FN_LCDOUT16, FN_IIC2_SCL, FN_I2C2_SCL,
401 FN_SCIFA2_TXD, FN_BPFCLK, FN_RX2, FN_DU2_DB1, FN_LCDOUT17,
402 FN_IIC2_SDA, FN_I2C2_SDA, FN_HSCK0, FN_TS_SDEN0,
403 FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C, FN_HRX0,
404 FN_DU2_DB2, FN_LCDOUT18, FN_HTX0, FN_DU2_DB3,
405 FN_LCDOUT19, FN_HCTS0_N, FN_SSI_SCK9, FN_DU2_DB4,
406 FN_LCDOUT20, FN_HRTS0_N, FN_SSI_WS9, FN_DU2_DB5,
407 FN_LCDOUT21, FN_MSIOF0_SCK, FN_TS_SDAT0, FN_ADICLK,
408 FN_DU2_DB6, FN_LCDOUT22, FN_MSIOF0_SYNC, FN_TS_SCK0,
409 FN_SSI_SCK2, FN_ADIDATA, FN_DU2_DB7, FN_LCDOUT23,
410 FN_HRX0_C, FN_MSIOF0_SS1, FN_ADICHS0,
411 FN_DU2_DG5, FN_LCDOUT13, FN_MSIOF0_TXD, FN_ADICHS1,
412 FN_DU2_DG6, FN_LCDOUT14,
415 FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2,
416 FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B,
417 FN_MSIOF0_RXD, FN_TS_SPSYNC0, FN_SSI_WS2,
418 FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_SCIFA2_RXD_B,
419 FN_USB1_PWEN, FN_AUDIO_CLKOUT_D, FN_USB1_OVC,
422 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
424 FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2,
425 FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2,
426 FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
428 FN_SEL_SCIFB1_5, FN_SEL_SCIFB1_6,
429 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, FN_SEL_SCIFA1_3,
430 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1,
431 FN_SEL_SCFA_0, FN_SEL_SCFA_1,
432 FN_SEL_SOF1_0, FN_SEL_SOF1_1,
433 FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2,
434 FN_SEL_SSI6_0, FN_SEL_SSI6_1,
435 FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2,
436 FN_SEL_VI3_0, FN_SEL_VI3_1,
437 FN_SEL_VI2_0, FN_SEL_VI2_1,
438 FN_SEL_VI1_0, FN_SEL_VI1_1,
439 FN_SEL_VI0_0, FN_SEL_VI0_1,
440 FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2,
441 FN_SEL_LBS_0, FN_SEL_LBS_1,
442 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
443 FN_SEL_SOF3_0, FN_SEL_SOF3_1,
444 FN_SEL_SOF0_0, FN_SEL_SOF0_1,
446 FN_SEL_TMU1_0, FN_SEL_TMU1_1,
447 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
448 FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1,
449 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
450 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
451 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2,
452 FN_SEL_CAN1_0, FN_SEL_CAN1_1,
453 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1,
454 FN_SEL_ADI_0, FN_SEL_ADI_1,
455 FN_SEL_SSP_0, FN_SEL_SSP_1,
456 FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3,
457 FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6,
458 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, FN_SEL_HSCIF0_3,
459 FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5,
460 FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2,
461 FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2,
462 FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2,
464 FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1,
465 FN_SEL_IIC0_0, FN_SEL_IIC0_1,
466 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
467 FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
469 FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2,
470 FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
472 FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2,
477 VI1_DATA7_VI1_B7_MARK,
479 USB0_PWEN_MARK, USB0_OVC_VBUS_MARK,
480 USB2_PWEN_MARK, USB2_OVC_MARK, AVS1_MARK, AVS2_MARK,
481 DU_DOTCLKIN0_MARK, DU_DOTCLKIN2_MARK,
483 D0_MARK, MSIOF3_SCK_B_MARK, VI3_DATA0_MARK, VI0_G4_MARK, VI0_G4_B_MARK,
484 D1_MARK, MSIOF3_SYNC_B_MARK, VI3_DATA1_MARK, VI0_G5_MARK,
485 VI0_G5_B_MARK, D2_MARK, MSIOF3_RXD_B_MARK, VI3_DATA2_MARK,
486 VI0_G6_MARK, VI0_G6_B_MARK, D3_MARK, MSIOF3_TXD_B_MARK,
487 VI3_DATA3_MARK, VI0_G7_MARK, VI0_G7_B_MARK, D4_MARK,
488 SCIFB1_RXD_F_MARK, SCIFB0_RXD_C_MARK, VI3_DATA4_MARK,
489 VI0_R0_MARK, VI0_R0_B_MARK, RX0_B_MARK, D5_MARK,
490 SCIFB1_TXD_F_MARK, SCIFB0_TXD_C_MARK, VI3_DATA5_MARK,
491 VI0_R1_MARK, VI0_R1_B_MARK, TX0_B_MARK, D6_MARK,
492 IIC2_SCL_C_MARK, VI3_DATA6_MARK, VI0_R2_MARK, VI0_R2_B_MARK,
493 I2C2_SCL_C_MARK, D7_MARK, AD_DI_B_MARK, IIC2_SDA_C_MARK,
494 VI3_DATA7_MARK, VI0_R3_MARK, VI0_R3_B_MARK, I2C2_SDA_C_MARK, TCLK1_MARK,
495 D8_MARK, SCIFA1_SCK_C_MARK, AVB_TXD0_MARK,
496 VI0_G0_MARK, VI0_G0_B_MARK, VI2_DATA0_VI2_B0_MARK,
498 D9_MARK, SCIFA1_RXD_C_MARK, AVB_TXD1_MARK,
499 VI0_G1_MARK, VI0_G1_B_MARK, VI2_DATA1_VI2_B1_MARK, D10_MARK,
500 SCIFA1_TXD_C_MARK, AVB_TXD2_MARK,
501 VI0_G2_MARK, VI0_G2_B_MARK, VI2_DATA2_VI2_B2_MARK, D11_MARK,
502 SCIFA1_CTS_N_C_MARK, AVB_TXD3_MARK,
503 VI0_G3_MARK, VI0_G3_B_MARK, VI2_DATA3_VI2_B3_MARK,
504 D12_MARK, SCIFA1_RTS_N_C_MARK, AVB_TXD4_MARK,
505 VI0_HSYNC_N_MARK, VI0_HSYNC_N_B_MARK, VI2_DATA4_VI2_B4_MARK,
506 D13_MARK, AVB_TXD5_MARK, VI0_VSYNC_N_MARK,
507 VI0_VSYNC_N_B_MARK, VI2_DATA5_VI2_B5_MARK, D14_MARK,
508 SCIFB1_RXD_C_MARK, AVB_TXD6_MARK, RX1_B_MARK,
509 VI0_CLKENB_MARK, VI0_CLKENB_B_MARK, VI2_DATA6_VI2_B6_MARK,
510 D15_MARK, SCIFB1_TXD_C_MARK, AVB_TXD7_MARK, TX1_B_MARK,
511 VI0_FIELD_MARK, VI0_FIELD_B_MARK, VI2_DATA7_VI2_B7_MARK,
512 A0_MARK, PWM3_MARK, A1_MARK, PWM4_MARK,
514 A2_MARK, PWM5_MARK, MSIOF1_SS1_B_MARK, A3_MARK,
515 PWM6_MARK, MSIOF1_SS2_B_MARK, A4_MARK, MSIOF1_TXD_B_MARK,
516 TPU0TO0_MARK, A5_MARK, SCIFA1_TXD_B_MARK, TPU0TO1_MARK,
517 A6_MARK, SCIFA1_RTS_N_B_MARK, TPU0TO2_MARK, A7_MARK,
518 SCIFA1_SCK_B_MARK, AUDIO_CLKOUT_B_MARK, TPU0TO3_MARK,
519 A8_MARK, SCIFA1_RXD_B_MARK, SSI_SCK5_B_MARK, VI0_R4_MARK,
520 VI0_R4_B_MARK, SCIFB2_RXD_C_MARK, RX2_B_MARK, VI2_DATA0_VI2_B0_B_MARK,
521 A9_MARK, SCIFA1_CTS_N_B_MARK, SSI_WS5_B_MARK, VI0_R5_MARK,
522 VI0_R5_B_MARK, SCIFB2_TXD_C_MARK, TX2_B_MARK, VI2_DATA1_VI2_B1_B_MARK,
523 A10_MARK, SSI_SDATA5_B_MARK, MSIOF2_SYNC_MARK, VI0_R6_MARK,
524 VI0_R6_B_MARK, VI2_DATA2_VI2_B2_B_MARK,
526 A11_MARK, SCIFB2_CTS_N_B_MARK, MSIOF2_SCK_MARK, VI1_R0_MARK,
527 VI1_R0_B_MARK, VI2_G0_MARK, VI2_DATA3_VI2_B3_B_MARK,
528 A12_MARK, SCIFB2_RXD_B_MARK, MSIOF2_TXD_MARK, VI1_R1_MARK,
529 VI1_R1_B_MARK, VI2_G1_MARK, VI2_DATA4_VI2_B4_B_MARK,
530 A13_MARK, SCIFB2_RTS_N_B_MARK, EX_WAIT2_MARK,
531 MSIOF2_RXD_MARK, VI1_R2_MARK, VI1_R2_B_MARK, VI2_G2_MARK,
532 VI2_DATA5_VI2_B5_B_MARK, A14_MARK, SCIFB2_TXD_B_MARK,
533 ATACS11_N_MARK, MSIOF2_SS1_MARK, A15_MARK, SCIFB2_SCK_B_MARK,
534 ATARD1_N_MARK, MSIOF2_SS2_MARK, A16_MARK, ATAWR1_N_MARK,
535 A17_MARK, AD_DO_B_MARK, ATADIR1_N_MARK, A18_MARK,
536 AD_CLK_B_MARK, ATAG1_N_MARK, A19_MARK, AD_NCS_N_B_MARK,
537 ATACS01_N_MARK, EX_WAIT0_B_MARK, A20_MARK, SPCLK_MARK,
538 VI1_R3_MARK, VI1_R3_B_MARK, VI2_G4_MARK,
540 A21_MARK, MOSI_IO0_MARK, VI1_R4_MARK, VI1_R4_B_MARK, VI2_G5_MARK,
541 A22_MARK, MISO_IO1_MARK, VI1_R5_MARK, VI1_R5_B_MARK,
542 VI2_G6_MARK, A23_MARK, IO2_MARK, VI1_G7_MARK,
543 VI1_G7_B_MARK, VI2_G7_MARK, A24_MARK, IO3_MARK,
544 VI1_R7_MARK, VI1_R7_B_MARK, VI2_CLKENB_MARK,
545 VI2_CLKENB_B_MARK, A25_MARK, SSL_MARK, VI1_G6_MARK,
546 VI1_G6_B_MARK, VI2_FIELD_MARK, VI2_FIELD_B_MARK, CS0_N_MARK,
547 VI1_R6_MARK, VI1_R6_B_MARK, VI2_G3_MARK, MSIOF0_SS2_B_MARK,
548 CS1_N_A26_MARK, SPEEDIN_MARK, VI0_R7_MARK, VI0_R7_B_MARK,
549 VI2_CLK_MARK, VI2_CLK_B_MARK, EX_CS0_N_MARK, HRX1_B_MARK,
550 VI1_G5_MARK, VI1_G5_B_MARK, VI2_R0_MARK, HTX0_B_MARK,
551 MSIOF0_SS1_B_MARK, EX_CS1_N_MARK, GPS_CLK_MARK,
552 HCTS1_N_B_MARK, VI1_FIELD_MARK, VI1_FIELD_B_MARK,
553 VI2_R1_MARK, EX_CS2_N_MARK, GPS_SIGN_MARK, HRTS1_N_B_MARK,
554 VI3_CLKENB_MARK, VI1_G0_MARK, VI1_G0_B_MARK, VI2_R2_MARK,
556 EX_CS3_N_MARK, GPS_MAG_MARK, VI3_FIELD_MARK,
557 VI1_G1_MARK, VI1_G1_B_MARK, VI2_R3_MARK,
558 EX_CS4_N_MARK, MSIOF1_SCK_B_MARK, VI3_HSYNC_N_MARK,
559 VI2_HSYNC_N_MARK, IIC1_SCL_MARK, VI2_HSYNC_N_B_MARK,
560 INTC_EN0_N_MARK, I2C1_SCL_MARK, EX_CS5_N_MARK, CAN0_RX_MARK,
561 MSIOF1_RXD_B_MARK, VI3_VSYNC_N_MARK, VI1_G2_MARK,
562 VI1_G2_B_MARK, VI2_R4_MARK, IIC1_SDA_MARK, INTC_EN1_N_MARK,
563 I2C1_SDA_MARK, BS_N_MARK, IETX_MARK, HTX1_B_MARK,
564 CAN1_TX_MARK, DRACK0_MARK, IETX_C_MARK, RD_N_MARK,
565 CAN0_TX_MARK, SCIFA0_SCK_B_MARK, RD_WR_N_MARK, VI1_G3_MARK,
566 VI1_G3_B_MARK, VI2_R5_MARK, SCIFA0_RXD_B_MARK,
567 INTC_IRQ4_N_MARK, WE0_N_MARK, IECLK_MARK, CAN_CLK_MARK,
568 VI2_VSYNC_N_MARK, SCIFA0_TXD_B_MARK, VI2_VSYNC_N_B_MARK,
569 WE1_N_MARK, IERX_MARK, CAN1_RX_MARK, VI1_G4_MARK,
570 VI1_G4_B_MARK, VI2_R6_MARK, SCIFA0_CTS_N_B_MARK,
571 IERX_C_MARK, EX_WAIT0_MARK, IRQ3_MARK, INTC_IRQ3_N_MARK,
572 VI3_CLK_MARK, SCIFA0_RTS_N_B_MARK, HRX0_B_MARK,
573 MSIOF0_SCK_B_MARK, DREQ0_N_MARK, VI1_HSYNC_N_MARK,
574 VI1_HSYNC_N_B_MARK, VI2_R7_MARK, SSI_SCK78_C_MARK,
577 DACK0_MARK, IRQ0_MARK, INTC_IRQ0_N_MARK, SSI_SCK6_B_MARK,
578 VI1_VSYNC_N_MARK, VI1_VSYNC_N_B_MARK, SSI_WS78_C_MARK,
579 DREQ1_N_MARK, VI1_CLKENB_MARK, VI1_CLKENB_B_MARK,
580 SSI_SDATA7_C_MARK, SSI_SCK78_B_MARK, DACK1_MARK, IRQ1_MARK,
581 INTC_IRQ1_N_MARK, SSI_WS6_B_MARK, SSI_SDATA8_C_MARK,
582 DREQ2_N_MARK, HSCK1_B_MARK, HCTS0_N_B_MARK,
583 MSIOF0_TXD_B_MARK, DACK2_MARK, IRQ2_MARK, INTC_IRQ2_N_MARK,
584 SSI_SDATA6_B_MARK, HRTS0_N_B_MARK, MSIOF0_RXD_B_MARK,
585 ETH_CRS_DV_MARK, STP_ISCLK_0_B_MARK,
586 TS_SDEN0_D_MARK, GLO_Q0_C_MARK, IIC2_SCL_E_MARK,
587 I2C2_SCL_E_MARK, ETH_RX_ER_MARK,
588 STP_ISD_0_B_MARK, TS_SPSYNC0_D_MARK, GLO_Q1_C_MARK,
589 IIC2_SDA_E_MARK, I2C2_SDA_E_MARK, ETH_RXD0_MARK,
590 STP_ISEN_0_B_MARK, TS_SDAT0_D_MARK, GLO_I0_C_MARK,
591 SCIFB1_SCK_G_MARK, SCK1_E_MARK, ETH_RXD1_MARK,
592 HRX0_E_MARK, STP_ISSYNC_0_B_MARK,
593 TS_SCK0_D_MARK, GLO_I1_C_MARK, SCIFB1_RXD_G_MARK,
594 RX1_E_MARK, ETH_LINK_MARK, HTX0_E_MARK,
595 STP_IVCXO27_0_B_MARK, SCIFB1_TXD_G_MARK, TX1_E_MARK,
596 ETH_REF_CLK_MARK, HCTS0_N_E_MARK,
597 STP_IVCXO27_1_B_MARK, HRX0_F_MARK,
599 ETH_MDIO_MARK, HRTS0_N_E_MARK,
600 SIM0_D_C_MARK, HCTS0_N_F_MARK, ETH_TXD1_MARK,
601 HTX0_F_MARK, BPFCLK_G_MARK,
602 ETH_TX_EN_MARK, SIM0_CLK_C_MARK,
603 HRTS0_N_F_MARK, ETH_MAGIC_MARK,
604 SIM0_RST_C_MARK, ETH_TXD0_MARK,
605 STP_ISCLK_1_B_MARK, TS_SDEN1_C_MARK, GLO_SCLK_C_MARK,
606 ETH_MDC_MARK, STP_ISD_1_B_MARK,
607 TS_SPSYNC1_C_MARK, GLO_SDATA_C_MARK, PWM0_MARK,
608 SCIFA2_SCK_C_MARK, STP_ISEN_1_B_MARK, TS_SDAT1_C_MARK,
609 GLO_SS_C_MARK, PWM1_MARK, SCIFA2_TXD_C_MARK,
610 STP_ISSYNC_1_B_MARK, TS_SCK1_C_MARK, GLO_RFON_C_MARK,
611 PCMOE_N_MARK, PWM2_MARK, PWMFSW0_MARK, SCIFA2_RXD_C_MARK,
612 PCMWE_N_MARK, IECLK_C_MARK, DU_DOTCLKIN1_MARK,
613 AUDIO_CLKC_MARK, AUDIO_CLKOUT_C_MARK, VI0_CLK_MARK,
614 ATACS00_N_MARK, AVB_RXD1_MARK,
615 VI0_DATA0_VI0_B0_MARK, ATACS10_N_MARK, AVB_RXD2_MARK,
617 VI0_DATA1_VI0_B1_MARK, ATARD0_N_MARK, AVB_RXD3_MARK,
618 VI0_DATA2_VI0_B2_MARK, ATAWR0_N_MARK,
619 AVB_RXD4_MARK, VI0_DATA3_VI0_B3_MARK, ATADIR0_N_MARK,
620 AVB_RXD5_MARK, VI0_DATA4_VI0_B4_MARK, ATAG0_N_MARK,
621 AVB_RXD6_MARK, VI0_DATA5_VI0_B5_MARK, EX_WAIT1_MARK,
622 AVB_RXD7_MARK, VI0_DATA6_VI0_B6_MARK, AVB_RX_ER_MARK,
623 VI0_DATA7_VI0_B7_MARK, AVB_RX_CLK_MARK,
624 VI1_CLK_MARK, AVB_RX_DV_MARK,
625 VI1_DATA0_VI1_B0_MARK, SCIFA1_SCK_D_MARK,
626 AVB_CRS_MARK, VI1_DATA1_VI1_B1_MARK,
627 SCIFA1_RXD_D_MARK, AVB_MDC_MARK,
628 VI1_DATA2_VI1_B2_MARK, SCIFA1_TXD_D_MARK, AVB_MDIO_MARK,
629 VI1_DATA3_VI1_B3_MARK, SCIFA1_CTS_N_D_MARK,
630 AVB_GTX_CLK_MARK, VI1_DATA4_VI1_B4_MARK, SCIFA1_RTS_N_D_MARK,
631 AVB_MAGIC_MARK, VI1_DATA5_VI1_B5_MARK,
632 AVB_PHY_INT_MARK, VI1_DATA6_VI1_B6_MARK, AVB_GTXREFCLK_MARK,
633 SD0_CLK_MARK, VI1_DATA0_VI1_B0_B_MARK, SD0_CMD_MARK,
634 SCIFB1_SCK_B_MARK, VI1_DATA1_VI1_B1_B_MARK,
636 SD0_DAT0_MARK, SCIFB1_RXD_B_MARK, VI1_DATA2_VI1_B2_B_MARK,
637 SD0_DAT1_MARK, SCIFB1_TXD_B_MARK, VI1_DATA3_VI1_B3_B_MARK,
638 SD0_DAT2_MARK, SCIFB1_CTS_N_B_MARK, VI1_DATA4_VI1_B4_B_MARK,
639 SD0_DAT3_MARK, SCIFB1_RTS_N_B_MARK, VI1_DATA5_VI1_B5_B_MARK,
640 SD0_CD_MARK, MMC0_D6_MARK, TS_SDEN0_B_MARK, USB0_EXTP_MARK,
641 GLO_SCLK_MARK, VI1_DATA6_VI1_B6_B_MARK, IIC1_SCL_B_MARK,
642 I2C1_SCL_B_MARK, VI2_DATA6_VI2_B6_B_MARK, SD0_WP_MARK,
643 MMC0_D7_MARK, TS_SPSYNC0_B_MARK, USB0_IDIN_MARK,
644 GLO_SDATA_MARK, VI1_DATA7_VI1_B7_B_MARK, IIC1_SDA_B_MARK,
645 I2C1_SDA_B_MARK, VI2_DATA7_VI2_B7_B_MARK, SD1_CLK_MARK,
646 AVB_TX_EN_MARK, SD1_CMD_MARK,
647 AVB_TX_ER_MARK, SCIFB0_SCK_B_MARK,
648 SD1_DAT0_MARK, AVB_TX_CLK_MARK,
649 SCIFB0_RXD_B_MARK, SD1_DAT1_MARK, AVB_LINK_MARK,
650 SCIFB0_TXD_B_MARK, SD1_DAT2_MARK,
651 AVB_COL_MARK, SCIFB0_CTS_N_B_MARK,
652 SD1_DAT3_MARK, AVB_RXD0_MARK,
653 SCIFB0_RTS_N_B_MARK, SD1_CD_MARK, MMC1_D6_MARK,
654 TS_SDEN1_MARK, USB1_EXTP_MARK, GLO_SS_MARK, VI0_CLK_B_MARK,
655 IIC2_SCL_D_MARK, I2C2_SCL_D_MARK, SIM0_CLK_B_MARK,
658 SD1_WP_MARK, MMC1_D7_MARK, TS_SPSYNC1_MARK, USB1_IDIN_MARK,
659 GLO_RFON_MARK, VI1_CLK_B_MARK, IIC2_SDA_D_MARK, I2C2_SDA_D_MARK,
660 SIM0_D_B_MARK, SD2_CLK_MARK, MMC0_CLK_MARK, SIM0_CLK_MARK,
661 VI0_DATA0_VI0_B0_B_MARK, TS_SDEN0_C_MARK, GLO_SCLK_B_MARK,
662 VI3_DATA0_B_MARK, SD2_CMD_MARK, MMC0_CMD_MARK, SIM0_D_MARK,
663 VI0_DATA1_VI0_B1_B_MARK, SCIFB1_SCK_E_MARK, SCK1_D_MARK,
664 TS_SPSYNC0_C_MARK, GLO_SDATA_B_MARK, VI3_DATA1_B_MARK,
665 SD2_DAT0_MARK, MMC0_D0_MARK, FMCLK_B_MARK,
666 VI0_DATA2_VI0_B2_B_MARK, SCIFB1_RXD_E_MARK, RX1_D_MARK,
667 TS_SDAT0_C_MARK, GLO_SS_B_MARK, VI3_DATA2_B_MARK,
668 SD2_DAT1_MARK, MMC0_D1_MARK, FMIN_B_MARK,
669 VI0_DATA3_VI0_B3_B_MARK, SCIFB1_TXD_E_MARK, TX1_D_MARK,
670 TS_SCK0_C_MARK, GLO_RFON_B_MARK, VI3_DATA3_B_MARK,
671 SD2_DAT2_MARK, MMC0_D2_MARK, BPFCLK_B_MARK,
672 VI0_DATA4_VI0_B4_B_MARK, HRX0_D_MARK, TS_SDEN1_B_MARK,
673 GLO_Q0_B_MARK, VI3_DATA4_B_MARK, SD2_DAT3_MARK,
674 MMC0_D3_MARK, SIM0_RST_MARK, VI0_DATA5_VI0_B5_B_MARK,
675 HTX0_D_MARK, TS_SPSYNC1_B_MARK, GLO_Q1_B_MARK,
676 VI3_DATA5_B_MARK, SD2_CD_MARK, MMC0_D4_MARK,
677 TS_SDAT0_B_MARK, USB2_EXTP_MARK, GLO_I0_MARK,
678 VI0_DATA6_VI0_B6_B_MARK, HCTS0_N_D_MARK, TS_SDAT1_B_MARK,
679 GLO_I0_B_MARK, VI3_DATA6_B_MARK,
681 SD2_WP_MARK, MMC0_D5_MARK, TS_SCK0_B_MARK, USB2_IDIN_MARK,
682 GLO_I1_MARK, VI0_DATA7_VI0_B7_B_MARK, HRTS0_N_D_MARK,
683 TS_SCK1_B_MARK, GLO_I1_B_MARK, VI3_DATA7_B_MARK,
684 SD3_CLK_MARK, MMC1_CLK_MARK, SD3_CMD_MARK, MMC1_CMD_MARK,
685 MTS_N_MARK, SD3_DAT0_MARK, MMC1_D0_MARK, STM_N_MARK,
686 SD3_DAT1_MARK, MMC1_D1_MARK, MDATA_MARK, SD3_DAT2_MARK,
687 MMC1_D2_MARK, SDATA_MARK, SD3_DAT3_MARK, MMC1_D3_MARK,
688 SCKZ_MARK, SD3_CD_MARK, MMC1_D4_MARK, TS_SDAT1_MARK,
689 VSP_MARK, GLO_Q0_MARK, SIM0_RST_B_MARK, SD3_WP_MARK,
690 MMC1_D5_MARK, TS_SCK1_MARK, GLO_Q1_MARK, FMIN_C_MARK,
691 FMIN_E_MARK, FMIN_F_MARK,
692 MLB_CLK_MARK, IIC2_SCL_B_MARK, I2C2_SCL_B_MARK,
693 MLB_SIG_MARK, SCIFB1_RXD_D_MARK, RX1_C_MARK, IIC2_SDA_B_MARK,
694 I2C2_SDA_B_MARK, MLB_DAT_MARK,
695 SCIFB1_TXD_D_MARK, TX1_C_MARK, BPFCLK_C_MARK,
696 SSI_SCK0129_MARK, CAN_CLK_B_MARK,
699 SSI_WS0129_MARK, CAN0_TX_B_MARK, MOUT1_MARK,
700 SSI_SDATA0_MARK, CAN0_RX_B_MARK, MOUT2_MARK,
701 SSI_SDATA1_MARK, CAN1_TX_B_MARK, MOUT5_MARK,
702 SSI_SDATA2_MARK, CAN1_RX_B_MARK, SSI_SCK1_MARK, MOUT6_MARK,
703 SSI_SCK34_MARK, STP_OPWM_0_MARK, SCIFB0_SCK_MARK,
704 MSIOF1_SCK_MARK, CAN_DEBUG_HW_TRIGGER_MARK, SSI_WS34_MARK,
705 STP_IVCXO27_0_MARK, SCIFB0_RXD_MARK, MSIOF1_SYNC_MARK,
706 CAN_STEP0_MARK, SSI_SDATA3_MARK, STP_ISCLK_0_MARK,
707 SCIFB0_TXD_MARK, MSIOF1_SS1_MARK, CAN_TXCLK_MARK,
708 SSI_SCK4_MARK, STP_ISD_0_MARK, SCIFB0_CTS_N_MARK,
709 MSIOF1_SS2_MARK, SSI_SCK5_C_MARK, CAN_DEBUGOUT0_MARK,
710 SSI_WS4_MARK, STP_ISEN_0_MARK, SCIFB0_RTS_N_MARK,
711 MSIOF1_TXD_MARK, SSI_WS5_C_MARK, CAN_DEBUGOUT1_MARK,
712 SSI_SDATA4_MARK, STP_ISSYNC_0_MARK, MSIOF1_RXD_MARK,
713 CAN_DEBUGOUT2_MARK, SSI_SCK5_MARK, SCIFB1_SCK_MARK,
714 IERX_B_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK, QSTH_QHS_MARK,
715 CAN_DEBUGOUT3_MARK, SSI_WS5_MARK, SCIFB1_RXD_MARK,
716 IECLK_B_MARK, DU2_EXVSYNC_DU2_VSYNC_MARK, QSTB_QHE_MARK,
719 SSI_SDATA5_MARK, SCIFB1_TXD_MARK, IETX_B_MARK, DU2_DR2_MARK,
720 LCDOUT2_MARK, CAN_DEBUGOUT5_MARK, SSI_SCK6_MARK,
721 SCIFB1_CTS_N_MARK, BPFCLK_D_MARK,
722 DU2_DR3_MARK, LCDOUT3_MARK, CAN_DEBUGOUT6_MARK,
723 BPFCLK_F_MARK, SSI_WS6_MARK,
724 SCIFB1_RTS_N_MARK, CAN0_TX_D_MARK, DU2_DR4_MARK,
725 LCDOUT4_MARK, CAN_DEBUGOUT7_MARK, SSI_SDATA6_MARK,
726 FMIN_D_MARK, DU2_DR5_MARK, LCDOUT5_MARK,
727 CAN_DEBUGOUT8_MARK, SSI_SCK78_MARK, STP_IVCXO27_1_MARK,
728 SCK1_MARK, SCIFA1_SCK_MARK, DU2_DR6_MARK, LCDOUT6_MARK,
729 CAN_DEBUGOUT9_MARK, SSI_WS78_MARK, STP_ISCLK_1_MARK,
730 SCIFB2_SCK_MARK, SCIFA2_CTS_N_MARK, DU2_DR7_MARK,
731 LCDOUT7_MARK, CAN_DEBUGOUT10_MARK, SSI_SDATA7_MARK,
732 STP_ISD_1_MARK, SCIFB2_RXD_MARK, SCIFA2_RTS_N_MARK,
733 TCLK2_MARK, QSTVA_QVS_MARK, CAN_DEBUGOUT11_MARK,
734 BPFCLK_E_MARK, SSI_SDATA7_B_MARK,
735 FMIN_G_MARK, SSI_SDATA8_MARK,
736 STP_ISEN_1_MARK, SCIFB2_TXD_MARK, CAN0_TX_C_MARK,
737 CAN_DEBUGOUT12_MARK, SSI_SDATA8_B_MARK, SSI_SDATA9_MARK,
738 STP_ISSYNC_1_MARK, SCIFB2_CTS_N_MARK, SSI_WS1_MARK,
739 SSI_SDATA5_C_MARK, CAN_DEBUGOUT13_MARK, AUDIO_CLKA_MARK,
740 SCIFB2_RTS_N_MARK, CAN_DEBUGOUT14_MARK,
742 AUDIO_CLKB_MARK, SCIF_CLK_MARK, CAN0_RX_D_MARK,
743 DVC_MUTE_MARK, CAN0_RX_C_MARK, CAN_DEBUGOUT15_MARK,
744 REMOCON_MARK, SCIFA0_SCK_MARK, HSCK1_MARK, SCK0_MARK,
745 MSIOF3_SS2_MARK, DU2_DG2_MARK, LCDOUT10_MARK, IIC1_SDA_C_MARK,
746 I2C1_SDA_C_MARK, SCIFA0_RXD_MARK, HRX1_MARK, RX0_MARK,
747 DU2_DR0_MARK, LCDOUT0_MARK, SCIFA0_TXD_MARK, HTX1_MARK,
748 TX0_MARK, DU2_DR1_MARK, LCDOUT1_MARK, SCIFA0_CTS_N_MARK,
749 HCTS1_N_MARK, CTS0_N_MARK, MSIOF3_SYNC_MARK, DU2_DG3_MARK,
750 LCDOUT11_MARK, PWM0_B_MARK, IIC1_SCL_C_MARK, I2C1_SCL_C_MARK,
751 SCIFA0_RTS_N_MARK, HRTS1_N_MARK, RTS0_N_MARK,
752 MSIOF3_SS1_MARK, DU2_DG0_MARK, LCDOUT8_MARK, PWM1_B_MARK,
753 SCIFA1_RXD_MARK, AD_DI_MARK, RX1_MARK,
754 DU2_EXODDF_DU2_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK,
755 SCIFA1_TXD_MARK, AD_DO_MARK, TX1_MARK, DU2_DG1_MARK,
756 LCDOUT9_MARK, SCIFA1_CTS_N_MARK, AD_CLK_MARK,
757 CTS1_N_MARK, MSIOF3_RXD_MARK, DU0_DOTCLKOUT_MARK, QCLK_MARK,
758 SCIFA1_RTS_N_MARK, AD_NCS_N_MARK, RTS1_N_MARK,
759 MSIOF3_TXD_MARK, DU1_DOTCLKOUT_MARK, QSTVB_QVE_MARK,
762 SCIFA2_SCK_MARK, FMCLK_MARK, SCK2_MARK, MSIOF3_SCK_MARK, DU2_DG7_MARK,
763 LCDOUT15_MARK, SCIF_CLK_B_MARK, SCIFA2_RXD_MARK, FMIN_MARK,
764 TX2_MARK, DU2_DB0_MARK, LCDOUT16_MARK, IIC2_SCL_MARK, I2C2_SCL_MARK,
765 SCIFA2_TXD_MARK, BPFCLK_MARK, RX2_MARK, DU2_DB1_MARK, LCDOUT17_MARK,
766 IIC2_SDA_MARK, I2C2_SDA_MARK, HSCK0_MARK, TS_SDEN0_MARK,
767 DU2_DG4_MARK, LCDOUT12_MARK, HCTS0_N_C_MARK, HRX0_MARK,
768 DU2_DB2_MARK, LCDOUT18_MARK, HTX0_MARK, DU2_DB3_MARK,
769 LCDOUT19_MARK, HCTS0_N_MARK, SSI_SCK9_MARK, DU2_DB4_MARK,
770 LCDOUT20_MARK, HRTS0_N_MARK, SSI_WS9_MARK, DU2_DB5_MARK,
771 LCDOUT21_MARK, MSIOF0_SCK_MARK, TS_SDAT0_MARK, ADICLK_MARK,
772 DU2_DB6_MARK, LCDOUT22_MARK, MSIOF0_SYNC_MARK, TS_SCK0_MARK,
773 SSI_SCK2_MARK, ADIDATA_MARK, DU2_DB7_MARK, LCDOUT23_MARK,
774 HRX0_C_MARK, MSIOF0_SS1_MARK, ADICHS0_MARK,
775 DU2_DG5_MARK, LCDOUT13_MARK, MSIOF0_TXD_MARK, ADICHS1_MARK,
776 DU2_DG6_MARK, LCDOUT14_MARK,
778 MSIOF0_SS2_MARK, AUDIO_CLKOUT_MARK, ADICHS2_MARK,
779 DU2_DISP_MARK, QPOLA_MARK, HTX0_C_MARK, SCIFA2_TXD_B_MARK,
780 MSIOF0_RXD_MARK, TS_SPSYNC0_MARK, SSI_WS2_MARK,
781 ADICS_SAMP_MARK, DU2_CDE_MARK, QPOLB_MARK, SCIFA2_RXD_B_MARK,
782 USB1_PWEN_MARK, AUDIO_CLKOUT_D_MARK, USB1_OVC_MARK,
785 I2C3_SCL_MARK, I2C3_SDA_MARK,
789 static const u16 pinmux_data[] = {
790 PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
792 PINMUX_DATA(VI1_DATA7_VI1_B7_MARK, FN_VI1_DATA7_VI1_B7),
793 PINMUX_DATA(USB0_PWEN_MARK, FN_USB0_PWEN),
794 PINMUX_DATA(USB0_OVC_VBUS_MARK, FN_USB0_OVC_VBUS),
795 PINMUX_DATA(USB2_PWEN_MARK, FN_USB2_PWEN),
796 PINMUX_DATA(USB2_OVC_MARK, FN_USB2_OVC),
797 PINMUX_DATA(AVS1_MARK, FN_AVS1),
798 PINMUX_DATA(AVS2_MARK, FN_AVS2),
799 PINMUX_DATA(DU_DOTCLKIN0_MARK, FN_DU_DOTCLKIN0),
800 PINMUX_DATA(DU_DOTCLKIN2_MARK, FN_DU_DOTCLKIN2),
802 PINMUX_IPSR_DATA(IP0_2_0, D0),
803 PINMUX_IPSR_MODSEL_DATA(IP0_2_0, MSIOF3_SCK_B, SEL_SOF3_1),
804 PINMUX_IPSR_MODSEL_DATA(IP0_2_0, VI3_DATA0, SEL_VI3_0),
805 PINMUX_IPSR_MODSEL_DATA(IP0_2_0, VI0_G4, SEL_VI0_0),
806 PINMUX_IPSR_MODSEL_DATA(IP0_2_0, VI0_G4_B, SEL_VI0_1),
807 PINMUX_IPSR_DATA(IP0_5_3, D1),
808 PINMUX_IPSR_MODSEL_DATA(IP0_5_3, MSIOF3_SYNC_B, SEL_SOF3_1),
809 PINMUX_IPSR_MODSEL_DATA(IP0_5_3, VI3_DATA1, SEL_VI3_0),
810 PINMUX_IPSR_MODSEL_DATA(IP0_5_3, VI0_G5, SEL_VI0_0),
811 PINMUX_IPSR_MODSEL_DATA(IP0_5_3, VI0_G5_B, SEL_VI0_1),
812 PINMUX_IPSR_DATA(IP0_8_6, D2),
813 PINMUX_IPSR_MODSEL_DATA(IP0_8_6, MSIOF3_RXD_B, SEL_SOF3_1),
814 PINMUX_IPSR_MODSEL_DATA(IP0_8_6, VI3_DATA2, SEL_VI3_0),
815 PINMUX_IPSR_MODSEL_DATA(IP0_8_6, VI0_G6, SEL_VI0_0),
816 PINMUX_IPSR_MODSEL_DATA(IP0_8_6, VI0_G6_B, SEL_VI0_1),
817 PINMUX_IPSR_DATA(IP0_11_9, D3),
818 PINMUX_IPSR_MODSEL_DATA(IP0_11_9, MSIOF3_TXD_B, SEL_SOF3_1),
819 PINMUX_IPSR_MODSEL_DATA(IP0_11_9, VI3_DATA3, SEL_VI3_0),
820 PINMUX_IPSR_MODSEL_DATA(IP0_11_9, VI0_G7, SEL_VI0_0),
821 PINMUX_IPSR_MODSEL_DATA(IP0_11_9, VI0_G7_B, SEL_VI0_1),
822 PINMUX_IPSR_DATA(IP0_15_12, D4),
823 PINMUX_IPSR_MODSEL_DATA(IP0_15_12, SCIFB1_RXD_F, SEL_SCIFB1_5),
824 PINMUX_IPSR_MODSEL_DATA(IP0_15_12, SCIFB0_RXD_C, SEL_SCIFB_2),
825 PINMUX_IPSR_MODSEL_DATA(IP0_15_12, VI3_DATA4, SEL_VI3_0),
826 PINMUX_IPSR_MODSEL_DATA(IP0_15_12, VI0_R0, SEL_VI0_0),
827 PINMUX_IPSR_MODSEL_DATA(IP0_15_12, VI0_R0_B, SEL_VI0_1),
828 PINMUX_IPSR_MODSEL_DATA(IP0_15_12, RX0_B, SEL_SCIF0_1),
829 PINMUX_IPSR_DATA(IP0_19_16, D5),
830 PINMUX_IPSR_MODSEL_DATA(IP0_19_16, SCIFB1_TXD_F, SEL_SCIFB1_5),
831 PINMUX_IPSR_MODSEL_DATA(IP0_19_16, SCIFB0_TXD_C, SEL_SCIFB_2),
832 PINMUX_IPSR_MODSEL_DATA(IP0_19_16, VI3_DATA5, SEL_VI3_0),
833 PINMUX_IPSR_MODSEL_DATA(IP0_19_16, VI0_R1, SEL_VI0_0),
834 PINMUX_IPSR_MODSEL_DATA(IP0_19_16, VI0_R1_B, SEL_VI0_1),
835 PINMUX_IPSR_MODSEL_DATA(IP0_19_16, TX0_B, SEL_SCIF0_1),
836 PINMUX_IPSR_DATA(IP0_22_20, D6),
837 PINMUX_IPSR_MODSEL_DATA(IP0_22_20, IIC2_SCL_C, SEL_IIC2_2),
838 PINMUX_IPSR_MODSEL_DATA(IP0_22_20, VI3_DATA6, SEL_VI3_0),
839 PINMUX_IPSR_MODSEL_DATA(IP0_22_20, VI0_R2, SEL_VI0_0),
840 PINMUX_IPSR_MODSEL_DATA(IP0_22_20, VI0_R2_B, SEL_VI0_1),
841 PINMUX_IPSR_MODSEL_DATA(IP0_22_20, I2C2_SCL_C, SEL_I2C2_2),
842 PINMUX_IPSR_DATA(IP0_26_23, D7),
843 PINMUX_IPSR_MODSEL_DATA(IP0_26_23, AD_DI_B, SEL_ADI_1),
844 PINMUX_IPSR_MODSEL_DATA(IP0_26_23, IIC2_SDA_C, SEL_IIC2_2),
845 PINMUX_IPSR_MODSEL_DATA(IP0_26_23, VI3_DATA7, SEL_VI3_0),
846 PINMUX_IPSR_MODSEL_DATA(IP0_26_23, VI0_R3, SEL_VI0_0),
847 PINMUX_IPSR_MODSEL_DATA(IP0_26_23, VI0_R3_B, SEL_VI0_1),
848 PINMUX_IPSR_MODSEL_DATA(IP0_26_23, I2C2_SDA_C, SEL_I2C2_2),
849 PINMUX_IPSR_MODSEL_DATA(IP0_26_23, TCLK1, SEL_TMU1_0),
850 PINMUX_IPSR_DATA(IP0_30_27, D8),
851 PINMUX_IPSR_MODSEL_DATA(IP0_30_27, SCIFA1_SCK_C, SEL_SCIFA1_2),
852 PINMUX_IPSR_DATA(IP0_30_27, AVB_TXD0),
853 PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI0_G0, SEL_VI0_0),
854 PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI0_G0_B, SEL_VI0_1),
855 PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI2_DATA0_VI2_B0, SEL_VI2_0),
857 PINMUX_IPSR_DATA(IP1_3_0, D9),
858 PINMUX_IPSR_MODSEL_DATA(IP1_3_0, SCIFA1_RXD_C, SEL_SCIFA1_2),
859 PINMUX_IPSR_DATA(IP1_3_0, AVB_TXD1),
860 PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI0_G1, SEL_VI0_0),
861 PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI0_G1_B, SEL_VI0_1),
862 PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI2_DATA1_VI2_B1, SEL_VI2_0),
863 PINMUX_IPSR_DATA(IP1_7_4, D10),
864 PINMUX_IPSR_MODSEL_DATA(IP1_7_4, SCIFA1_TXD_C, SEL_SCIFA1_2),
865 PINMUX_IPSR_DATA(IP1_7_4, AVB_TXD2),
866 PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI0_G2, SEL_VI0_0),
867 PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI0_G2_B, SEL_VI0_1),
868 PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI2_DATA2_VI2_B2, SEL_VI2_0),
869 PINMUX_IPSR_DATA(IP1_11_8, D11),
870 PINMUX_IPSR_MODSEL_DATA(IP1_11_8, SCIFA1_CTS_N_C, SEL_SCIFA1_2),
871 PINMUX_IPSR_DATA(IP1_11_8, AVB_TXD3),
872 PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI0_G3, SEL_VI0_0),
873 PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI0_G3_B, SEL_VI0_1),
874 PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI2_DATA3_VI2_B3, SEL_VI2_0),
875 PINMUX_IPSR_DATA(IP1_14_12, D12),
876 PINMUX_IPSR_MODSEL_DATA(IP1_14_12, SCIFA1_RTS_N_C, SEL_SCIFA1_2),
877 PINMUX_IPSR_DATA(IP1_14_12, AVB_TXD4),
878 PINMUX_IPSR_MODSEL_DATA(IP1_14_12, VI0_HSYNC_N, SEL_VI0_0),
879 PINMUX_IPSR_MODSEL_DATA(IP1_14_12, VI0_HSYNC_N_B, SEL_VI0_1),
880 PINMUX_IPSR_MODSEL_DATA(IP1_14_12, VI2_DATA4_VI2_B4, SEL_VI2_0),
881 PINMUX_IPSR_DATA(IP1_17_15, D13),
882 PINMUX_IPSR_DATA(IP1_17_15, AVB_TXD5),
883 PINMUX_IPSR_MODSEL_DATA(IP1_17_15, VI0_VSYNC_N, SEL_VI0_0),
884 PINMUX_IPSR_MODSEL_DATA(IP1_17_15, VI0_VSYNC_N_B, SEL_VI0_1),
885 PINMUX_IPSR_MODSEL_DATA(IP1_17_15, VI2_DATA5_VI2_B5, SEL_VI2_0),
886 PINMUX_IPSR_DATA(IP1_21_18, D14),
887 PINMUX_IPSR_MODSEL_DATA(IP1_21_18, SCIFB1_RXD_C, SEL_SCIFB1_2),
888 PINMUX_IPSR_DATA(IP1_21_18, AVB_TXD6),
889 PINMUX_IPSR_MODSEL_DATA(IP1_21_18, RX1_B, SEL_SCIF1_1),
890 PINMUX_IPSR_MODSEL_DATA(IP1_21_18, VI0_CLKENB, SEL_VI0_0),
891 PINMUX_IPSR_MODSEL_DATA(IP1_21_18, VI0_CLKENB_B, SEL_VI0_1),
892 PINMUX_IPSR_MODSEL_DATA(IP1_21_18, VI2_DATA6_VI2_B6, SEL_VI2_0),
893 PINMUX_IPSR_DATA(IP1_25_22, D15),
894 PINMUX_IPSR_MODSEL_DATA(IP1_25_22, SCIFB1_TXD_C, SEL_SCIFB1_2),
895 PINMUX_IPSR_DATA(IP1_25_22, AVB_TXD7),
896 PINMUX_IPSR_MODSEL_DATA(IP1_25_22, TX1_B, SEL_SCIF1_1),
897 PINMUX_IPSR_MODSEL_DATA(IP1_25_22, VI0_FIELD, SEL_VI0_0),
898 PINMUX_IPSR_MODSEL_DATA(IP1_25_22, VI0_FIELD_B, SEL_VI0_1),
899 PINMUX_IPSR_MODSEL_DATA(IP1_25_22, VI2_DATA7_VI2_B7, SEL_VI2_0),
900 PINMUX_IPSR_DATA(IP1_27_26, A0),
901 PINMUX_IPSR_DATA(IP1_27_26, PWM3),
902 PINMUX_IPSR_DATA(IP1_29_28, A1),
903 PINMUX_IPSR_DATA(IP1_29_28, PWM4),
905 PINMUX_IPSR_DATA(IP2_2_0, A2),
906 PINMUX_IPSR_DATA(IP2_2_0, PWM5),
907 PINMUX_IPSR_MODSEL_DATA(IP2_2_0, MSIOF1_SS1_B, SEL_SOF1_1),
908 PINMUX_IPSR_DATA(IP2_5_3, A3),
909 PINMUX_IPSR_DATA(IP2_5_3, PWM6),
910 PINMUX_IPSR_MODSEL_DATA(IP2_5_3, MSIOF1_SS2_B, SEL_SOF1_1),
911 PINMUX_IPSR_DATA(IP2_8_6, A4),
912 PINMUX_IPSR_MODSEL_DATA(IP2_8_6, MSIOF1_TXD_B, SEL_SOF1_1),
913 PINMUX_IPSR_DATA(IP2_8_6, TPU0TO0),
914 PINMUX_IPSR_DATA(IP2_11_9, A5),
915 PINMUX_IPSR_MODSEL_DATA(IP2_11_9, SCIFA1_TXD_B, SEL_SCIFA1_1),
916 PINMUX_IPSR_DATA(IP2_11_9, TPU0TO1),
917 PINMUX_IPSR_DATA(IP2_14_12, A6),
918 PINMUX_IPSR_MODSEL_DATA(IP2_14_12, SCIFA1_RTS_N_B, SEL_SCIFA1_1),
919 PINMUX_IPSR_DATA(IP2_14_12, TPU0TO2),
920 PINMUX_IPSR_DATA(IP2_17_15, A7),
921 PINMUX_IPSR_MODSEL_DATA(IP2_17_15, SCIFA1_SCK_B, SEL_SCIFA1_1),
922 PINMUX_IPSR_DATA(IP2_17_15, AUDIO_CLKOUT_B),
923 PINMUX_IPSR_DATA(IP2_17_15, TPU0TO3),
924 PINMUX_IPSR_DATA(IP2_21_18, A8),
925 PINMUX_IPSR_MODSEL_DATA(IP2_21_18, SCIFA1_RXD_B, SEL_SCIFA1_1),
926 PINMUX_IPSR_MODSEL_DATA(IP2_21_18, SSI_SCK5_B, SEL_SSI5_1),
927 PINMUX_IPSR_MODSEL_DATA(IP2_21_18, VI0_R4, SEL_VI0_0),
928 PINMUX_IPSR_MODSEL_DATA(IP2_21_18, VI0_R4_B, SEL_VI0_1),
929 PINMUX_IPSR_MODSEL_DATA(IP2_21_18, SCIFB2_RXD_C, SEL_SCIFB2_2),
930 PINMUX_IPSR_MODSEL_DATA(IP2_21_18, RX2_B, SEL_SCIF2_1),
931 PINMUX_IPSR_MODSEL_DATA(IP2_21_18, VI2_DATA0_VI2_B0_B, SEL_VI2_1),
932 PINMUX_IPSR_DATA(IP2_25_22, A9),
933 PINMUX_IPSR_MODSEL_DATA(IP2_25_22, SCIFA1_CTS_N_B, SEL_SCIFA1_1),
934 PINMUX_IPSR_MODSEL_DATA(IP2_25_22, SSI_WS5_B, SEL_SSI5_1),
935 PINMUX_IPSR_MODSEL_DATA(IP2_25_22, VI0_R5, SEL_VI0_0),
936 PINMUX_IPSR_MODSEL_DATA(IP2_25_22, VI0_R5_B, SEL_VI0_1),
937 PINMUX_IPSR_MODSEL_DATA(IP2_25_22, SCIFB2_TXD_C, SEL_SCIFB2_2),
938 PINMUX_IPSR_MODSEL_DATA(IP2_25_22, TX2_B, SEL_SCIF2_1),
939 PINMUX_IPSR_MODSEL_DATA(IP2_25_22, VI2_DATA1_VI2_B1_B, SEL_VI2_1),
940 PINMUX_IPSR_DATA(IP2_28_26, A10),
941 PINMUX_IPSR_MODSEL_DATA(IP2_28_26, SSI_SDATA5_B, SEL_SSI5_1),
942 PINMUX_IPSR_DATA(IP2_28_26, MSIOF2_SYNC),
943 PINMUX_IPSR_MODSEL_DATA(IP2_28_26, VI0_R6, SEL_VI0_0),
944 PINMUX_IPSR_MODSEL_DATA(IP2_28_26, VI0_R6_B, SEL_VI0_1),
945 PINMUX_IPSR_MODSEL_DATA(IP2_28_26, VI2_DATA2_VI2_B2_B, SEL_VI2_1),
947 PINMUX_IPSR_DATA(IP3_3_0, A11),
948 PINMUX_IPSR_MODSEL_DATA(IP3_3_0, SCIFB2_CTS_N_B, SEL_SCIFB2_1),
949 PINMUX_IPSR_DATA(IP3_3_0, MSIOF2_SCK),
950 PINMUX_IPSR_MODSEL_DATA(IP3_3_0, VI1_R0, SEL_VI1_0),
951 PINMUX_IPSR_MODSEL_DATA(IP3_3_0, VI1_R0_B, SEL_VI1_1),
952 PINMUX_IPSR_DATA(IP3_3_0, VI2_G0),
953 PINMUX_IPSR_MODSEL_DATA(IP3_3_0, VI2_DATA3_VI2_B3_B, SEL_VI2_1),
954 PINMUX_IPSR_DATA(IP3_7_4, A12),
955 PINMUX_IPSR_MODSEL_DATA(IP3_7_4, SCIFB2_RXD_B, SEL_SCIFB2_1),
956 PINMUX_IPSR_DATA(IP3_7_4, MSIOF2_TXD),
957 PINMUX_IPSR_MODSEL_DATA(IP3_7_4, VI1_R1, SEL_VI1_0),
958 PINMUX_IPSR_MODSEL_DATA(IP3_7_4, VI1_R1_B, SEL_VI1_1),
959 PINMUX_IPSR_DATA(IP3_7_4, VI2_G1),
960 PINMUX_IPSR_MODSEL_DATA(IP3_7_4, VI2_DATA4_VI2_B4_B, SEL_VI2_1),
961 PINMUX_IPSR_DATA(IP3_11_8, A13),
962 PINMUX_IPSR_MODSEL_DATA(IP3_11_8, SCIFB2_RTS_N_B, SEL_SCIFB2_1),
963 PINMUX_IPSR_DATA(IP3_11_8, EX_WAIT2),
964 PINMUX_IPSR_DATA(IP3_11_8, MSIOF2_RXD),
965 PINMUX_IPSR_MODSEL_DATA(IP3_11_8, VI1_R2, SEL_VI1_0),
966 PINMUX_IPSR_MODSEL_DATA(IP3_11_8, VI1_R2_B, SEL_VI1_1),
967 PINMUX_IPSR_DATA(IP3_11_8, VI2_G2),
968 PINMUX_IPSR_MODSEL_DATA(IP3_11_8, VI2_DATA5_VI2_B5_B, SEL_VI2_1),
969 PINMUX_IPSR_DATA(IP3_14_12, A14),
970 PINMUX_IPSR_MODSEL_DATA(IP3_14_12, SCIFB2_TXD_B, SEL_SCIFB2_1),
971 PINMUX_IPSR_DATA(IP3_14_12, ATACS11_N),
972 PINMUX_IPSR_DATA(IP3_14_12, MSIOF2_SS1),
973 PINMUX_IPSR_DATA(IP3_17_15, A15),
974 PINMUX_IPSR_MODSEL_DATA(IP3_17_15, SCIFB2_SCK_B, SEL_SCIFB2_1),
975 PINMUX_IPSR_DATA(IP3_17_15, ATARD1_N),
976 PINMUX_IPSR_DATA(IP3_17_15, MSIOF2_SS2),
977 PINMUX_IPSR_DATA(IP3_19_18, A16),
978 PINMUX_IPSR_DATA(IP3_19_18, ATAWR1_N),
979 PINMUX_IPSR_DATA(IP3_22_20, A17),
980 PINMUX_IPSR_MODSEL_DATA(IP3_22_20, AD_DO_B, SEL_ADI_1),
981 PINMUX_IPSR_DATA(IP3_22_20, ATADIR1_N),
982 PINMUX_IPSR_DATA(IP3_25_23, A18),
983 PINMUX_IPSR_MODSEL_DATA(IP3_25_23, AD_CLK_B, SEL_ADI_1),
984 PINMUX_IPSR_DATA(IP3_25_23, ATAG1_N),
985 PINMUX_IPSR_DATA(IP3_28_26, A19),
986 PINMUX_IPSR_MODSEL_DATA(IP3_28_26, AD_NCS_N_B, SEL_ADI_1),
987 PINMUX_IPSR_DATA(IP3_28_26, ATACS01_N),
988 PINMUX_IPSR_MODSEL_DATA(IP3_28_26, EX_WAIT0_B, SEL_LBS_1),
989 PINMUX_IPSR_DATA(IP3_31_29, A20),
990 PINMUX_IPSR_DATA(IP3_31_29, SPCLK),
991 PINMUX_IPSR_MODSEL_DATA(IP3_31_29, VI1_R3, SEL_VI1_0),
992 PINMUX_IPSR_MODSEL_DATA(IP3_31_29, VI1_R3_B, SEL_VI1_1),
993 PINMUX_IPSR_DATA(IP3_31_29, VI2_G4),
995 PINMUX_IPSR_DATA(IP4_2_0, A21),
996 PINMUX_IPSR_DATA(IP4_2_0, MOSI_IO0),
997 PINMUX_IPSR_MODSEL_DATA(IP4_2_0, VI1_R4, SEL_VI1_0),
998 PINMUX_IPSR_MODSEL_DATA(IP4_2_0, VI1_R4_B, SEL_VI1_1),
999 PINMUX_IPSR_DATA(IP4_2_0, VI2_G5),
1000 PINMUX_IPSR_DATA(IP4_5_3, A22),
1001 PINMUX_IPSR_DATA(IP4_5_3, MISO_IO1),
1002 PINMUX_IPSR_MODSEL_DATA(IP4_5_3, VI1_R5, SEL_VI1_0),
1003 PINMUX_IPSR_MODSEL_DATA(IP4_5_3, VI1_R5_B, SEL_VI1_1),
1004 PINMUX_IPSR_DATA(IP4_5_3, VI2_G6),
1005 PINMUX_IPSR_DATA(IP4_8_6, A23),
1006 PINMUX_IPSR_DATA(IP4_8_6, IO2),
1007 PINMUX_IPSR_MODSEL_DATA(IP4_8_6, VI1_G7, SEL_VI1_0),
1008 PINMUX_IPSR_MODSEL_DATA(IP4_8_6, VI1_G7_B, SEL_VI1_1),
1009 PINMUX_IPSR_DATA(IP4_8_6, VI2_G7),
1010 PINMUX_IPSR_DATA(IP4_11_9, A24),
1011 PINMUX_IPSR_DATA(IP4_11_9, IO3),
1012 PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI1_R7, SEL_VI1_0),
1013 PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI1_R7_B, SEL_VI1_1),
1014 PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI2_CLKENB, SEL_VI2_0),
1015 PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI2_CLKENB_B, SEL_VI2_1),
1016 PINMUX_IPSR_DATA(IP4_14_12, A25),
1017 PINMUX_IPSR_DATA(IP4_14_12, SSL),
1018 PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI1_G6, SEL_VI1_0),
1019 PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI1_G6_B, SEL_VI1_1),
1020 PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI2_FIELD, SEL_VI2_0),
1021 PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI2_FIELD_B, SEL_VI2_1),
1022 PINMUX_IPSR_DATA(IP4_17_15, CS0_N),
1023 PINMUX_IPSR_MODSEL_DATA(IP4_17_15, VI1_R6, SEL_VI1_0),
1024 PINMUX_IPSR_MODSEL_DATA(IP4_17_15, VI1_R6_B, SEL_VI1_1),
1025 PINMUX_IPSR_DATA(IP4_17_15, VI2_G3),
1026 PINMUX_IPSR_MODSEL_DATA(IP4_17_15, MSIOF0_SS2_B, SEL_SOF0_1),
1027 PINMUX_IPSR_DATA(IP4_20_18, CS1_N_A26),
1028 PINMUX_IPSR_DATA(IP4_20_18, SPEEDIN),
1029 PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI0_R7, SEL_VI0_0),
1030 PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI0_R7_B, SEL_VI0_1),
1031 PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI2_CLK, SEL_VI2_0),
1032 PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI2_CLK_B, SEL_VI2_1),
1033 PINMUX_IPSR_DATA(IP4_23_21, EX_CS0_N),
1034 PINMUX_IPSR_MODSEL_DATA(IP4_23_21, HRX1_B, SEL_HSCIF1_1),
1035 PINMUX_IPSR_MODSEL_DATA(IP4_23_21, VI1_G5, SEL_VI1_0),
1036 PINMUX_IPSR_MODSEL_DATA(IP4_23_21, VI1_G5_B, SEL_VI1_1),
1037 PINMUX_IPSR_DATA(IP4_23_21, VI2_R0),
1038 PINMUX_IPSR_MODSEL_DATA(IP4_23_21, HTX0_B, SEL_HSCIF0_1),
1039 PINMUX_IPSR_MODSEL_DATA(IP4_23_21, MSIOF0_SS1_B, SEL_SOF0_1),
1040 PINMUX_IPSR_DATA(IP4_26_24, EX_CS1_N),
1041 PINMUX_IPSR_DATA(IP4_26_24, GPS_CLK),
1042 PINMUX_IPSR_MODSEL_DATA(IP4_26_24, HCTS1_N_B, SEL_HSCIF1_1),
1043 PINMUX_IPSR_MODSEL_DATA(IP4_26_24, VI1_FIELD, SEL_VI1_0),
1044 PINMUX_IPSR_MODSEL_DATA(IP4_26_24, VI1_FIELD_B, SEL_VI1_1),
1045 PINMUX_IPSR_DATA(IP4_26_24, VI2_R1),
1046 PINMUX_IPSR_DATA(IP4_29_27, EX_CS2_N),
1047 PINMUX_IPSR_DATA(IP4_29_27, GPS_SIGN),
1048 PINMUX_IPSR_MODSEL_DATA(IP4_29_27, HRTS1_N_B, SEL_HSCIF1_1),
1049 PINMUX_IPSR_DATA(IP4_29_27, VI3_CLKENB),
1050 PINMUX_IPSR_MODSEL_DATA(IP4_29_27, VI1_G0, SEL_VI1_0),
1051 PINMUX_IPSR_MODSEL_DATA(IP4_29_27, VI1_G0_B, SEL_VI1_1),
1052 PINMUX_IPSR_DATA(IP4_29_27, VI2_R2),
1054 PINMUX_IPSR_DATA(IP5_2_0, EX_CS3_N),
1055 PINMUX_IPSR_DATA(IP5_2_0, GPS_MAG),
1056 PINMUX_IPSR_DATA(IP5_2_0, VI3_FIELD),
1057 PINMUX_IPSR_MODSEL_DATA(IP5_2_0, VI1_G1, SEL_VI1_0),
1058 PINMUX_IPSR_MODSEL_DATA(IP5_2_0, VI1_G1_B, SEL_VI1_1),
1059 PINMUX_IPSR_DATA(IP5_2_0, VI2_R3),
1060 PINMUX_IPSR_DATA(IP5_5_3, EX_CS4_N),
1061 PINMUX_IPSR_MODSEL_DATA(IP5_5_3, MSIOF1_SCK_B, SEL_SOF1_1),
1062 PINMUX_IPSR_DATA(IP5_5_3, VI3_HSYNC_N),
1063 PINMUX_IPSR_MODSEL_DATA(IP5_5_3, VI2_HSYNC_N, SEL_VI2_0),
1064 PINMUX_IPSR_MODSEL_DATA(IP5_5_3, IIC1_SCL, SEL_IIC1_0),
1065 PINMUX_IPSR_MODSEL_DATA(IP5_5_3, VI2_HSYNC_N_B, SEL_VI2_1),
1066 PINMUX_IPSR_DATA(IP5_5_3, INTC_EN0_N),
1067 PINMUX_IPSR_MODSEL_DATA(IP5_5_3, I2C1_SCL, SEL_I2C1_0),
1068 PINMUX_IPSR_DATA(IP5_9_6, EX_CS5_N),
1069 PINMUX_IPSR_MODSEL_DATA(IP5_9_6, CAN0_RX, SEL_CAN0_0),
1070 PINMUX_IPSR_MODSEL_DATA(IP5_9_6, MSIOF1_RXD_B, SEL_SOF1_1),
1071 PINMUX_IPSR_DATA(IP5_9_6, VI3_VSYNC_N),
1072 PINMUX_IPSR_MODSEL_DATA(IP5_9_6, VI1_G2, SEL_VI1_0),
1073 PINMUX_IPSR_MODSEL_DATA(IP5_9_6, VI1_G2_B, SEL_VI1_1),
1074 PINMUX_IPSR_DATA(IP5_9_6, VI2_R4),
1075 PINMUX_IPSR_MODSEL_DATA(IP5_9_6, IIC1_SDA, SEL_IIC1_0),
1076 PINMUX_IPSR_DATA(IP5_9_6, INTC_EN1_N),
1077 PINMUX_IPSR_MODSEL_DATA(IP5_9_6, I2C1_SDA, SEL_I2C1_0),
1078 PINMUX_IPSR_DATA(IP5_12_10, BS_N),
1079 PINMUX_IPSR_MODSEL_DATA(IP5_12_10, IETX, SEL_IEB_0),
1080 PINMUX_IPSR_MODSEL_DATA(IP5_12_10, HTX1_B, SEL_HSCIF1_1),
1081 PINMUX_IPSR_MODSEL_DATA(IP5_12_10, CAN1_TX, SEL_CAN1_0),
1082 PINMUX_IPSR_DATA(IP5_12_10, DRACK0),
1083 PINMUX_IPSR_MODSEL_DATA(IP5_12_10, IETX_C, SEL_IEB_2),
1084 PINMUX_IPSR_DATA(IP5_14_13, RD_N),
1085 PINMUX_IPSR_MODSEL_DATA(IP5_14_13, CAN0_TX, SEL_CAN0_0),
1086 PINMUX_IPSR_MODSEL_DATA(IP5_14_13, SCIFA0_SCK_B, SEL_SCFA_1),
1087 PINMUX_IPSR_DATA(IP5_17_15, RD_WR_N),
1088 PINMUX_IPSR_MODSEL_DATA(IP5_17_15, VI1_G3, SEL_VI1_0),
1089 PINMUX_IPSR_MODSEL_DATA(IP5_17_15, VI1_G3_B, SEL_VI1_1),
1090 PINMUX_IPSR_DATA(IP5_17_15, VI2_R5),
1091 PINMUX_IPSR_MODSEL_DATA(IP5_17_15, SCIFA0_RXD_B, SEL_SCFA_1),
1092 PINMUX_IPSR_DATA(IP5_17_15, INTC_IRQ4_N),
1093 PINMUX_IPSR_DATA(IP5_20_18, WE0_N),
1094 PINMUX_IPSR_MODSEL_DATA(IP5_20_18, IECLK, SEL_IEB_0),
1095 PINMUX_IPSR_MODSEL_DATA(IP5_20_18, CAN_CLK, SEL_CANCLK_0),
1096 PINMUX_IPSR_MODSEL_DATA(IP5_20_18, VI2_VSYNC_N, SEL_VI2_0),
1097 PINMUX_IPSR_MODSEL_DATA(IP5_20_18, SCIFA0_TXD_B, SEL_SCFA_1),
1098 PINMUX_IPSR_MODSEL_DATA(IP5_20_18, VI2_VSYNC_N_B, SEL_VI2_1),
1099 PINMUX_IPSR_DATA(IP5_23_21, WE1_N),
1100 PINMUX_IPSR_MODSEL_DATA(IP5_23_21, IERX, SEL_IEB_0),
1101 PINMUX_IPSR_MODSEL_DATA(IP5_23_21, CAN1_RX, SEL_CAN1_0),
1102 PINMUX_IPSR_MODSEL_DATA(IP5_23_21, VI1_G4, SEL_VI1_0),
1103 PINMUX_IPSR_MODSEL_DATA(IP5_23_21, VI1_G4_B, SEL_VI1_1),
1104 PINMUX_IPSR_DATA(IP5_23_21, VI2_R6),
1105 PINMUX_IPSR_MODSEL_DATA(IP5_23_21, SCIFA0_CTS_N_B, SEL_SCFA_1),
1106 PINMUX_IPSR_MODSEL_DATA(IP5_23_21, IERX_C, SEL_IEB_2),
1107 PINMUX_IPSR_MODSEL_DATA(IP5_26_24, EX_WAIT0, SEL_LBS_0),
1108 PINMUX_IPSR_DATA(IP5_26_24, IRQ3),
1109 PINMUX_IPSR_DATA(IP5_26_24, INTC_IRQ3_N),
1110 PINMUX_IPSR_MODSEL_DATA(IP5_26_24, VI3_CLK, SEL_VI3_0),
1111 PINMUX_IPSR_MODSEL_DATA(IP5_26_24, SCIFA0_RTS_N_B, SEL_SCFA_1),
1112 PINMUX_IPSR_MODSEL_DATA(IP5_26_24, HRX0_B, SEL_HSCIF0_1),
1113 PINMUX_IPSR_MODSEL_DATA(IP5_26_24, MSIOF0_SCK_B, SEL_SOF0_1),
1114 PINMUX_IPSR_DATA(IP5_29_27, DREQ0_N),
1115 PINMUX_IPSR_MODSEL_DATA(IP5_29_27, VI1_HSYNC_N, SEL_VI1_0),
1116 PINMUX_IPSR_MODSEL_DATA(IP5_29_27, VI1_HSYNC_N_B, SEL_VI1_1),
1117 PINMUX_IPSR_DATA(IP5_29_27, VI2_R7),
1118 PINMUX_IPSR_MODSEL_DATA(IP5_29_27, SSI_SCK78_C, SEL_SSI7_2),
1119 PINMUX_IPSR_MODSEL_DATA(IP5_29_27, SSI_WS78_B, SEL_SSI7_1),
1121 PINMUX_IPSR_DATA(IP6_2_0, DACK0),
1122 PINMUX_IPSR_DATA(IP6_2_0, IRQ0),
1123 PINMUX_IPSR_DATA(IP6_2_0, INTC_IRQ0_N),
1124 PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SSI_SCK6_B, SEL_SSI6_1),
1125 PINMUX_IPSR_MODSEL_DATA(IP6_2_0, VI1_VSYNC_N, SEL_VI1_0),
1126 PINMUX_IPSR_MODSEL_DATA(IP6_2_0, VI1_VSYNC_N_B, SEL_VI1_1),
1127 PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SSI_WS78_C, SEL_SSI7_2),
1128 PINMUX_IPSR_DATA(IP6_5_3, DREQ1_N),
1129 PINMUX_IPSR_MODSEL_DATA(IP6_5_3, VI1_CLKENB, SEL_VI1_0),
1130 PINMUX_IPSR_MODSEL_DATA(IP6_5_3, VI1_CLKENB_B, SEL_VI1_1),
1131 PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SSI_SDATA7_C, SEL_SSI7_2),
1132 PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SSI_SCK78_B, SEL_SSI7_1),
1133 PINMUX_IPSR_DATA(IP6_8_6, DACK1),
1134 PINMUX_IPSR_DATA(IP6_8_6, IRQ1),
1135 PINMUX_IPSR_DATA(IP6_8_6, INTC_IRQ1_N),
1136 PINMUX_IPSR_MODSEL_DATA(IP6_8_6, SSI_WS6_B, SEL_SSI6_1),
1137 PINMUX_IPSR_MODSEL_DATA(IP6_8_6, SSI_SDATA8_C, SEL_SSI8_2),
1138 PINMUX_IPSR_DATA(IP6_10_9, DREQ2_N),
1139 PINMUX_IPSR_MODSEL_DATA(IP6_10_9, HSCK1_B, SEL_HSCIF1_1),
1140 PINMUX_IPSR_MODSEL_DATA(IP6_10_9, HCTS0_N_B, SEL_HSCIF0_1),
1141 PINMUX_IPSR_MODSEL_DATA(IP6_10_9, MSIOF0_TXD_B, SEL_SOF0_1),
1142 PINMUX_IPSR_DATA(IP6_13_11, DACK2),
1143 PINMUX_IPSR_DATA(IP6_13_11, IRQ2),
1144 PINMUX_IPSR_DATA(IP6_13_11, INTC_IRQ2_N),
1145 PINMUX_IPSR_MODSEL_DATA(IP6_13_11, SSI_SDATA6_B, SEL_SSI6_1),
1146 PINMUX_IPSR_MODSEL_DATA(IP6_13_11, HRTS0_N_B, SEL_HSCIF0_1),
1147 PINMUX_IPSR_MODSEL_DATA(IP6_13_11, MSIOF0_RXD_B, SEL_SOF0_1),
1148 PINMUX_IPSR_DATA(IP6_16_14, ETH_CRS_DV),
1149 PINMUX_IPSR_MODSEL_DATA(IP6_16_14, STP_ISCLK_0_B, SEL_SSP_1),
1150 PINMUX_IPSR_MODSEL_DATA(IP6_16_14, TS_SDEN0_D, SEL_TSIF0_3),
1151 PINMUX_IPSR_MODSEL_DATA(IP6_16_14, GLO_Q0_C, SEL_GPS_2),
1152 PINMUX_IPSR_MODSEL_DATA(IP6_16_14, IIC2_SCL_E, SEL_IIC2_4),
1153 PINMUX_IPSR_MODSEL_DATA(IP6_16_14, I2C2_SCL_E, SEL_I2C2_4),
1154 PINMUX_IPSR_DATA(IP6_19_17, ETH_RX_ER),
1155 PINMUX_IPSR_MODSEL_DATA(IP6_19_17, STP_ISD_0_B, SEL_SSP_1),
1156 PINMUX_IPSR_MODSEL_DATA(IP6_19_17, TS_SPSYNC0_D, SEL_TSIF0_3),
1157 PINMUX_IPSR_MODSEL_DATA(IP6_19_17, GLO_Q1_C, SEL_GPS_2),
1158 PINMUX_IPSR_MODSEL_DATA(IP6_19_17, IIC2_SDA_E, SEL_IIC2_4),
1159 PINMUX_IPSR_MODSEL_DATA(IP6_19_17, I2C2_SDA_E, SEL_I2C2_4),
1160 PINMUX_IPSR_DATA(IP6_22_20, ETH_RXD0),
1161 PINMUX_IPSR_MODSEL_DATA(IP6_22_20, STP_ISEN_0_B, SEL_SSP_1),
1162 PINMUX_IPSR_MODSEL_DATA(IP6_22_20, TS_SDAT0_D, SEL_TSIF0_3),
1163 PINMUX_IPSR_MODSEL_DATA(IP6_22_20, GLO_I0_C, SEL_GPS_2),
1164 PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCIFB1_SCK_G, SEL_SCIFB1_6),
1165 PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCK1_E, SEL_SCIF1_4),
1166 PINMUX_IPSR_DATA(IP6_25_23, ETH_RXD1),
1167 PINMUX_IPSR_MODSEL_DATA(IP6_25_23, HRX0_E, SEL_HSCIF0_4),
1168 PINMUX_IPSR_MODSEL_DATA(IP6_25_23, STP_ISSYNC_0_B, SEL_SSP_1),
1169 PINMUX_IPSR_MODSEL_DATA(IP6_25_23, TS_SCK0_D, SEL_TSIF0_3),
1170 PINMUX_IPSR_MODSEL_DATA(IP6_25_23, GLO_I1_C, SEL_GPS_2),
1171 PINMUX_IPSR_MODSEL_DATA(IP6_25_23, SCIFB1_RXD_G, SEL_SCIFB1_6),
1172 PINMUX_IPSR_MODSEL_DATA(IP6_25_23, RX1_E, SEL_SCIF1_4),
1173 PINMUX_IPSR_DATA(IP6_28_26, ETH_LINK),
1174 PINMUX_IPSR_MODSEL_DATA(IP6_28_26, HTX0_E, SEL_HSCIF0_4),
1175 PINMUX_IPSR_MODSEL_DATA(IP6_28_26, STP_IVCXO27_0_B, SEL_SSP_1),
1176 PINMUX_IPSR_MODSEL_DATA(IP6_28_26, SCIFB1_TXD_G, SEL_SCIFB1_6),
1177 PINMUX_IPSR_MODSEL_DATA(IP6_28_26, TX1_E, SEL_SCIF1_4),
1178 PINMUX_IPSR_DATA(IP6_31_29, ETH_REF_CLK),
1179 PINMUX_IPSR_MODSEL_DATA(IP6_31_29, HCTS0_N_E, SEL_HSCIF0_4),
1180 PINMUX_IPSR_MODSEL_DATA(IP6_31_29, STP_IVCXO27_1_B, SEL_SSP_1),
1181 PINMUX_IPSR_MODSEL_DATA(IP6_31_29, HRX0_F, SEL_HSCIF0_5),
1183 PINMUX_IPSR_DATA(IP7_2_0, ETH_MDIO),
1184 PINMUX_IPSR_MODSEL_DATA(IP7_2_0, HRTS0_N_E, SEL_HSCIF0_4),
1185 PINMUX_IPSR_MODSEL_DATA(IP7_2_0, SIM0_D_C, SEL_SIM_2),
1186 PINMUX_IPSR_MODSEL_DATA(IP7_2_0, HCTS0_N_F, SEL_HSCIF0_5),
1187 PINMUX_IPSR_DATA(IP7_5_3, ETH_TXD1),
1188 PINMUX_IPSR_MODSEL_DATA(IP7_5_3, HTX0_F, SEL_HSCIF0_5),
1189 PINMUX_IPSR_MODSEL_DATA(IP7_5_3, BPFCLK_G, SEL_FM_6),
1190 PINMUX_IPSR_DATA(IP7_7_6, ETH_TX_EN),
1191 PINMUX_IPSR_MODSEL_DATA(IP7_7_6, SIM0_CLK_C, SEL_SIM_2),
1192 PINMUX_IPSR_MODSEL_DATA(IP7_7_6, HRTS0_N_F, SEL_HSCIF0_5),
1193 PINMUX_IPSR_DATA(IP7_9_8, ETH_MAGIC),
1194 PINMUX_IPSR_MODSEL_DATA(IP7_9_8, SIM0_RST_C, SEL_SIM_2),
1195 PINMUX_IPSR_DATA(IP7_12_10, ETH_TXD0),
1196 PINMUX_IPSR_MODSEL_DATA(IP7_12_10, STP_ISCLK_1_B, SEL_SSP_1),
1197 PINMUX_IPSR_MODSEL_DATA(IP7_12_10, TS_SDEN1_C, SEL_TSIF1_2),
1198 PINMUX_IPSR_MODSEL_DATA(IP7_12_10, GLO_SCLK_C, SEL_GPS_2),
1199 PINMUX_IPSR_DATA(IP7_15_13, ETH_MDC),
1200 PINMUX_IPSR_MODSEL_DATA(IP7_15_13, STP_ISD_1_B, SEL_SSP_1),
1201 PINMUX_IPSR_MODSEL_DATA(IP7_15_13, TS_SPSYNC1_C, SEL_TSIF1_2),
1202 PINMUX_IPSR_MODSEL_DATA(IP7_15_13, GLO_SDATA_C, SEL_GPS_2),
1203 PINMUX_IPSR_DATA(IP7_18_16, PWM0),
1204 PINMUX_IPSR_MODSEL_DATA(IP7_18_16, SCIFA2_SCK_C, SEL_SCIFA2_2),
1205 PINMUX_IPSR_MODSEL_DATA(IP7_18_16, STP_ISEN_1_B, SEL_SSP_1),
1206 PINMUX_IPSR_MODSEL_DATA(IP7_18_16, TS_SDAT1_C, SEL_TSIF1_2),
1207 PINMUX_IPSR_MODSEL_DATA(IP7_18_16, GLO_SS_C, SEL_GPS_2),
1208 PINMUX_IPSR_DATA(IP7_21_19, PWM1),
1209 PINMUX_IPSR_MODSEL_DATA(IP7_21_19, SCIFA2_TXD_C, SEL_SCIFA2_2),
1210 PINMUX_IPSR_MODSEL_DATA(IP7_21_19, STP_ISSYNC_1_B, SEL_SSP_1),
1211 PINMUX_IPSR_MODSEL_DATA(IP7_21_19, TS_SCK1_C, SEL_TSIF1_2),
1212 PINMUX_IPSR_MODSEL_DATA(IP7_21_19, GLO_RFON_C, SEL_GPS_2),
1213 PINMUX_IPSR_DATA(IP7_21_19, PCMOE_N),
1214 PINMUX_IPSR_DATA(IP7_24_22, PWM2),
1215 PINMUX_IPSR_DATA(IP7_24_22, PWMFSW0),
1216 PINMUX_IPSR_MODSEL_DATA(IP7_24_22, SCIFA2_RXD_C, SEL_SCIFA2_2),
1217 PINMUX_IPSR_DATA(IP7_24_22, PCMWE_N),
1218 PINMUX_IPSR_MODSEL_DATA(IP7_24_22, IECLK_C, SEL_IEB_2),
1219 PINMUX_IPSR_DATA(IP7_26_25, DU_DOTCLKIN1),
1220 PINMUX_IPSR_DATA(IP7_26_25, AUDIO_CLKC),
1221 PINMUX_IPSR_DATA(IP7_26_25, AUDIO_CLKOUT_C),
1222 PINMUX_IPSR_MODSEL_DATA(IP7_28_27, VI0_CLK, SEL_VI0_0),
1223 PINMUX_IPSR_DATA(IP7_28_27, ATACS00_N),
1224 PINMUX_IPSR_DATA(IP7_28_27, AVB_RXD1),
1225 PINMUX_IPSR_MODSEL_DATA(IP7_30_29, VI0_DATA0_VI0_B0, SEL_VI0_0),
1226 PINMUX_IPSR_DATA(IP7_30_29, ATACS10_N),
1227 PINMUX_IPSR_DATA(IP7_30_29, AVB_RXD2),
1229 PINMUX_IPSR_MODSEL_DATA(IP8_1_0, VI0_DATA1_VI0_B1, SEL_VI0_0),
1230 PINMUX_IPSR_DATA(IP8_1_0, ATARD0_N),
1231 PINMUX_IPSR_DATA(IP8_1_0, AVB_RXD3),
1232 PINMUX_IPSR_MODSEL_DATA(IP8_3_2, VI0_DATA2_VI0_B2, SEL_VI0_0),
1233 PINMUX_IPSR_DATA(IP8_3_2, ATAWR0_N),
1234 PINMUX_IPSR_DATA(IP8_3_2, AVB_RXD4),
1235 PINMUX_IPSR_MODSEL_DATA(IP8_5_4, VI0_DATA3_VI0_B3, SEL_VI0_0),
1236 PINMUX_IPSR_DATA(IP8_5_4, ATADIR0_N),
1237 PINMUX_IPSR_DATA(IP8_5_4, AVB_RXD5),
1238 PINMUX_IPSR_MODSEL_DATA(IP8_7_6, VI0_DATA4_VI0_B4, SEL_VI0_0),
1239 PINMUX_IPSR_DATA(IP8_7_6, ATAG0_N),
1240 PINMUX_IPSR_DATA(IP8_7_6, AVB_RXD6),
1241 PINMUX_IPSR_MODSEL_DATA(IP8_9_8, VI0_DATA5_VI0_B5, SEL_VI0_0),
1242 PINMUX_IPSR_DATA(IP8_9_8, EX_WAIT1),
1243 PINMUX_IPSR_DATA(IP8_9_8, AVB_RXD7),
1244 PINMUX_IPSR_MODSEL_DATA(IP8_11_10, VI0_DATA6_VI0_B6, SEL_VI0_0),
1245 PINMUX_IPSR_DATA(IP8_11_10, AVB_RX_ER),
1246 PINMUX_IPSR_MODSEL_DATA(IP8_13_12, VI0_DATA7_VI0_B7, SEL_VI0_0),
1247 PINMUX_IPSR_DATA(IP8_13_12, AVB_RX_CLK),
1248 PINMUX_IPSR_MODSEL_DATA(IP8_15_14, VI1_CLK, SEL_VI1_0),
1249 PINMUX_IPSR_DATA(IP8_15_14, AVB_RX_DV),
1250 PINMUX_IPSR_MODSEL_DATA(IP8_17_16, VI1_DATA0_VI1_B0, SEL_VI1_0),
1251 PINMUX_IPSR_MODSEL_DATA(IP8_17_16, SCIFA1_SCK_D, SEL_SCIFA1_3),
1252 PINMUX_IPSR_DATA(IP8_17_16, AVB_CRS),
1253 PINMUX_IPSR_MODSEL_DATA(IP8_19_18, VI1_DATA1_VI1_B1, SEL_VI1_0),
1254 PINMUX_IPSR_MODSEL_DATA(IP8_19_18, SCIFA1_RXD_D, SEL_SCIFA1_3),
1255 PINMUX_IPSR_DATA(IP8_19_18, AVB_MDC),
1256 PINMUX_IPSR_MODSEL_DATA(IP8_21_20, VI1_DATA2_VI1_B2, SEL_VI1_0),
1257 PINMUX_IPSR_MODSEL_DATA(IP8_21_20, SCIFA1_TXD_D, SEL_SCIFA1_3),
1258 PINMUX_IPSR_DATA(IP8_21_20, AVB_MDIO),
1259 PINMUX_IPSR_MODSEL_DATA(IP8_23_22, VI1_DATA3_VI1_B3, SEL_VI1_0),
1260 PINMUX_IPSR_MODSEL_DATA(IP8_23_22, SCIFA1_CTS_N_D, SEL_SCIFA1_3),
1261 PINMUX_IPSR_DATA(IP8_23_22, AVB_GTX_CLK),
1262 PINMUX_IPSR_MODSEL_DATA(IP8_25_24, VI1_DATA4_VI1_B4, SEL_VI1_0),
1263 PINMUX_IPSR_MODSEL_DATA(IP8_25_24, SCIFA1_RTS_N_D, SEL_SCIFA1_3),
1264 PINMUX_IPSR_DATA(IP8_25_24, AVB_MAGIC),
1265 PINMUX_IPSR_MODSEL_DATA(IP8_26, VI1_DATA5_VI1_B5, SEL_VI1_0),
1266 PINMUX_IPSR_DATA(IP8_26, AVB_PHY_INT),
1267 PINMUX_IPSR_MODSEL_DATA(IP8_27, VI1_DATA6_VI1_B6, SEL_VI1_0),
1268 PINMUX_IPSR_DATA(IP8_27, AVB_GTXREFCLK),
1269 PINMUX_IPSR_DATA(IP8_28, SD0_CLK),
1270 PINMUX_IPSR_MODSEL_DATA(IP8_28, VI1_DATA0_VI1_B0_B, SEL_VI1_1),
1271 PINMUX_IPSR_DATA(IP8_30_29, SD0_CMD),
1272 PINMUX_IPSR_MODSEL_DATA(IP8_30_29, SCIFB1_SCK_B, SEL_SCIFB1_1),
1273 PINMUX_IPSR_MODSEL_DATA(IP8_30_29, VI1_DATA1_VI1_B1_B, SEL_VI1_1),
1275 PINMUX_IPSR_DATA(IP9_1_0, SD0_DAT0),
1276 PINMUX_IPSR_MODSEL_DATA(IP9_1_0, SCIFB1_RXD_B, SEL_SCIFB1_1),
1277 PINMUX_IPSR_MODSEL_DATA(IP9_1_0, VI1_DATA2_VI1_B2_B, SEL_VI1_1),
1278 PINMUX_IPSR_DATA(IP9_3_2, SD0_DAT1),
1279 PINMUX_IPSR_MODSEL_DATA(IP9_3_2, SCIFB1_TXD_B, SEL_SCIFB1_1),
1280 PINMUX_IPSR_MODSEL_DATA(IP9_3_2, VI1_DATA3_VI1_B3_B, SEL_VI1_1),
1281 PINMUX_IPSR_DATA(IP9_5_4, SD0_DAT2),
1282 PINMUX_IPSR_MODSEL_DATA(IP9_5_4, SCIFB1_CTS_N_B, SEL_SCIFB1_1),
1283 PINMUX_IPSR_MODSEL_DATA(IP9_5_4, VI1_DATA4_VI1_B4_B, SEL_VI1_1),
1284 PINMUX_IPSR_DATA(IP9_7_6, SD0_DAT3),
1285 PINMUX_IPSR_MODSEL_DATA(IP9_7_6, SCIFB1_RTS_N_B, SEL_SCIFB1_1),
1286 PINMUX_IPSR_MODSEL_DATA(IP9_7_6, VI1_DATA5_VI1_B5_B, SEL_VI1_1),
1287 PINMUX_IPSR_DATA(IP9_11_8, SD0_CD),
1288 PINMUX_IPSR_DATA(IP9_11_8, MMC0_D6),
1289 PINMUX_IPSR_MODSEL_DATA(IP9_11_8, TS_SDEN0_B, SEL_TSIF0_1),
1290 PINMUX_IPSR_DATA(IP9_11_8, USB0_EXTP),
1291 PINMUX_IPSR_MODSEL_DATA(IP9_11_8, GLO_SCLK, SEL_GPS_0),
1292 PINMUX_IPSR_MODSEL_DATA(IP9_11_8, VI1_DATA6_VI1_B6_B, SEL_VI1_1),
1293 PINMUX_IPSR_MODSEL_DATA(IP9_11_8, IIC1_SCL_B, SEL_IIC1_1),
1294 PINMUX_IPSR_MODSEL_DATA(IP9_11_8, I2C1_SCL_B, SEL_I2C1_1),
1295 PINMUX_IPSR_MODSEL_DATA(IP9_11_8, VI2_DATA6_VI2_B6_B, SEL_VI2_1),
1296 PINMUX_IPSR_DATA(IP9_15_12, SD0_WP),
1297 PINMUX_IPSR_DATA(IP9_15_12, MMC0_D7),
1298 PINMUX_IPSR_MODSEL_DATA(IP9_15_12, TS_SPSYNC0_B, SEL_TSIF0_1),
1299 PINMUX_IPSR_DATA(IP9_15_12, USB0_IDIN),
1300 PINMUX_IPSR_MODSEL_DATA(IP9_15_12, GLO_SDATA, SEL_GPS_0),
1301 PINMUX_IPSR_MODSEL_DATA(IP9_15_12, VI1_DATA7_VI1_B7_B, SEL_VI1_1),
1302 PINMUX_IPSR_MODSEL_DATA(IP9_15_12, IIC1_SDA_B, SEL_IIC1_1),
1303 PINMUX_IPSR_MODSEL_DATA(IP9_15_12, I2C1_SDA_B, SEL_I2C1_1),
1304 PINMUX_IPSR_MODSEL_DATA(IP9_15_12, VI2_DATA7_VI2_B7_B, SEL_VI2_1),
1305 PINMUX_IPSR_DATA(IP9_17_16, SD1_CLK),
1306 PINMUX_IPSR_DATA(IP9_17_16, AVB_TX_EN),
1307 PINMUX_IPSR_DATA(IP9_19_18, SD1_CMD),
1308 PINMUX_IPSR_DATA(IP9_19_18, AVB_TX_ER),
1309 PINMUX_IPSR_MODSEL_DATA(IP9_19_18, SCIFB0_SCK_B, SEL_SCIFB_1),
1310 PINMUX_IPSR_DATA(IP9_21_20, SD1_DAT0),
1311 PINMUX_IPSR_DATA(IP9_21_20, AVB_TX_CLK),
1312 PINMUX_IPSR_MODSEL_DATA(IP9_21_20, SCIFB0_RXD_B, SEL_SCIFB_1),
1313 PINMUX_IPSR_DATA(IP9_23_22, SD1_DAT1),
1314 PINMUX_IPSR_DATA(IP9_23_22, AVB_LINK),
1315 PINMUX_IPSR_MODSEL_DATA(IP9_23_22, SCIFB0_TXD_B, SEL_SCIFB_1),
1316 PINMUX_IPSR_DATA(IP9_25_24, SD1_DAT2),
1317 PINMUX_IPSR_DATA(IP9_25_24, AVB_COL),
1318 PINMUX_IPSR_MODSEL_DATA(IP9_25_24, SCIFB0_CTS_N_B, SEL_SCIFB_1),
1319 PINMUX_IPSR_DATA(IP9_27_26, SD1_DAT3),
1320 PINMUX_IPSR_DATA(IP9_27_26, AVB_RXD0),
1321 PINMUX_IPSR_MODSEL_DATA(IP9_27_26, SCIFB0_RTS_N_B, SEL_SCIFB_1),
1322 PINMUX_IPSR_DATA(IP9_31_28, SD1_CD),
1323 PINMUX_IPSR_DATA(IP9_31_28, MMC1_D6),
1324 PINMUX_IPSR_MODSEL_DATA(IP9_31_28, TS_SDEN1, SEL_TSIF1_0),
1325 PINMUX_IPSR_DATA(IP9_31_28, USB1_EXTP),
1326 PINMUX_IPSR_MODSEL_DATA(IP9_31_28, GLO_SS, SEL_GPS_0),
1327 PINMUX_IPSR_MODSEL_DATA(IP9_31_28, VI0_CLK_B, SEL_VI0_1),
1328 PINMUX_IPSR_MODSEL_DATA(IP9_31_28, IIC2_SCL_D, SEL_IIC2_3),
1329 PINMUX_IPSR_MODSEL_DATA(IP9_31_28, I2C2_SCL_D, SEL_I2C2_3),
1330 PINMUX_IPSR_MODSEL_DATA(IP9_31_28, SIM0_CLK_B, SEL_SIM_1),
1331 PINMUX_IPSR_MODSEL_DATA(IP9_31_28, VI3_CLK_B, SEL_VI3_1),
1333 PINMUX_IPSR_DATA(IP10_3_0, SD1_WP),
1334 PINMUX_IPSR_DATA(IP10_3_0, MMC1_D7),
1335 PINMUX_IPSR_MODSEL_DATA(IP10_3_0, TS_SPSYNC1, SEL_TSIF1_0),
1336 PINMUX_IPSR_DATA(IP10_3_0, USB1_IDIN),
1337 PINMUX_IPSR_MODSEL_DATA(IP10_3_0, GLO_RFON, SEL_GPS_0),
1338 PINMUX_IPSR_MODSEL_DATA(IP10_3_0, VI1_CLK_B, SEL_VI1_1),
1339 PINMUX_IPSR_MODSEL_DATA(IP10_3_0, IIC2_SDA_D, SEL_IIC2_3),
1340 PINMUX_IPSR_MODSEL_DATA(IP10_3_0, I2C2_SDA_D, SEL_I2C2_3),
1341 PINMUX_IPSR_MODSEL_DATA(IP10_3_0, SIM0_D_B, SEL_SIM_1),
1342 PINMUX_IPSR_DATA(IP10_6_4, SD2_CLK),
1343 PINMUX_IPSR_DATA(IP10_6_4, MMC0_CLK),
1344 PINMUX_IPSR_MODSEL_DATA(IP10_6_4, SIM0_CLK, SEL_SIM_0),
1345 PINMUX_IPSR_MODSEL_DATA(IP10_6_4, VI0_DATA0_VI0_B0_B, SEL_VI0_1),
1346 PINMUX_IPSR_MODSEL_DATA(IP10_6_4, TS_SDEN0_C, SEL_TSIF0_2),
1347 PINMUX_IPSR_MODSEL_DATA(IP10_6_4, GLO_SCLK_B, SEL_GPS_1),
1348 PINMUX_IPSR_MODSEL_DATA(IP10_6_4, VI3_DATA0_B, SEL_VI3_1),
1349 PINMUX_IPSR_DATA(IP10_10_7, SD2_CMD),
1350 PINMUX_IPSR_DATA(IP10_10_7, MMC0_CMD),
1351 PINMUX_IPSR_MODSEL_DATA(IP10_10_7, SIM0_D, SEL_SIM_0),
1352 PINMUX_IPSR_MODSEL_DATA(IP10_10_7, VI0_DATA1_VI0_B1_B, SEL_VI0_1),
1353 PINMUX_IPSR_MODSEL_DATA(IP10_10_7, SCIFB1_SCK_E, SEL_SCIFB1_4),
1354 PINMUX_IPSR_MODSEL_DATA(IP10_10_7, SCK1_D, SEL_SCIF1_3),
1355 PINMUX_IPSR_MODSEL_DATA(IP10_10_7, TS_SPSYNC0_C, SEL_TSIF0_2),
1356 PINMUX_IPSR_MODSEL_DATA(IP10_10_7, GLO_SDATA_B, SEL_GPS_1),
1357 PINMUX_IPSR_MODSEL_DATA(IP10_10_7, VI3_DATA1_B, SEL_VI3_1),
1358 PINMUX_IPSR_DATA(IP10_14_11, SD2_DAT0),
1359 PINMUX_IPSR_DATA(IP10_14_11, MMC0_D0),
1360 PINMUX_IPSR_MODSEL_DATA(IP10_14_11, FMCLK_B, SEL_FM_1),
1361 PINMUX_IPSR_MODSEL_DATA(IP10_14_11, VI0_DATA2_VI0_B2_B, SEL_VI0_1),
1362 PINMUX_IPSR_MODSEL_DATA(IP10_14_11, SCIFB1_RXD_E, SEL_SCIFB1_4),
1363 PINMUX_IPSR_MODSEL_DATA(IP10_14_11, RX1_D, SEL_SCIF1_3),
1364 PINMUX_IPSR_MODSEL_DATA(IP10_14_11, TS_SDAT0_C, SEL_TSIF0_2),
1365 PINMUX_IPSR_MODSEL_DATA(IP10_14_11, GLO_SS_B, SEL_GPS_1),
1366 PINMUX_IPSR_MODSEL_DATA(IP10_14_11, VI3_DATA2_B, SEL_VI3_1),
1367 PINMUX_IPSR_DATA(IP10_18_15, SD2_DAT1),
1368 PINMUX_IPSR_DATA(IP10_18_15, MMC0_D1),
1369 PINMUX_IPSR_MODSEL_DATA(IP10_18_15, FMIN_B, SEL_FM_1),
1370 PINMUX_IPSR_MODSEL_DATA(IP10_18_15, VI0_DATA3_VI0_B3_B, SEL_VI0_1),
1371 PINMUX_IPSR_MODSEL_DATA(IP10_18_15, SCIFB1_TXD_E, SEL_SCIFB1_4),
1372 PINMUX_IPSR_MODSEL_DATA(IP10_18_15, TX1_D, SEL_SCIF1_3),
1373 PINMUX_IPSR_MODSEL_DATA(IP10_18_15, TS_SCK0_C, SEL_TSIF0_2),
1374 PINMUX_IPSR_MODSEL_DATA(IP10_18_15, GLO_RFON_B, SEL_GPS_1),
1375 PINMUX_IPSR_MODSEL_DATA(IP10_18_15, VI3_DATA3_B, SEL_VI3_1),
1376 PINMUX_IPSR_DATA(IP10_22_19, SD2_DAT2),
1377 PINMUX_IPSR_DATA(IP10_22_19, MMC0_D2),
1378 PINMUX_IPSR_MODSEL_DATA(IP10_22_19, BPFCLK_B, SEL_FM_1),
1379 PINMUX_IPSR_MODSEL_DATA(IP10_22_19, VI0_DATA4_VI0_B4_B, SEL_VI0_1),
1380 PINMUX_IPSR_MODSEL_DATA(IP10_22_19, HRX0_D, SEL_HSCIF0_3),
1381 PINMUX_IPSR_MODSEL_DATA(IP10_22_19, TS_SDEN1_B, SEL_TSIF1_1),
1382 PINMUX_IPSR_MODSEL_DATA(IP10_22_19, GLO_Q0_B, SEL_GPS_1),
1383 PINMUX_IPSR_MODSEL_DATA(IP10_22_19, VI3_DATA4_B, SEL_VI3_1),
1384 PINMUX_IPSR_DATA(IP10_25_23, SD2_DAT3),
1385 PINMUX_IPSR_DATA(IP10_25_23, MMC0_D3),
1386 PINMUX_IPSR_MODSEL_DATA(IP10_25_23, SIM0_RST, SEL_SIM_0),
1387 PINMUX_IPSR_MODSEL_DATA(IP10_25_23, VI0_DATA5_VI0_B5_B, SEL_VI0_1),
1388 PINMUX_IPSR_MODSEL_DATA(IP10_25_23, HTX0_D, SEL_HSCIF0_3),
1389 PINMUX_IPSR_MODSEL_DATA(IP10_25_23, TS_SPSYNC1_B, SEL_TSIF1_1),
1390 PINMUX_IPSR_MODSEL_DATA(IP10_25_23, GLO_Q1_B, SEL_GPS_1),
1391 PINMUX_IPSR_MODSEL_DATA(IP10_25_23, VI3_DATA5_B, SEL_VI3_1),
1392 PINMUX_IPSR_DATA(IP10_29_26, SD2_CD),
1393 PINMUX_IPSR_DATA(IP10_29_26, MMC0_D4),
1394 PINMUX_IPSR_MODSEL_DATA(IP10_29_26, TS_SDAT0_B, SEL_TSIF0_1),
1395 PINMUX_IPSR_DATA(IP10_29_26, USB2_EXTP),
1396 PINMUX_IPSR_MODSEL_DATA(IP10_29_26, GLO_I0, SEL_GPS_0),
1397 PINMUX_IPSR_MODSEL_DATA(IP10_29_26, VI0_DATA6_VI0_B6_B, SEL_VI0_1),
1398 PINMUX_IPSR_MODSEL_DATA(IP10_29_26, HCTS0_N_D, SEL_HSCIF0_3),
1399 PINMUX_IPSR_MODSEL_DATA(IP10_29_26, TS_SDAT1_B, SEL_TSIF1_1),
1400 PINMUX_IPSR_MODSEL_DATA(IP10_29_26, GLO_I0_B, SEL_GPS_1),
1401 PINMUX_IPSR_MODSEL_DATA(IP10_29_26, VI3_DATA6_B, SEL_VI3_1),
1403 PINMUX_IPSR_DATA(IP11_3_0, SD2_WP),
1404 PINMUX_IPSR_DATA(IP11_3_0, MMC0_D5),
1405 PINMUX_IPSR_MODSEL_DATA(IP11_3_0, TS_SCK0_B, SEL_TSIF0_1),
1406 PINMUX_IPSR_DATA(IP11_3_0, USB2_IDIN),
1407 PINMUX_IPSR_MODSEL_DATA(IP11_3_0, GLO_I1, SEL_GPS_0),
1408 PINMUX_IPSR_MODSEL_DATA(IP11_3_0, VI0_DATA7_VI0_B7_B, SEL_VI0_1),
1409 PINMUX_IPSR_MODSEL_DATA(IP11_3_0, HRTS0_N_D, SEL_HSCIF0_3),
1410 PINMUX_IPSR_MODSEL_DATA(IP11_3_0, TS_SCK1_B, SEL_TSIF1_1),
1411 PINMUX_IPSR_MODSEL_DATA(IP11_3_0, GLO_I1_B, SEL_GPS_1),
1412 PINMUX_IPSR_MODSEL_DATA(IP11_3_0, VI3_DATA7_B, SEL_VI3_1),
1413 PINMUX_IPSR_DATA(IP11_4, SD3_CLK),
1414 PINMUX_IPSR_DATA(IP11_4, MMC1_CLK),
1415 PINMUX_IPSR_DATA(IP11_6_5, SD3_CMD),
1416 PINMUX_IPSR_DATA(IP11_6_5, MMC1_CMD),
1417 PINMUX_IPSR_DATA(IP11_6_5, MTS_N),
1418 PINMUX_IPSR_DATA(IP11_8_7, SD3_DAT0),
1419 PINMUX_IPSR_DATA(IP11_8_7, MMC1_D0),
1420 PINMUX_IPSR_DATA(IP11_8_7, STM_N),
1421 PINMUX_IPSR_DATA(IP11_10_9, SD3_DAT1),
1422 PINMUX_IPSR_DATA(IP11_10_9, MMC1_D1),
1423 PINMUX_IPSR_DATA(IP11_10_9, MDATA),
1424 PINMUX_IPSR_DATA(IP11_12_11, SD3_DAT2),
1425 PINMUX_IPSR_DATA(IP11_12_11, MMC1_D2),
1426 PINMUX_IPSR_DATA(IP11_12_11, SDATA),
1427 PINMUX_IPSR_DATA(IP11_14_13, SD3_DAT3),
1428 PINMUX_IPSR_DATA(IP11_14_13, MMC1_D3),
1429 PINMUX_IPSR_DATA(IP11_14_13, SCKZ),
1430 PINMUX_IPSR_DATA(IP11_17_15, SD3_CD),
1431 PINMUX_IPSR_DATA(IP11_17_15, MMC1_D4),
1432 PINMUX_IPSR_MODSEL_DATA(IP11_17_15, TS_SDAT1, SEL_TSIF1_0),
1433 PINMUX_IPSR_DATA(IP11_17_15, VSP),
1434 PINMUX_IPSR_MODSEL_DATA(IP11_17_15, GLO_Q0, SEL_GPS_0),
1435 PINMUX_IPSR_MODSEL_DATA(IP11_17_15, SIM0_RST_B, SEL_SIM_1),
1436 PINMUX_IPSR_DATA(IP11_21_18, SD3_WP),
1437 PINMUX_IPSR_DATA(IP11_21_18, MMC1_D5),
1438 PINMUX_IPSR_MODSEL_DATA(IP11_21_18, TS_SCK1, SEL_TSIF1_0),
1439 PINMUX_IPSR_MODSEL_DATA(IP11_21_18, GLO_Q1, SEL_GPS_0),
1440 PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_C, SEL_FM_2),
1441 PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_E, SEL_FM_4),
1442 PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_F, SEL_FM_5),
1443 PINMUX_IPSR_DATA(IP11_23_22, MLB_CLK),
1444 PINMUX_IPSR_MODSEL_DATA(IP11_23_22, IIC2_SCL_B, SEL_IIC2_1),
1445 PINMUX_IPSR_MODSEL_DATA(IP11_23_22, I2C2_SCL_B, SEL_I2C2_1),
1446 PINMUX_IPSR_DATA(IP11_26_24, MLB_SIG),
1447 PINMUX_IPSR_MODSEL_DATA(IP11_26_24, SCIFB1_RXD_D, SEL_SCIFB1_3),
1448 PINMUX_IPSR_MODSEL_DATA(IP11_26_24, RX1_C, SEL_SCIF1_2),
1449 PINMUX_IPSR_MODSEL_DATA(IP11_26_24, IIC2_SDA_B, SEL_IIC2_1),
1450 PINMUX_IPSR_MODSEL_DATA(IP11_26_24, I2C2_SDA_B, SEL_I2C2_1),
1451 PINMUX_IPSR_DATA(IP11_29_27, MLB_DAT),
1452 PINMUX_IPSR_MODSEL_DATA(IP11_29_27, SCIFB1_TXD_D, SEL_SCIFB1_3),
1453 PINMUX_IPSR_MODSEL_DATA(IP11_29_27, TX1_C, SEL_SCIF1_2),
1454 PINMUX_IPSR_MODSEL_DATA(IP11_29_27, BPFCLK_C, SEL_FM_2),
1455 PINMUX_IPSR_DATA(IP11_31_30, SSI_SCK0129),
1456 PINMUX_IPSR_MODSEL_DATA(IP11_31_30, CAN_CLK_B, SEL_CANCLK_1),
1457 PINMUX_IPSR_DATA(IP11_31_30, MOUT0),
1459 PINMUX_IPSR_DATA(IP12_1_0, SSI_WS0129),
1460 PINMUX_IPSR_MODSEL_DATA(IP12_1_0, CAN0_TX_B, SEL_CAN0_1),
1461 PINMUX_IPSR_DATA(IP12_1_0, MOUT1),
1462 PINMUX_IPSR_DATA(IP12_3_2, SSI_SDATA0),
1463 PINMUX_IPSR_MODSEL_DATA(IP12_3_2, CAN0_RX_B, SEL_CAN0_1),
1464 PINMUX_IPSR_DATA(IP12_3_2, MOUT2),
1465 PINMUX_IPSR_DATA(IP12_5_4, SSI_SDATA1),
1466 PINMUX_IPSR_MODSEL_DATA(IP12_5_4, CAN1_TX_B, SEL_CAN1_1),
1467 PINMUX_IPSR_DATA(IP12_5_4, MOUT5),
1468 PINMUX_IPSR_DATA(IP12_7_6, SSI_SDATA2),
1469 PINMUX_IPSR_MODSEL_DATA(IP12_7_6, CAN1_RX_B, SEL_CAN1_1),
1470 PINMUX_IPSR_DATA(IP12_7_6, SSI_SCK1),
1471 PINMUX_IPSR_DATA(IP12_7_6, MOUT6),
1472 PINMUX_IPSR_DATA(IP12_10_8, SSI_SCK34),
1473 PINMUX_IPSR_DATA(IP12_10_8, STP_OPWM_0),
1474 PINMUX_IPSR_MODSEL_DATA(IP12_10_8, SCIFB0_SCK, SEL_SCIFB_0),
1475 PINMUX_IPSR_MODSEL_DATA(IP12_10_8, MSIOF1_SCK, SEL_SOF1_0),
1476 PINMUX_IPSR_DATA(IP12_10_8, CAN_DEBUG_HW_TRIGGER),
1477 PINMUX_IPSR_DATA(IP12_13_11, SSI_WS34),
1478 PINMUX_IPSR_MODSEL_DATA(IP12_13_11, STP_IVCXO27_0, SEL_SSP_0),
1479 PINMUX_IPSR_MODSEL_DATA(IP12_13_11, SCIFB0_RXD, SEL_SCIFB_0),
1480 PINMUX_IPSR_DATA(IP12_13_11, MSIOF1_SYNC),
1481 PINMUX_IPSR_DATA(IP12_13_11, CAN_STEP0),
1482 PINMUX_IPSR_DATA(IP12_16_14, SSI_SDATA3),
1483 PINMUX_IPSR_MODSEL_DATA(IP12_16_14, STP_ISCLK_0, SEL_SSP_0),
1484 PINMUX_IPSR_MODSEL_DATA(IP12_16_14, SCIFB0_TXD, SEL_SCIFB_0),
1485 PINMUX_IPSR_MODSEL_DATA(IP12_16_14, MSIOF1_SS1, SEL_SOF1_0),
1486 PINMUX_IPSR_DATA(IP12_16_14, CAN_TXCLK),
1487 PINMUX_IPSR_DATA(IP12_19_17, SSI_SCK4),
1488 PINMUX_IPSR_MODSEL_DATA(IP12_19_17, STP_ISD_0, SEL_SSP_0),
1489 PINMUX_IPSR_MODSEL_DATA(IP12_19_17, SCIFB0_CTS_N, SEL_SCIFB_0),
1490 PINMUX_IPSR_MODSEL_DATA(IP12_19_17, MSIOF1_SS2, SEL_SOF1_0),
1491 PINMUX_IPSR_MODSEL_DATA(IP12_19_17, SSI_SCK5_C, SEL_SSI5_2),
1492 PINMUX_IPSR_DATA(IP12_19_17, CAN_DEBUGOUT0),
1493 PINMUX_IPSR_DATA(IP12_22_20, SSI_WS4),
1494 PINMUX_IPSR_MODSEL_DATA(IP12_22_20, STP_ISEN_0, SEL_SSP_0),
1495 PINMUX_IPSR_MODSEL_DATA(IP12_22_20, SCIFB0_RTS_N, SEL_SCIFB_0),
1496 PINMUX_IPSR_MODSEL_DATA(IP12_22_20, MSIOF1_TXD, SEL_SOF1_0),
1497 PINMUX_IPSR_MODSEL_DATA(IP12_22_20, SSI_WS5_C, SEL_SSI5_2),
1498 PINMUX_IPSR_DATA(IP12_22_20, CAN_DEBUGOUT1),
1499 PINMUX_IPSR_DATA(IP12_24_23, SSI_SDATA4),
1500 PINMUX_IPSR_MODSEL_DATA(IP12_24_23, STP_ISSYNC_0, SEL_SSP_0),
1501 PINMUX_IPSR_MODSEL_DATA(IP12_24_23, MSIOF1_RXD, SEL_SOF1_0),
1502 PINMUX_IPSR_DATA(IP12_24_23, CAN_DEBUGOUT2),
1503 PINMUX_IPSR_MODSEL_DATA(IP12_27_25, SSI_SCK5, SEL_SSI5_0),
1504 PINMUX_IPSR_MODSEL_DATA(IP12_27_25, SCIFB1_SCK, SEL_SCIFB1_0),
1505 PINMUX_IPSR_MODSEL_DATA(IP12_27_25, IERX_B, SEL_IEB_1),
1506 PINMUX_IPSR_DATA(IP12_27_25, DU2_EXHSYNC_DU2_HSYNC),
1507 PINMUX_IPSR_DATA(IP12_27_25, QSTH_QHS),
1508 PINMUX_IPSR_DATA(IP12_27_25, CAN_DEBUGOUT3),
1509 PINMUX_IPSR_MODSEL_DATA(IP12_30_28, SSI_WS5, SEL_SSI5_0),
1510 PINMUX_IPSR_MODSEL_DATA(IP12_30_28, SCIFB1_RXD, SEL_SCIFB1_0),
1511 PINMUX_IPSR_MODSEL_DATA(IP12_30_28, IECLK_B, SEL_IEB_1),
1512 PINMUX_IPSR_DATA(IP12_30_28, DU2_EXVSYNC_DU2_VSYNC),
1513 PINMUX_IPSR_DATA(IP12_30_28, QSTB_QHE),
1514 PINMUX_IPSR_DATA(IP12_30_28, CAN_DEBUGOUT4),
1516 PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SSI_SDATA5, SEL_SSI5_0),
1517 PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SCIFB1_TXD, SEL_SCIFB1_0),
1518 PINMUX_IPSR_MODSEL_DATA(IP13_2_0, IETX_B, SEL_IEB_1),
1519 PINMUX_IPSR_DATA(IP13_2_0, DU2_DR2),
1520 PINMUX_IPSR_DATA(IP13_2_0, LCDOUT2),
1521 PINMUX_IPSR_DATA(IP13_2_0, CAN_DEBUGOUT5),
1522 PINMUX_IPSR_MODSEL_DATA(IP13_6_3, SSI_SCK6, SEL_SSI6_0),
1523 PINMUX_IPSR_MODSEL_DATA(IP13_6_3, SCIFB1_CTS_N, SEL_SCIFB1_0),
1524 PINMUX_IPSR_MODSEL_DATA(IP13_6_3, BPFCLK_D, SEL_FM_3),
1525 PINMUX_IPSR_DATA(IP13_6_3, DU2_DR3),
1526 PINMUX_IPSR_DATA(IP13_6_3, LCDOUT3),
1527 PINMUX_IPSR_DATA(IP13_6_3, CAN_DEBUGOUT6),
1528 PINMUX_IPSR_MODSEL_DATA(IP13_6_3, BPFCLK_F, SEL_FM_5),
1529 PINMUX_IPSR_MODSEL_DATA(IP13_9_7, SSI_WS6, SEL_SSI6_0),
1530 PINMUX_IPSR_MODSEL_DATA(IP13_9_7, SCIFB1_RTS_N, SEL_SCIFB1_0),
1531 PINMUX_IPSR_MODSEL_DATA(IP13_9_7, CAN0_TX_D, SEL_CAN0_3),
1532 PINMUX_IPSR_DATA(IP13_9_7, DU2_DR4),
1533 PINMUX_IPSR_DATA(IP13_9_7, LCDOUT4),
1534 PINMUX_IPSR_DATA(IP13_9_7, CAN_DEBUGOUT7),
1535 PINMUX_IPSR_MODSEL_DATA(IP13_12_10, SSI_SDATA6, SEL_SSI6_0),
1536 PINMUX_IPSR_MODSEL_DATA(IP13_12_10, FMIN_D, SEL_FM_3),
1537 PINMUX_IPSR_DATA(IP13_12_10, DU2_DR5),
1538 PINMUX_IPSR_DATA(IP13_12_10, LCDOUT5),
1539 PINMUX_IPSR_DATA(IP13_12_10, CAN_DEBUGOUT8),
1540 PINMUX_IPSR_MODSEL_DATA(IP13_15_13, SSI_SCK78, SEL_SSI7_0),
1541 PINMUX_IPSR_MODSEL_DATA(IP13_15_13, STP_IVCXO27_1, SEL_SSP_0),
1542 PINMUX_IPSR_MODSEL_DATA(IP13_15_13, SCK1, SEL_SCIF1_0),
1543 PINMUX_IPSR_MODSEL_DATA(IP13_15_13, SCIFA1_SCK, SEL_SCIFA1_0),
1544 PINMUX_IPSR_DATA(IP13_15_13, DU2_DR6),
1545 PINMUX_IPSR_DATA(IP13_15_13, LCDOUT6),
1546 PINMUX_IPSR_DATA(IP13_15_13, CAN_DEBUGOUT9),
1547 PINMUX_IPSR_MODSEL_DATA(IP13_18_16, SSI_WS78, SEL_SSI7_0),
1548 PINMUX_IPSR_MODSEL_DATA(IP13_18_16, STP_ISCLK_1, SEL_SSP_0),
1549 PINMUX_IPSR_MODSEL_DATA(IP13_18_16, SCIFB2_SCK, SEL_SCIFB2_0),
1550 PINMUX_IPSR_DATA(IP13_18_16, SCIFA2_CTS_N),
1551 PINMUX_IPSR_DATA(IP13_18_16, DU2_DR7),
1552 PINMUX_IPSR_DATA(IP13_18_16, LCDOUT7),
1553 PINMUX_IPSR_DATA(IP13_18_16, CAN_DEBUGOUT10),
1554 PINMUX_IPSR_MODSEL_DATA(IP13_22_19, SSI_SDATA7, SEL_SSI7_0),
1555 PINMUX_IPSR_MODSEL_DATA(IP13_22_19, STP_ISD_1, SEL_SSP_0),
1556 PINMUX_IPSR_MODSEL_DATA(IP13_22_19, SCIFB2_RXD, SEL_SCIFB2_0),
1557 PINMUX_IPSR_DATA(IP13_22_19, SCIFA2_RTS_N),
1558 PINMUX_IPSR_DATA(IP13_22_19, TCLK2),
1559 PINMUX_IPSR_DATA(IP13_22_19, QSTVA_QVS),
1560 PINMUX_IPSR_DATA(IP13_22_19, CAN_DEBUGOUT11),
1561 PINMUX_IPSR_MODSEL_DATA(IP13_22_19, BPFCLK_E, SEL_FM_4),
1562 PINMUX_IPSR_MODSEL_DATA(IP13_22_19, SSI_SDATA7_B, SEL_SSI7_1),
1563 PINMUX_IPSR_MODSEL_DATA(IP13_22_19, FMIN_G, SEL_FM_6),
1564 PINMUX_IPSR_MODSEL_DATA(IP13_25_23, SSI_SDATA8, SEL_SSI8_0),
1565 PINMUX_IPSR_MODSEL_DATA(IP13_25_23, STP_ISEN_1, SEL_SSP_0),
1566 PINMUX_IPSR_MODSEL_DATA(IP13_25_23, SCIFB2_TXD, SEL_SCIFB2_0),
1567 PINMUX_IPSR_MODSEL_DATA(IP13_25_23, CAN0_TX_C, SEL_CAN0_2),
1568 PINMUX_IPSR_DATA(IP13_25_23, CAN_DEBUGOUT12),
1569 PINMUX_IPSR_MODSEL_DATA(IP13_25_23, SSI_SDATA8_B, SEL_SSI8_1),
1570 PINMUX_IPSR_DATA(IP13_28_26, SSI_SDATA9),
1571 PINMUX_IPSR_MODSEL_DATA(IP13_28_26, STP_ISSYNC_1, SEL_SSP_0),
1572 PINMUX_IPSR_MODSEL_DATA(IP13_28_26, SCIFB2_CTS_N, SEL_SCIFB2_0),
1573 PINMUX_IPSR_DATA(IP13_28_26, SSI_WS1),
1574 PINMUX_IPSR_MODSEL_DATA(IP13_28_26, SSI_SDATA5_C, SEL_SSI5_2),
1575 PINMUX_IPSR_DATA(IP13_28_26, CAN_DEBUGOUT13),
1576 PINMUX_IPSR_DATA(IP13_30_29, AUDIO_CLKA),
1577 PINMUX_IPSR_MODSEL_DATA(IP13_30_29, SCIFB2_RTS_N, SEL_SCIFB2_0),
1578 PINMUX_IPSR_DATA(IP13_30_29, CAN_DEBUGOUT14),
1580 PINMUX_IPSR_DATA(IP14_2_0, AUDIO_CLKB),
1581 PINMUX_IPSR_MODSEL_DATA(IP14_2_0, SCIF_CLK, SEL_SCIFCLK_0),
1582 PINMUX_IPSR_MODSEL_DATA(IP14_2_0, CAN0_RX_D, SEL_CAN0_3),
1583 PINMUX_IPSR_DATA(IP14_2_0, DVC_MUTE),
1584 PINMUX_IPSR_MODSEL_DATA(IP14_2_0, CAN0_RX_C, SEL_CAN0_2),
1585 PINMUX_IPSR_DATA(IP14_2_0, CAN_DEBUGOUT15),
1586 PINMUX_IPSR_DATA(IP14_2_0, REMOCON),
1587 PINMUX_IPSR_MODSEL_DATA(IP14_5_3, SCIFA0_SCK, SEL_SCFA_0),
1588 PINMUX_IPSR_MODSEL_DATA(IP14_5_3, HSCK1, SEL_HSCIF1_0),
1589 PINMUX_IPSR_DATA(IP14_5_3, SCK0),
1590 PINMUX_IPSR_DATA(IP14_5_3, MSIOF3_SS2),
1591 PINMUX_IPSR_DATA(IP14_5_3, DU2_DG2),
1592 PINMUX_IPSR_DATA(IP14_5_3, LCDOUT10),
1593 PINMUX_IPSR_MODSEL_DATA(IP14_5_3, IIC1_SDA_C, SEL_IIC1_2),
1594 PINMUX_IPSR_MODSEL_DATA(IP14_5_3, I2C1_SDA_C, SEL_I2C1_2),
1595 PINMUX_IPSR_MODSEL_DATA(IP14_8_6, SCIFA0_RXD, SEL_SCFA_0),
1596 PINMUX_IPSR_MODSEL_DATA(IP14_8_6, HRX1, SEL_HSCIF1_0),
1597 PINMUX_IPSR_MODSEL_DATA(IP14_8_6, RX0, SEL_SCIF0_0),
1598 PINMUX_IPSR_DATA(IP14_8_6, DU2_DR0),
1599 PINMUX_IPSR_DATA(IP14_8_6, LCDOUT0),
1600 PINMUX_IPSR_MODSEL_DATA(IP14_11_9, SCIFA0_TXD, SEL_SCFA_0),
1601 PINMUX_IPSR_MODSEL_DATA(IP14_11_9, HTX1, SEL_HSCIF1_0),
1602 PINMUX_IPSR_MODSEL_DATA(IP14_11_9, TX0, SEL_SCIF0_0),
1603 PINMUX_IPSR_DATA(IP14_11_9, DU2_DR1),
1604 PINMUX_IPSR_DATA(IP14_11_9, LCDOUT1),
1605 PINMUX_IPSR_MODSEL_DATA(IP14_15_12, SCIFA0_CTS_N, SEL_SCFA_0),
1606 PINMUX_IPSR_MODSEL_DATA(IP14_15_12, HCTS1_N, SEL_HSCIF1_0),
1607 PINMUX_IPSR_DATA(IP14_15_12, CTS0_N),
1608 PINMUX_IPSR_MODSEL_DATA(IP14_15_12, MSIOF3_SYNC, SEL_SOF3_0),
1609 PINMUX_IPSR_DATA(IP14_15_12, DU2_DG3),
1610 PINMUX_IPSR_DATA(IP14_15_12, LCDOUT11),
1611 PINMUX_IPSR_DATA(IP14_15_12, PWM0_B),
1612 PINMUX_IPSR_MODSEL_DATA(IP14_15_12, IIC1_SCL_C, SEL_IIC1_2),
1613 PINMUX_IPSR_MODSEL_DATA(IP14_15_12, I2C1_SCL_C, SEL_I2C1_2),
1614 PINMUX_IPSR_MODSEL_DATA(IP14_18_16, SCIFA0_RTS_N, SEL_SCFA_0),
1615 PINMUX_IPSR_MODSEL_DATA(IP14_18_16, HRTS1_N, SEL_HSCIF1_0),
1616 PINMUX_IPSR_DATA(IP14_18_16, RTS0_N),
1617 PINMUX_IPSR_DATA(IP14_18_16, MSIOF3_SS1),
1618 PINMUX_IPSR_DATA(IP14_18_16, DU2_DG0),
1619 PINMUX_IPSR_DATA(IP14_18_16, LCDOUT8),
1620 PINMUX_IPSR_DATA(IP14_18_16, PWM1_B),
1621 PINMUX_IPSR_MODSEL_DATA(IP14_21_19, SCIFA1_RXD, SEL_SCIFA1_0),
1622 PINMUX_IPSR_MODSEL_DATA(IP14_21_19, AD_DI, SEL_ADI_0),
1623 PINMUX_IPSR_MODSEL_DATA(IP14_21_19, RX1, SEL_SCIF1_0),
1624 PINMUX_IPSR_DATA(IP14_21_19, DU2_EXODDF_DU2_ODDF_DISP_CDE),
1625 PINMUX_IPSR_DATA(IP14_21_19, QCPV_QDE),
1626 PINMUX_IPSR_MODSEL_DATA(IP14_24_22, SCIFA1_TXD, SEL_SCIFA1_0),
1627 PINMUX_IPSR_MODSEL_DATA(IP14_24_22, AD_DO, SEL_ADI_0),
1628 PINMUX_IPSR_MODSEL_DATA(IP14_24_22, TX1, SEL_SCIF1_0),
1629 PINMUX_IPSR_DATA(IP14_24_22, DU2_DG1),
1630 PINMUX_IPSR_DATA(IP14_24_22, LCDOUT9),
1631 PINMUX_IPSR_MODSEL_DATA(IP14_27_25, SCIFA1_CTS_N, SEL_SCIFA1_0),
1632 PINMUX_IPSR_MODSEL_DATA(IP14_27_25, AD_CLK, SEL_ADI_0),
1633 PINMUX_IPSR_DATA(IP14_27_25, CTS1_N),
1634 PINMUX_IPSR_MODSEL_DATA(IP14_27_25, MSIOF3_RXD, SEL_SOF3_0),
1635 PINMUX_IPSR_DATA(IP14_27_25, DU0_DOTCLKOUT),
1636 PINMUX_IPSR_DATA(IP14_27_25, QCLK),
1637 PINMUX_IPSR_MODSEL_DATA(IP14_30_28, SCIFA1_RTS_N, SEL_SCIFA1_0),
1638 PINMUX_IPSR_MODSEL_DATA(IP14_30_28, AD_NCS_N, SEL_ADI_0),
1639 PINMUX_IPSR_DATA(IP14_30_28, RTS1_N),
1640 PINMUX_IPSR_MODSEL_DATA(IP14_30_28, MSIOF3_TXD, SEL_SOF3_0),
1641 PINMUX_IPSR_DATA(IP14_30_28, DU1_DOTCLKOUT),
1642 PINMUX_IPSR_DATA(IP14_30_28, QSTVB_QVE),
1643 PINMUX_IPSR_MODSEL_DATA(IP14_30_28, HRTS0_N_C, SEL_HSCIF0_2),
1645 PINMUX_IPSR_MODSEL_DATA(IP15_2_0, SCIFA2_SCK, SEL_SCIFA2_0),
1646 PINMUX_IPSR_MODSEL_DATA(IP15_2_0, FMCLK, SEL_FM_0),
1647 PINMUX_IPSR_DATA(IP15_2_0, SCK2),
1648 PINMUX_IPSR_MODSEL_DATA(IP15_2_0, MSIOF3_SCK, SEL_SOF3_0),
1649 PINMUX_IPSR_DATA(IP15_2_0, DU2_DG7),
1650 PINMUX_IPSR_DATA(IP15_2_0, LCDOUT15),
1651 PINMUX_IPSR_MODSEL_DATA(IP15_2_0, SCIF_CLK_B, SEL_SCIFCLK_1),
1652 PINMUX_IPSR_MODSEL_DATA(IP15_5_3, SCIFA2_RXD, SEL_SCIFA2_0),
1653 PINMUX_IPSR_MODSEL_DATA(IP15_5_3, FMIN, SEL_FM_0),
1654 PINMUX_IPSR_MODSEL_DATA(IP15_5_3, TX2, SEL_SCIF2_0),
1655 PINMUX_IPSR_DATA(IP15_5_3, DU2_DB0),
1656 PINMUX_IPSR_DATA(IP15_5_3, LCDOUT16),
1657 PINMUX_IPSR_MODSEL_DATA(IP15_5_3, IIC2_SCL, SEL_IIC2_0),
1658 PINMUX_IPSR_MODSEL_DATA(IP15_5_3, I2C2_SCL, SEL_I2C2_0),
1659 PINMUX_IPSR_MODSEL_DATA(IP15_8_6, SCIFA2_TXD, SEL_SCIFA2_0),
1660 PINMUX_IPSR_MODSEL_DATA(IP15_8_6, BPFCLK, SEL_FM_0),
1661 PINMUX_IPSR_MODSEL_DATA(IP15_8_6, RX2, SEL_SCIF2_0),
1662 PINMUX_IPSR_DATA(IP15_8_6, DU2_DB1),
1663 PINMUX_IPSR_DATA(IP15_8_6, LCDOUT17),
1664 PINMUX_IPSR_MODSEL_DATA(IP15_8_6, IIC2_SDA, SEL_IIC2_0),
1665 PINMUX_IPSR_MODSEL_DATA(IP15_8_6, I2C2_SDA, SEL_I2C2_0),
1666 PINMUX_IPSR_DATA(IP15_11_9, HSCK0),
1667 PINMUX_IPSR_MODSEL_DATA(IP15_11_9, TS_SDEN0, SEL_TSIF0_0),
1668 PINMUX_IPSR_DATA(IP15_11_9, DU2_DG4),
1669 PINMUX_IPSR_DATA(IP15_11_9, LCDOUT12),
1670 PINMUX_IPSR_MODSEL_DATA(IP15_11_9, HCTS0_N_C, SEL_HSCIF0_2),
1671 PINMUX_IPSR_MODSEL_DATA(IP15_13_12, HRX0, SEL_HSCIF0_0),
1672 PINMUX_IPSR_DATA(IP15_13_12, DU2_DB2),
1673 PINMUX_IPSR_DATA(IP15_13_12, LCDOUT18),
1674 PINMUX_IPSR_MODSEL_DATA(IP15_15_14, HTX0, SEL_HSCIF0_0),
1675 PINMUX_IPSR_DATA(IP15_15_14, DU2_DB3),
1676 PINMUX_IPSR_DATA(IP15_15_14, LCDOUT19),
1677 PINMUX_IPSR_MODSEL_DATA(IP15_17_16, HCTS0_N, SEL_HSCIF0_0),
1678 PINMUX_IPSR_DATA(IP15_17_16, SSI_SCK9),
1679 PINMUX_IPSR_DATA(IP15_17_16, DU2_DB4),
1680 PINMUX_IPSR_DATA(IP15_17_16, LCDOUT20),
1681 PINMUX_IPSR_MODSEL_DATA(IP15_19_18, HRTS0_N, SEL_HSCIF0_0),
1682 PINMUX_IPSR_DATA(IP15_19_18, SSI_WS9),
1683 PINMUX_IPSR_DATA(IP15_19_18, DU2_DB5),
1684 PINMUX_IPSR_DATA(IP15_19_18, LCDOUT21),
1685 PINMUX_IPSR_MODSEL_DATA(IP15_22_20, MSIOF0_SCK, SEL_SOF0_0),
1686 PINMUX_IPSR_MODSEL_DATA(IP15_22_20, TS_SDAT0, SEL_TSIF0_0),
1687 PINMUX_IPSR_DATA(IP15_22_20, ADICLK),
1688 PINMUX_IPSR_DATA(IP15_22_20, DU2_DB6),
1689 PINMUX_IPSR_DATA(IP15_22_20, LCDOUT22),
1690 PINMUX_IPSR_DATA(IP15_25_23, MSIOF0_SYNC),
1691 PINMUX_IPSR_MODSEL_DATA(IP15_25_23, TS_SCK0, SEL_TSIF0_0),
1692 PINMUX_IPSR_DATA(IP15_25_23, SSI_SCK2),
1693 PINMUX_IPSR_DATA(IP15_25_23, ADIDATA),
1694 PINMUX_IPSR_DATA(IP15_25_23, DU2_DB7),
1695 PINMUX_IPSR_DATA(IP15_25_23, LCDOUT23),
1696 PINMUX_IPSR_MODSEL_DATA(IP15_25_23, HRX0_C, SEL_SCIFA2_1),
1697 PINMUX_IPSR_MODSEL_DATA(IP15_27_26, MSIOF0_SS1, SEL_SOF0_0),
1698 PINMUX_IPSR_DATA(IP15_27_26, ADICHS0),
1699 PINMUX_IPSR_DATA(IP15_27_26, DU2_DG5),
1700 PINMUX_IPSR_DATA(IP15_27_26, LCDOUT13),
1701 PINMUX_IPSR_MODSEL_DATA(IP15_29_28, MSIOF0_TXD, SEL_SOF0_0),
1702 PINMUX_IPSR_DATA(IP15_29_28, ADICHS1),
1703 PINMUX_IPSR_DATA(IP15_29_28, DU2_DG6),
1704 PINMUX_IPSR_DATA(IP15_29_28, LCDOUT14),
1706 PINMUX_IPSR_MODSEL_DATA(IP16_2_0, MSIOF0_SS2, SEL_SOF0_0),
1707 PINMUX_IPSR_DATA(IP16_2_0, AUDIO_CLKOUT),
1708 PINMUX_IPSR_DATA(IP16_2_0, ADICHS2),
1709 PINMUX_IPSR_DATA(IP16_2_0, DU2_DISP),
1710 PINMUX_IPSR_DATA(IP16_2_0, QPOLA),
1711 PINMUX_IPSR_MODSEL_DATA(IP16_2_0, HTX0_C, SEL_HSCIF0_2),
1712 PINMUX_IPSR_MODSEL_DATA(IP16_2_0, SCIFA2_TXD_B, SEL_SCIFA2_1),
1713 PINMUX_IPSR_MODSEL_DATA(IP16_5_3, MSIOF0_RXD, SEL_SOF0_0),
1714 PINMUX_IPSR_MODSEL_DATA(IP16_5_3, TS_SPSYNC0, SEL_TSIF0_0),
1715 PINMUX_IPSR_DATA(IP16_5_3, SSI_WS2),
1716 PINMUX_IPSR_DATA(IP16_5_3, ADICS_SAMP),
1717 PINMUX_IPSR_DATA(IP16_5_3, DU2_CDE),
1718 PINMUX_IPSR_DATA(IP16_5_3, QPOLB),
1719 PINMUX_IPSR_MODSEL_DATA(IP16_5_3, SCIFA2_RXD_B, SEL_HSCIF0_2),
1720 PINMUX_IPSR_DATA(IP16_6, USB1_PWEN),
1721 PINMUX_IPSR_DATA(IP16_6, AUDIO_CLKOUT_D),
1722 PINMUX_IPSR_DATA(IP16_7, USB1_OVC),
1723 PINMUX_IPSR_MODSEL_DATA(IP16_7, TCLK1_B, SEL_TMU1_1),
1725 PINMUX_DATA(I2C3_SCL_MARK, FN_SEL_IICDVFS_1),
1726 PINMUX_DATA(I2C3_SDA_MARK, FN_SEL_IICDVFS_1),
1729 /* R8A7790 has 6 banks with 32 GPIOs in each = 192 GPIOs */
1730 #define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
1731 #define PIN_NUMBER(r, c) (((r) - 'A') * 31 + (c) + 200)
1732 #define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
1734 static struct sh_pfc_pin pinmux_pins[] = {
1735 PINMUX_GPIO_GP_ALL(),
1737 /* Pins not associated with a GPIO port */
1738 SH_PFC_PIN_NAMED(ROW_GROUP_A('J'), 15, AJ15),
1739 SH_PFC_PIN_NAMED(ROW_GROUP_A('H'), 15, AH15),
1742 /* - DU RGB ----------------------------------------------------------------- */
1743 static const unsigned int du_rgb666_pins[] = {
1744 /* R[7:2], G[7:2], B[7:2] */
1745 RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19),
1746 RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16),
1747 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 14),
1748 RCAR_GP_PIN(5, 7), RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27),
1749 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 11),
1750 RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 8),
1752 static const unsigned int du_rgb666_mux[] = {
1753 DU2_DR7_MARK, DU2_DR6_MARK, DU2_DR5_MARK, DU2_DR4_MARK,
1754 DU2_DR3_MARK, DU2_DR2_MARK,
1755 DU2_DG7_MARK, DU2_DG6_MARK, DU2_DG5_MARK, DU2_DG4_MARK,
1756 DU2_DG3_MARK, DU2_DG2_MARK,
1757 DU2_DB7_MARK, DU2_DB6_MARK, DU2_DB5_MARK, DU2_DB4_MARK,
1758 DU2_DB3_MARK, DU2_DB2_MARK,
1760 static const unsigned int du_rgb888_pins[] = {
1761 /* R[7:0], G[7:0], B[7:0] */
1762 RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19),
1763 RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16),
1764 RCAR_GP_PIN(4, 29), RCAR_GP_PIN(4, 28), RCAR_GP_PIN(5, 4),
1765 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 7),
1766 RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27), RCAR_GP_PIN(5, 1),
1767 RCAR_GP_PIN(4, 31), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 12),
1768 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 9),
1769 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 5),
1771 static const unsigned int du_rgb888_mux[] = {
1772 DU2_DR7_MARK, DU2_DR6_MARK, DU2_DR5_MARK, DU2_DR4_MARK,
1773 DU2_DR3_MARK, DU2_DR2_MARK, DU2_DR1_MARK, DU2_DR0_MARK,
1774 DU2_DG7_MARK, DU2_DG6_MARK, DU2_DG5_MARK, DU2_DG4_MARK,
1775 DU2_DG3_MARK, DU2_DG2_MARK, DU2_DG1_MARK, DU2_DG0_MARK,
1776 DU2_DB7_MARK, DU2_DB6_MARK, DU2_DB5_MARK, DU2_DB4_MARK,
1777 DU2_DB3_MARK, DU2_DB2_MARK, DU2_DB1_MARK, DU2_DB0_MARK,
1779 static const unsigned int du_clk_out_0_pins[] = {
1783 static const unsigned int du_clk_out_0_mux[] = {
1786 static const unsigned int du_clk_out_1_pins[] = {
1790 static const unsigned int du_clk_out_1_mux[] = {
1793 static const unsigned int du_sync_0_pins[] = {
1794 /* VSYNC, HSYNC, DISP */
1795 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(5, 0),
1797 static const unsigned int du_sync_0_mux[] = {
1798 DU2_EXVSYNC_DU2_VSYNC_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK,
1799 DU2_EXODDF_DU2_ODDF_DISP_CDE_MARK
1801 static const unsigned int du_sync_1_pins[] = {
1802 /* VSYNC, HSYNC, DISP */
1803 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(5, 16),
1805 static const unsigned int du_sync_1_mux[] = {
1806 DU2_EXVSYNC_DU2_VSYNC_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK,
1809 static const unsigned int du_cde_pins[] = {
1813 static const unsigned int du_cde_mux[] = {
1816 /* - DU0 -------------------------------------------------------------------- */
1817 static const unsigned int du0_clk_in_pins[] = {
1821 static const unsigned int du0_clk_in_mux[] = {
1824 /* - DU1 -------------------------------------------------------------------- */
1825 static const unsigned int du1_clk_in_pins[] = {
1829 static const unsigned int du1_clk_in_mux[] = {
1832 /* - DU2 -------------------------------------------------------------------- */
1833 static const unsigned int du2_clk_in_pins[] = {
1837 static const unsigned int du2_clk_in_mux[] = {
1840 /* - ETH -------------------------------------------------------------------- */
1841 static const unsigned int eth_link_pins[] = {
1845 static const unsigned int eth_link_mux[] = {
1848 static const unsigned int eth_magic_pins[] = {
1852 static const unsigned int eth_magic_mux[] = {
1855 static const unsigned int eth_mdio_pins[] = {
1857 RCAR_GP_PIN(2, 29), RCAR_GP_PIN(2, 24),
1859 static const unsigned int eth_mdio_mux[] = {
1860 ETH_MDC_MARK, ETH_MDIO_MARK,
1862 static const unsigned int eth_rmii_pins[] = {
1863 /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
1864 RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 19),
1865 RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 25),
1866 RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 23),
1868 static const unsigned int eth_rmii_mux[] = {
1869 ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK,
1870 ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REF_CLK_MARK,
1872 /* - HSCIF0 ----------------------------------------------------------------- */
1873 static const unsigned int hscif0_data_pins[] = {
1875 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
1877 static const unsigned int hscif0_data_mux[] = {
1878 HRX0_MARK, HTX0_MARK,
1880 static const unsigned int hscif0_clk_pins[] = {
1884 static const unsigned int hscif0_clk_mux[] = {
1887 static const unsigned int hscif0_ctrl_pins[] = {
1889 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
1891 static const unsigned int hscif0_ctrl_mux[] = {
1892 HRTS0_N_MARK, HCTS0_N_MARK,
1894 static const unsigned int hscif0_data_b_pins[] = {
1896 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 12),
1898 static const unsigned int hscif0_data_b_mux[] = {
1899 HRX0_B_MARK, HTX0_B_MARK,
1901 static const unsigned int hscif0_ctrl_b_pins[] = {
1903 RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 28),
1905 static const unsigned int hscif0_ctrl_b_mux[] = {
1906 HRTS0_N_B_MARK, HCTS0_N_B_MARK,
1908 static const unsigned int hscif0_data_c_pins[] = {
1910 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 16),
1912 static const unsigned int hscif0_data_c_mux[] = {
1913 HRX0_C_MARK, HTX0_C_MARK,
1915 static const unsigned int hscif0_ctrl_c_pins[] = {
1917 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 7),
1919 static const unsigned int hscif0_ctrl_c_mux[] = {
1920 HRTS0_N_C_MARK, HCTS0_N_C_MARK,
1922 static const unsigned int hscif0_data_d_pins[] = {
1924 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
1926 static const unsigned int hscif0_data_d_mux[] = {
1927 HRX0_D_MARK, HTX0_D_MARK,
1929 static const unsigned int hscif0_ctrl_d_pins[] = {
1931 RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22),
1933 static const unsigned int hscif0_ctrl_d_mux[] = {
1934 HRTS0_N_D_MARK, HCTS0_N_D_MARK,
1936 static const unsigned int hscif0_data_e_pins[] = {
1938 RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
1940 static const unsigned int hscif0_data_e_mux[] = {
1941 HRX0_E_MARK, HTX0_E_MARK,
1943 static const unsigned int hscif0_ctrl_e_pins[] = {
1945 RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 23),
1947 static const unsigned int hscif0_ctrl_e_mux[] = {
1948 HRTS0_N_E_MARK, HCTS0_N_E_MARK,
1950 static const unsigned int hscif0_data_f_pins[] = {
1952 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 25),
1954 static const unsigned int hscif0_data_f_mux[] = {
1955 HRX0_F_MARK, HTX0_F_MARK,
1957 static const unsigned int hscif0_ctrl_f_pins[] = {
1959 RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 24),
1961 static const unsigned int hscif0_ctrl_f_mux[] = {
1962 HRTS0_N_F_MARK, HCTS0_N_F_MARK,
1964 /* - HSCIF1 ----------------------------------------------------------------- */
1965 static const unsigned int hscif1_data_pins[] = {
1967 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
1969 static const unsigned int hscif1_data_mux[] = {
1970 HRX1_MARK, HTX1_MARK,
1972 static const unsigned int hscif1_clk_pins[] = {
1976 static const unsigned int hscif1_clk_mux[] = {
1979 static const unsigned int hscif1_ctrl_pins[] = {
1981 RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
1983 static const unsigned int hscif1_ctrl_mux[] = {
1984 HRTS1_N_MARK, HCTS1_N_MARK,
1986 static const unsigned int hscif1_data_b_pins[] = {
1988 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 18),
1990 static const unsigned int hscif1_data_b_mux[] = {
1991 HRX1_B_MARK, HTX1_B_MARK,
1993 static const unsigned int hscif1_clk_b_pins[] = {
1997 static const unsigned int hscif1_clk_b_mux[] = {
2000 static const unsigned int hscif1_ctrl_b_pins[] = {
2002 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2004 static const unsigned int hscif1_ctrl_b_mux[] = {
2005 HRTS1_N_B_MARK, HCTS1_N_B_MARK,
2007 /* - I2C1 ------------------------------------------------------------------- */
2008 static const unsigned int i2c1_pins[] = {
2010 RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
2012 static const unsigned int i2c1_mux[] = {
2013 I2C1_SCL_MARK, I2C1_SDA_MARK,
2015 static const unsigned int i2c1_b_pins[] = {
2017 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
2019 static const unsigned int i2c1_b_mux[] = {
2020 I2C1_SCL_B_MARK, I2C1_SDA_B_MARK,
2022 static const unsigned int i2c1_c_pins[] = {
2024 RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27),
2026 static const unsigned int i2c1_c_mux[] = {
2027 I2C1_SCL_C_MARK, I2C1_SDA_C_MARK,
2029 /* - I2C2 ------------------------------------------------------------------- */
2030 static const unsigned int i2c2_pins[] = {
2032 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2034 static const unsigned int i2c2_mux[] = {
2035 I2C2_SCL_MARK, I2C2_SDA_MARK,
2037 static const unsigned int i2c2_b_pins[] = {
2039 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
2041 static const unsigned int i2c2_b_mux[] = {
2042 I2C2_SCL_B_MARK, I2C2_SDA_B_MARK,
2044 static const unsigned int i2c2_c_pins[] = {
2046 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
2048 static const unsigned int i2c2_c_mux[] = {
2049 I2C2_SCL_C_MARK, I2C2_SDA_C_MARK,
2051 static const unsigned int i2c2_d_pins[] = {
2053 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2055 static const unsigned int i2c2_d_mux[] = {
2056 I2C2_SCL_D_MARK, I2C2_SDA_D_MARK,
2058 static const unsigned int i2c2_e_pins[] = {
2060 RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
2062 static const unsigned int i2c2_e_mux[] = {
2063 I2C2_SCL_E_MARK, I2C2_SDA_E_MARK,
2065 /* - I2C3 ------------------------------------------------------------------- */
2066 static const unsigned int i2c3_pins[] = {
2068 PIN_A_NUMBER('J', 15), PIN_A_NUMBER('H', 15),
2070 static const unsigned int i2c3_mux[] = {
2071 I2C3_SCL_MARK, I2C3_SDA_MARK,
2073 /* - INTC ------------------------------------------------------------------- */
2074 static const unsigned int intc_irq0_pins[] = {
2078 static const unsigned int intc_irq0_mux[] = {
2081 static const unsigned int intc_irq1_pins[] = {
2085 static const unsigned int intc_irq1_mux[] = {
2088 static const unsigned int intc_irq2_pins[] = {
2092 static const unsigned int intc_irq2_mux[] = {
2095 static const unsigned int intc_irq3_pins[] = {
2099 static const unsigned int intc_irq3_mux[] = {
2102 /* - MMCIF0 ----------------------------------------------------------------- */
2103 static const unsigned int mmc0_data1_pins[] = {
2107 static const unsigned int mmc0_data1_mux[] = {
2110 static const unsigned int mmc0_data4_pins[] = {
2112 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
2113 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
2115 static const unsigned int mmc0_data4_mux[] = {
2116 MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
2118 static const unsigned int mmc0_data8_pins[] = {
2120 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
2121 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
2122 RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
2123 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
2125 static const unsigned int mmc0_data8_mux[] = {
2126 MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
2127 MMC0_D4_MARK, MMC0_D5_MARK, MMC0_D6_MARK, MMC0_D7_MARK,
2129 static const unsigned int mmc0_ctrl_pins[] = {
2131 RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17),
2133 static const unsigned int mmc0_ctrl_mux[] = {
2134 MMC0_CLK_MARK, MMC0_CMD_MARK,
2136 /* - MMCIF1 ----------------------------------------------------------------- */
2137 static const unsigned int mmc1_data1_pins[] = {
2141 static const unsigned int mmc1_data1_mux[] = {
2144 static const unsigned int mmc1_data4_pins[] = {
2146 RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27),
2147 RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
2149 static const unsigned int mmc1_data4_mux[] = {
2150 MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
2152 static const unsigned int mmc1_data8_pins[] = {
2154 RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27),
2155 RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
2156 RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31),
2157 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2159 static const unsigned int mmc1_data8_mux[] = {
2160 MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
2161 MMC1_D4_MARK, MMC1_D5_MARK, MMC1_D6_MARK, MMC1_D7_MARK,
2163 static const unsigned int mmc1_ctrl_pins[] = {
2165 RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25),
2167 static const unsigned int mmc1_ctrl_mux[] = {
2168 MMC1_CLK_MARK, MMC1_CMD_MARK,
2170 /* - MSIOF0 ----------------------------------------------------------------- */
2171 static const unsigned int msiof0_clk_pins[] = {
2175 static const unsigned int msiof0_clk_mux[] = {
2178 static const unsigned int msiof0_sync_pins[] = {
2182 static const unsigned int msiof0_sync_mux[] = {
2185 static const unsigned int msiof0_ss1_pins[] = {
2189 static const unsigned int msiof0_ss1_mux[] = {
2192 static const unsigned int msiof0_ss2_pins[] = {
2196 static const unsigned int msiof0_ss2_mux[] = {
2199 static const unsigned int msiof0_rx_pins[] = {
2203 static const unsigned int msiof0_rx_mux[] = {
2206 static const unsigned int msiof0_tx_pins[] = {
2210 static const unsigned int msiof0_tx_mux[] = {
2213 /* - MSIOF1 ----------------------------------------------------------------- */
2214 static const unsigned int msiof1_clk_pins[] = {
2218 static const unsigned int msiof1_clk_mux[] = {
2221 static const unsigned int msiof1_sync_pins[] = {
2225 static const unsigned int msiof1_sync_mux[] = {
2228 static const unsigned int msiof1_ss1_pins[] = {
2232 static const unsigned int msiof1_ss1_mux[] = {
2235 static const unsigned int msiof1_ss2_pins[] = {
2239 static const unsigned int msiof1_ss2_mux[] = {
2242 static const unsigned int msiof1_rx_pins[] = {
2246 static const unsigned int msiof1_rx_mux[] = {
2249 static const unsigned int msiof1_tx_pins[] = {
2253 static const unsigned int msiof1_tx_mux[] = {
2256 /* - MSIOF2 ----------------------------------------------------------------- */
2257 static const unsigned int msiof2_clk_pins[] = {
2261 static const unsigned int msiof2_clk_mux[] = {
2264 static const unsigned int msiof2_sync_pins[] = {
2268 static const unsigned int msiof2_sync_mux[] = {
2271 static const unsigned int msiof2_ss1_pins[] = {
2275 static const unsigned int msiof2_ss1_mux[] = {
2278 static const unsigned int msiof2_ss2_pins[] = {
2282 static const unsigned int msiof2_ss2_mux[] = {
2285 static const unsigned int msiof2_rx_pins[] = {
2289 static const unsigned int msiof2_rx_mux[] = {
2292 static const unsigned int msiof2_tx_pins[] = {
2296 static const unsigned int msiof2_tx_mux[] = {
2299 /* - MSIOF3 ----------------------------------------------------------------- */
2300 static const unsigned int msiof3_clk_pins[] = {
2304 static const unsigned int msiof3_clk_mux[] = {
2307 static const unsigned int msiof3_sync_pins[] = {
2311 static const unsigned int msiof3_sync_mux[] = {
2314 static const unsigned int msiof3_ss1_pins[] = {
2318 static const unsigned int msiof3_ss1_mux[] = {
2321 static const unsigned int msiof3_ss2_pins[] = {
2325 static const unsigned int msiof3_ss2_mux[] = {
2328 static const unsigned int msiof3_rx_pins[] = {
2332 static const unsigned int msiof3_rx_mux[] = {
2335 static const unsigned int msiof3_tx_pins[] = {
2339 static const unsigned int msiof3_tx_mux[] = {
2342 /* - SCIF0 ------------------------------------------------------------------ */
2343 static const unsigned int scif0_data_pins[] = {
2345 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
2347 static const unsigned int scif0_data_mux[] = {
2350 static const unsigned int scif0_clk_pins[] = {
2354 static const unsigned int scif0_clk_mux[] = {
2357 static const unsigned int scif0_ctrl_pins[] = {
2359 RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
2361 static const unsigned int scif0_ctrl_mux[] = {
2362 RTS0_N_MARK, CTS0_N_MARK,
2364 static const unsigned int scif0_data_b_pins[] = {
2366 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
2368 static const unsigned int scif0_data_b_mux[] = {
2369 RX0_B_MARK, TX0_B_MARK,
2371 /* - SCIF1 ------------------------------------------------------------------ */
2372 static const unsigned int scif1_data_pins[] = {
2374 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1),
2376 static const unsigned int scif1_data_mux[] = {
2379 static const unsigned int scif1_clk_pins[] = {
2383 static const unsigned int scif1_clk_mux[] = {
2386 static const unsigned int scif1_ctrl_pins[] = {
2388 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2),
2390 static const unsigned int scif1_ctrl_mux[] = {
2391 RTS1_N_MARK, CTS1_N_MARK,
2393 static const unsigned int scif1_data_b_pins[] = {
2395 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2397 static const unsigned int scif1_data_b_mux[] = {
2398 RX1_B_MARK, TX1_B_MARK,
2400 static const unsigned int scif1_data_c_pins[] = {
2402 RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
2404 static const unsigned int scif1_data_c_mux[] = {
2405 RX1_C_MARK, TX1_C_MARK,
2407 static const unsigned int scif1_data_d_pins[] = {
2409 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
2411 static const unsigned int scif1_data_d_mux[] = {
2412 RX1_D_MARK, TX1_D_MARK,
2414 static const unsigned int scif1_clk_d_pins[] = {
2418 static const unsigned int scif1_clk_d_mux[] = {
2421 static const unsigned int scif1_data_e_pins[] = {
2423 RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
2425 static const unsigned int scif1_data_e_mux[] = {
2426 RX1_E_MARK, TX1_E_MARK,
2428 static const unsigned int scif1_clk_e_pins[] = {
2432 static const unsigned int scif1_clk_e_mux[] = {
2435 /* - SCIF2 ------------------------------------------------------------------ */
2436 static const unsigned int scif2_data_pins[] = {
2438 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 5),
2440 static const unsigned int scif2_data_mux[] = {
2443 static const unsigned int scif2_clk_pins[] = {
2447 static const unsigned int scif2_clk_mux[] = {
2450 static const unsigned int scif2_data_b_pins[] = {
2452 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
2454 static const unsigned int scif2_data_b_mux[] = {
2455 RX2_B_MARK, TX2_B_MARK,
2457 /* - SCIFA0 ----------------------------------------------------------------- */
2458 static const unsigned int scifa0_data_pins[] = {
2460 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
2462 static const unsigned int scifa0_data_mux[] = {
2463 SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
2465 static const unsigned int scifa0_clk_pins[] = {
2469 static const unsigned int scifa0_clk_mux[] = {
2472 static const unsigned int scifa0_ctrl_pins[] = {
2474 RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
2476 static const unsigned int scifa0_ctrl_mux[] = {
2477 SCIFA0_RTS_N_MARK, SCIFA0_CTS_N_MARK,
2479 static const unsigned int scifa0_data_b_pins[] = {
2481 RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21),
2483 static const unsigned int scifa0_data_b_mux[] = {
2484 SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK
2486 static const unsigned int scifa0_clk_b_pins[] = {
2490 static const unsigned int scifa0_clk_b_mux[] = {
2493 static const unsigned int scifa0_ctrl_b_pins[] = {
2495 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22),
2497 static const unsigned int scifa0_ctrl_b_mux[] = {
2498 SCIFA0_RTS_N_B_MARK, SCIFA0_CTS_N_B_MARK,
2500 /* - SCIFA1 ----------------------------------------------------------------- */
2501 static const unsigned int scifa1_data_pins[] = {
2503 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1),
2505 static const unsigned int scifa1_data_mux[] = {
2506 SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
2508 static const unsigned int scifa1_clk_pins[] = {
2512 static const unsigned int scifa1_clk_mux[] = {
2515 static const unsigned int scifa1_ctrl_pins[] = {
2517 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2),
2519 static const unsigned int scifa1_ctrl_mux[] = {
2520 SCIFA1_RTS_N_MARK, SCIFA1_CTS_N_MARK,
2522 static const unsigned int scifa1_data_b_pins[] = {
2524 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 21),
2526 static const unsigned int scifa1_data_b_mux[] = {
2527 SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK,
2529 static const unsigned int scifa1_clk_b_pins[] = {
2533 static const unsigned int scifa1_clk_b_mux[] = {
2536 static const unsigned int scifa1_ctrl_b_pins[] = {
2538 RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 25),
2540 static const unsigned int scifa1_ctrl_b_mux[] = {
2541 SCIFA1_RTS_N_B_MARK, SCIFA1_CTS_N_B_MARK,
2543 static const unsigned int scifa1_data_c_pins[] = {
2545 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
2547 static const unsigned int scifa1_data_c_mux[] = {
2548 SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK,
2550 static const unsigned int scifa1_clk_c_pins[] = {
2554 static const unsigned int scifa1_clk_c_mux[] = {
2557 static const unsigned int scifa1_ctrl_c_pins[] = {
2559 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11),
2561 static const unsigned int scifa1_ctrl_c_mux[] = {
2562 SCIFA1_RTS_N_C_MARK, SCIFA1_CTS_N_C_MARK,
2564 static const unsigned int scifa1_data_d_pins[] = {
2566 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
2568 static const unsigned int scifa1_data_d_mux[] = {
2569 SCIFA1_RXD_D_MARK, SCIFA1_TXD_D_MARK,
2571 static const unsigned int scifa1_clk_d_pins[] = {
2575 static const unsigned int scifa1_clk_d_mux[] = {
2578 static const unsigned int scifa1_ctrl_d_pins[] = {
2580 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
2582 static const unsigned int scifa1_ctrl_d_mux[] = {
2583 SCIFA1_RTS_N_D_MARK, SCIFA1_CTS_N_D_MARK,
2585 /* - SCIFA2 ----------------------------------------------------------------- */
2586 static const unsigned int scifa2_data_pins[] = {
2588 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2590 static const unsigned int scifa2_data_mux[] = {
2591 SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
2593 static const unsigned int scifa2_clk_pins[] = {
2597 static const unsigned int scifa2_clk_mux[] = {
2600 static const unsigned int scifa2_ctrl_pins[] = {
2602 RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21),
2604 static const unsigned int scifa2_ctrl_mux[] = {
2605 SCIFA2_RTS_N_MARK, SCIFA2_CTS_N_MARK,
2607 static const unsigned int scifa2_data_b_pins[] = {
2609 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 16),
2611 static const unsigned int scifa2_data_b_mux[] = {
2612 SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK,
2614 static const unsigned int scifa2_data_c_pins[] = {
2616 RCAR_GP_PIN(5, 31), RCAR_GP_PIN(5, 30),
2618 static const unsigned int scifa2_data_c_mux[] = {
2619 SCIFA2_RXD_C_MARK, SCIFA2_TXD_C_MARK,
2621 static const unsigned int scifa2_clk_c_pins[] = {
2625 static const unsigned int scifa2_clk_c_mux[] = {
2628 /* - SCIFB0 ----------------------------------------------------------------- */
2629 static const unsigned int scifb0_data_pins[] = {
2631 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
2633 static const unsigned int scifb0_data_mux[] = {
2634 SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
2636 static const unsigned int scifb0_clk_pins[] = {
2640 static const unsigned int scifb0_clk_mux[] = {
2643 static const unsigned int scifb0_ctrl_pins[] = {
2645 RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11),
2647 static const unsigned int scifb0_ctrl_mux[] = {
2648 SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK,
2650 static const unsigned int scifb0_data_b_pins[] = {
2652 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
2654 static const unsigned int scifb0_data_b_mux[] = {
2655 SCIFB0_RXD_B_MARK, SCIFB0_TXD_B_MARK,
2657 static const unsigned int scifb0_clk_b_pins[] = {
2661 static const unsigned int scifb0_clk_b_mux[] = {
2664 static const unsigned int scifb0_ctrl_b_pins[] = {
2666 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
2668 static const unsigned int scifb0_ctrl_b_mux[] = {
2669 SCIFB0_RTS_N_B_MARK, SCIFB0_CTS_N_B_MARK,
2671 static const unsigned int scifb0_data_c_pins[] = {
2673 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
2675 static const unsigned int scifb0_data_c_mux[] = {
2676 SCIFB0_RXD_C_MARK, SCIFB0_TXD_C_MARK,
2678 /* - SCIFB1 ----------------------------------------------------------------- */
2679 static const unsigned int scifb1_data_pins[] = {
2681 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
2683 static const unsigned int scifb1_data_mux[] = {
2684 SCIFB1_RXD_MARK, SCIFB1_TXD_MARK,
2686 static const unsigned int scifb1_clk_pins[] = {
2690 static const unsigned int scifb1_clk_mux[] = {
2693 static const unsigned int scifb1_ctrl_pins[] = {
2695 RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17),
2697 static const unsigned int scifb1_ctrl_mux[] = {
2698 SCIFB1_RTS_N_MARK, SCIFB1_CTS_N_MARK,
2700 static const unsigned int scifb1_data_b_pins[] = {
2702 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
2704 static const unsigned int scifb1_data_b_mux[] = {
2705 SCIFB1_RXD_B_MARK, SCIFB1_TXD_B_MARK,
2707 static const unsigned int scifb1_clk_b_pins[] = {
2711 static const unsigned int scifb1_clk_b_mux[] = {
2714 static const unsigned int scifb1_ctrl_b_pins[] = {
2716 RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 4),
2718 static const unsigned int scifb1_ctrl_b_mux[] = {
2719 SCIFB1_RTS_N_B_MARK, SCIFB1_CTS_N_B_MARK,
2721 static const unsigned int scifb1_data_c_pins[] = {
2723 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2725 static const unsigned int scifb1_data_c_mux[] = {
2726 SCIFB1_RXD_C_MARK, SCIFB1_TXD_C_MARK,
2728 static const unsigned int scifb1_data_d_pins[] = {
2730 RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
2732 static const unsigned int scifb1_data_d_mux[] = {
2733 SCIFB1_RXD_D_MARK, SCIFB1_TXD_D_MARK,
2735 static const unsigned int scifb1_data_e_pins[] = {
2737 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
2739 static const unsigned int scifb1_data_e_mux[] = {
2740 SCIFB1_RXD_E_MARK, SCIFB1_TXD_E_MARK,
2742 static const unsigned int scifb1_clk_e_pins[] = {
2746 static const unsigned int scifb1_clk_e_mux[] = {
2749 static const unsigned int scifb1_data_f_pins[] = {
2751 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
2753 static const unsigned int scifb1_data_f_mux[] = {
2754 SCIFB1_RXD_F_MARK, SCIFB1_TXD_F_MARK,
2756 static const unsigned int scifb1_data_g_pins[] = {
2758 RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
2760 static const unsigned int scifb1_data_g_mux[] = {
2761 SCIFB1_RXD_G_MARK, SCIFB1_TXD_G_MARK,
2763 static const unsigned int scifb1_clk_g_pins[] = {
2767 static const unsigned int scifb1_clk_g_mux[] = {
2770 /* - SCIFB2 ----------------------------------------------------------------- */
2771 static const unsigned int scifb2_data_pins[] = {
2773 RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
2775 static const unsigned int scifb2_data_mux[] = {
2776 SCIFB2_RXD_MARK, SCIFB2_TXD_MARK,
2778 static const unsigned int scifb2_clk_pins[] = {
2782 static const unsigned int scifb2_clk_mux[] = {
2785 static const unsigned int scifb2_ctrl_pins[] = {
2787 RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 24),
2789 static const unsigned int scifb2_ctrl_mux[] = {
2790 SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK,
2792 static const unsigned int scifb2_data_b_pins[] = {
2794 RCAR_GP_PIN(0, 28), RCAR_GP_PIN(0, 30),
2796 static const unsigned int scifb2_data_b_mux[] = {
2797 SCIFB2_RXD_B_MARK, SCIFB2_TXD_B_MARK,
2799 static const unsigned int scifb2_clk_b_pins[] = {
2803 static const unsigned int scifb2_clk_b_mux[] = {
2806 static const unsigned int scifb2_ctrl_b_pins[] = {
2808 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(0, 27),
2810 static const unsigned int scifb2_ctrl_b_mux[] = {
2811 SCIFB2_RTS_N_B_MARK, SCIFB2_CTS_N_B_MARK,
2813 static const unsigned int scifb2_data_c_pins[] = {
2815 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
2817 static const unsigned int scifb2_data_c_mux[] = {
2818 SCIFB2_RXD_C_MARK, SCIFB2_TXD_C_MARK,
2820 /* - SDHI0 ------------------------------------------------------------------ */
2821 static const unsigned int sdhi0_data1_pins[] = {
2825 static const unsigned int sdhi0_data1_mux[] = {
2828 static const unsigned int sdhi0_data4_pins[] = {
2830 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
2832 static const unsigned int sdhi0_data4_mux[] = {
2833 SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
2835 static const unsigned int sdhi0_ctrl_pins[] = {
2837 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
2839 static const unsigned int sdhi0_ctrl_mux[] = {
2840 SD0_CLK_MARK, SD0_CMD_MARK,
2842 static const unsigned int sdhi0_cd_pins[] = {
2846 static const unsigned int sdhi0_cd_mux[] = {
2849 static const unsigned int sdhi0_wp_pins[] = {
2853 static const unsigned int sdhi0_wp_mux[] = {
2856 /* - SDHI1 ------------------------------------------------------------------ */
2857 static const unsigned int sdhi1_data1_pins[] = {
2861 static const unsigned int sdhi1_data1_mux[] = {
2864 static const unsigned int sdhi1_data4_pins[] = {
2866 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
2868 static const unsigned int sdhi1_data4_mux[] = {
2869 SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK,
2871 static const unsigned int sdhi1_ctrl_pins[] = {
2873 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
2875 static const unsigned int sdhi1_ctrl_mux[] = {
2876 SD1_CLK_MARK, SD1_CMD_MARK,
2878 static const unsigned int sdhi1_cd_pins[] = {
2882 static const unsigned int sdhi1_cd_mux[] = {
2885 static const unsigned int sdhi1_wp_pins[] = {
2889 static const unsigned int sdhi1_wp_mux[] = {
2892 /* - SDHI2 ------------------------------------------------------------------ */
2893 static const unsigned int sdhi2_data1_pins[] = {
2897 static const unsigned int sdhi2_data1_mux[] = {
2900 static const unsigned int sdhi2_data4_pins[] = {
2902 RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
2904 static const unsigned int sdhi2_data4_mux[] = {
2905 SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK,
2907 static const unsigned int sdhi2_ctrl_pins[] = {
2909 RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17),
2911 static const unsigned int sdhi2_ctrl_mux[] = {
2912 SD2_CLK_MARK, SD2_CMD_MARK,
2914 static const unsigned int sdhi2_cd_pins[] = {
2918 static const unsigned int sdhi2_cd_mux[] = {
2921 static const unsigned int sdhi2_wp_pins[] = {
2925 static const unsigned int sdhi2_wp_mux[] = {
2928 /* - SDHI3 ------------------------------------------------------------------ */
2929 static const unsigned int sdhi3_data1_pins[] = {
2933 static const unsigned int sdhi3_data1_mux[] = {
2936 static const unsigned int sdhi3_data4_pins[] = {
2938 RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
2940 static const unsigned int sdhi3_data4_mux[] = {
2941 SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK,
2943 static const unsigned int sdhi3_ctrl_pins[] = {
2945 RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25),
2947 static const unsigned int sdhi3_ctrl_mux[] = {
2948 SD3_CLK_MARK, SD3_CMD_MARK,
2950 static const unsigned int sdhi3_cd_pins[] = {
2954 static const unsigned int sdhi3_cd_mux[] = {
2957 static const unsigned int sdhi3_wp_pins[] = {
2961 static const unsigned int sdhi3_wp_mux[] = {
2964 /* - TPU0 ------------------------------------------------------------------- */
2965 static const unsigned int tpu0_to0_pins[] = {
2969 static const unsigned int tpu0_to0_mux[] = {
2972 static const unsigned int tpu0_to1_pins[] = {
2976 static const unsigned int tpu0_to1_mux[] = {
2979 static const unsigned int tpu0_to2_pins[] = {
2983 static const unsigned int tpu0_to2_mux[] = {
2986 static const unsigned int tpu0_to3_pins[] = {
2990 static const unsigned int tpu0_to3_mux[] = {
2993 /* - USB0 ------------------------------------------------------------------- */
2994 static const unsigned int usb0_pins[] = {
2995 /* PWEN, OVC/VBUS */
2996 RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
2998 static const unsigned int usb0_mux[] = {
2999 USB0_PWEN_MARK, USB0_OVC_VBUS_MARK,
3001 /* - USB1 ------------------------------------------------------------------- */
3002 static const unsigned int usb1_pins[] = {
3004 RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21),
3006 static const unsigned int usb1_mux[] = {
3007 USB1_PWEN_MARK, USB1_OVC_MARK,
3009 /* - USB2 ------------------------------------------------------------------- */
3010 static const unsigned int usb2_pins[] = {
3012 RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
3014 static const unsigned int usb2_mux[] = {
3015 USB2_PWEN_MARK, USB2_OVC_MARK,
3017 /* - VIN0 ------------------------------------------------------------------- */
3018 static const unsigned int vin0_data_g_pins[] = {
3019 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
3020 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
3021 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3023 static const unsigned int vin0_data_g_mux[] = {
3024 VI0_G0_MARK, VI0_G1_MARK, VI0_G2_MARK,
3025 VI0_G3_MARK, VI0_G4_MARK, VI0_G5_MARK,
3026 VI0_G6_MARK, VI0_G7_MARK,
3028 static const unsigned int vin0_data_r_pins[] = {
3029 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
3030 RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
3031 RCAR_GP_PIN(0, 26), RCAR_GP_PIN(1, 11),
3033 static const unsigned int vin0_data_r_mux[] = {
3034 VI0_R0_MARK, VI0_R1_MARK, VI0_R2_MARK,
3035 VI0_R3_MARK, VI0_R4_MARK, VI0_R5_MARK,
3036 VI0_R6_MARK, VI0_R7_MARK,
3038 static const unsigned int vin0_data_b_pins[] = {
3039 RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
3040 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
3041 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
3043 static const unsigned int vin0_data_b_mux[] = {
3044 VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK, VI0_DATA2_VI0_B2_MARK,
3045 VI0_DATA3_VI0_B3_MARK, VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
3046 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
3048 static const unsigned int vin0_hsync_signal_pins[] = {
3051 static const unsigned int vin0_hsync_signal_mux[] = {
3054 static const unsigned int vin0_vsync_signal_pins[] = {
3057 static const unsigned int vin0_vsync_signal_mux[] = {
3060 static const unsigned int vin0_field_signal_pins[] = {
3063 static const unsigned int vin0_field_signal_mux[] = {
3066 static const unsigned int vin0_data_enable_pins[] = {
3069 static const unsigned int vin0_data_enable_mux[] = {
3072 static const unsigned int vin0_clk_pins[] = {
3075 static const unsigned int vin0_clk_mux[] = {
3078 /* - VIN1 ------------------------------------------------------------------- */
3079 static const unsigned int vin1_data_pins[] = {
3080 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
3081 RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
3082 RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
3084 static const unsigned int vin1_data_mux[] = {
3085 VI1_DATA0_VI1_B0_MARK, VI1_DATA1_VI1_B1_MARK, VI1_DATA2_VI1_B2_MARK,
3086 VI1_DATA3_VI1_B3_MARK, VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK,
3087 VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK,
3089 static const unsigned int vin1_clk_pins[] = {
3092 static const unsigned int vin1_clk_mux[] = {
3096 static const struct sh_pfc_pin_group pinmux_groups[] = {
3097 SH_PFC_PIN_GROUP(du_rgb666),
3098 SH_PFC_PIN_GROUP(du_rgb888),
3099 SH_PFC_PIN_GROUP(du_clk_out_0),
3100 SH_PFC_PIN_GROUP(du_clk_out_1),
3101 SH_PFC_PIN_GROUP(du_sync_0),
3102 SH_PFC_PIN_GROUP(du_sync_1),
3103 SH_PFC_PIN_GROUP(du_cde),
3104 SH_PFC_PIN_GROUP(du0_clk_in),
3105 SH_PFC_PIN_GROUP(du1_clk_in),
3106 SH_PFC_PIN_GROUP(du2_clk_in),
3107 SH_PFC_PIN_GROUP(eth_link),
3108 SH_PFC_PIN_GROUP(eth_magic),
3109 SH_PFC_PIN_GROUP(eth_mdio),
3110 SH_PFC_PIN_GROUP(eth_rmii),
3111 SH_PFC_PIN_GROUP(hscif0_data),
3112 SH_PFC_PIN_GROUP(hscif0_clk),
3113 SH_PFC_PIN_GROUP(hscif0_ctrl),
3114 SH_PFC_PIN_GROUP(hscif0_data_b),
3115 SH_PFC_PIN_GROUP(hscif0_ctrl_b),
3116 SH_PFC_PIN_GROUP(hscif0_data_c),
3117 SH_PFC_PIN_GROUP(hscif0_ctrl_c),
3118 SH_PFC_PIN_GROUP(hscif0_data_d),
3119 SH_PFC_PIN_GROUP(hscif0_ctrl_d),
3120 SH_PFC_PIN_GROUP(hscif0_data_e),
3121 SH_PFC_PIN_GROUP(hscif0_ctrl_e),
3122 SH_PFC_PIN_GROUP(hscif0_data_f),
3123 SH_PFC_PIN_GROUP(hscif0_ctrl_f),
3124 SH_PFC_PIN_GROUP(hscif1_data),
3125 SH_PFC_PIN_GROUP(hscif1_clk),
3126 SH_PFC_PIN_GROUP(hscif1_ctrl),
3127 SH_PFC_PIN_GROUP(hscif1_data_b),
3128 SH_PFC_PIN_GROUP(hscif1_clk_b),
3129 SH_PFC_PIN_GROUP(hscif1_ctrl_b),
3130 SH_PFC_PIN_GROUP(i2c1),
3131 SH_PFC_PIN_GROUP(i2c1_b),
3132 SH_PFC_PIN_GROUP(i2c1_c),
3133 SH_PFC_PIN_GROUP(i2c2),
3134 SH_PFC_PIN_GROUP(i2c2_b),
3135 SH_PFC_PIN_GROUP(i2c2_c),
3136 SH_PFC_PIN_GROUP(i2c2_d),
3137 SH_PFC_PIN_GROUP(i2c2_e),
3138 SH_PFC_PIN_GROUP(i2c3),
3139 SH_PFC_PIN_GROUP(intc_irq0),
3140 SH_PFC_PIN_GROUP(intc_irq1),
3141 SH_PFC_PIN_GROUP(intc_irq2),
3142 SH_PFC_PIN_GROUP(intc_irq3),
3143 SH_PFC_PIN_GROUP(mmc0_data1),
3144 SH_PFC_PIN_GROUP(mmc0_data4),
3145 SH_PFC_PIN_GROUP(mmc0_data8),
3146 SH_PFC_PIN_GROUP(mmc0_ctrl),
3147 SH_PFC_PIN_GROUP(mmc1_data1),
3148 SH_PFC_PIN_GROUP(mmc1_data4),
3149 SH_PFC_PIN_GROUP(mmc1_data8),
3150 SH_PFC_PIN_GROUP(mmc1_ctrl),
3151 SH_PFC_PIN_GROUP(msiof0_clk),
3152 SH_PFC_PIN_GROUP(msiof0_sync),
3153 SH_PFC_PIN_GROUP(msiof0_ss1),
3154 SH_PFC_PIN_GROUP(msiof0_ss2),
3155 SH_PFC_PIN_GROUP(msiof0_rx),
3156 SH_PFC_PIN_GROUP(msiof0_tx),
3157 SH_PFC_PIN_GROUP(msiof1_clk),
3158 SH_PFC_PIN_GROUP(msiof1_sync),
3159 SH_PFC_PIN_GROUP(msiof1_ss1),
3160 SH_PFC_PIN_GROUP(msiof1_ss2),
3161 SH_PFC_PIN_GROUP(msiof1_rx),
3162 SH_PFC_PIN_GROUP(msiof1_tx),
3163 SH_PFC_PIN_GROUP(msiof2_clk),
3164 SH_PFC_PIN_GROUP(msiof2_sync),
3165 SH_PFC_PIN_GROUP(msiof2_ss1),
3166 SH_PFC_PIN_GROUP(msiof2_ss2),
3167 SH_PFC_PIN_GROUP(msiof2_rx),
3168 SH_PFC_PIN_GROUP(msiof2_tx),
3169 SH_PFC_PIN_GROUP(msiof3_clk),
3170 SH_PFC_PIN_GROUP(msiof3_sync),
3171 SH_PFC_PIN_GROUP(msiof3_ss1),
3172 SH_PFC_PIN_GROUP(msiof3_ss2),
3173 SH_PFC_PIN_GROUP(msiof3_rx),
3174 SH_PFC_PIN_GROUP(msiof3_tx),
3175 SH_PFC_PIN_GROUP(scif0_data),
3176 SH_PFC_PIN_GROUP(scif0_clk),
3177 SH_PFC_PIN_GROUP(scif0_ctrl),
3178 SH_PFC_PIN_GROUP(scif0_data_b),
3179 SH_PFC_PIN_GROUP(scif1_data),
3180 SH_PFC_PIN_GROUP(scif1_clk),
3181 SH_PFC_PIN_GROUP(scif1_ctrl),
3182 SH_PFC_PIN_GROUP(scif1_data_b),
3183 SH_PFC_PIN_GROUP(scif1_data_c),
3184 SH_PFC_PIN_GROUP(scif1_data_d),
3185 SH_PFC_PIN_GROUP(scif1_clk_d),
3186 SH_PFC_PIN_GROUP(scif1_data_e),
3187 SH_PFC_PIN_GROUP(scif1_clk_e),
3188 SH_PFC_PIN_GROUP(scif2_data),
3189 SH_PFC_PIN_GROUP(scif2_clk),
3190 SH_PFC_PIN_GROUP(scif2_data_b),
3191 SH_PFC_PIN_GROUP(scifa0_data),
3192 SH_PFC_PIN_GROUP(scifa0_clk),
3193 SH_PFC_PIN_GROUP(scifa0_ctrl),
3194 SH_PFC_PIN_GROUP(scifa0_data_b),
3195 SH_PFC_PIN_GROUP(scifa0_clk_b),
3196 SH_PFC_PIN_GROUP(scifa0_ctrl_b),
3197 SH_PFC_PIN_GROUP(scifa1_data),
3198 SH_PFC_PIN_GROUP(scifa1_clk),
3199 SH_PFC_PIN_GROUP(scifa1_ctrl),
3200 SH_PFC_PIN_GROUP(scifa1_data_b),
3201 SH_PFC_PIN_GROUP(scifa1_clk_b),
3202 SH_PFC_PIN_GROUP(scifa1_ctrl_b),
3203 SH_PFC_PIN_GROUP(scifa1_data_c),
3204 SH_PFC_PIN_GROUP(scifa1_clk_c),
3205 SH_PFC_PIN_GROUP(scifa1_ctrl_c),
3206 SH_PFC_PIN_GROUP(scifa1_data_d),
3207 SH_PFC_PIN_GROUP(scifa1_clk_d),
3208 SH_PFC_PIN_GROUP(scifa1_ctrl_d),
3209 SH_PFC_PIN_GROUP(scifa2_data),
3210 SH_PFC_PIN_GROUP(scifa2_clk),
3211 SH_PFC_PIN_GROUP(scifa2_ctrl),
3212 SH_PFC_PIN_GROUP(scifa2_data_b),
3213 SH_PFC_PIN_GROUP(scifa2_data_c),
3214 SH_PFC_PIN_GROUP(scifa2_clk_c),
3215 SH_PFC_PIN_GROUP(scifb0_data),
3216 SH_PFC_PIN_GROUP(scifb0_clk),
3217 SH_PFC_PIN_GROUP(scifb0_ctrl),
3218 SH_PFC_PIN_GROUP(scifb0_data_b),
3219 SH_PFC_PIN_GROUP(scifb0_clk_b),
3220 SH_PFC_PIN_GROUP(scifb0_ctrl_b),
3221 SH_PFC_PIN_GROUP(scifb0_data_c),
3222 SH_PFC_PIN_GROUP(scifb1_data),
3223 SH_PFC_PIN_GROUP(scifb1_clk),
3224 SH_PFC_PIN_GROUP(scifb1_ctrl),
3225 SH_PFC_PIN_GROUP(scifb1_data_b),
3226 SH_PFC_PIN_GROUP(scifb1_clk_b),
3227 SH_PFC_PIN_GROUP(scifb1_ctrl_b),
3228 SH_PFC_PIN_GROUP(scifb1_data_c),
3229 SH_PFC_PIN_GROUP(scifb1_data_d),
3230 SH_PFC_PIN_GROUP(scifb1_data_e),
3231 SH_PFC_PIN_GROUP(scifb1_clk_e),
3232 SH_PFC_PIN_GROUP(scifb1_data_f),
3233 SH_PFC_PIN_GROUP(scifb1_data_g),
3234 SH_PFC_PIN_GROUP(scifb1_clk_g),
3235 SH_PFC_PIN_GROUP(scifb2_data),
3236 SH_PFC_PIN_GROUP(scifb2_clk),
3237 SH_PFC_PIN_GROUP(scifb2_ctrl),
3238 SH_PFC_PIN_GROUP(scifb2_data_b),
3239 SH_PFC_PIN_GROUP(scifb2_clk_b),
3240 SH_PFC_PIN_GROUP(scifb2_ctrl_b),
3241 SH_PFC_PIN_GROUP(scifb2_data_c),
3242 SH_PFC_PIN_GROUP(sdhi0_data1),
3243 SH_PFC_PIN_GROUP(sdhi0_data4),
3244 SH_PFC_PIN_GROUP(sdhi0_ctrl),
3245 SH_PFC_PIN_GROUP(sdhi0_cd),
3246 SH_PFC_PIN_GROUP(sdhi0_wp),
3247 SH_PFC_PIN_GROUP(sdhi1_data1),
3248 SH_PFC_PIN_GROUP(sdhi1_data4),
3249 SH_PFC_PIN_GROUP(sdhi1_ctrl),
3250 SH_PFC_PIN_GROUP(sdhi1_cd),
3251 SH_PFC_PIN_GROUP(sdhi1_wp),
3252 SH_PFC_PIN_GROUP(sdhi2_data1),
3253 SH_PFC_PIN_GROUP(sdhi2_data4),
3254 SH_PFC_PIN_GROUP(sdhi2_ctrl),
3255 SH_PFC_PIN_GROUP(sdhi2_cd),
3256 SH_PFC_PIN_GROUP(sdhi2_wp),
3257 SH_PFC_PIN_GROUP(sdhi3_data1),
3258 SH_PFC_PIN_GROUP(sdhi3_data4),
3259 SH_PFC_PIN_GROUP(sdhi3_ctrl),
3260 SH_PFC_PIN_GROUP(sdhi3_cd),
3261 SH_PFC_PIN_GROUP(sdhi3_wp),
3262 SH_PFC_PIN_GROUP(tpu0_to0),
3263 SH_PFC_PIN_GROUP(tpu0_to1),
3264 SH_PFC_PIN_GROUP(tpu0_to2),
3265 SH_PFC_PIN_GROUP(tpu0_to3),
3266 SH_PFC_PIN_GROUP(usb0),
3267 SH_PFC_PIN_GROUP(usb1),
3268 SH_PFC_PIN_GROUP(usb2),
3269 SH_PFC_PIN_GROUP(vin0_data_g),
3270 SH_PFC_PIN_GROUP(vin0_data_r),
3271 SH_PFC_PIN_GROUP(vin0_data_b),
3272 SH_PFC_PIN_GROUP(vin0_hsync_signal),
3273 SH_PFC_PIN_GROUP(vin0_vsync_signal),
3274 SH_PFC_PIN_GROUP(vin0_field_signal),
3275 SH_PFC_PIN_GROUP(vin0_data_enable),
3276 SH_PFC_PIN_GROUP(vin0_clk),
3277 SH_PFC_PIN_GROUP(vin1_data),
3278 SH_PFC_PIN_GROUP(vin1_clk),
3281 static const char * const du_groups[] = {
3291 static const char * const du0_groups[] = {
3295 static const char * const du1_groups[] = {
3299 static const char * const du2_groups[] = {
3303 static const char * const eth_groups[] = {
3310 static const char * const hscif0_groups[] = {
3326 static const char * const hscif1_groups[] = {
3335 static const char * const i2c1_groups[] = {
3341 static const char * const i2c2_groups[] = {
3349 static const char * const i2c3_groups[] = {
3353 static const char * const intc_groups[] = {
3360 static const char * const mmc0_groups[] = {
3367 static const char * const mmc1_groups[] = {
3374 static const char * const msiof0_groups[] = {
3383 static const char * const msiof1_groups[] = {
3392 static const char * const msiof2_groups[] = {
3401 static const char * const msiof3_groups[] = {
3410 static const char * const scif0_groups[] = {
3417 static const char * const scif1_groups[] = {
3429 static const char * const scif2_groups[] = {
3435 static const char * const scifa0_groups[] = {
3444 static const char * const scifa1_groups[] = {
3459 static const char * const scifa2_groups[] = {
3468 static const char * const scifb0_groups[] = {
3478 static const char * const scifb1_groups[] = {
3494 static const char * const scifb2_groups[] = {
3504 static const char * const sdhi0_groups[] = {
3512 static const char * const sdhi1_groups[] = {
3520 static const char * const sdhi2_groups[] = {
3528 static const char * const sdhi3_groups[] = {
3536 static const char * const tpu0_groups[] = {
3543 static const char * const usb0_groups[] = {
3547 static const char * const usb1_groups[] = {
3551 static const char * const usb2_groups[] = {
3555 static const char * const vin0_groups[] = {
3559 "vin0_hsync_signal",
3560 "vin0_vsync_signal",
3561 "vin0_field_signal",
3566 static const char * const vin1_groups[] = {
3571 static const struct sh_pfc_function pinmux_functions[] = {
3572 SH_PFC_FUNCTION(du),
3573 SH_PFC_FUNCTION(du0),
3574 SH_PFC_FUNCTION(du1),
3575 SH_PFC_FUNCTION(du2),
3576 SH_PFC_FUNCTION(eth),
3577 SH_PFC_FUNCTION(hscif0),
3578 SH_PFC_FUNCTION(hscif1),
3579 SH_PFC_FUNCTION(i2c1),
3580 SH_PFC_FUNCTION(i2c2),
3581 SH_PFC_FUNCTION(i2c3),
3582 SH_PFC_FUNCTION(intc),
3583 SH_PFC_FUNCTION(mmc0),
3584 SH_PFC_FUNCTION(mmc1),
3585 SH_PFC_FUNCTION(msiof0),
3586 SH_PFC_FUNCTION(msiof1),
3587 SH_PFC_FUNCTION(msiof2),
3588 SH_PFC_FUNCTION(msiof3),
3589 SH_PFC_FUNCTION(scif0),
3590 SH_PFC_FUNCTION(scif1),
3591 SH_PFC_FUNCTION(scif2),
3592 SH_PFC_FUNCTION(scifa0),
3593 SH_PFC_FUNCTION(scifa1),
3594 SH_PFC_FUNCTION(scifa2),
3595 SH_PFC_FUNCTION(scifb0),
3596 SH_PFC_FUNCTION(scifb1),
3597 SH_PFC_FUNCTION(scifb2),
3598 SH_PFC_FUNCTION(sdhi0),
3599 SH_PFC_FUNCTION(sdhi1),
3600 SH_PFC_FUNCTION(sdhi2),
3601 SH_PFC_FUNCTION(sdhi3),
3602 SH_PFC_FUNCTION(tpu0),
3603 SH_PFC_FUNCTION(usb0),
3604 SH_PFC_FUNCTION(usb1),
3605 SH_PFC_FUNCTION(usb2),
3606 SH_PFC_FUNCTION(vin0),
3607 SH_PFC_FUNCTION(vin1),
3610 static struct pinmux_cfg_reg pinmux_config_regs[] = {
3611 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
3612 GP_0_31_FN, FN_IP3_17_15,
3613 GP_0_30_FN, FN_IP3_14_12,
3614 GP_0_29_FN, FN_IP3_11_8,
3615 GP_0_28_FN, FN_IP3_7_4,
3616 GP_0_27_FN, FN_IP3_3_0,
3617 GP_0_26_FN, FN_IP2_28_26,
3618 GP_0_25_FN, FN_IP2_25_22,
3619 GP_0_24_FN, FN_IP2_21_18,
3620 GP_0_23_FN, FN_IP2_17_15,
3621 GP_0_22_FN, FN_IP2_14_12,
3622 GP_0_21_FN, FN_IP2_11_9,
3623 GP_0_20_FN, FN_IP2_8_6,
3624 GP_0_19_FN, FN_IP2_5_3,
3625 GP_0_18_FN, FN_IP2_2_0,
3626 GP_0_17_FN, FN_IP1_29_28,
3627 GP_0_16_FN, FN_IP1_27_26,
3628 GP_0_15_FN, FN_IP1_25_22,
3629 GP_0_14_FN, FN_IP1_21_18,
3630 GP_0_13_FN, FN_IP1_17_15,
3631 GP_0_12_FN, FN_IP1_14_12,
3632 GP_0_11_FN, FN_IP1_11_8,
3633 GP_0_10_FN, FN_IP1_7_4,
3634 GP_0_9_FN, FN_IP1_3_0,
3635 GP_0_8_FN, FN_IP0_30_27,
3636 GP_0_7_FN, FN_IP0_26_23,
3637 GP_0_6_FN, FN_IP0_22_20,
3638 GP_0_5_FN, FN_IP0_19_16,
3639 GP_0_4_FN, FN_IP0_15_12,
3640 GP_0_3_FN, FN_IP0_11_9,
3641 GP_0_2_FN, FN_IP0_8_6,
3642 GP_0_1_FN, FN_IP0_5_3,
3643 GP_0_0_FN, FN_IP0_2_0 }
3645 { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
3648 GP_1_29_FN, FN_IP6_13_11,
3649 GP_1_28_FN, FN_IP6_10_9,
3650 GP_1_27_FN, FN_IP6_8_6,
3651 GP_1_26_FN, FN_IP6_5_3,
3652 GP_1_25_FN, FN_IP6_2_0,
3653 GP_1_24_FN, FN_IP5_29_27,
3654 GP_1_23_FN, FN_IP5_26_24,
3655 GP_1_22_FN, FN_IP5_23_21,
3656 GP_1_21_FN, FN_IP5_20_18,
3657 GP_1_20_FN, FN_IP5_17_15,
3658 GP_1_19_FN, FN_IP5_14_13,
3659 GP_1_18_FN, FN_IP5_12_10,
3660 GP_1_17_FN, FN_IP5_9_6,
3661 GP_1_16_FN, FN_IP5_5_3,
3662 GP_1_15_FN, FN_IP5_2_0,
3663 GP_1_14_FN, FN_IP4_29_27,
3664 GP_1_13_FN, FN_IP4_26_24,
3665 GP_1_12_FN, FN_IP4_23_21,
3666 GP_1_11_FN, FN_IP4_20_18,
3667 GP_1_10_FN, FN_IP4_17_15,
3668 GP_1_9_FN, FN_IP4_14_12,
3669 GP_1_8_FN, FN_IP4_11_9,
3670 GP_1_7_FN, FN_IP4_8_6,
3671 GP_1_6_FN, FN_IP4_5_3,
3672 GP_1_5_FN, FN_IP4_2_0,
3673 GP_1_4_FN, FN_IP3_31_29,
3674 GP_1_3_FN, FN_IP3_28_26,
3675 GP_1_2_FN, FN_IP3_25_23,
3676 GP_1_1_FN, FN_IP3_22_20,
3677 GP_1_0_FN, FN_IP3_19_18, }
3679 { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
3682 GP_2_29_FN, FN_IP7_15_13,
3683 GP_2_28_FN, FN_IP7_12_10,
3684 GP_2_27_FN, FN_IP7_9_8,
3685 GP_2_26_FN, FN_IP7_7_6,
3686 GP_2_25_FN, FN_IP7_5_3,
3687 GP_2_24_FN, FN_IP7_2_0,
3688 GP_2_23_FN, FN_IP6_31_29,
3689 GP_2_22_FN, FN_IP6_28_26,
3690 GP_2_21_FN, FN_IP6_25_23,
3691 GP_2_20_FN, FN_IP6_22_20,
3692 GP_2_19_FN, FN_IP6_19_17,
3693 GP_2_18_FN, FN_IP6_16_14,
3694 GP_2_17_FN, FN_VI1_DATA7_VI1_B7,
3695 GP_2_16_FN, FN_IP8_27,
3696 GP_2_15_FN, FN_IP8_26,
3697 GP_2_14_FN, FN_IP8_25_24,
3698 GP_2_13_FN, FN_IP8_23_22,
3699 GP_2_12_FN, FN_IP8_21_20,
3700 GP_2_11_FN, FN_IP8_19_18,
3701 GP_2_10_FN, FN_IP8_17_16,
3702 GP_2_9_FN, FN_IP8_15_14,
3703 GP_2_8_FN, FN_IP8_13_12,
3704 GP_2_7_FN, FN_IP8_11_10,
3705 GP_2_6_FN, FN_IP8_9_8,
3706 GP_2_5_FN, FN_IP8_7_6,
3707 GP_2_4_FN, FN_IP8_5_4,
3708 GP_2_3_FN, FN_IP8_3_2,
3709 GP_2_2_FN, FN_IP8_1_0,
3710 GP_2_1_FN, FN_IP7_30_29,
3711 GP_2_0_FN, FN_IP7_28_27 }
3713 { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
3714 GP_3_31_FN, FN_IP11_21_18,
3715 GP_3_30_FN, FN_IP11_17_15,
3716 GP_3_29_FN, FN_IP11_14_13,
3717 GP_3_28_FN, FN_IP11_12_11,
3718 GP_3_27_FN, FN_IP11_10_9,
3719 GP_3_26_FN, FN_IP11_8_7,
3720 GP_3_25_FN, FN_IP11_6_5,
3721 GP_3_24_FN, FN_IP11_4,
3722 GP_3_23_FN, FN_IP11_3_0,
3723 GP_3_22_FN, FN_IP10_29_26,
3724 GP_3_21_FN, FN_IP10_25_23,
3725 GP_3_20_FN, FN_IP10_22_19,
3726 GP_3_19_FN, FN_IP10_18_15,
3727 GP_3_18_FN, FN_IP10_14_11,
3728 GP_3_17_FN, FN_IP10_10_7,
3729 GP_3_16_FN, FN_IP10_6_4,
3730 GP_3_15_FN, FN_IP10_3_0,
3731 GP_3_14_FN, FN_IP9_31_28,
3732 GP_3_13_FN, FN_IP9_27_26,
3733 GP_3_12_FN, FN_IP9_25_24,
3734 GP_3_11_FN, FN_IP9_23_22,
3735 GP_3_10_FN, FN_IP9_21_20,
3736 GP_3_9_FN, FN_IP9_19_18,
3737 GP_3_8_FN, FN_IP9_17_16,
3738 GP_3_7_FN, FN_IP9_15_12,
3739 GP_3_6_FN, FN_IP9_11_8,
3740 GP_3_5_FN, FN_IP9_7_6,
3741 GP_3_4_FN, FN_IP9_5_4,
3742 GP_3_3_FN, FN_IP9_3_2,
3743 GP_3_2_FN, FN_IP9_1_0,
3744 GP_3_1_FN, FN_IP8_30_29,
3745 GP_3_0_FN, FN_IP8_28 }
3747 { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
3748 GP_4_31_FN, FN_IP14_18_16,
3749 GP_4_30_FN, FN_IP14_15_12,
3750 GP_4_29_FN, FN_IP14_11_9,
3751 GP_4_28_FN, FN_IP14_8_6,
3752 GP_4_27_FN, FN_IP14_5_3,
3753 GP_4_26_FN, FN_IP14_2_0,
3754 GP_4_25_FN, FN_IP13_30_29,
3755 GP_4_24_FN, FN_IP13_28_26,
3756 GP_4_23_FN, FN_IP13_25_23,
3757 GP_4_22_FN, FN_IP13_22_19,
3758 GP_4_21_FN, FN_IP13_18_16,
3759 GP_4_20_FN, FN_IP13_15_13,
3760 GP_4_19_FN, FN_IP13_12_10,
3761 GP_4_18_FN, FN_IP13_9_7,
3762 GP_4_17_FN, FN_IP13_6_3,
3763 GP_4_16_FN, FN_IP13_2_0,
3764 GP_4_15_FN, FN_IP12_30_28,
3765 GP_4_14_FN, FN_IP12_27_25,
3766 GP_4_13_FN, FN_IP12_24_23,
3767 GP_4_12_FN, FN_IP12_22_20,
3768 GP_4_11_FN, FN_IP12_19_17,
3769 GP_4_10_FN, FN_IP12_16_14,
3770 GP_4_9_FN, FN_IP12_13_11,
3771 GP_4_8_FN, FN_IP12_10_8,
3772 GP_4_7_FN, FN_IP12_7_6,
3773 GP_4_6_FN, FN_IP12_5_4,
3774 GP_4_5_FN, FN_IP12_3_2,
3775 GP_4_4_FN, FN_IP12_1_0,
3776 GP_4_3_FN, FN_IP11_31_30,
3777 GP_4_2_FN, FN_IP11_29_27,
3778 GP_4_1_FN, FN_IP11_26_24,
3779 GP_4_0_FN, FN_IP11_23_22 }
3781 { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
3782 GP_5_31_FN, FN_IP7_24_22,
3783 GP_5_30_FN, FN_IP7_21_19,
3784 GP_5_29_FN, FN_IP7_18_16,
3785 GP_5_28_FN, FN_DU_DOTCLKIN2,
3786 GP_5_27_FN, FN_IP7_26_25,
3787 GP_5_26_FN, FN_DU_DOTCLKIN0,
3788 GP_5_25_FN, FN_AVS2,
3789 GP_5_24_FN, FN_AVS1,
3790 GP_5_23_FN, FN_USB2_OVC,
3791 GP_5_22_FN, FN_USB2_PWEN,
3792 GP_5_21_FN, FN_IP16_7,
3793 GP_5_20_FN, FN_IP16_6,
3794 GP_5_19_FN, FN_USB0_OVC_VBUS,
3795 GP_5_18_FN, FN_USB0_PWEN,
3796 GP_5_17_FN, FN_IP16_5_3,
3797 GP_5_16_FN, FN_IP16_2_0,
3798 GP_5_15_FN, FN_IP15_29_28,
3799 GP_5_14_FN, FN_IP15_27_26,
3800 GP_5_13_FN, FN_IP15_25_23,
3801 GP_5_12_FN, FN_IP15_22_20,
3802 GP_5_11_FN, FN_IP15_19_18,
3803 GP_5_10_FN, FN_IP15_17_16,
3804 GP_5_9_FN, FN_IP15_15_14,
3805 GP_5_8_FN, FN_IP15_13_12,
3806 GP_5_7_FN, FN_IP15_11_9,
3807 GP_5_6_FN, FN_IP15_8_6,
3808 GP_5_5_FN, FN_IP15_5_3,
3809 GP_5_4_FN, FN_IP15_2_0,
3810 GP_5_3_FN, FN_IP14_30_28,
3811 GP_5_2_FN, FN_IP14_27_25,
3812 GP_5_1_FN, FN_IP14_24_22,
3813 GP_5_0_FN, FN_IP14_21_19 }
3815 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
3816 1, 4, 4, 3, 4, 4, 3, 3, 3, 3) {
3820 FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0, 0,
3821 FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0,
3822 0, 0, 0, 0, 0, 0, 0, 0, 0,
3824 FN_D7, FN_AD_DI_B, FN_IIC2_SDA_C,
3825 FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_I2C2_SDA_C,
3826 FN_TCLK1, 0, 0, 0, 0, 0, 0, 0, 0,
3828 FN_D6, FN_IIC2_SCL_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B,
3829 FN_I2C2_SCL_C, 0, 0,
3831 FN_D5, FN_SCIFB1_TXD_F, FN_SCIFB0_TXD_C, FN_VI3_DATA5,
3832 FN_VI0_R1, FN_VI0_R1_B, FN_TX0_B,
3833 0, 0, 0, 0, 0, 0, 0, 0, 0,
3835 FN_D4, FN_SCIFB1_RXD_F, FN_SCIFB0_RXD_C, FN_VI3_DATA4,
3836 FN_VI0_R0, FN_VI0_R0_B, FN_RX0_B,
3837 0, 0, 0, 0, 0, 0, 0, 0, 0,
3839 FN_D3, FN_MSIOF3_TXD_B, FN_VI3_DATA3, FN_VI0_G7, FN_VI0_G7_B,
3842 FN_D2, FN_MSIOF3_RXD_B, FN_VI3_DATA2, FN_VI0_G6, FN_VI0_G6_B,
3845 FN_D1, FN_MSIOF3_SYNC_B, FN_VI3_DATA1, FN_VI0_G5, FN_VI0_G5_B,
3848 FN_D0, FN_MSIOF3_SCK_B, FN_VI3_DATA0, FN_VI0_G4, FN_VI0_G4_B,
3851 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
3852 2, 2, 2, 4, 4, 3, 3, 4, 4, 4) {
3856 FN_A1, FN_PWM4, 0, 0,
3858 FN_A0, FN_PWM3, 0, 0,
3860 FN_D15, FN_SCIFB1_TXD_C, FN_AVB_TXD7, FN_TX1_B,
3861 FN_VI0_FIELD, FN_VI0_FIELD_B, FN_VI2_DATA7_VI2_B7,
3862 0, 0, 0, 0, 0, 0, 0, 0, 0,
3864 FN_D14, FN_SCIFB1_RXD_C, FN_AVB_TXD6, FN_RX1_B,
3865 FN_VI0_CLKENB, FN_VI0_CLKENB_B, FN_VI2_DATA6_VI2_B6,
3866 0, 0, 0, 0, 0, 0, 0, 0, 0,
3868 FN_D13, FN_AVB_TXD5, FN_VI0_VSYNC_N,
3869 FN_VI0_VSYNC_N_B, FN_VI2_DATA5_VI2_B5,
3872 FN_D12, FN_SCIFA1_RTS_N_C, FN_AVB_TXD4,
3873 FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4,
3876 FN_D11, FN_SCIFA1_CTS_N_C, FN_AVB_TXD3, 0,
3877 FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3,
3878 0, 0, 0, 0, 0, 0, 0, 0, 0,
3880 FN_D10, FN_SCIFA1_TXD_C, FN_AVB_TXD2, 0,
3881 FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2,
3882 0, 0, 0, 0, 0, 0, 0, 0, 0,
3884 FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1, 0,
3885 FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1,
3886 0, 0, 0, 0, 0, 0, 0, 0, 0, }
3888 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
3889 3, 3, 4, 4, 3, 3, 3, 3, 3, 3) {
3891 0, 0, 0, 0, 0, 0, 0, 0,
3893 FN_A10, FN_SSI_SDATA5_B, FN_MSIOF2_SYNC, FN_VI0_R6,
3894 FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B, 0, 0,
3896 FN_A9, FN_SCIFA1_CTS_N_B, FN_SSI_WS5_B, FN_VI0_R5,
3897 FN_VI0_R5_B, FN_SCIFB2_TXD_C, FN_TX2_B, FN_VI2_DATA1_VI2_B1_B,
3898 0, 0, 0, 0, 0, 0, 0, 0,
3900 FN_A8, FN_SCIFA1_RXD_B, FN_SSI_SCK5_B, FN_VI0_R4,
3901 FN_VI0_R4_B, FN_SCIFB2_RXD_C, FN_RX2_B, FN_VI2_DATA0_VI2_B0_B,
3902 0, 0, 0, 0, 0, 0, 0, 0,
3904 FN_A7, FN_SCIFA1_SCK_B, FN_AUDIO_CLKOUT_B, FN_TPU0TO3,
3907 FN_A6, FN_SCIFA1_RTS_N_B, FN_TPU0TO2, 0, 0, 0, 0, 0,
3909 FN_A5, FN_SCIFA1_TXD_B, FN_TPU0TO1, 0, 0, 0, 0, 0,
3911 FN_A4, FN_MSIOF1_TXD_B, FN_TPU0TO0, 0, 0, 0, 0, 0,
3913 FN_A3, FN_PWM6, FN_MSIOF1_SS2_B, 0, 0, 0, 0, 0,
3915 FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, 0, 0, 0, 0, 0, }
3917 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
3918 3, 3, 3, 3, 2, 3, 3, 4, 4, 4) {
3920 FN_A20, FN_SPCLK, FN_VI1_R3, FN_VI1_R3_B, FN_VI2_G4,
3923 FN_A19, FN_AD_NCS_N_B, FN_ATACS01_N, FN_EX_WAIT0_B,
3926 FN_A18, FN_AD_CLK_B, FN_ATAG1_N, 0, 0, 0, 0, 0,
3928 FN_A17, FN_AD_DO_B, FN_ATADIR1_N, 0, 0, 0, 0, 0,
3930 FN_A16, FN_ATAWR1_N, 0, 0,
3932 FN_A15, FN_SCIFB2_SCK_B, FN_ATARD1_N, FN_MSIOF2_SS2,
3935 FN_A14, FN_SCIFB2_TXD_B, FN_ATACS11_N, FN_MSIOF2_SS1,
3938 FN_A13, FN_SCIFB2_RTS_N_B, FN_EX_WAIT2,
3939 FN_MSIOF2_RXD, FN_VI1_R2, FN_VI1_R2_B, FN_VI2_G2,
3940 FN_VI2_DATA5_VI2_B5_B, 0, 0, 0, 0, 0, 0, 0, 0,
3942 FN_A12, FN_SCIFB2_RXD_B, FN_MSIOF2_TXD, FN_VI1_R1,
3943 FN_VI1_R1_B, FN_VI2_G1, FN_VI2_DATA4_VI2_B4_B,
3944 0, 0, 0, 0, 0, 0, 0, 0, 0,
3946 FN_A11, FN_SCIFB2_CTS_N_B, FN_MSIOF2_SCK, FN_VI1_R0,
3947 FN_VI1_R0_B, FN_VI2_G0, FN_VI2_DATA3_VI2_B3_B, 0,
3948 0, 0, 0, 0, 0, 0, 0, 0, }
3950 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
3951 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
3955 FN_EX_CS2_N, FN_GPS_SIGN, FN_HRTS1_N_B,
3956 FN_VI3_CLKENB, FN_VI1_G0, FN_VI1_G0_B, FN_VI2_R2, 0,
3958 FN_EX_CS1_N, FN_GPS_CLK, FN_HCTS1_N_B, FN_VI1_FIELD,
3959 FN_VI1_FIELD_B, FN_VI2_R1, 0, 0,
3961 FN_EX_CS0_N, FN_HRX1_B, FN_VI1_G5, FN_VI1_G5_B, FN_VI2_R0,
3962 FN_HTX0_B, FN_MSIOF0_SS1_B, 0,
3964 FN_CS1_N_A26, FN_SPEEDIN, FN_VI0_R7, FN_VI0_R7_B,
3965 FN_VI2_CLK, FN_VI2_CLK_B, 0, 0,
3967 FN_CS0_N, FN_VI1_R6, FN_VI1_R6_B, FN_VI2_G3, FN_MSIOF0_SS2_B,
3970 FN_A25, FN_SSL, FN_VI1_G6, FN_VI1_G6_B, FN_VI2_FIELD,
3971 FN_VI2_FIELD_B, 0, 0,
3973 FN_A24, FN_IO3, FN_VI1_R7, FN_VI1_R7_B, FN_VI2_CLKENB,
3974 FN_VI2_CLKENB_B, 0, 0,
3976 FN_A23, FN_IO2, FN_VI1_G7, FN_VI1_G7_B, FN_VI2_G7, 0, 0, 0,
3978 FN_A22, FN_MISO_IO1, FN_VI1_R5, FN_VI1_R5_B, FN_VI2_G6, 0, 0, 0,
3980 FN_A21, FN_MOSI_IO0, FN_VI1_R4, FN_VI1_R4_B, FN_VI2_G5, 0, 0, 0,
3983 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
3984 2, 3, 3, 3, 3, 3, 2, 3, 4, 3, 3) {
3988 FN_DREQ0_N, FN_VI1_HSYNC_N, FN_VI1_HSYNC_N_B, FN_VI2_R7,
3989 FN_SSI_SCK78_C, FN_SSI_WS78_B, 0, 0,
3991 FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N,
3992 FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B,
3995 FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4,
3996 FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B,
3999 FN_WE0_N, FN_IECLK, FN_CAN_CLK,
4000 FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B, 0, 0,
4002 FN_RD_WR_N, FN_VI1_G3, FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B,
4003 FN_INTC_IRQ4_N, 0, 0,
4005 FN_RD_N, FN_CAN0_TX, FN_SCIFA0_SCK_B, 0,
4007 FN_BS_N, FN_IETX, FN_HTX1_B, FN_CAN1_TX, FN_DRACK0, FN_IETX_C,
4010 FN_EX_CS5_N, FN_CAN0_RX, FN_MSIOF1_RXD_B, FN_VI3_VSYNC_N,
4011 FN_VI1_G2, FN_VI1_G2_B, FN_VI2_R4, FN_IIC1_SDA, FN_INTC_EN1_N,
4012 FN_I2C1_SDA, 0, 0, 0, 0, 0, 0,
4014 FN_EX_CS4_N, FN_MSIOF1_SCK_B, FN_VI3_HSYNC_N,
4015 FN_VI2_HSYNC_N, FN_IIC1_SCL, FN_VI2_HSYNC_N_B,
4016 FN_INTC_EN0_N, FN_I2C1_SCL,
4018 FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B,
4021 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
4022 3, 3, 3, 3, 3, 3, 3, 2, 3, 3, 3) {
4024 FN_ETH_REF_CLK, 0, FN_HCTS0_N_E,
4025 FN_STP_IVCXO27_1_B, FN_HRX0_F, 0, 0, 0,
4027 FN_ETH_LINK, 0, FN_HTX0_E,
4028 FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E, 0, 0,
4030 FN_ETH_RXD1, 0, FN_HRX0_E, FN_STP_ISSYNC_0_B,
4031 FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G, FN_RX1_E,
4033 FN_ETH_RXD0, 0, FN_STP_ISEN_0_B, FN_TS_SDAT0_D,
4034 FN_GLO_I0_C, FN_SCIFB1_SCK_G, FN_SCK1_E, 0,
4036 FN_ETH_RX_ER, 0, FN_STP_ISD_0_B,
4037 FN_TS_SPSYNC0_D, FN_GLO_Q1_C, FN_IIC2_SDA_E, FN_I2C2_SDA_E, 0,
4039 FN_ETH_CRS_DV, 0, FN_STP_ISCLK_0_B,
4040 FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E,
4043 FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N,
4044 FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B, 0, 0,
4046 FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B, FN_MSIOF0_TXD_B,
4048 FN_DACK1, FN_IRQ1, FN_INTC_IRQ1_N, FN_SSI_WS6_B,
4049 FN_SSI_SDATA8_C, 0, 0, 0,
4051 FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B,
4052 FN_SSI_SDATA7_C, FN_SSI_SCK78_B, 0, 0, 0,
4054 FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B,
4055 FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 0, }
4057 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
4058 1, 2, 2, 2, 3, 3, 3, 3, 3, 2, 2, 3, 3) {
4062 FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2, 0,
4064 FN_VI0_CLK, FN_ATACS00_N, FN_AVB_RXD1, 0,
4066 FN_DU_DOTCLKIN1, FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, 0,
4068 FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C, FN_PCMWE_N, FN_IECLK_C,
4071 FN_PWM1, FN_SCIFA2_TXD_C, FN_STP_ISSYNC_1_B, FN_TS_SCK1_C,
4072 FN_GLO_RFON_C, FN_PCMOE_N, 0, 0,
4074 FN_PWM0, FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C,
4075 FN_GLO_SS_C, 0, 0, 0,
4077 FN_ETH_MDC, 0, FN_STP_ISD_1_B,
4078 FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, 0, 0, 0,
4080 FN_ETH_TXD0, 0, FN_STP_ISCLK_1_B, FN_TS_SDEN1_C,
4081 FN_GLO_SCLK_C, 0, 0, 0,
4083 FN_ETH_MAGIC, 0, FN_SIM0_RST_C, 0,
4085 FN_ETH_TX_EN, 0, FN_SIM0_CLK_C, FN_HRTS0_N_F,
4087 FN_ETH_TXD1, 0, FN_HTX0_F, FN_BPFCLK_G, 0, 0, 0, 0,
4089 FN_ETH_MDIO, 0, FN_HRTS0_N_E,
4090 FN_SIM0_D_C, FN_HCTS0_N_F, 0, 0, 0, }
4092 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
4093 1, 2, 1, 1, 1, 2, 2, 2, 2, 2, 2,
4094 2, 2, 2, 2, 2, 2, 2) {
4098 FN_SD0_CMD, FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B, 0,
4100 FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B,
4102 FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK,
4104 FN_VI1_DATA5_VI1_B5, FN_AVB_PHY_INT,
4106 FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D,
4109 FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D, FN_AVB_GTX_CLK, 0,
4111 FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO, 0,
4113 FN_VI1_DATA1_VI1_B1, FN_SCIFA1_RXD_D, FN_AVB_MDC, 0,
4115 FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D, FN_AVB_CRS, 0,
4117 FN_VI1_CLK, FN_AVB_RX_DV, 0, 0,
4119 FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK, 0, 0,
4121 FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER, 0, 0,
4123 FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1, FN_AVB_RXD7, 0,
4125 FN_VI0_DATA4_VI0_B4, FN_ATAG0_N, FN_AVB_RXD6, 0,
4127 FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N, FN_AVB_RXD5, 0,
4129 FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N, FN_AVB_RXD4, 0,
4131 FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3, 0, }
4133 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
4134 4, 2, 2, 2, 2, 2, 2, 4, 4, 2, 2, 2, 2) {
4136 FN_SD1_CD, FN_MMC1_D6, FN_TS_SDEN1, FN_USB1_EXTP,
4137 FN_GLO_SS, FN_VI0_CLK_B, FN_IIC2_SCL_D, FN_I2C2_SCL_D,
4138 FN_SIM0_CLK_B, FN_VI3_CLK_B, 0, 0, 0, 0, 0, 0,
4140 FN_SD1_DAT3, FN_AVB_RXD0, 0, FN_SCIFB0_RTS_N_B,
4142 FN_SD1_DAT2, FN_AVB_COL, 0, FN_SCIFB0_CTS_N_B,
4144 FN_SD1_DAT1, FN_AVB_LINK, 0, FN_SCIFB0_TXD_B,
4146 FN_SD1_DAT0, FN_AVB_TX_CLK, 0, FN_SCIFB0_RXD_B,
4148 FN_SD1_CMD, FN_AVB_TX_ER, 0, FN_SCIFB0_SCK_B,
4150 FN_SD1_CLK, FN_AVB_TX_EN, 0, 0,
4152 FN_SD0_WP, FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN,
4153 FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_IIC1_SDA_B,
4154 FN_I2C1_SDA_B, FN_VI2_DATA7_VI2_B7_B, 0, 0, 0, 0, 0, 0, 0,
4156 FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP,
4157 FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_IIC1_SCL_B,
4158 FN_I2C1_SCL_B, FN_VI2_DATA6_VI2_B6_B, 0, 0, 0, 0, 0, 0, 0,
4160 FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B, 0,
4162 FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B, 0,
4164 FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B, 0,
4166 FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B, 0, }
4168 { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
4169 2, 4, 3, 4, 4, 4, 4, 3, 4) {
4170 /* IP10_31_30 [2] */
4172 /* IP10_29_26 [4] */
4173 FN_SD2_CD, FN_MMC0_D4, FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0,
4174 FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B,
4175 FN_GLO_I0_B, FN_VI3_DATA6_B, 0, 0, 0, 0, 0, 0,
4176 /* IP10_25_23 [3] */
4177 FN_SD2_DAT3, FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B,
4178 FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B, FN_VI3_DATA5_B,
4179 /* IP10_22_19 [4] */
4180 FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B, 0,
4181 FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B,
4182 FN_GLO_Q0_B, FN_VI3_DATA4_B, 0, 0, 0, 0, 0, 0, 0,
4183 /* IP10_18_15 [4] */
4184 FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B, 0,
4185 FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D,
4186 FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B,
4188 /* IP10_14_11 [4] */
4189 FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B,
4190 FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D,
4191 FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B,
4192 0, 0, 0, 0, 0, 0, 0,
4194 FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D,
4195 FN_VI0_DATA1_VI0_B1_B, FN_SCIFB1_SCK_E, FN_SCK1_D,
4196 FN_TS_SPSYNC0_C, FN_GLO_SDATA_B, FN_VI3_DATA1_B,
4197 0, 0, 0, 0, 0, 0, 0,
4199 FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK,
4200 FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B,
4203 FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN,
4204 FN_GLO_RFON, FN_VI1_CLK_B, FN_IIC2_SDA_D, FN_I2C2_SDA_D,
4205 FN_SIM0_D_B, 0, 0, 0, 0, 0, 0, 0, }
4207 { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
4208 2, 3, 3, 2, 4, 3, 2, 2, 2, 2, 2, 1, 4) {
4209 /* IP11_31_30 [2] */
4210 FN_SSI_SCK0129, FN_CAN_CLK_B, FN_MOUT0, 0,
4211 /* IP11_29_27 [3] */
4212 FN_MLB_DAT, 0, FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C,
4214 /* IP11_26_24 [3] */
4215 FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_IIC2_SDA_B, FN_I2C2_SDA_B,
4217 /* IP11_23_22 [2] */
4218 FN_MLB_CLK, FN_IIC2_SCL_B, FN_I2C2_SCL_B, 0,
4219 /* IP11_21_18 [4] */
4220 FN_SD3_WP, FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C,
4221 0, FN_FMIN_E, 0, FN_FMIN_F, 0, 0, 0, 0, 0, 0, 0,
4222 /* IP11_17_15 [3] */
4223 FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1,
4224 FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, 0, 0,
4225 /* IP11_14_13 [2] */
4226 FN_SD3_DAT3, FN_MMC1_D3, FN_SCKZ, 0,
4227 /* IP11_12_11 [2] */
4228 FN_SD3_DAT2, FN_MMC1_D2, FN_SDATA, 0,
4230 FN_SD3_DAT1, FN_MMC1_D1, FN_MDATA, 0,
4232 FN_SD3_DAT0, FN_MMC1_D0, FN_STM_N, 0,
4234 FN_SD3_CMD, FN_MMC1_CMD, FN_MTS_N, 0,
4236 FN_SD3_CLK, FN_MMC1_CLK,
4238 FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN,
4239 FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D,
4240 FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B, 0, 0, 0, 0, 0, 0, }
4242 { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
4243 1, 3, 3, 2, 3, 3, 3, 3, 3, 2, 2, 2, 2) {
4246 /* IP12_30_28 [3] */
4247 FN_SSI_WS5, FN_SCIFB1_RXD, FN_IECLK_B,
4248 FN_DU2_EXVSYNC_DU2_VSYNC, FN_QSTB_QHE,
4249 FN_CAN_DEBUGOUT4, 0, 0,
4250 /* IP12_27_25 [3] */
4251 FN_SSI_SCK5, FN_SCIFB1_SCK,
4252 FN_IERX_B, FN_DU2_EXHSYNC_DU2_HSYNC, FN_QSTH_QHS,
4253 FN_CAN_DEBUGOUT3, 0, 0,
4254 /* IP12_24_23 [2] */
4255 FN_SSI_SDATA4, FN_STP_ISSYNC_0, FN_MSIOF1_RXD,
4257 /* IP12_22_20 [3] */
4258 FN_SSI_WS4, FN_STP_ISEN_0, FN_SCIFB0_RTS_N,
4259 FN_MSIOF1_TXD, FN_SSI_WS5_C, FN_CAN_DEBUGOUT1, 0, 0,
4260 /* IP12_19_17 [3] */
4261 FN_SSI_SCK4, FN_STP_ISD_0, FN_SCIFB0_CTS_N,
4262 FN_MSIOF1_SS2, FN_SSI_SCK5_C, FN_CAN_DEBUGOUT0, 0, 0,
4263 /* IP12_16_14 [3] */
4264 FN_SSI_SDATA3, FN_STP_ISCLK_0,
4265 FN_SCIFB0_TXD, FN_MSIOF1_SS1, FN_CAN_TXCLK, 0, 0, 0,
4266 /* IP12_13_11 [3] */
4267 FN_SSI_WS34, FN_STP_IVCXO27_0, FN_SCIFB0_RXD, FN_MSIOF1_SYNC,
4268 FN_CAN_STEP0, 0, 0, 0,
4270 FN_SSI_SCK34, FN_STP_OPWM_0, FN_SCIFB0_SCK,
4271 FN_MSIOF1_SCK, FN_CAN_DEBUG_HW_TRIGGER, 0, 0, 0,
4273 FN_SSI_SDATA2, FN_CAN1_RX_B, FN_SSI_SCK1, FN_MOUT6,
4275 FN_SSI_SDATA1, FN_CAN1_TX_B, FN_MOUT5, 0,
4277 FN_SSI_SDATA0, FN_CAN0_RX_B, FN_MOUT2, 0,
4279 FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1, 0, }
4281 { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
4282 1, 2, 3, 3, 4, 3, 3, 3, 3, 4, 3) {
4285 /* IP13_30_29 [2] */
4286 FN_AUDIO_CLKA, FN_SCIFB2_RTS_N, FN_CAN_DEBUGOUT14, 0,
4287 /* IP13_28_26 [3] */
4288 FN_SSI_SDATA9, FN_STP_ISSYNC_1, FN_SCIFB2_CTS_N, FN_SSI_WS1,
4289 FN_SSI_SDATA5_C, FN_CAN_DEBUGOUT13, 0, 0,
4290 /* IP13_25_23 [3] */
4291 FN_SSI_SDATA8, FN_STP_ISEN_1, FN_SCIFB2_TXD, FN_CAN0_TX_C,
4292 FN_CAN_DEBUGOUT12, FN_SSI_SDATA8_B, 0, 0,
4293 /* IP13_22_19 [4] */
4294 FN_SSI_SDATA7, FN_STP_ISD_1, FN_SCIFB2_RXD, FN_SCIFA2_RTS_N,
4295 FN_TCLK2, FN_QSTVA_QVS, FN_CAN_DEBUGOUT11, FN_BPFCLK_E,
4296 0, FN_SSI_SDATA7_B, FN_FMIN_G, 0, 0, 0, 0, 0,
4297 /* IP13_18_16 [3] */
4298 FN_SSI_WS78, FN_STP_ISCLK_1, FN_SCIFB2_SCK, FN_SCIFA2_CTS_N,
4299 FN_DU2_DR7, FN_LCDOUT7, FN_CAN_DEBUGOUT10, 0,
4300 /* IP13_15_13 [3] */
4301 FN_SSI_SCK78, FN_STP_IVCXO27_1, FN_SCK1, FN_SCIFA1_SCK,
4302 FN_DU2_DR6, FN_LCDOUT6, FN_CAN_DEBUGOUT9, 0,
4303 /* IP13_12_10 [3] */
4304 FN_SSI_SDATA6, FN_FMIN_D, 0, FN_DU2_DR5, FN_LCDOUT5,
4305 FN_CAN_DEBUGOUT8, 0, 0,
4307 FN_SSI_WS6, FN_SCIFB1_RTS_N, FN_CAN0_TX_D, FN_DU2_DR4,
4308 FN_LCDOUT4, FN_CAN_DEBUGOUT7, 0, 0,
4310 FN_SSI_SCK6, FN_SCIFB1_CTS_N, FN_BPFCLK_D, 0,
4311 FN_DU2_DR3, FN_LCDOUT3, FN_CAN_DEBUGOUT6,
4312 FN_BPFCLK_F, 0, 0, 0, 0, 0, 0, 0, 0,
4314 FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2,
4315 FN_LCDOUT2, FN_CAN_DEBUGOUT5, 0, 0, }
4317 { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32,
4318 1, 3, 3, 3, 3, 3, 4, 3, 3, 3, 3) {
4321 /* IP14_30_28 [3] */
4322 FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N,
4323 FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE,
4325 /* IP14_27_25 [3] */
4326 FN_SCIFA1_CTS_N, FN_AD_CLK, FN_CTS1_N, FN_MSIOF3_RXD,
4327 FN_DU0_DOTCLKOUT, FN_QCLK, 0, 0,
4328 /* IP14_24_22 [3] */
4329 FN_SCIFA1_TXD, FN_AD_DO, FN_TX1, FN_DU2_DG1,
4330 FN_LCDOUT9, 0, 0, 0,
4331 /* IP14_21_19 [3] */
4332 FN_SCIFA1_RXD, FN_AD_DI, FN_RX1,
4333 FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, FN_QCPV_QDE, 0, 0, 0,
4334 /* IP14_18_16 [3] */
4335 FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N,
4336 FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B, 0,
4337 /* IP14_15_12 [4] */
4338 FN_SCIFA0_CTS_N, FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC,
4339 FN_DU2_DG3, FN_LCDOUT11, FN_PWM0_B, FN_IIC1_SCL_C, FN_I2C1_SCL_C,
4340 0, 0, 0, 0, 0, 0, 0,
4342 FN_SCIFA0_TXD, FN_HTX1, FN_TX0, FN_DU2_DR1, FN_LCDOUT1,
4345 FN_SCIFA0_RXD, FN_HRX1, FN_RX0, FN_DU2_DR0, FN_LCDOUT0,
4348 FN_SCIFA0_SCK, FN_HSCK1, FN_SCK0, FN_MSIOF3_SS2, FN_DU2_DG2,
4349 FN_LCDOUT10, FN_IIC1_SDA_C, FN_I2C1_SDA_C,
4351 FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D,
4352 FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15,
4355 { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32,
4356 2, 2, 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3) {
4357 /* IP15_31_30 [2] */
4359 /* IP15_29_28 [2] */
4360 FN_MSIOF0_TXD, FN_ADICHS1, FN_DU2_DG6, FN_LCDOUT14,
4361 /* IP15_27_26 [2] */
4362 FN_MSIOF0_SS1, FN_ADICHS0, FN_DU2_DG5, FN_LCDOUT13,
4363 /* IP15_25_23 [3] */
4364 FN_MSIOF0_SYNC, FN_TS_SCK0, FN_SSI_SCK2, FN_ADIDATA,
4365 FN_DU2_DB7, FN_LCDOUT23, FN_HRX0_C, 0,
4366 /* IP15_22_20 [3] */
4367 FN_MSIOF0_SCK, FN_TS_SDAT0, FN_ADICLK,
4368 FN_DU2_DB6, FN_LCDOUT22, 0, 0, 0,
4369 /* IP15_19_18 [2] */
4370 FN_HRTS0_N, FN_SSI_WS9, FN_DU2_DB5, FN_LCDOUT21,
4371 /* IP15_17_16 [2] */
4372 FN_HCTS0_N, FN_SSI_SCK9, FN_DU2_DB4, FN_LCDOUT20,
4373 /* IP15_15_14 [2] */
4374 FN_HTX0, FN_DU2_DB3, FN_LCDOUT19, 0,
4375 /* IP15_13_12 [2] */
4376 FN_HRX0, FN_DU2_DB2, FN_LCDOUT18, 0,
4378 FN_HSCK0, FN_TS_SDEN0, FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C,
4381 FN_SCIFA2_TXD, FN_BPFCLK, FN_RX2, FN_DU2_DB1, FN_LCDOUT17,
4382 FN_IIC2_SDA, FN_I2C2_SDA, 0,
4384 FN_SCIFA2_RXD, FN_FMIN, FN_TX2, FN_DU2_DB0, FN_LCDOUT16,
4385 FN_IIC2_SCL, FN_I2C2_SCL, 0,
4387 FN_SCIFA2_SCK, FN_FMCLK, FN_SCK2, FN_MSIOF3_SCK, FN_DU2_DG7,
4388 FN_LCDOUT15, FN_SCIF_CLK_B, 0, }
4390 { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32,
4391 4, 4, 4, 4, 4, 4, 1, 1, 3, 3) {
4392 /* IP16_31_28 [4] */
4393 0, 0, 0, 0, 0, 0, 0, 0,
4394 0, 0, 0, 0, 0, 0, 0, 0,
4395 /* IP16_27_24 [4] */
4396 0, 0, 0, 0, 0, 0, 0, 0,
4397 0, 0, 0, 0, 0, 0, 0, 0,
4398 /* IP16_23_20 [4] */
4399 0, 0, 0, 0, 0, 0, 0, 0,
4400 0, 0, 0, 0, 0, 0, 0, 0,
4401 /* IP16_19_16 [4] */
4402 0, 0, 0, 0, 0, 0, 0, 0,
4403 0, 0, 0, 0, 0, 0, 0, 0,
4404 /* IP16_15_12 [4] */
4405 0, 0, 0, 0, 0, 0, 0, 0,
4406 0, 0, 0, 0, 0, 0, 0, 0,
4408 0, 0, 0, 0, 0, 0, 0, 0,
4409 0, 0, 0, 0, 0, 0, 0, 0,
4411 FN_USB1_OVC, FN_TCLK1_B,
4413 FN_USB1_PWEN, FN_AUDIO_CLKOUT_D,
4415 FN_MSIOF0_RXD, FN_TS_SPSYNC0, FN_SSI_WS2,
4416 FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_SCIFA2_RXD_B, 0,
4418 FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2,
4419 FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B, 0, }
4421 { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
4422 3, 2, 2, 3, 2, 1, 1, 1, 2, 1,
4423 2, 1, 1, 1, 1, 2, 1, 1, 2, 1, 1) {
4425 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
4426 FN_SEL_SCIF1_4, 0, 0, 0,
4428 FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, 0,
4429 /* SEL_SCIFB2 [2] */
4430 FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, 0,
4431 /* SEL_SCIFB1 [3] */
4432 FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2,
4433 FN_SEL_SCIFB1_3, FN_SEL_SCIFB1_4, FN_SEL_SCIFB1_5,
4435 /* SEL_SCIFA1 [2] */
4436 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2,
4439 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1,
4441 FN_SEL_SCFA_0, FN_SEL_SCFA_1,
4443 FN_SEL_SOF1_0, FN_SEL_SOF1_1,
4445 FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2, 0,
4447 FN_SEL_SSI6_0, FN_SEL_SSI6_1,
4449 FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2, 0,
4451 FN_SEL_VI3_0, FN_SEL_VI3_1,
4453 FN_SEL_VI2_0, FN_SEL_VI2_1,
4455 FN_SEL_VI1_0, FN_SEL_VI1_1,
4457 FN_SEL_VI0_0, FN_SEL_VI0_1,
4459 FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2, 0,
4463 FN_SEL_LBS_0, FN_SEL_LBS_1,
4465 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
4467 FN_SEL_SOF3_0, FN_SEL_SOF3_1,
4469 FN_SEL_SOF0_0, FN_SEL_SOF0_1, }
4471 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
4472 3, 1, 1, 1, 2, 1, 2, 1, 2,
4473 1, 1, 1, 3, 3, 2, 3, 2, 2) {
4475 0, 0, 0, 0, 0, 0, 0, 0,
4477 FN_SEL_TMU1_0, FN_SEL_TMU1_1,
4478 /* SEL_HSCIF1 [1] */
4479 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
4480 /* SEL_SCIFCLK [1] */
4481 FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1,
4483 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
4484 /* SEL_CANCLK [1] */
4485 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
4486 /* SEL_SCIFA2 [2] */
4487 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2, 0,
4489 FN_SEL_CAN1_0, FN_SEL_CAN1_1,
4493 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1,
4495 FN_SEL_ADI_0, FN_SEL_ADI_1,
4497 FN_SEL_SSP_0, FN_SEL_SSP_1,
4499 FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3,
4500 FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6, 0,
4501 /* SEL_HSCIF0 [3] */
4502 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2,
4503 FN_SEL_HSCIF0_3, FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5, 0, 0,
4505 FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, 0,
4507 0, 0, 0, 0, 0, 0, 0, 0,
4509 FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2, 0,
4511 FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, 0, }
4513 { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
4514 1, 1, 2, 4, 4, 2, 2,
4516 /* SEL_IICDVFS [1] */
4517 FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1,
4519 FN_SEL_IIC0_0, FN_SEL_IIC0_1,
4523 0, 0, 0, 0, 0, 0, 0, 0,
4524 0, 0, 0, 0, 0, 0, 0, 0,
4526 0, 0, 0, 0, 0, 0, 0, 0,
4527 0, 0, 0, 0, 0, 0, 0, 0,
4531 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
4533 0, 0, 0, 0, 0, 0, 0, 0,
4534 0, 0, 0, 0, 0, 0, 0, 0,
4538 FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
4539 FN_SEL_IIC2_4, 0, 0, 0,
4541 FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, 0,
4543 FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
4544 FN_SEL_I2C2_4, 0, 0, 0,
4546 FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, 0, }
4551 const struct sh_pfc_soc_info r8a7790_pinmux_info = {
4552 .name = "r8a77900_pfc",
4553 .unlock_reg = 0xe6060000, /* PMMR */
4555 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
4557 .pins = pinmux_pins,
4558 .nr_pins = ARRAY_SIZE(pinmux_pins),
4559 .groups = pinmux_groups,
4560 .nr_groups = ARRAY_SIZE(pinmux_groups),
4561 .functions = pinmux_functions,
4562 .nr_functions = ARRAY_SIZE(pinmux_functions),
4564 .cfg_regs = pinmux_config_regs,
4566 .gpio_data = pinmux_data,
4567 .gpio_data_size = ARRAY_SIZE(pinmux_data),