drivers/pinctrl/sh-pfc/pfc-r8a7792.c

   1 /*
   2  * r8a7792 processor support - PFC hardware block.
   3  *
   4  * Copyright (C) 2013-2014 Renesas Electronics Corporation
   5  * Copyright (C) 2016 Cogent Embedded, Inc., <source@cogentembedded.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2
   9  * as published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/kernel.h>
  13
  14 #include "core.h"
  15 #include "sh_pfc.h"
  16
  17 #define CPU_ALL_PORT(fn, sfx)                                           \
  18         PORT_GP_29(0, fn, sfx),                                         \
  19         PORT_GP_23(1, fn, sfx),                                         \
  20         PORT_GP_32(2, fn, sfx),                                         \
  21         PORT_GP_28(3, fn, sfx),                                         \
  22         PORT_GP_17(4, fn, sfx),                                         \
  23         PORT_GP_17(5, fn, sfx),                                         \
  24         PORT_GP_17(6, fn, sfx),                                         \
  25         PORT_GP_17(7, fn, sfx),                                         \
  26         PORT_GP_17(8, fn, sfx),                                         \
  27         PORT_GP_17(9, fn, sfx),                                         \
  28         PORT_GP_32(10, fn, sfx),                                        \
  29         PORT_GP_30(11, fn, sfx)
  30
  31 enum {
  32         PINMUX_RESERVED = 0,
  33
  34         PINMUX_DATA_BEGIN,
  35         GP_ALL(DATA),
  36         PINMUX_DATA_END,
  37
  38         PINMUX_FUNCTION_BEGIN,
  39         GP_ALL(FN),
  40
  41         /* GPSR0 */
  42         FN_IP0_0, FN_IP0_1, FN_IP0_2, FN_IP0_3, FN_IP0_4, FN_IP0_5,
  43         FN_IP0_6, FN_IP0_7, FN_IP0_8, FN_IP0_9, FN_IP0_10, FN_IP0_11,
  44         FN_IP0_12, FN_IP0_13, FN_IP0_14, FN_IP0_15, FN_IP0_16,
  45         FN_IP0_17, FN_IP0_18, FN_IP0_19, FN_IP0_20, FN_IP0_21,
  46         FN_IP0_22, FN_IP0_23, FN_IP1_0, FN_IP1_1, FN_IP1_2,
  47         FN_IP1_3, FN_IP1_4,
  48
  49         /* GPSR1 */
  50         FN_IP1_5, FN_IP1_6, FN_IP1_7, FN_IP1_8, FN_IP1_9, FN_IP1_10,
  51         FN_IP1_11, FN_IP1_12, FN_IP1_13, FN_IP1_14, FN_IP1_15, FN_IP1_16,
  52         FN_DU1_DB2_C0_DATA12, FN_DU1_DB3_C1_DATA13, FN_DU1_DB4_C2_DATA14,
  53         FN_DU1_DB5_C3_DATA15, FN_DU1_DB6_C4, FN_DU1_DB7_C5,
  54         FN_DU1_EXHSYNC_DU1_HSYNC, FN_DU1_EXVSYNC_DU1_VSYNC,
  55         FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_DU1_DISP, FN_DU1_CDE,
  56
  57         /* GPSR2 */
  58         FN_D0, FN_D1, FN_D2, FN_D3, FN_D4, FN_D5, FN_D6, FN_D7,
  59         FN_D8, FN_D9, FN_D10, FN_D11, FN_D12, FN_D13, FN_D14, FN_D15,
  60         FN_A0, FN_A1, FN_A2, FN_A3, FN_A4, FN_A5, FN_A6, FN_A7,
  61         FN_A8, FN_A9, FN_A10, FN_A11, FN_A12, FN_A13, FN_A14, FN_A15,
  62
  63         /* GPSR3 */
  64         FN_A16, FN_A17, FN_A18, FN_A19, FN_IP1_17, FN_IP1_18,
  65         FN_CS1_N_A26, FN_EX_CS0_N, FN_EX_CS1_N, FN_EX_CS2_N, FN_EX_CS3_N,
  66         FN_EX_CS4_N, FN_EX_CS5_N, FN_BS_N, FN_RD_N, FN_RD_WR_N,
  67         FN_WE0_N, FN_WE1_N, FN_EX_WAIT0, FN_IRQ0, FN_IRQ1, FN_IRQ2, FN_IRQ3,
  68         FN_IP1_19, FN_IP1_20, FN_IP1_21, FN_IP1_22, FN_CS0_N,
  69
  70         /* GPSR4 */
  71         FN_VI0_CLK, FN_VI0_CLKENB, FN_VI0_HSYNC_N, FN_VI0_VSYNC_N,
  72         FN_VI0_D0_B0_C0, FN_VI0_D1_B1_C1, FN_VI0_D2_B2_C2, FN_VI0_D3_B3_C3,
  73         FN_VI0_D4_B4_C4, FN_VI0_D5_B5_C5, FN_VI0_D6_B6_C6, FN_VI0_D7_B7_C7,
  74         FN_VI0_D8_G0_Y0, FN_VI0_D9_G1_Y1, FN_VI0_D10_G2_Y2, FN_VI0_D11_G3_Y3,
  75         FN_VI0_FIELD,
  76
  77         /* GPSR5 */
  78         FN_VI1_CLK, FN_VI1_CLKENB, FN_VI1_HSYNC_N, FN_VI1_VSYNC_N,
  79         FN_VI1_D0_B0_C0, FN_VI1_D1_B1_C1, FN_VI1_D2_B2_C2, FN_VI1_D3_B3_C3,
  80         FN_VI1_D4_B4_C4, FN_VI1_D5_B5_C5, FN_VI1_D6_B6_C6, FN_VI1_D7_B7_C7,
  81         FN_VI1_D8_G0_Y0, FN_VI1_D9_G1_Y1, FN_VI1_D10_G2_Y2, FN_VI1_D11_G3_Y3,
  82         FN_VI1_FIELD,
  83
  84         /* GPSR6 */
  85         FN_IP2_0, FN_IP2_1, FN_IP2_2, FN_IP2_3, FN_IP2_4, FN_IP2_5, FN_IP2_6,
  86         FN_IP2_7, FN_IP2_8, FN_IP2_9, FN_IP2_10, FN_IP2_11, FN_IP2_12,
  87         FN_IP2_13, FN_IP2_14, FN_IP2_15, FN_IP2_16,
  88
  89         /* GPSR7 */
  90         FN_IP3_0, FN_IP3_1, FN_IP3_2, FN_IP3_3, FN_IP3_4, FN_IP3_5, FN_IP3_6,
  91         FN_IP3_7, FN_IP3_8, FN_IP3_9, FN_IP3_10, FN_IP3_11, FN_IP3_12,
  92         FN_IP3_13, FN_VI3_D10_Y2, FN_IP3_14, FN_VI3_FIELD,
  93
  94         /* GPSR8 */
  95         FN_VI4_CLK, FN_IP4_0, FN_IP4_1, FN_IP4_3_2, FN_IP4_4, FN_IP4_6_5,
  96         FN_IP4_8_7, FN_IP4_10_9, FN_IP4_12_11, FN_IP4_14_13, FN_IP4_16_15,
  97         FN_IP4_18_17, FN_IP4_20_19, FN_IP4_21, FN_IP4_22, FN_IP4_23, FN_IP4_24,
  98
  99         /* GPSR9 */
 100         FN_VI5_CLK, FN_IP5_0, FN_IP5_1, FN_IP5_2, FN_IP5_3, FN_IP5_4, FN_IP5_5,
 101         FN_IP5_6, FN_IP5_7, FN_IP5_8, FN_IP5_9, FN_IP5_10, FN_IP5_11,
 102         FN_VI5_D9_Y1, FN_VI5_D10_Y2, FN_VI5_D11_Y3, FN_VI5_FIELD,
 103
 104         /* GPSR10 */
 105         FN_IP6_0, FN_IP6_1, FN_HRTS0_N, FN_IP6_2, FN_IP6_3, FN_IP6_4, FN_IP6_5,
 106         FN_HCTS1_N, FN_IP6_6, FN_IP6_7, FN_SCK0, FN_CTS0_N, FN_RTS0_N,
 107         FN_TX0, FN_RX0, FN_SCK1, FN_CTS1_N, FN_RTS1_N, FN_TX1, FN_RX1,
 108         FN_IP6_9_8, FN_IP6_11_10, FN_IP6_13_12, FN_IP6_15_14, FN_IP6_16,
 109         FN_IP6_18_17, FN_SCIF_CLK, FN_CAN0_TX, FN_CAN0_RX, FN_CAN_CLK,
 110         FN_CAN1_TX, FN_CAN1_RX,
 111
 112         /* GPSR11 */
 113         FN_IP7_1_0, FN_IP7_3_2, FN_IP7_5_4, FN_IP7_6, FN_IP7_7, FN_SD0_CLK,
 114         FN_SD0_CMD, FN_SD0_DAT0, FN_SD0_DAT1, FN_SD0_DAT2, FN_SD0_DAT3,
 115         FN_SD0_CD, FN_SD0_WP, FN_IP7_9_8, FN_IP7_11_10, FN_IP7_13_12,
 116         FN_IP7_15_14, FN_IP7_16, FN_IP7_17, FN_IP7_18, FN_IP7_19, FN_IP7_20,
 117         FN_ADICLK, FN_ADICS_SAMP, FN_ADIDATA, FN_ADICHS0, FN_ADICHS1,
 118         FN_ADICHS2, FN_AVS1, FN_AVS2,
 119
 120         /* IPSR0 */
 121         FN_DU0_DR0_DATA0, FN_DU0_DR1_DATA1, FN_DU0_DR2_Y4_DATA2,
 122         FN_DU0_DR3_Y5_DATA3, FN_DU0_DR4_Y6_DATA4, FN_DU0_DR5_Y7_DATA5,
 123         FN_DU0_DR6_Y8_DATA6, FN_DU0_DR7_Y9_DATA7, FN_DU0_DG0_DATA8,
 124         FN_DU0_DG1_DATA9, FN_DU0_DG2_C6_DATA10, FN_DU0_DG3_C7_DATA11,
 125         FN_DU0_DG4_Y0_DATA12, FN_DU0_DG5_Y1_DATA13, FN_DU0_DG6_Y2_DATA14,
 126         FN_DU0_DG7_Y3_DATA15, FN_DU0_DB0, FN_DU0_DB1, FN_DU0_DB2_C0,
 127         FN_DU0_DB3_C1, FN_DU0_DB4_C2, FN_DU0_DB5_C3, FN_DU0_DB6_C4,
 128         FN_DU0_DB7_C5,
 129
 130         /* IPSR1 */
 131         FN_DU0_EXHSYNC_DU0_HSYNC, FN_DU0_EXVSYNC_DU0_VSYNC,
 132         FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_DU0_DISP, FN_DU0_CDE,
 133         FN_DU1_DR2_Y4_DATA0, FN_DU1_DR3_Y5_DATA1, FN_DU1_DR4_Y6_DATA2,
 134         FN_DU1_DR5_Y7_DATA3, FN_DU1_DR6_DATA4, FN_DU1_DR7_DATA5,
 135         FN_DU1_DG2_C6_DATA6, FN_DU1_DG3_C7_DATA7, FN_DU1_DG4_Y0_DATA8,
 136         FN_DU1_DG5_Y1_DATA9, FN_DU1_DG6_Y2_DATA10, FN_DU1_DG7_Y3_DATA11,
 137         FN_A20, FN_MOSI_IO0, FN_A21, FN_MISO_IO1, FN_A22, FN_IO2,
 138         FN_A23, FN_IO3, FN_A24, FN_SPCLK, FN_A25, FN_SSL,
 139
 140         /* IPSR2 */
 141         FN_VI2_CLK, FN_AVB_RX_CLK, FN_VI2_CLKENB, FN_AVB_RX_DV,
 142         FN_VI2_HSYNC_N, FN_AVB_RXD0, FN_VI2_VSYNC_N, FN_AVB_RXD1,
 143         FN_VI2_D0_C0, FN_AVB_RXD2, FN_VI2_D1_C1, FN_AVB_RXD3,
 144         FN_VI2_D2_C2, FN_AVB_RXD4, FN_VI2_D3_C3, FN_AVB_RXD5,
 145         FN_VI2_D4_C4, FN_AVB_RXD6, FN_VI2_D5_C5, FN_AVB_RXD7,
 146         FN_VI2_D6_C6, FN_AVB_RX_ER, FN_VI2_D7_C7, FN_AVB_COL,
 147         FN_VI2_D8_Y0, FN_AVB_TXD3, FN_VI2_D9_Y1, FN_AVB_TX_EN,
 148         FN_VI2_D10_Y2, FN_AVB_TXD0, FN_VI2_D11_Y3, FN_AVB_TXD1,
 149         FN_VI2_FIELD, FN_AVB_TXD2,
 150
 151         /* IPSR3 */
 152         FN_VI3_CLK, FN_AVB_TX_CLK, FN_VI3_CLKENB, FN_AVB_TXD4,
 153         FN_VI3_HSYNC_N, FN_AVB_TXD5, FN_VI3_VSYNC_N, FN_AVB_TXD6,
 154         FN_VI3_D0_C0, FN_AVB_TXD7, FN_VI3_D1_C1, FN_AVB_TX_ER,
 155         FN_VI3_D2_C2, FN_AVB_GTX_CLK, FN_VI3_D3_C3, FN_AVB_MDC,
 156         FN_VI3_D4_C4, FN_AVB_MDIO, FN_VI3_D5_C5, FN_AVB_LINK,
 157         FN_VI3_D6_C6, FN_AVB_MAGIC, FN_VI3_D7_C7, FN_AVB_PHY_INT,
 158         FN_VI3_D8_Y0, FN_AVB_CRS, FN_VI3_D9_Y1, FN_AVB_GTXREFCLK,
 159         FN_VI3_D11_Y3, FN_AVB_AVTP_MATCH,
 160
 161         /* IPSR4 */
 162         FN_VI4_CLKENB, FN_VI0_D12_G4_Y4, FN_VI4_HSYNC_N, FN_VI0_D13_G5_Y5,
 163         FN_VI4_VSYNC_N, FN_VI0_D14_G6_Y6, FN_RDR_CLKOUT,
 164         FN_VI4_D0_C0, FN_VI0_D15_G7_Y7,
 165         FN_VI4_D1_C1, FN_VI0_D16_R0, FN_VI1_D12_G4_Y4,
 166         FN_VI4_D2_C2, FN_VI0_D17_R1, FN_VI1_D13_G5_Y5,
 167         FN_VI4_D3_C3, FN_VI0_D18_R2, FN_VI1_D14_G6_Y6,
 168         FN_VI4_D4_C4, FN_VI0_D19_R3, FN_VI1_D15_G7_Y7,
 169         FN_VI4_D5_C5, FN_VI0_D20_R4, FN_VI2_D12_Y4,
 170         FN_VI4_D6_C6, FN_VI0_D21_R5, FN_VI2_D13_Y5,
 171         FN_VI4_D7_C7, FN_VI0_D22_R6, FN_VI2_D14_Y6,
 172         FN_VI4_D8_Y0, FN_VI0_D23_R7, FN_VI2_D15_Y7,
 173         FN_VI4_D9_Y1, FN_VI3_D12_Y4, FN_VI4_D10_Y2, FN_VI3_D13_Y5,
 174         FN_VI4_D11_Y3, FN_VI3_D14_Y6, FN_VI4_FIELD, FN_VI3_D15_Y7,
 175
 176         /* IPSR5 */
 177         FN_VI5_CLKENB, FN_VI1_D12_G4_Y4_B, FN_VI5_HSYNC_N, FN_VI1_D13_G5_Y5_B,
 178         FN_VI5_VSYNC_N, FN_VI1_D14_G6_Y6_B, FN_VI5_D0_C0, FN_VI1_D15_G7_Y7_B,
 179         FN_VI5_D1_C1, FN_VI1_D16_R0, FN_VI5_D2_C2, FN_VI1_D17_R1,
 180         FN_VI5_D3_C3, FN_VI1_D18_R2, FN_VI5_D4_C4, FN_VI1_D19_R3,
 181         FN_VI5_D5_C5, FN_VI1_D20_R4, FN_VI5_D6_C6, FN_VI1_D21_R5,
 182         FN_VI5_D7_C7, FN_VI1_D22_R6, FN_VI5_D8_Y0, FN_VI1_D23_R7,
 183
 184         /* IPSR6 */
 185         FN_MSIOF0_SCK, FN_HSCK0, FN_MSIOF0_SYNC, FN_HCTS0_N,
 186         FN_MSIOF0_TXD, FN_HTX0, FN_MSIOF0_RXD, FN_HRX0,
 187         FN_MSIOF1_SCK, FN_HSCK1, FN_MSIOF1_SYNC, FN_HRTS1_N,
 188         FN_MSIOF1_TXD, FN_HTX1, FN_MSIOF1_RXD, FN_HRX1,
 189         FN_DRACK0, FN_SCK2, FN_DACK0, FN_TX2, FN_DREQ0_N, FN_RX2,
 190         FN_DACK1, FN_SCK3, FN_TX3, FN_DREQ1_N, FN_RX3,
 191
 192         /* IPSR7 */
 193         FN_PWM0, FN_TCLK1, FN_FSO_CFE_0, FN_PWM1, FN_TCLK2, FN_FSO_CFE_1,
 194         FN_PWM2, FN_TCLK3, FN_FSO_TOE, FN_PWM3, FN_PWM4,
 195         FN_SSI_SCK34, FN_TPU0TO0, FN_SSI_WS34, FN_TPU0TO1,
 196         FN_SSI_SDATA3, FN_TPU0TO2, FN_SSI_SCK4, FN_TPU0TO3,
 197         FN_SSI_WS4, FN_SSI_SDATA4, FN_AUDIO_CLKOUT,
 198         FN_AUDIO_CLKA, FN_AUDIO_CLKB,
 199
 200         /* MOD_SEL */
 201         FN_SEL_VI1_0, FN_SEL_VI1_1,
 202         PINMUX_FUNCTION_END,
 203
 204         PINMUX_MARK_BEGIN,
 205         DU1_DB2_C0_DATA12_MARK, DU1_DB3_C1_DATA13_MARK,
 206         DU1_DB4_C2_DATA14_MARK, DU1_DB5_C3_DATA15_MARK,
 207         DU1_DB6_C4_MARK, DU1_DB7_C5_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
 208         DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
 209         DU1_DISP_MARK, DU1_CDE_MARK,
 210
 211         D0_MARK, D1_MARK, D2_MARK, D3_MARK, D4_MARK, D5_MARK, D6_MARK,
 212         D7_MARK, D8_MARK, D9_MARK, D10_MARK, D11_MARK, D12_MARK, D13_MARK,
 213         D14_MARK, D15_MARK, A0_MARK, A1_MARK, A2_MARK, A3_MARK, A4_MARK,
 214         A5_MARK, A6_MARK, A7_MARK, A8_MARK, A9_MARK, A10_MARK, A11_MARK,
 215         A12_MARK, A13_MARK, A14_MARK, A15_MARK,
 216
 217         A16_MARK, A17_MARK, A18_MARK, A19_MARK, CS1_N_A26_MARK,
 218         EX_CS0_N_MARK, EX_CS1_N_MARK, EX_CS2_N_MARK, EX_CS3_N_MARK,
 219         EX_CS4_N_MARK, EX_CS5_N_MARK, BS_N_MARK, RD_N_MARK, RD_WR_N_MARK,
 220         WE0_N_MARK, WE1_N_MARK, EX_WAIT0_MARK,
 221         IRQ0_MARK, IRQ1_MARK, IRQ2_MARK, IRQ3_MARK, CS0_N_MARK,
 222
 223         VI0_CLK_MARK, VI0_CLKENB_MARK, VI0_HSYNC_N_MARK, VI0_VSYNC_N_MARK,
 224         VI0_D0_B0_C0_MARK, VI0_D1_B1_C1_MARK, VI0_D2_B2_C2_MARK,
 225         VI0_D3_B3_C3_MARK, VI0_D4_B4_C4_MARK, VI0_D5_B5_C5_MARK,
 226         VI0_D6_B6_C6_MARK, VI0_D7_B7_C7_MARK, VI0_D8_G0_Y0_MARK,
 227         VI0_D9_G1_Y1_MARK, VI0_D10_G2_Y2_MARK, VI0_D11_G3_Y3_MARK,
 228         VI0_FIELD_MARK,
 229
 230         VI1_CLK_MARK, VI1_CLKENB_MARK, VI1_HSYNC_N_MARK, VI1_VSYNC_N_MARK,
 231         VI1_D0_B0_C0_MARK, VI1_D1_B1_C1_MARK, VI1_D2_B2_C2_MARK,
 232         VI1_D3_B3_C3_MARK, VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,
 233         VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK, VI1_D8_G0_Y0_MARK,
 234         VI1_D9_G1_Y1_MARK, VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,
 235         VI1_FIELD_MARK,
 236
 237         VI3_D10_Y2_MARK, VI3_FIELD_MARK,
 238
 239         VI4_CLK_MARK,
 240
 241         VI5_CLK_MARK, VI5_D9_Y1_MARK, VI5_D10_Y2_MARK, VI5_D11_Y3_MARK,
 242         VI5_FIELD_MARK,
 243
 244         HRTS0_N_MARK, HCTS1_N_MARK, SCK0_MARK, CTS0_N_MARK, RTS0_N_MARK,
 245         TX0_MARK, RX0_MARK, SCK1_MARK, CTS1_N_MARK, RTS1_N_MARK,
 246         TX1_MARK, RX1_MARK, SCIF_CLK_MARK, CAN0_TX_MARK, CAN0_RX_MARK,
 247         CAN_CLK_MARK, CAN1_TX_MARK, CAN1_RX_MARK,
 248
 249         SD0_CLK_MARK, SD0_CMD_MARK, SD0_DAT0_MARK, SD0_DAT1_MARK,
 250         SD0_DAT2_MARK, SD0_DAT3_MARK, SD0_CD_MARK, SD0_WP_MARK,
 251         ADICLK_MARK, ADICS_SAMP_MARK, ADIDATA_MARK, ADICHS0_MARK,
 252         ADICHS1_MARK, ADICHS2_MARK, AVS1_MARK, AVS2_MARK,
 253
 254         /* IPSR0 */
 255         DU0_DR0_DATA0_MARK, DU0_DR1_DATA1_MARK, DU0_DR2_Y4_DATA2_MARK,
 256         DU0_DR3_Y5_DATA3_MARK, DU0_DR4_Y6_DATA4_MARK, DU0_DR5_Y7_DATA5_MARK,
 257         DU0_DR6_Y8_DATA6_MARK, DU0_DR7_Y9_DATA7_MARK, DU0_DG0_DATA8_MARK,
 258         DU0_DG1_DATA9_MARK, DU0_DG2_C6_DATA10_MARK, DU0_DG3_C7_DATA11_MARK,
 259         DU0_DG4_Y0_DATA12_MARK, DU0_DG5_Y1_DATA13_MARK, DU0_DG6_Y2_DATA14_MARK,
 260         DU0_DG7_Y3_DATA15_MARK, DU0_DB0_MARK, DU0_DB1_MARK,
 261         DU0_DB2_C0_MARK, DU0_DB3_C1_MARK, DU0_DB4_C2_MARK, DU0_DB5_C3_MARK,
 262         DU0_DB6_C4_MARK, DU0_DB7_C5_MARK,
 263
 264         /* IPSR1 */
 265         DU0_EXHSYNC_DU0_HSYNC_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK,
 266         DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, DU0_DISP_MARK, DU0_CDE_MARK,
 267         DU1_DR2_Y4_DATA0_MARK, DU1_DR3_Y5_DATA1_MARK, DU1_DR4_Y6_DATA2_MARK,
 268         DU1_DR5_Y7_DATA3_MARK, DU1_DR6_DATA4_MARK, DU1_DR7_DATA5_MARK,
 269         DU1_DG2_C6_DATA6_MARK, DU1_DG3_C7_DATA7_MARK, DU1_DG4_Y0_DATA8_MARK,
 270         DU1_DG5_Y1_DATA9_MARK, DU1_DG6_Y2_DATA10_MARK, DU1_DG7_Y3_DATA11_MARK,
 271         A20_MARK, MOSI_IO0_MARK, A21_MARK, MISO_IO1_MARK, A22_MARK, IO2_MARK,
 272         A23_MARK, IO3_MARK, A24_MARK, SPCLK_MARK, A25_MARK, SSL_MARK,
 273
 274         /* IPSR2 */
 275         VI2_CLK_MARK, AVB_RX_CLK_MARK, VI2_CLKENB_MARK, AVB_RX_DV_MARK,
 276         VI2_HSYNC_N_MARK, AVB_RXD0_MARK, VI2_VSYNC_N_MARK, AVB_RXD1_MARK,
 277         VI2_D0_C0_MARK, AVB_RXD2_MARK, VI2_D1_C1_MARK, AVB_TX_CLK_MARK,
 278         VI2_D2_C2_MARK, AVB_RXD4_MARK, VI2_D3_C3_MARK, AVB_RXD5_MARK,
 279         VI2_D4_C4_MARK, AVB_RXD6_MARK, VI2_D5_C5_MARK, AVB_RXD7_MARK,
 280         VI2_D6_C6_MARK, AVB_RX_ER_MARK, VI2_D7_C7_MARK, AVB_COL_MARK,
 281         VI2_D8_Y0_MARK, AVB_RXD3_MARK, VI2_D9_Y1_MARK, AVB_TX_EN_MARK,
 282         VI2_D10_Y2_MARK, AVB_TXD0_MARK,
 283         VI2_D11_Y3_MARK, AVB_TXD1_MARK, VI2_FIELD_MARK, AVB_TXD2_MARK,
 284
 285         /* IPSR3 */
 286         VI3_CLK_MARK, AVB_TXD3_MARK, VI3_CLKENB_MARK, AVB_TXD4_MARK,
 287         VI3_HSYNC_N_MARK, AVB_TXD5_MARK, VI3_VSYNC_N_MARK, AVB_TXD6_MARK,
 288         VI3_D0_C0_MARK, AVB_TXD7_MARK, VI3_D1_C1_MARK, AVB_TX_ER_MARK,
 289         VI3_D2_C2_MARK, AVB_GTX_CLK_MARK, VI3_D3_C3_MARK, AVB_MDC_MARK,
 290         VI3_D4_C4_MARK, AVB_MDIO_MARK, VI3_D5_C5_MARK, AVB_LINK_MARK,
 291         VI3_D6_C6_MARK, AVB_MAGIC_MARK, VI3_D7_C7_MARK, AVB_PHY_INT_MARK,
 292         VI3_D8_Y0_MARK, AVB_CRS_MARK, VI3_D9_Y1_MARK, AVB_GTXREFCLK_MARK,
 293         VI3_D11_Y3_MARK, AVB_AVTP_MATCH_MARK,
 294
 295         /* IPSR4 */
 296         VI4_CLKENB_MARK, VI0_D12_G4_Y4_MARK, VI4_HSYNC_N_MARK,
 297         VI0_D13_G5_Y5_MARK, VI4_VSYNC_N_MARK, VI0_D14_G6_Y6_MARK,
 298         RDR_CLKOUT_MARK, VI4_D0_C0_MARK, VI0_D15_G7_Y7_MARK, VI4_D1_C1_MARK,
 299         VI0_D16_R0_MARK, VI1_D12_G4_Y4_MARK, VI4_D2_C2_MARK, VI0_D17_R1_MARK,
 300         VI1_D13_G5_Y5_MARK, VI4_D3_C3_MARK, VI0_D18_R2_MARK, VI1_D14_G6_Y6_MARK,
 301         VI4_D4_C4_MARK, VI0_D19_R3_MARK, VI1_D15_G7_Y7_MARK, VI4_D5_C5_MARK,
 302         VI0_D20_R4_MARK, VI2_D12_Y4_MARK, VI4_D6_C6_MARK, VI0_D21_R5_MARK,
 303         VI2_D13_Y5_MARK, VI4_D7_C7_MARK, VI0_D22_R6_MARK, VI2_D14_Y6_MARK,
 304         VI4_D8_Y0_MARK, VI0_D23_R7_MARK, VI2_D15_Y7_MARK, VI4_D9_Y1_MARK,
 305         VI3_D12_Y4_MARK, VI4_D10_Y2_MARK, VI3_D13_Y5_MARK, VI4_D11_Y3_MARK,
 306         VI3_D14_Y6_MARK, VI4_FIELD_MARK, VI3_D15_Y7_MARK,
 307
 308         /* IPSR5 */
 309         VI5_CLKENB_MARK, VI1_D12_G4_Y4_B_MARK, VI5_HSYNC_N_MARK,
 310         VI1_D13_G5_Y5_B_MARK, VI5_VSYNC_N_MARK, VI1_D14_G6_Y6_B_MARK,
 311         VI5_D0_C0_MARK, VI1_D15_G7_Y7_B_MARK, VI5_D1_C1_MARK, VI1_D16_R0_MARK,
 312         VI5_D2_C2_MARK, VI1_D17_R1_MARK, VI5_D3_C3_MARK, VI1_D18_R2_MARK,
 313         VI5_D4_C4_MARK, VI1_D19_R3_MARK, VI5_D5_C5_MARK, VI1_D20_R4_MARK,
 314         VI5_D6_C6_MARK, VI1_D21_R5_MARK, VI5_D7_C7_MARK, VI1_D22_R6_MARK,
 315         VI5_D8_Y0_MARK, VI1_D23_R7_MARK,
 316
 317         /* IPSR6 */
 318         MSIOF0_SCK_MARK, HSCK0_MARK, MSIOF0_SYNC_MARK, HCTS0_N_MARK,
 319         MSIOF0_TXD_MARK, HTX0_MARK, MSIOF0_RXD_MARK, HRX0_MARK,
 320         MSIOF1_SCK_MARK, HSCK1_MARK, MSIOF1_SYNC_MARK, HRTS1_N_MARK,
 321         MSIOF1_TXD_MARK, HTX1_MARK, MSIOF1_RXD_MARK, HRX1_MARK,
 322         DRACK0_MARK, SCK2_MARK, DACK0_MARK, TX2_MARK, DREQ0_N_MARK,
 323         RX2_MARK, DACK1_MARK, SCK3_MARK, TX3_MARK, DREQ1_N_MARK,
 324         RX3_MARK,
 325
 326         /* IPSR7 */
 327         PWM0_MARK, TCLK1_MARK, FSO_CFE_0_MARK, PWM1_MARK, TCLK2_MARK,
 328         FSO_CFE_1_MARK, PWM2_MARK, TCLK3_MARK, FSO_TOE_MARK, PWM3_MARK,
 329         PWM4_MARK, SSI_SCK34_MARK, TPU0TO0_MARK, SSI_WS34_MARK, TPU0TO1_MARK,
 330         SSI_SDATA3_MARK, TPU0TO2_MARK, SSI_SCK4_MARK, TPU0TO3_MARK,
 331         SSI_WS4_MARK, SSI_SDATA4_MARK, AUDIO_CLKOUT_MARK, AUDIO_CLKA_MARK,
 332         AUDIO_CLKB_MARK,
 333         PINMUX_MARK_END,
 334 };
 335
 336 static const u16 pinmux_data[] = {
 337         PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
 338
 339         PINMUX_SINGLE(DU1_DB2_C0_DATA12),
 340         PINMUX_SINGLE(DU1_DB3_C1_DATA13),
 341         PINMUX_SINGLE(DU1_DB4_C2_DATA14),
 342         PINMUX_SINGLE(DU1_DB5_C3_DATA15),
 343         PINMUX_SINGLE(DU1_DB6_C4),
 344         PINMUX_SINGLE(DU1_DB7_C5),
 345         PINMUX_SINGLE(DU1_EXHSYNC_DU1_HSYNC),
 346         PINMUX_SINGLE(DU1_EXVSYNC_DU1_VSYNC),
 347         PINMUX_SINGLE(DU1_EXODDF_DU1_ODDF_DISP_CDE),
 348         PINMUX_SINGLE(DU1_DISP),
 349         PINMUX_SINGLE(DU1_CDE),
 350         PINMUX_SINGLE(D0),
 351         PINMUX_SINGLE(D1),
 352         PINMUX_SINGLE(D2),
 353         PINMUX_SINGLE(D3),
 354         PINMUX_SINGLE(D4),
 355         PINMUX_SINGLE(D5),
 356         PINMUX_SINGLE(D6),
 357         PINMUX_SINGLE(D7),
 358         PINMUX_SINGLE(D8),
 359         PINMUX_SINGLE(D9),
 360         PINMUX_SINGLE(D10),
 361         PINMUX_SINGLE(D11),
 362         PINMUX_SINGLE(D12),
 363         PINMUX_SINGLE(D13),
 364         PINMUX_SINGLE(D14),
 365         PINMUX_SINGLE(D15),
 366         PINMUX_SINGLE(A0),
 367         PINMUX_SINGLE(A1),
 368         PINMUX_SINGLE(A2),
 369         PINMUX_SINGLE(A3),
 370         PINMUX_SINGLE(A4),
 371         PINMUX_SINGLE(A5),
 372         PINMUX_SINGLE(A6),
 373         PINMUX_SINGLE(A7),
 374         PINMUX_SINGLE(A8),
 375         PINMUX_SINGLE(A9),
 376         PINMUX_SINGLE(A10),
 377         PINMUX_SINGLE(A11),
 378         PINMUX_SINGLE(A12),
 379         PINMUX_SINGLE(A13),
 380         PINMUX_SINGLE(A14),
 381         PINMUX_SINGLE(A15),
 382         PINMUX_SINGLE(A16),
 383         PINMUX_SINGLE(A17),
 384         PINMUX_SINGLE(A18),
 385         PINMUX_SINGLE(A19),
 386         PINMUX_SINGLE(CS1_N_A26),
 387         PINMUX_SINGLE(EX_CS0_N),
 388         PINMUX_SINGLE(EX_CS1_N),
 389         PINMUX_SINGLE(EX_CS2_N),
 390         PINMUX_SINGLE(EX_CS3_N),
 391         PINMUX_SINGLE(EX_CS4_N),
 392         PINMUX_SINGLE(EX_CS5_N),
 393         PINMUX_SINGLE(BS_N),
 394         PINMUX_SINGLE(RD_N),
 395         PINMUX_SINGLE(RD_WR_N),
 396         PINMUX_SINGLE(WE0_N),
 397         PINMUX_SINGLE(WE1_N),
 398         PINMUX_SINGLE(EX_WAIT0),
 399         PINMUX_SINGLE(IRQ0),
 400         PINMUX_SINGLE(IRQ1),
 401         PINMUX_SINGLE(IRQ2),
 402         PINMUX_SINGLE(IRQ3),
 403         PINMUX_SINGLE(CS0_N),
 404         PINMUX_SINGLE(VI0_CLK),
 405         PINMUX_SINGLE(VI0_CLKENB),
 406         PINMUX_SINGLE(VI0_HSYNC_N),
 407         PINMUX_SINGLE(VI0_VSYNC_N),
 408         PINMUX_SINGLE(VI0_D0_B0_C0),
 409         PINMUX_SINGLE(VI0_D1_B1_C1),
 410         PINMUX_SINGLE(VI0_D2_B2_C2),
 411         PINMUX_SINGLE(VI0_D3_B3_C3),
 412         PINMUX_SINGLE(VI0_D4_B4_C4),
 413         PINMUX_SINGLE(VI0_D5_B5_C5),
 414         PINMUX_SINGLE(VI0_D6_B6_C6),
 415         PINMUX_SINGLE(VI0_D7_B7_C7),
 416         PINMUX_SINGLE(VI0_D8_G0_Y0),
 417         PINMUX_SINGLE(VI0_D9_G1_Y1),
 418         PINMUX_SINGLE(VI0_D10_G2_Y2),
 419         PINMUX_SINGLE(VI0_D11_G3_Y3),
 420         PINMUX_SINGLE(VI0_FIELD),
 421         PINMUX_SINGLE(VI1_CLK),
 422         PINMUX_SINGLE(VI1_CLKENB),
 423         PINMUX_SINGLE(VI1_HSYNC_N),
 424         PINMUX_SINGLE(VI1_VSYNC_N),
 425         PINMUX_SINGLE(VI1_D0_B0_C0),
 426         PINMUX_SINGLE(VI1_D1_B1_C1),
 427         PINMUX_SINGLE(VI1_D2_B2_C2),
 428         PINMUX_SINGLE(VI1_D3_B3_C3),
 429         PINMUX_SINGLE(VI1_D4_B4_C4),
 430         PINMUX_SINGLE(VI1_D5_B5_C5),
 431         PINMUX_SINGLE(VI1_D6_B6_C6),
 432         PINMUX_SINGLE(VI1_D7_B7_C7),
 433         PINMUX_SINGLE(VI1_D8_G0_Y0),
 434         PINMUX_SINGLE(VI1_D9_G1_Y1),
 435         PINMUX_SINGLE(VI1_D10_G2_Y2),
 436         PINMUX_SINGLE(VI1_D11_G3_Y3),
 437         PINMUX_SINGLE(VI1_FIELD),
 438         PINMUX_SINGLE(VI3_D10_Y2),
 439         PINMUX_SINGLE(VI3_FIELD),
 440         PINMUX_SINGLE(VI4_CLK),
 441         PINMUX_SINGLE(VI5_CLK),
 442         PINMUX_SINGLE(VI5_D9_Y1),
 443         PINMUX_SINGLE(VI5_D10_Y2),
 444         PINMUX_SINGLE(VI5_D11_Y3),
 445         PINMUX_SINGLE(VI5_FIELD),
 446         PINMUX_SINGLE(HRTS0_N),
 447         PINMUX_SINGLE(HCTS1_N),
 448         PINMUX_SINGLE(SCK0),
 449         PINMUX_SINGLE(CTS0_N),
 450         PINMUX_SINGLE(RTS0_N),
 451         PINMUX_SINGLE(TX0),
 452         PINMUX_SINGLE(RX0),
 453         PINMUX_SINGLE(SCK1),
 454         PINMUX_SINGLE(CTS1_N),
 455         PINMUX_SINGLE(RTS1_N),
 456         PINMUX_SINGLE(TX1),
 457         PINMUX_SINGLE(RX1),
 458         PINMUX_SINGLE(SCIF_CLK),
 459         PINMUX_SINGLE(CAN0_TX),
 460         PINMUX_SINGLE(CAN0_RX),
 461         PINMUX_SINGLE(CAN_CLK),
 462         PINMUX_SINGLE(CAN1_TX),
 463         PINMUX_SINGLE(CAN1_RX),
 464         PINMUX_SINGLE(SD0_CLK),
 465         PINMUX_SINGLE(SD0_CMD),
 466         PINMUX_SINGLE(SD0_DAT0),
 467         PINMUX_SINGLE(SD0_DAT1),
 468         PINMUX_SINGLE(SD0_DAT2),
 469         PINMUX_SINGLE(SD0_DAT3),
 470         PINMUX_SINGLE(SD0_CD),
 471         PINMUX_SINGLE(SD0_WP),
 472         PINMUX_SINGLE(ADICLK),
 473         PINMUX_SINGLE(ADICS_SAMP),
 474         PINMUX_SINGLE(ADIDATA),
 475         PINMUX_SINGLE(ADICHS0),
 476         PINMUX_SINGLE(ADICHS1),
 477         PINMUX_SINGLE(ADICHS2),
 478         PINMUX_SINGLE(AVS1),
 479         PINMUX_SINGLE(AVS2),
 480
 481         /* IPSR0 */
 482         PINMUX_IPSR_GPSR(IP0_0, DU0_DR0_DATA0),
 483         PINMUX_IPSR_GPSR(IP0_1, DU0_DR1_DATA1),
 484         PINMUX_IPSR_GPSR(IP0_2, DU0_DR2_Y4_DATA2),
 485         PINMUX_IPSR_GPSR(IP0_3, DU0_DR3_Y5_DATA3),
 486         PINMUX_IPSR_GPSR(IP0_4, DU0_DR4_Y6_DATA4),
 487         PINMUX_IPSR_GPSR(IP0_5, DU0_DR5_Y7_DATA5),
 488         PINMUX_IPSR_GPSR(IP0_6, DU0_DR6_Y8_DATA6),
 489         PINMUX_IPSR_GPSR(IP0_7, DU0_DR7_Y9_DATA7),
 490         PINMUX_IPSR_GPSR(IP0_8, DU0_DG0_DATA8),
 491         PINMUX_IPSR_GPSR(IP0_9, DU0_DG1_DATA9),
 492         PINMUX_IPSR_GPSR(IP0_10, DU0_DG2_C6_DATA10),
 493         PINMUX_IPSR_GPSR(IP0_11, DU0_DG3_C7_DATA11),
 494         PINMUX_IPSR_GPSR(IP0_12, DU0_DG4_Y0_DATA12),
 495         PINMUX_IPSR_GPSR(IP0_13, DU0_DG5_Y1_DATA13),
 496         PINMUX_IPSR_GPSR(IP0_14, DU0_DG6_Y2_DATA14),
 497         PINMUX_IPSR_GPSR(IP0_15, DU0_DG7_Y3_DATA15),
 498         PINMUX_IPSR_GPSR(IP0_16, DU0_DB0),
 499         PINMUX_IPSR_GPSR(IP0_17, DU0_DB1),
 500         PINMUX_IPSR_GPSR(IP0_18, DU0_DB2_C0),
 501         PINMUX_IPSR_GPSR(IP0_19, DU0_DB3_C1),
 502         PINMUX_IPSR_GPSR(IP0_20, DU0_DB4_C2),
 503         PINMUX_IPSR_GPSR(IP0_21, DU0_DB5_C3),
 504         PINMUX_IPSR_GPSR(IP0_22, DU0_DB6_C4),
 505         PINMUX_IPSR_GPSR(IP0_23, DU0_DB7_C5),
 506
 507         /* IPSR1 */
 508         PINMUX_IPSR_GPSR(IP1_0, DU0_EXHSYNC_DU0_HSYNC),
 509         PINMUX_IPSR_GPSR(IP1_1, DU0_EXVSYNC_DU0_VSYNC),
 510         PINMUX_IPSR_GPSR(IP1_2, DU0_EXODDF_DU0_ODDF_DISP_CDE),
 511         PINMUX_IPSR_GPSR(IP1_3, DU0_DISP),
 512         PINMUX_IPSR_GPSR(IP1_4, DU0_CDE),
 513         PINMUX_IPSR_GPSR(IP1_5, DU1_DR2_Y4_DATA0),
 514         PINMUX_IPSR_GPSR(IP1_6, DU1_DR3_Y5_DATA1),
 515         PINMUX_IPSR_GPSR(IP1_7, DU1_DR4_Y6_DATA2),
 516         PINMUX_IPSR_GPSR(IP1_8, DU1_DR5_Y7_DATA3),
 517         PINMUX_IPSR_GPSR(IP1_9, DU1_DR6_DATA4),
 518         PINMUX_IPSR_GPSR(IP1_10, DU1_DR7_DATA5),
 519         PINMUX_IPSR_GPSR(IP1_11, DU1_DG2_C6_DATA6),
 520         PINMUX_IPSR_GPSR(IP1_12, DU1_DG3_C7_DATA7),
 521         PINMUX_IPSR_GPSR(IP1_13, DU1_DG4_Y0_DATA8),
 522         PINMUX_IPSR_GPSR(IP1_14, DU1_DG5_Y1_DATA9),
 523         PINMUX_IPSR_GPSR(IP1_15, DU1_DG6_Y2_DATA10),
 524         PINMUX_IPSR_GPSR(IP1_16, DU1_DG7_Y3_DATA11),
 525         PINMUX_IPSR_GPSR(IP1_17, A20),
 526         PINMUX_IPSR_GPSR(IP1_17, MOSI_IO0),
 527         PINMUX_IPSR_GPSR(IP1_18, A21),
 528         PINMUX_IPSR_GPSR(IP1_18, MISO_IO1),
 529         PINMUX_IPSR_GPSR(IP1_19, A22),
 530         PINMUX_IPSR_GPSR(IP1_19, IO2),
 531         PINMUX_IPSR_GPSR(IP1_20, A23),
 532         PINMUX_IPSR_GPSR(IP1_20, IO3),
 533         PINMUX_IPSR_GPSR(IP1_21, A24),
 534         PINMUX_IPSR_GPSR(IP1_21, SPCLK),
 535         PINMUX_IPSR_GPSR(IP1_22, A25),
 536         PINMUX_IPSR_GPSR(IP1_22, SSL),
 537
 538         /* IPSR2 */
 539         PINMUX_IPSR_GPSR(IP2_0, VI2_CLK),
 540         PINMUX_IPSR_GPSR(IP2_0, AVB_RX_CLK),
 541         PINMUX_IPSR_GPSR(IP2_1, VI2_CLKENB),
 542         PINMUX_IPSR_GPSR(IP2_1, AVB_RX_DV),
 543         PINMUX_IPSR_GPSR(IP2_2, VI2_HSYNC_N),
 544         PINMUX_IPSR_GPSR(IP2_2, AVB_RXD0),
 545         PINMUX_IPSR_GPSR(IP2_3, VI2_VSYNC_N),
 546         PINMUX_IPSR_GPSR(IP2_3, AVB_RXD1),
 547         PINMUX_IPSR_GPSR(IP2_4, VI2_D0_C0),
 548         PINMUX_IPSR_GPSR(IP2_4, AVB_RXD2),
 549         PINMUX_IPSR_GPSR(IP2_5, VI2_D1_C1),
 550         PINMUX_IPSR_GPSR(IP2_5, AVB_RXD3),
 551         PINMUX_IPSR_GPSR(IP2_6, VI2_D2_C2),
 552         PINMUX_IPSR_GPSR(IP2_6, AVB_RXD4),
 553         PINMUX_IPSR_GPSR(IP2_7, VI2_D3_C3),
 554         PINMUX_IPSR_GPSR(IP2_7, AVB_RXD5),
 555         PINMUX_IPSR_GPSR(IP2_8, VI2_D4_C4),
 556         PINMUX_IPSR_GPSR(IP2_8, AVB_RXD6),
 557         PINMUX_IPSR_GPSR(IP2_9, VI2_D5_C5),
 558         PINMUX_IPSR_GPSR(IP2_9, AVB_RXD7),
 559         PINMUX_IPSR_GPSR(IP2_10, VI2_D6_C6),
 560         PINMUX_IPSR_GPSR(IP2_10, AVB_RX_ER),
 561         PINMUX_IPSR_GPSR(IP2_11, VI2_D7_C7),
 562         PINMUX_IPSR_GPSR(IP2_11, AVB_COL),
 563         PINMUX_IPSR_GPSR(IP2_12, VI2_D8_Y0),
 564         PINMUX_IPSR_GPSR(IP2_12, AVB_TXD3),
 565         PINMUX_IPSR_GPSR(IP2_13, VI2_D9_Y1),
 566         PINMUX_IPSR_GPSR(IP2_13, AVB_TX_EN),
 567         PINMUX_IPSR_GPSR(IP2_14, VI2_D10_Y2),
 568         PINMUX_IPSR_GPSR(IP2_14, AVB_TXD0),
 569         PINMUX_IPSR_GPSR(IP2_15, VI2_D11_Y3),
 570         PINMUX_IPSR_GPSR(IP2_15, AVB_TXD1),
 571         PINMUX_IPSR_GPSR(IP2_16, VI2_FIELD),
 572         PINMUX_IPSR_GPSR(IP2_16, AVB_TXD2),
 573
 574         /* IPSR3 */
 575         PINMUX_IPSR_GPSR(IP3_0, VI3_CLK),
 576         PINMUX_IPSR_GPSR(IP3_0, AVB_TX_CLK),
 577         PINMUX_IPSR_GPSR(IP3_1, VI3_CLKENB),
 578         PINMUX_IPSR_GPSR(IP3_1, AVB_TXD4),
 579         PINMUX_IPSR_GPSR(IP3_2, VI3_HSYNC_N),
 580         PINMUX_IPSR_GPSR(IP3_2, AVB_TXD5),
 581         PINMUX_IPSR_GPSR(IP3_3, VI3_VSYNC_N),
 582         PINMUX_IPSR_GPSR(IP3_3, AVB_TXD6),
 583         PINMUX_IPSR_GPSR(IP3_4, VI3_D0_C0),
 584         PINMUX_IPSR_GPSR(IP3_4, AVB_TXD7),
 585         PINMUX_IPSR_GPSR(IP3_5, VI3_D1_C1),
 586         PINMUX_IPSR_GPSR(IP3_5, AVB_TX_ER),
 587         PINMUX_IPSR_GPSR(IP3_6, VI3_D2_C2),
 588         PINMUX_IPSR_GPSR(IP3_6, AVB_GTX_CLK),
 589         PINMUX_IPSR_GPSR(IP3_7, VI3_D3_C3),
 590         PINMUX_IPSR_GPSR(IP3_7, AVB_MDC),
 591         PINMUX_IPSR_GPSR(IP3_8, VI3_D4_C4),
 592         PINMUX_IPSR_GPSR(IP3_8, AVB_MDIO),
 593         PINMUX_IPSR_GPSR(IP3_9, VI3_D5_C5),
 594         PINMUX_IPSR_GPSR(IP3_9, AVB_LINK),
 595         PINMUX_IPSR_GPSR(IP3_10, VI3_D6_C6),
 596         PINMUX_IPSR_GPSR(IP3_10, AVB_MAGIC),
 597         PINMUX_IPSR_GPSR(IP3_11, VI3_D7_C7),
 598         PINMUX_IPSR_GPSR(IP3_11, AVB_PHY_INT),
 599         PINMUX_IPSR_GPSR(IP3_12, VI3_D8_Y0),
 600         PINMUX_IPSR_GPSR(IP3_12, AVB_CRS),
 601         PINMUX_IPSR_GPSR(IP3_13, VI3_D9_Y1),
 602         PINMUX_IPSR_GPSR(IP3_13, AVB_GTXREFCLK),
 603         PINMUX_IPSR_GPSR(IP3_14, VI3_D11_Y3),
 604         PINMUX_IPSR_GPSR(IP3_14, AVB_AVTP_MATCH),
 605
 606         /* IPSR4 */
 607         PINMUX_IPSR_GPSR(IP4_0, VI4_CLKENB),
 608         PINMUX_IPSR_GPSR(IP4_0, VI0_D12_G4_Y4),
 609         PINMUX_IPSR_GPSR(IP4_1, VI4_HSYNC_N),
 610         PINMUX_IPSR_GPSR(IP4_1, VI0_D13_G5_Y5),
 611         PINMUX_IPSR_GPSR(IP4_3_2, VI4_VSYNC_N),
 612         PINMUX_IPSR_GPSR(IP4_3_2, VI0_D14_G6_Y6),
 613         PINMUX_IPSR_GPSR(IP4_4, VI4_D0_C0),
 614         PINMUX_IPSR_GPSR(IP4_4, VI0_D15_G7_Y7),
 615         PINMUX_IPSR_GPSR(IP4_6_5, VI4_D1_C1),
 616         PINMUX_IPSR_GPSR(IP4_6_5, VI0_D16_R0),
 617         PINMUX_IPSR_MSEL(IP4_6_5, VI1_D12_G4_Y4, SEL_VI1_0),
 618         PINMUX_IPSR_GPSR(IP4_8_7, VI4_D2_C2),
 619         PINMUX_IPSR_GPSR(IP4_8_7, VI0_D17_R1),
 620         PINMUX_IPSR_MSEL(IP4_8_7, VI1_D13_G5_Y5, SEL_VI1_0),
 621         PINMUX_IPSR_GPSR(IP4_10_9, VI4_D3_C3),
 622         PINMUX_IPSR_GPSR(IP4_10_9, VI0_D18_R2),
 623         PINMUX_IPSR_MSEL(IP4_10_9, VI1_D14_G6_Y6, SEL_VI1_0),
 624         PINMUX_IPSR_GPSR(IP4_12_11, VI4_D4_C4),
 625         PINMUX_IPSR_GPSR(IP4_12_11, VI0_D19_R3),
 626         PINMUX_IPSR_MSEL(IP4_12_11, VI1_D15_G7_Y7, SEL_VI1_0),
 627         PINMUX_IPSR_GPSR(IP4_14_13, VI4_D5_C5),
 628         PINMUX_IPSR_GPSR(IP4_14_13, VI0_D20_R4),
 629         PINMUX_IPSR_GPSR(IP4_14_13, VI2_D12_Y4),
 630         PINMUX_IPSR_GPSR(IP4_16_15, VI4_D6_C6),
 631         PINMUX_IPSR_GPSR(IP4_16_15, VI0_D21_R5),
 632         PINMUX_IPSR_GPSR(IP4_16_15, VI2_D13_Y5),
 633         PINMUX_IPSR_GPSR(IP4_18_17, VI4_D7_C7),
 634         PINMUX_IPSR_GPSR(IP4_18_17, VI0_D22_R6),
 635         PINMUX_IPSR_GPSR(IP4_18_17, VI2_D14_Y6),
 636         PINMUX_IPSR_GPSR(IP4_20_19, VI4_D8_Y0),
 637         PINMUX_IPSR_GPSR(IP4_20_19, VI0_D23_R7),
 638         PINMUX_IPSR_GPSR(IP4_20_19, VI2_D15_Y7),
 639         PINMUX_IPSR_GPSR(IP4_21, VI4_D9_Y1),
 640         PINMUX_IPSR_GPSR(IP4_21, VI3_D12_Y4),
 641         PINMUX_IPSR_GPSR(IP4_22, VI4_D10_Y2),
 642         PINMUX_IPSR_GPSR(IP4_22, VI3_D13_Y5),
 643         PINMUX_IPSR_GPSR(IP4_23, VI4_D11_Y3),
 644         PINMUX_IPSR_GPSR(IP4_23, VI3_D14_Y6),
 645         PINMUX_IPSR_GPSR(IP4_24, VI4_FIELD),
 646         PINMUX_IPSR_GPSR(IP4_24, VI3_D15_Y7),
 647
 648         /* IPSR5 */
 649         PINMUX_IPSR_GPSR(IP5_0, VI5_CLKENB),
 650         PINMUX_IPSR_MSEL(IP5_0, VI1_D12_G4_Y4_B, SEL_VI1_1),
 651         PINMUX_IPSR_GPSR(IP5_1, VI5_HSYNC_N),
 652         PINMUX_IPSR_MSEL(IP5_1, VI1_D13_G5_Y5_B, SEL_VI1_1),
 653         PINMUX_IPSR_GPSR(IP5_2, VI5_VSYNC_N),
 654         PINMUX_IPSR_MSEL(IP5_2, VI1_D14_G6_Y6_B, SEL_VI1_1),
 655         PINMUX_IPSR_GPSR(IP5_3, VI5_D0_C0),
 656         PINMUX_IPSR_MSEL(IP5_3, VI1_D15_G7_Y7_B, SEL_VI1_1),
 657         PINMUX_IPSR_GPSR(IP5_4, VI5_D1_C1),
 658         PINMUX_IPSR_GPSR(IP5_4, VI1_D16_R0),
 659         PINMUX_IPSR_GPSR(IP5_5, VI5_D2_C2),
 660         PINMUX_IPSR_GPSR(IP5_5, VI1_D17_R1),
 661         PINMUX_IPSR_GPSR(IP5_6, VI5_D3_C3),
 662         PINMUX_IPSR_GPSR(IP5_6, VI1_D18_R2),
 663         PINMUX_IPSR_GPSR(IP5_7, VI5_D4_C4),
 664         PINMUX_IPSR_GPSR(IP5_7, VI1_D19_R3),
 665         PINMUX_IPSR_GPSR(IP5_8, VI5_D5_C5),
 666         PINMUX_IPSR_GPSR(IP5_8, VI1_D20_R4),
 667         PINMUX_IPSR_GPSR(IP5_9, VI5_D6_C6),
 668         PINMUX_IPSR_GPSR(IP5_9, VI1_D21_R5),
 669         PINMUX_IPSR_GPSR(IP5_10, VI5_D7_C7),
 670         PINMUX_IPSR_GPSR(IP5_10, VI1_D22_R6),
 671         PINMUX_IPSR_GPSR(IP5_11, VI5_D8_Y0),
 672         PINMUX_IPSR_GPSR(IP5_11, VI1_D23_R7),
 673
 674         /* IPSR6 */
 675         PINMUX_IPSR_GPSR(IP6_0, MSIOF0_SCK),
 676         PINMUX_IPSR_GPSR(IP6_0, HSCK0),
 677         PINMUX_IPSR_GPSR(IP6_1, MSIOF0_SYNC),
 678         PINMUX_IPSR_GPSR(IP6_1, HCTS0_N),
 679         PINMUX_IPSR_GPSR(IP6_2, MSIOF0_TXD),
 680         PINMUX_IPSR_GPSR(IP6_2, HTX0),
 681         PINMUX_IPSR_GPSR(IP6_3, MSIOF0_RXD),
 682         PINMUX_IPSR_GPSR(IP6_3, HRX0),
 683         PINMUX_IPSR_GPSR(IP6_4, MSIOF1_SCK),
 684         PINMUX_IPSR_GPSR(IP6_4, HSCK1),
 685         PINMUX_IPSR_GPSR(IP6_5, MSIOF1_SYNC),
 686         PINMUX_IPSR_GPSR(IP6_5, HRTS1_N),
 687         PINMUX_IPSR_GPSR(IP6_6, MSIOF1_TXD),
 688         PINMUX_IPSR_GPSR(IP6_6, HTX1),
 689         PINMUX_IPSR_GPSR(IP6_7, MSIOF1_RXD),
 690         PINMUX_IPSR_GPSR(IP6_7, HRX1),
 691         PINMUX_IPSR_GPSR(IP6_9_8, DRACK0),
 692         PINMUX_IPSR_GPSR(IP6_9_8, SCK2),
 693         PINMUX_IPSR_GPSR(IP6_11_10, DACK0),
 694         PINMUX_IPSR_GPSR(IP6_11_10, TX2),
 695         PINMUX_IPSR_GPSR(IP6_13_12, DREQ0_N),
 696         PINMUX_IPSR_GPSR(IP6_13_12, RX2),
 697         PINMUX_IPSR_GPSR(IP6_15_14, DACK1),
 698         PINMUX_IPSR_GPSR(IP6_15_14, SCK3),
 699         PINMUX_IPSR_GPSR(IP6_16, TX3),
 700         PINMUX_IPSR_GPSR(IP6_18_17, DREQ1_N),
 701         PINMUX_IPSR_GPSR(IP6_18_17, RX3),
 702
 703         /* IPSR7 */
 704         PINMUX_IPSR_GPSR(IP7_1_0, PWM0),
 705         PINMUX_IPSR_GPSR(IP7_1_0, TCLK1),
 706         PINMUX_IPSR_GPSR(IP7_1_0, FSO_CFE_0),
 707         PINMUX_IPSR_GPSR(IP7_3_2, PWM1),
 708         PINMUX_IPSR_GPSR(IP7_3_2, TCLK2),
 709         PINMUX_IPSR_GPSR(IP7_3_2, FSO_CFE_1),
 710         PINMUX_IPSR_GPSR(IP7_5_4, PWM2),
 711         PINMUX_IPSR_GPSR(IP7_5_4, TCLK3),
 712         PINMUX_IPSR_GPSR(IP7_5_4, FSO_TOE),
 713         PINMUX_IPSR_GPSR(IP7_6, PWM3),
 714         PINMUX_IPSR_GPSR(IP7_7, PWM4),
 715         PINMUX_IPSR_GPSR(IP7_9_8, SSI_SCK34),
 716         PINMUX_IPSR_GPSR(IP7_9_8, TPU0TO0),
 717         PINMUX_IPSR_GPSR(IP7_11_10, SSI_WS34),
 718         PINMUX_IPSR_GPSR(IP7_11_10, TPU0TO1),
 719         PINMUX_IPSR_GPSR(IP7_13_12, SSI_SDATA3),
 720         PINMUX_IPSR_GPSR(IP7_13_12, TPU0TO2),
 721         PINMUX_IPSR_GPSR(IP7_15_14, SSI_SCK4),
 722         PINMUX_IPSR_GPSR(IP7_15_14, TPU0TO3),
 723         PINMUX_IPSR_GPSR(IP7_16, SSI_WS4),
 724         PINMUX_IPSR_GPSR(IP7_17, SSI_SDATA4),
 725         PINMUX_IPSR_GPSR(IP7_18, AUDIO_CLKOUT),
 726         PINMUX_IPSR_GPSR(IP7_19, AUDIO_CLKA),
 727         PINMUX_IPSR_GPSR(IP7_20, AUDIO_CLKB),
 728 };
 729
 730 static const struct sh_pfc_pin pinmux_pins[] = {
 731         PINMUX_GPIO_GP_ALL(),
 732 };
 733
 734 /* - AVB -------------------------------------------------------------------- */
 735 static const unsigned int avb_link_pins[] = {
 736         RCAR_GP_PIN(7, 9),
 737 };
 738 static const unsigned int avb_link_mux[] = {
 739         AVB_LINK_MARK,
 740 };
 741 static const unsigned int avb_magic_pins[] = {
 742         RCAR_GP_PIN(7, 10),
 743 };
 744 static const unsigned int avb_magic_mux[] = {
 745         AVB_MAGIC_MARK,
 746 };
 747 static const unsigned int avb_phy_int_pins[] = {
 748         RCAR_GP_PIN(7, 11),
 749 };
 750 static const unsigned int avb_phy_int_mux[] = {
 751         AVB_PHY_INT_MARK,
 752 };
 753 static const unsigned int avb_mdio_pins[] = {
 754         RCAR_GP_PIN(7, 7), RCAR_GP_PIN(7, 8),
 755 };
 756 static const unsigned int avb_mdio_mux[] = {
 757         AVB_MDC_MARK, AVB_MDIO_MARK,
 758 };
 759 static const unsigned int avb_mii_pins[] = {
 760         RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15), RCAR_GP_PIN(6, 16),
 761         RCAR_GP_PIN(6, 12),
 762
 763         RCAR_GP_PIN(6, 2),  RCAR_GP_PIN(6, 3),  RCAR_GP_PIN(6, 4),
 764         RCAR_GP_PIN(6, 5),
 765
 766         RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 0),  RCAR_GP_PIN(6, 1),
 767         RCAR_GP_PIN(7, 12), RCAR_GP_PIN(6, 13), RCAR_GP_PIN(7, 5),
 768         RCAR_GP_PIN(7, 0),  RCAR_GP_PIN(6, 11),
 769 };
 770 static const unsigned int avb_mii_mux[] = {
 771         AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
 772         AVB_TXD3_MARK,
 773
 774         AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
 775         AVB_RXD3_MARK,
 776
 777         AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
 778         AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_ER_MARK,
 779         AVB_TX_CLK_MARK, AVB_COL_MARK,
 780 };
 781 static const unsigned int avb_gmii_pins[] = {
 782         RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15), RCAR_GP_PIN(6, 16),
 783         RCAR_GP_PIN(6, 12), RCAR_GP_PIN(7, 1),  RCAR_GP_PIN(7, 2),
 784         RCAR_GP_PIN(7, 3),  RCAR_GP_PIN(7, 4),
 785
 786         RCAR_GP_PIN(6, 2),  RCAR_GP_PIN(6, 3), RCAR_GP_PIN(6, 4),
 787         RCAR_GP_PIN(6, 5),  RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7),
 788         RCAR_GP_PIN(6, 8),  RCAR_GP_PIN(6, 9),
 789
 790         RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
 791         RCAR_GP_PIN(7, 12), RCAR_GP_PIN(7, 6), RCAR_GP_PIN(7, 13),
 792         RCAR_GP_PIN(6, 13), RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 0),
 793         RCAR_GP_PIN(6, 11),
 794 };
 795 static const unsigned int avb_gmii_mux[] = {
 796         AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
 797         AVB_TXD3_MARK, AVB_TXD4_MARK, AVB_TXD5_MARK,
 798         AVB_TXD6_MARK, AVB_TXD7_MARK,
 799
 800         AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
 801         AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK,
 802         AVB_RXD6_MARK, AVB_RXD7_MARK,
 803
 804         AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
 805         AVB_CRS_MARK, AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK,
 806         AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK,
 807         AVB_COL_MARK,
 808 };
 809 static const unsigned int avb_avtp_match_pins[] = {
 810         RCAR_GP_PIN(7, 15),
 811 };
 812 static const unsigned int avb_avtp_match_mux[] = {
 813         AVB_AVTP_MATCH_MARK,
 814 };
 815 /* - CAN -------------------------------------------------------------------- */
 816 static const unsigned int can0_data_pins[] = {
 817         /* TX, RX */
 818         RCAR_GP_PIN(10, 27), RCAR_GP_PIN(10, 28),
 819 };
 820 static const unsigned int can0_data_mux[] = {
 821         CAN0_TX_MARK, CAN0_RX_MARK,
 822 };
 823 static const unsigned int can1_data_pins[] = {
 824         /* TX, RX */
 825         RCAR_GP_PIN(10, 30), RCAR_GP_PIN(10, 31),
 826 };
 827 static const unsigned int can1_data_mux[] = {
 828         CAN1_TX_MARK, CAN1_RX_MARK,
 829 };
 830 static const unsigned int can_clk_pins[] = {
 831         /* CAN_CLK */
 832         RCAR_GP_PIN(10, 29),
 833 };
 834 static const unsigned int can_clk_mux[] = {
 835         CAN_CLK_MARK,
 836 };
 837 /* - DU --------------------------------------------------------------------- */
 838 static const unsigned int du0_rgb666_pins[] = {
 839         /* R[7:2], G[7:2], B[7:2] */
 840         RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 5),
 841         RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 2),
 842         RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
 843         RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
 844         RCAR_GP_PIN(0, 23), RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 21),
 845         RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 18),
 846 };
 847 static const unsigned int du0_rgb666_mux[] = {
 848         DU0_DR7_Y9_DATA7_MARK, DU0_DR6_Y8_DATA6_MARK, DU0_DR5_Y7_DATA5_MARK,
 849         DU0_DR4_Y6_DATA4_MARK, DU0_DR3_Y5_DATA3_MARK, DU0_DR2_Y4_DATA2_MARK,
 850         DU0_DG7_Y3_DATA15_MARK, DU0_DG6_Y2_DATA14_MARK, DU0_DG5_Y1_DATA13_MARK,
 851         DU0_DG4_Y0_DATA12_MARK, DU0_DG3_C7_DATA11_MARK, DU0_DG2_C6_DATA10_MARK,
 852         DU0_DB7_C5_MARK, DU0_DB6_C4_MARK, DU0_DB5_C3_MARK,
 853         DU0_DB4_C2_MARK, DU0_DB3_C1_MARK, DU0_DB2_C0_MARK,
 854 };
 855 static const unsigned int du0_rgb888_pins[] = {
 856         /* R[7:0], G[7:0], B[7:0] */
 857         RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 5),
 858         RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 2),
 859         RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0),
 860         RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
 861         RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
 862         RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
 863         RCAR_GP_PIN(0, 23), RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 21),
 864         RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 18),
 865         RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16),
 866 };
 867 static const unsigned int du0_rgb888_mux[] = {
 868         DU0_DR7_Y9_DATA7_MARK, DU0_DR6_Y8_DATA6_MARK, DU0_DR5_Y7_DATA5_MARK,
 869         DU0_DR4_Y6_DATA4_MARK, DU0_DR3_Y5_DATA3_MARK, DU0_DR2_Y4_DATA2_MARK,
 870         DU0_DR1_DATA1_MARK, DU0_DR0_DATA0_MARK,
 871         DU0_DG7_Y3_DATA15_MARK, DU0_DG6_Y2_DATA14_MARK, DU0_DG5_Y1_DATA13_MARK,
 872         DU0_DG4_Y0_DATA12_MARK, DU0_DG3_C7_DATA11_MARK, DU0_DG2_C6_DATA10_MARK,
 873         DU0_DG1_DATA9_MARK, DU0_DG0_DATA8_MARK,
 874         DU0_DB7_C5_MARK, DU0_DB6_C4_MARK, DU0_DB5_C3_MARK,
 875         DU0_DB4_C2_MARK, DU0_DB3_C1_MARK, DU0_DB2_C0_MARK,
 876         DU0_DB1_MARK, DU0_DB0_MARK,
 877 };
 878 static const unsigned int du0_sync_pins[] = {
 879         /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
 880         RCAR_GP_PIN(0, 25), RCAR_GP_PIN(0, 24),
 881 };
 882 static const unsigned int du0_sync_mux[] = {
 883         DU0_EXVSYNC_DU0_VSYNC_MARK, DU0_EXHSYNC_DU0_HSYNC_MARK,
 884 };
 885 static const unsigned int du0_oddf_pins[] = {
 886         /* EXODDF/ODDF/DISP/CDE */
 887         RCAR_GP_PIN(0, 26),
 888 };
 889 static const unsigned int du0_oddf_mux[] = {
 890         DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK
 891 };
 892 static const unsigned int du0_disp_pins[] = {
 893         /* DISP */
 894         RCAR_GP_PIN(0, 27),
 895 };
 896 static const unsigned int du0_disp_mux[] = {
 897         DU0_DISP_MARK,
 898 };
 899 static const unsigned int du0_cde_pins[] = {
 900         /* CDE */
 901         RCAR_GP_PIN(0, 28),
 902 };
 903 static const unsigned int du0_cde_mux[] = {
 904         DU0_CDE_MARK,
 905 };
 906 static const unsigned int du1_rgb666_pins[] = {
 907         /* R[7:2], G[7:2], B[7:2] */
 908         RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3),
 909         RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
 910         RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
 911         RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
 912         RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 15),
 913         RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 12),
 914 };
 915 static const unsigned int du1_rgb666_mux[] = {
 916         DU1_DR7_DATA5_MARK, DU1_DR6_DATA4_MARK, DU1_DR5_Y7_DATA3_MARK,
 917         DU1_DR4_Y6_DATA2_MARK, DU1_DR3_Y5_DATA1_MARK, DU1_DR2_Y4_DATA0_MARK,
 918         DU1_DG7_Y3_DATA11_MARK, DU1_DG6_Y2_DATA10_MARK, DU1_DG5_Y1_DATA9_MARK,
 919         DU1_DG4_Y0_DATA8_MARK, DU1_DG3_C7_DATA7_MARK, DU1_DG2_C6_DATA6_MARK,
 920         DU1_DB7_C5_MARK, DU1_DB6_C4_MARK, DU1_DB5_C3_DATA15_MARK,
 921         DU1_DB4_C2_DATA14_MARK, DU1_DB3_C1_DATA13_MARK, DU1_DB2_C0_DATA12_MARK,
 922 };
 923 static const unsigned int du1_sync_pins[] = {
 924         /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
 925         RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
 926 };
 927 static const unsigned int du1_sync_mux[] = {
 928         DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
 929 };
 930 static const unsigned int du1_oddf_pins[] = {
 931         /* EXODDF/ODDF/DISP/CDE */
 932         RCAR_GP_PIN(1, 20),
 933 };
 934 static const unsigned int du1_oddf_mux[] = {
 935         DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK
 936 };
 937 static const unsigned int du1_disp_pins[] = {
 938         /* DISP */
 939         RCAR_GP_PIN(1, 21),
 940 };
 941 static const unsigned int du1_disp_mux[] = {
 942         DU1_DISP_MARK,
 943 };
 944 static const unsigned int du1_cde_pins[] = {
 945         /* CDE */
 946         RCAR_GP_PIN(1, 22),
 947 };
 948 static const unsigned int du1_cde_mux[] = {
 949         DU1_CDE_MARK,
 950 };
 951 /* - INTC ------------------------------------------------------------------- */
 952 static const unsigned int intc_irq0_pins[] = {
 953         /* IRQ0 */
 954         RCAR_GP_PIN(3, 19),
 955 };
 956 static const unsigned int intc_irq0_mux[] = {
 957         IRQ0_MARK,
 958 };
 959 static const unsigned int intc_irq1_pins[] = {
 960         /* IRQ1 */
 961         RCAR_GP_PIN(3, 20),
 962 };
 963 static const unsigned int intc_irq1_mux[] = {
 964         IRQ1_MARK,
 965 };
 966 static const unsigned int intc_irq2_pins[] = {
 967         /* IRQ2 */
 968         RCAR_GP_PIN(3, 21),
 969 };
 970 static const unsigned int intc_irq2_mux[] = {
 971         IRQ2_MARK,
 972 };
 973 static const unsigned int intc_irq3_pins[] = {
 974         /* IRQ3 */
 975         RCAR_GP_PIN(3, 22),
 976 };
 977 static const unsigned int intc_irq3_mux[] = {
 978         IRQ3_MARK,
 979 };
 980 /* - LBSC ------------------------------------------------------------------- */
 981 static const unsigned int lbsc_cs0_pins[] = {
 982         /* CS0# */
 983         RCAR_GP_PIN(3, 27),
 984 };
 985 static const unsigned int lbsc_cs0_mux[] = {
 986         CS0_N_MARK,
 987 };
 988 static const unsigned int lbsc_cs1_pins[] = {
 989         /* CS1#_A26 */
 990         RCAR_GP_PIN(3, 6),
 991 };
 992 static const unsigned int lbsc_cs1_mux[] = {
 993         CS1_N_A26_MARK,
 994 };
 995 static const unsigned int lbsc_ex_cs0_pins[] = {
 996         /* EX_CS0# */
 997         RCAR_GP_PIN(3, 7),
 998 };
 999 static const unsigned int lbsc_ex_cs0_mux[] = {
1000         EX_CS0_N_MARK,
1001 };
1002 static const unsigned int lbsc_ex_cs1_pins[] = {
1003         /* EX_CS1# */
1004         RCAR_GP_PIN(3, 8),
1005 };
1006 static const unsigned int lbsc_ex_cs1_mux[] = {
1007         EX_CS1_N_MARK,
1008 };
1009 static const unsigned int lbsc_ex_cs2_pins[] = {
1010         /* EX_CS2# */
1011         RCAR_GP_PIN(3, 9),
1012 };
1013 static const unsigned int lbsc_ex_cs2_mux[] = {
1014         EX_CS2_N_MARK,
1015 };
1016 static const unsigned int lbsc_ex_cs3_pins[] = {
1017         /* EX_CS3# */
1018         RCAR_GP_PIN(3, 10),
1019 };
1020 static const unsigned int lbsc_ex_cs3_mux[] = {
1021         EX_CS3_N_MARK,
1022 };
1023 static const unsigned int lbsc_ex_cs4_pins[] = {
1024         /* EX_CS4# */
1025         RCAR_GP_PIN(3, 11),
1026 };
1027 static const unsigned int lbsc_ex_cs4_mux[] = {
1028         EX_CS4_N_MARK,
1029 };
1030 static const unsigned int lbsc_ex_cs5_pins[] = {
1031         /* EX_CS5# */
1032         RCAR_GP_PIN(3, 12),
1033 };
1034 static const unsigned int lbsc_ex_cs5_mux[] = {
1035         EX_CS5_N_MARK,
1036 };
1037 /* - QSPI ------------------------------------------------------------------- */
1038 static const unsigned int qspi_ctrl_pins[] = {
1039         /* SPCLK, SSL */
1040         RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
1041 };
1042 static const unsigned int qspi_ctrl_mux[] = {
1043         SPCLK_MARK, SSL_MARK,
1044 };
1045 static const unsigned int qspi_data2_pins[] = {
1046         /* MOSI_IO0, MISO_IO1 */
1047         RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
1048 };
1049 static const unsigned int qspi_data2_mux[] = {
1050         MOSI_IO0_MARK, MISO_IO1_MARK,
1051 };
1052 static const unsigned int qspi_data4_pins[] = {
1053         /* MOSI_IO0, MISO_IO1, IO2, IO3 */
1054         RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 23),
1055         RCAR_GP_PIN(3, 24),
1056 };
1057 static const unsigned int qspi_data4_mux[] = {
1058         MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
1059 };
1060 /* - SCIF0 ------------------------------------------------------------------ */
1061 static const unsigned int scif0_data_pins[] = {
1062         /* RX, TX */
1063         RCAR_GP_PIN(10, 14), RCAR_GP_PIN(10, 13),
1064 };
1065 static const unsigned int scif0_data_mux[] = {
1066         RX0_MARK, TX0_MARK,
1067 };
1068 static const unsigned int scif0_clk_pins[] = {
1069         /* SCK */
1070         RCAR_GP_PIN(10, 10),
1071 };
1072 static const unsigned int scif0_clk_mux[] = {
1073         SCK0_MARK,
1074 };
1075 static const unsigned int scif0_ctrl_pins[] = {
1076         /* RTS, CTS */
1077         RCAR_GP_PIN(10, 12), RCAR_GP_PIN(10, 11),
1078 };
1079 static const unsigned int scif0_ctrl_mux[] = {
1080         RTS0_N_MARK, CTS0_N_MARK,
1081 };
1082 /* - SCIF3 ------------------------------------------------------------------ */
1083 static const unsigned int scif3_data_pins[] = {
1084         /* RX, TX */
1085         RCAR_GP_PIN(10, 25), RCAR_GP_PIN(10, 24),
1086 };
1087 static const unsigned int scif3_data_mux[] = {
1088         RX3_MARK, TX3_MARK,
1089 };
1090 static const unsigned int scif3_clk_pins[] = {
1091         /* SCK */
1092         RCAR_GP_PIN(10, 23),
1093 };
1094 static const unsigned int scif3_clk_mux[] = {
1095         SCK3_MARK,
1096 };
1097 /* - SDHI0 ------------------------------------------------------------------ */
1098 static const unsigned int sdhi0_data1_pins[] = {
1099         /* DAT0 */
1100         RCAR_GP_PIN(11, 7),
1101 };
1102 static const unsigned int sdhi0_data1_mux[] = {
1103         SD0_DAT0_MARK,
1104 };
1105 static const unsigned int sdhi0_data4_pins[] = {
1106         /* DAT[0-3] */
1107         RCAR_GP_PIN(11, 7), RCAR_GP_PIN(11, 8),
1108         RCAR_GP_PIN(11, 9), RCAR_GP_PIN(11, 10),
1109 };
1110 static const unsigned int sdhi0_data4_mux[] = {
1111         SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
1112 };
1113 static const unsigned int sdhi0_ctrl_pins[] = {
1114         /* CLK, CMD */
1115         RCAR_GP_PIN(11, 5), RCAR_GP_PIN(11, 6),
1116 };
1117 static const unsigned int sdhi0_ctrl_mux[] = {
1118         SD0_CLK_MARK, SD0_CMD_MARK,
1119 };
1120 static const unsigned int sdhi0_cd_pins[] = {
1121         /* CD */
1122         RCAR_GP_PIN(11, 11),
1123 };
1124 static const unsigned int sdhi0_cd_mux[] = {
1125         SD0_CD_MARK,
1126 };
1127 static const unsigned int sdhi0_wp_pins[] = {
1128         /* WP */
1129         RCAR_GP_PIN(11, 12),
1130 };
1131 static const unsigned int sdhi0_wp_mux[] = {
1132         SD0_WP_MARK,
1133 };
1134 /* - VIN0 ------------------------------------------------------------------- */
1135 static const union vin_data vin0_data_pins = {
1136         .data24 = {
1137                 /* B */
1138                 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
1139                 RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
1140                 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
1141                 RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
1142                 /* G */
1143                 RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 13),
1144                 RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
1145                 RCAR_GP_PIN(8, 1), RCAR_GP_PIN(8, 2),
1146                 RCAR_GP_PIN(8, 3), RCAR_GP_PIN(8, 4),
1147                 /* R */
1148                 RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 6),
1149                 RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8),
1150                 RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 10),
1151                 RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 12),
1152         },
1153 };
1154 static const union vin_data vin0_data_mux = {
1155         .data24 = {
1156                 /* B */
1157                 VI0_D0_B0_C0_MARK, VI0_D1_B1_C1_MARK,
1158                 VI0_D2_B2_C2_MARK, VI0_D3_B3_C3_MARK,
1159                 VI0_D4_B4_C4_MARK, VI0_D5_B5_C5_MARK,
1160                 VI0_D6_B6_C6_MARK, VI0_D7_B7_C7_MARK,
1161                 /* G */
1162                 VI0_D8_G0_Y0_MARK, VI0_D9_G1_Y1_MARK,
1163                 VI0_D10_G2_Y2_MARK, VI0_D11_G3_Y3_MARK,
1164                 VI0_D12_G4_Y4_MARK, VI0_D13_G5_Y5_MARK,
1165                 VI0_D14_G6_Y6_MARK, VI0_D15_G7_Y7_MARK,
1166                 /* R */
1167                 VI0_D16_R0_MARK, VI0_D17_R1_MARK,
1168                 VI0_D18_R2_MARK, VI0_D19_R3_MARK,
1169                 VI0_D20_R4_MARK, VI0_D21_R5_MARK,
1170                 VI0_D22_R6_MARK, VI0_D23_R7_MARK,
1171         },
1172 };
1173 static const unsigned int vin0_data18_pins[] = {
1174         /* B */
1175         RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
1176         RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
1177         RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
1178         /* G */
1179         RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
1180         RCAR_GP_PIN(8, 1), RCAR_GP_PIN(8, 2),
1181         RCAR_GP_PIN(8, 3), RCAR_GP_PIN(8, 4),
1182         /* R */
1183         RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8),
1184         RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 10),
1185         RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 12),
1186 };
1187 static const unsigned int vin0_data18_mux[] = {
1188         /* B */
1189         VI0_D2_B2_C2_MARK, VI0_D3_B3_C3_MARK,
1190         VI0_D4_B4_C4_MARK, VI0_D5_B5_C5_MARK,
1191         VI0_D6_B6_C6_MARK, VI0_D7_B7_C7_MARK,
1192         /* G */
1193         VI0_D10_G2_Y2_MARK, VI0_D11_G3_Y3_MARK,
1194         VI0_D12_G4_Y4_MARK, VI0_D13_G5_Y5_MARK,
1195         VI0_D14_G6_Y6_MARK, VI0_D15_G7_Y7_MARK,
1196         /* R */
1197         VI0_D18_R2_MARK, VI0_D19_R3_MARK,
1198         VI0_D20_R4_MARK, VI0_D21_R5_MARK,
1199         VI0_D22_R6_MARK, VI0_D23_R7_MARK,
1200 };
1201 static const unsigned int vin0_sync_pins[] = {
1202         /* HSYNC#, VSYNC# */
1203         RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
1204 };
1205 static const unsigned int vin0_sync_mux[] = {
1206         VI0_HSYNC_N_MARK, VI0_VSYNC_N_MARK,
1207 };
1208 static const unsigned int vin0_field_pins[] = {
1209         RCAR_GP_PIN(4, 16),
1210 };
1211 static const unsigned int vin0_field_mux[] = {
1212         VI0_FIELD_MARK,
1213 };
1214 static const unsigned int vin0_clkenb_pins[] = {
1215         RCAR_GP_PIN(4, 1),
1216 };
1217 static const unsigned int vin0_clkenb_mux[] = {
1218         VI0_CLKENB_MARK,
1219 };
1220 static const unsigned int vin0_clk_pins[] = {
1221         RCAR_GP_PIN(4, 0),
1222 };
1223 static const unsigned int vin0_clk_mux[] = {
1224         VI0_CLK_MARK,
1225 };
1226 /* - VIN1 ------------------------------------------------------------------- */
1227 static const union vin_data vin1_data_pins = {
1228         .data24 = {
1229                 /* B */
1230                 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
1231                 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
1232                 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
1233                 RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
1234                 /* G */
1235                 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13),
1236                 RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
1237                 RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 6),
1238                 RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8),
1239                 /* R */
1240                 RCAR_GP_PIN(9, 5), RCAR_GP_PIN(9, 6),
1241                 RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8),
1242                 RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10),
1243                 RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12),
1244         },
1245 };
1246 static const union vin_data vin1_data_mux = {
1247         .data24 = {
1248                 /* B */
1249                 VI1_D0_B0_C0_MARK, VI1_D1_B1_C1_MARK,
1250                 VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK,
1251                 VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,
1252                 VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK,
1253                 /* G */
1254                 VI1_D8_G0_Y0_MARK, VI1_D9_G1_Y1_MARK,
1255                 VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,
1256                 VI1_D12_G4_Y4_MARK, VI1_D13_G5_Y5_MARK,
1257                 VI1_D14_G6_Y6_MARK, VI1_D15_G7_Y7_MARK,
1258                 /* R */
1259                 VI1_D16_R0_MARK, VI1_D17_R1_MARK,
1260                 VI1_D18_R2_MARK, VI1_D19_R3_MARK,
1261                 VI1_D20_R4_MARK, VI1_D21_R5_MARK,
1262                 VI1_D22_R6_MARK, VI1_D23_R7_MARK,
1263         },
1264 };
1265 static const unsigned int vin1_data18_pins[] = {
1266         /* B */
1267         RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
1268         RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
1269         RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
1270         /* G */
1271         RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
1272         RCAR_GP_PIN(8, 5), RCAR_GP_PIN(8, 6),
1273         RCAR_GP_PIN(8, 7), RCAR_GP_PIN(8, 8),
1274         /* R */
1275         RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8),
1276         RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10),
1277         RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12),
1278 };
1279 static const unsigned int vin1_data18_mux[] = {
1280         /* B */
1281         VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK,
1282         VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,
1283         VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK,
1284         /* G */
1285         VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,
1286         VI1_D12_G4_Y4_MARK, VI1_D13_G5_Y5_MARK,
1287         VI1_D14_G6_Y6_MARK, VI1_D15_G7_Y7_MARK,
1288         /* R */
1289         VI1_D18_R2_MARK, VI1_D19_R3_MARK,
1290         VI1_D20_R4_MARK, VI1_D21_R5_MARK,
1291         VI1_D22_R6_MARK, VI1_D23_R7_MARK,
1292 };
1293 static const union vin_data vin1_data_b_pins = {
1294         .data24 = {
1295                 /* B */
1296                 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
1297                 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
1298                 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
1299                 RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
1300                 /* G */
1301                 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13),
1302                 RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
1303                 RCAR_GP_PIN(9, 1), RCAR_GP_PIN(9, 2),
1304                 RCAR_GP_PIN(9, 3), RCAR_GP_PIN(9, 4),
1305                 /* R */
1306                 RCAR_GP_PIN(9, 5), RCAR_GP_PIN(9, 6),
1307                 RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8),
1308                 RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10),
1309                 RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12),
1310         },
1311 };
1312 static const union vin_data vin1_data_b_mux = {
1313         .data24 = {
1314                 /* B */
1315                 VI1_D0_B0_C0_MARK, VI1_D1_B1_C1_MARK,
1316                 VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK,
1317                 VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,
1318                 VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK,
1319                 /* G */
1320                 VI1_D8_G0_Y0_MARK, VI1_D9_G1_Y1_MARK,
1321                 VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,
1322                 VI1_D12_G4_Y4_B_MARK, VI1_D13_G5_Y5_B_MARK,
1323                 VI1_D14_G6_Y6_B_MARK, VI1_D15_G7_Y7_B_MARK,
1324                 /* R */
1325                 VI1_D16_R0_MARK, VI1_D17_R1_MARK,
1326                 VI1_D18_R2_MARK, VI1_D19_R3_MARK,
1327                 VI1_D20_R4_MARK, VI1_D21_R5_MARK,
1328                 VI1_D22_R6_MARK, VI1_D23_R7_MARK,
1329         },
1330 };
1331 static const unsigned int vin1_data18_b_pins[] = {
1332         /* B */
1333         RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
1334         RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
1335         RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
1336         /* G */
1337         RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
1338         RCAR_GP_PIN(9, 1), RCAR_GP_PIN(9, 2),
1339         RCAR_GP_PIN(9, 3), RCAR_GP_PIN(9, 4),
1340         /* R */
1341         RCAR_GP_PIN(9, 7), RCAR_GP_PIN(9, 8),
1342         RCAR_GP_PIN(9, 9), RCAR_GP_PIN(9, 10),
1343         RCAR_GP_PIN(9, 11), RCAR_GP_PIN(9, 12),
1344 };
1345 static const unsigned int vin1_data18_b_mux[] = {
1346         /* B */
1347         VI1_D2_B2_C2_MARK, VI1_D3_B3_C3_MARK,
1348         VI1_D4_B4_C4_MARK, VI1_D5_B5_C5_MARK,
1349         VI1_D6_B6_C6_MARK, VI1_D7_B7_C7_MARK,
1350         /* G */
1351         VI1_D10_G2_Y2_MARK, VI1_D11_G3_Y3_MARK,
1352         VI1_D12_G4_Y4_B_MARK, VI1_D13_G5_Y5_B_MARK,
1353         VI1_D14_G6_Y6_B_MARK, VI1_D15_G7_Y7_B_MARK,
1354         /* R */
1355         VI1_D18_R2_MARK, VI1_D19_R3_MARK,
1356         VI1_D20_R4_MARK, VI1_D21_R5_MARK,
1357         VI1_D22_R6_MARK, VI1_D23_R7_MARK,
1358 };
1359 static const unsigned int vin1_sync_pins[] = {
1360         /* HSYNC#, VSYNC# */
1361         RCAR_GP_PIN(5, 2), RCAR_GP_PIN(5, 3),
1362 };
1363 static const unsigned int vin1_sync_mux[] = {
1364         VI1_HSYNC_N_MARK, VI1_VSYNC_N_MARK,
1365 };
1366 static const unsigned int vin1_field_pins[] = {
1367         RCAR_GP_PIN(5, 16),
1368 };
1369 static const unsigned int vin1_field_mux[] = {
1370         VI1_FIELD_MARK,
1371 };
1372 static const unsigned int vin1_clkenb_pins[] = {
1373         RCAR_GP_PIN(5, 1),
1374 };
1375 static const unsigned int vin1_clkenb_mux[] = {
1376         VI1_CLKENB_MARK,
1377 };
1378 static const unsigned int vin1_clk_pins[] = {
1379         RCAR_GP_PIN(5, 0),
1380 };
1381 static const unsigned int vin1_clk_mux[] = {
1382         VI1_CLK_MARK,
1383 };
1384 /* - VIN2 ------------------------------------------------------------------- */
1385 static const union vin_data vin2_data_pins = {
1386         .data16 = {
1387                 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
1388                 RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7),
1389                 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1390                 RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11),
1391                 RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13),
1392                 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
1393                 RCAR_GP_PIN(8, 9), RCAR_GP_PIN(8, 10),
1394                 RCAR_GP_PIN(8, 11), RCAR_GP_PIN(8, 12),
1395         },
1396 };
1397 static const union vin_data vin2_data_mux = {
1398         .data16 = {
1399                 VI2_D0_C0_MARK, VI2_D1_C1_MARK,
1400                 VI2_D2_C2_MARK, VI2_D3_C3_MARK,
1401                 VI2_D4_C4_MARK, VI2_D5_C5_MARK,
1402                 VI2_D6_C6_MARK, VI2_D7_C7_MARK,
1403                 VI2_D8_Y0_MARK, VI2_D9_Y1_MARK,
1404                 VI2_D10_Y2_MARK, VI2_D11_Y3_MARK,
1405                 VI2_D12_Y4_MARK, VI2_D13_Y5_MARK,
1406                 VI2_D14_Y6_MARK, VI2_D15_Y7_MARK,
1407         },
1408 };
1409 static const unsigned int vin2_sync_pins[] = {
1410         /* HSYNC#, VSYNC# */
1411         RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
1412 };
1413 static const unsigned int vin2_sync_mux[] = {
1414         VI2_HSYNC_N_MARK, VI2_VSYNC_N_MARK,
1415 };
1416 static const unsigned int vin2_field_pins[] = {
1417         RCAR_GP_PIN(6, 16),
1418 };
1419 static const unsigned int vin2_field_mux[] = {
1420         VI2_FIELD_MARK,
1421 };
1422 static const unsigned int vin2_clkenb_pins[] = {
1423         RCAR_GP_PIN(6, 1),
1424 };
1425 static const unsigned int vin2_clkenb_mux[] = {
1426         VI2_CLKENB_MARK,
1427 };
1428 static const unsigned int vin2_clk_pins[] = {
1429         RCAR_GP_PIN(6, 0),
1430 };
1431 static const unsigned int vin2_clk_mux[] = {
1432         VI2_CLK_MARK,
1433 };
1434 /* - VIN3 ------------------------------------------------------------------- */
1435 static const union vin_data vin3_data_pins = {
1436         .data16 = {
1437                 RCAR_GP_PIN(7, 4), RCAR_GP_PIN(7, 5),
1438                 RCAR_GP_PIN(7, 6), RCAR_GP_PIN(7, 7),
1439                 RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9),
1440                 RCAR_GP_PIN(7, 10), RCAR_GP_PIN(7, 11),
1441                 RCAR_GP_PIN(7, 12), RCAR_GP_PIN(7, 13),
1442                 RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 15),
1443                 RCAR_GP_PIN(8, 13), RCAR_GP_PIN(8, 14),
1444                 RCAR_GP_PIN(8, 15), RCAR_GP_PIN(8, 16),
1445         },
1446 };
1447 static const union vin_data vin3_data_mux = {
1448         .data16 = {
1449                 VI3_D0_C0_MARK, VI3_D1_C1_MARK,
1450                 VI3_D2_C2_MARK, VI3_D3_C3_MARK,
1451                 VI3_D4_C4_MARK, VI3_D5_C5_MARK,
1452                 VI3_D6_C6_MARK, VI3_D7_C7_MARK,
1453                 VI3_D8_Y0_MARK, VI3_D9_Y1_MARK,
1454                 VI3_D10_Y2_MARK, VI3_D11_Y3_MARK,
1455                 VI3_D12_Y4_MARK, VI3_D13_Y5_MARK,
1456                 VI3_D14_Y6_MARK, VI3_D15_Y7_MARK,
1457         },
1458 };
1459 static const unsigned int vin3_sync_pins[] = {
1460         /* HSYNC#, VSYNC# */
1461         RCAR_GP_PIN(7, 2), RCAR_GP_PIN(7, 3),
1462 };
1463 static const unsigned int vin3_sync_mux[] = {
1464         VI3_HSYNC_N_MARK, VI3_VSYNC_N_MARK,
1465 };
1466 static const unsigned int vin3_field_pins[] = {
1467         RCAR_GP_PIN(7, 16),
1468 };
1469 static const unsigned int vin3_field_mux[] = {
1470         VI3_FIELD_MARK,
1471 };
1472 static const unsigned int vin3_clkenb_pins[] = {
1473         RCAR_GP_PIN(7, 1),
1474 };
1475 static const unsigned int vin3_clkenb_mux[] = {
1476         VI3_CLKENB_MARK,
1477 };
1478 static const unsigned int vin3_clk_pins[] = {
1479         RCAR_GP_PIN(7, 0),
1480 };
1481 static const unsigned int vin3_clk_mux[] = {
1482         VI3_CLK_MARK,
1483 };
1484 /* - VIN4 ------------------------------------------------------------------- */
1485 static const union vin_data vin4_data_pins = {
1486         .data12 = {
1487                 RCAR_GP_PIN(8, 4), RCAR_GP_PIN(8, 5),
1488                 RCAR_GP_PIN(8, 6), RCAR_GP_PIN(8, 7),
1489                 RCAR_GP_PIN(8, 8), RCAR_GP_PIN(8, 9),
1490                 RCAR_GP_PIN(8, 10), RCAR_GP_PIN(8, 11),
1491                 RCAR_GP_PIN(8, 12), RCAR_GP_PIN(8, 13),
1492                 RCAR_GP_PIN(8, 14), RCAR_GP_PIN(8, 15),
1493         },
1494 };
1495 static const union vin_data vin4_data_mux = {
1496         .data12 = {
1497                 VI4_D0_C0_MARK, VI4_D1_C1_MARK,
1498                 VI4_D2_C2_MARK, VI4_D3_C3_MARK,
1499                 VI4_D4_C4_MARK, VI4_D5_C5_MARK,
1500                 VI4_D6_C6_MARK, VI4_D7_C7_MARK,
1501                 VI4_D8_Y0_MARK, VI4_D9_Y1_MARK,
1502                 VI4_D10_Y2_MARK, VI4_D11_Y3_MARK,
1503         },
1504 };
1505 static const unsigned int vin4_sync_pins[] = {
1506          /* HSYNC#, VSYNC# */
1507         RCAR_GP_PIN(8, 2), RCAR_GP_PIN(8, 3),
1508 };
1509 static const unsigned int vin4_sync_mux[] = {
1510         VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
1511 };
1512 static const unsigned int vin4_field_pins[] = {
1513         RCAR_GP_PIN(8, 16),
1514 };
1515 static const unsigned int vin4_field_mux[] = {
1516         VI4_FIELD_MARK,
1517 };
1518 static const unsigned int vin4_clkenb_pins[] = {
1519         RCAR_GP_PIN(8, 1),
1520 };
1521 static const unsigned int vin4_clkenb_mux[] = {
1522         VI4_CLKENB_MARK,
1523 };
1524 static const unsigned int vin4_clk_pins[] = {
1525         RCAR_GP_PIN(8, 0),
1526 };
1527 static const unsigned int vin4_clk_mux[] = {
1528         VI4_CLK_MARK,
1529 };
1530 /* - VIN5 ------------------------------------------------------------------- */
1531 static const union vin_data vin5_data_pins = {
1532         .data12 = {
1533                 RCAR_GP_PIN(9, 4), RCAR_GP_PIN(9, 5),
1534                 RCAR_GP_PIN(9, 6), RCAR_GP_PIN(9, 7),
1535                 RCAR_GP_PIN(9, 8), RCAR_GP_PIN(9, 9),
1536                 RCAR_GP_PIN(9, 10), RCAR_GP_PIN(9, 11),
1537                 RCAR_GP_PIN(9, 12), RCAR_GP_PIN(9, 13),
1538                 RCAR_GP_PIN(9, 14), RCAR_GP_PIN(9, 15),
1539         },
1540 };
1541 static const union vin_data vin5_data_mux = {
1542         .data12 = {
1543                 VI5_D0_C0_MARK, VI5_D1_C1_MARK,
1544                 VI5_D2_C2_MARK, VI5_D3_C3_MARK,
1545                 VI5_D4_C4_MARK, VI5_D5_C5_MARK,
1546                 VI5_D6_C6_MARK, VI5_D7_C7_MARK,
1547                 VI5_D8_Y0_MARK, VI5_D9_Y1_MARK,
1548                 VI5_D10_Y2_MARK, VI5_D11_Y3_MARK,
1549         },
1550 };
1551 static const unsigned int vin5_sync_pins[] = {
1552         /* HSYNC#, VSYNC# */
1553         RCAR_GP_PIN(9, 2), RCAR_GP_PIN(9, 3),
1554 };
1555 static const unsigned int vin5_sync_mux[] = {
1556         VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK,
1557 };
1558 static const unsigned int vin5_field_pins[] = {
1559         RCAR_GP_PIN(9, 16),
1560 };
1561 static const unsigned int vin5_field_mux[] = {
1562         VI5_FIELD_MARK,
1563 };
1564 static const unsigned int vin5_clkenb_pins[] = {
1565         RCAR_GP_PIN(9, 1),
1566 };
1567 static const unsigned int vin5_clkenb_mux[] = {
1568         VI5_CLKENB_MARK,
1569 };
1570 static const unsigned int vin5_clk_pins[] = {
1571         RCAR_GP_PIN(9, 0),
1572 };
1573 static const unsigned int vin5_clk_mux[] = {
1574         VI5_CLK_MARK,
1575 };
1576
1577 static const struct sh_pfc_pin_group pinmux_groups[] = {
1578         SH_PFC_PIN_GROUP(avb_link),
1579         SH_PFC_PIN_GROUP(avb_magic),
1580         SH_PFC_PIN_GROUP(avb_phy_int),
1581         SH_PFC_PIN_GROUP(avb_mdio),
1582         SH_PFC_PIN_GROUP(avb_mii),
1583         SH_PFC_PIN_GROUP(avb_gmii),
1584         SH_PFC_PIN_GROUP(avb_avtp_match),
1585         SH_PFC_PIN_GROUP(can0_data),
1586         SH_PFC_PIN_GROUP(can1_data),
1587         SH_PFC_PIN_GROUP(can_clk),
1588         SH_PFC_PIN_GROUP(du0_rgb666),
1589         SH_PFC_PIN_GROUP(du0_rgb888),
1590         SH_PFC_PIN_GROUP(du0_sync),
1591         SH_PFC_PIN_GROUP(du0_oddf),
1592         SH_PFC_PIN_GROUP(du0_disp),
1593         SH_PFC_PIN_GROUP(du0_cde),
1594         SH_PFC_PIN_GROUP(du1_rgb666),
1595         SH_PFC_PIN_GROUP(du1_sync),
1596         SH_PFC_PIN_GROUP(du1_oddf),
1597         SH_PFC_PIN_GROUP(du1_disp),
1598         SH_PFC_PIN_GROUP(du1_cde),
1599         SH_PFC_PIN_GROUP(intc_irq0),
1600         SH_PFC_PIN_GROUP(intc_irq1),
1601         SH_PFC_PIN_GROUP(intc_irq2),
1602         SH_PFC_PIN_GROUP(intc_irq3),
1603         SH_PFC_PIN_GROUP(lbsc_cs0),
1604         SH_PFC_PIN_GROUP(lbsc_cs1),
1605         SH_PFC_PIN_GROUP(lbsc_ex_cs0),
1606         SH_PFC_PIN_GROUP(lbsc_ex_cs1),
1607         SH_PFC_PIN_GROUP(lbsc_ex_cs2),
1608         SH_PFC_PIN_GROUP(lbsc_ex_cs3),
1609         SH_PFC_PIN_GROUP(lbsc_ex_cs4),
1610         SH_PFC_PIN_GROUP(lbsc_ex_cs5),
1611         SH_PFC_PIN_GROUP(qspi_ctrl),
1612         SH_PFC_PIN_GROUP(qspi_data2),
1613         SH_PFC_PIN_GROUP(qspi_data4),
1614         SH_PFC_PIN_GROUP(scif0_data),
1615         SH_PFC_PIN_GROUP(scif0_clk),
1616         SH_PFC_PIN_GROUP(scif0_ctrl),
1617         SH_PFC_PIN_GROUP(scif3_data),
1618         SH_PFC_PIN_GROUP(scif3_clk),
1619         SH_PFC_PIN_GROUP(sdhi0_data1),
1620         SH_PFC_PIN_GROUP(sdhi0_data4),
1621         SH_PFC_PIN_GROUP(sdhi0_ctrl),
1622         SH_PFC_PIN_GROUP(sdhi0_cd),
1623         SH_PFC_PIN_GROUP(sdhi0_wp),
1624         VIN_DATA_PIN_GROUP(vin0_data, 24),
1625         VIN_DATA_PIN_GROUP(vin0_data, 20),
1626         SH_PFC_PIN_GROUP(vin0_data18),
1627         VIN_DATA_PIN_GROUP(vin0_data, 16),
1628         VIN_DATA_PIN_GROUP(vin0_data, 12),
1629         VIN_DATA_PIN_GROUP(vin0_data, 10),
1630         VIN_DATA_PIN_GROUP(vin0_data, 8),
1631         SH_PFC_PIN_GROUP(vin0_sync),
1632         SH_PFC_PIN_GROUP(vin0_field),
1633         SH_PFC_PIN_GROUP(vin0_clkenb),
1634         SH_PFC_PIN_GROUP(vin0_clk),
1635         VIN_DATA_PIN_GROUP(vin1_data, 24),
1636         VIN_DATA_PIN_GROUP(vin1_data, 20),
1637         SH_PFC_PIN_GROUP(vin1_data18),
1638         VIN_DATA_PIN_GROUP(vin1_data, 16),
1639         VIN_DATA_PIN_GROUP(vin1_data, 12),
1640         VIN_DATA_PIN_GROUP(vin1_data, 10),
1641         VIN_DATA_PIN_GROUP(vin1_data, 8),
1642         VIN_DATA_PIN_GROUP(vin1_data_b, 24),
1643         VIN_DATA_PIN_GROUP(vin1_data_b, 20),
1644         SH_PFC_PIN_GROUP(vin1_data18_b),
1645         VIN_DATA_PIN_GROUP(vin1_data_b, 16),
1646         SH_PFC_PIN_GROUP(vin1_sync),
1647         SH_PFC_PIN_GROUP(vin1_field),
1648         SH_PFC_PIN_GROUP(vin1_clkenb),
1649         SH_PFC_PIN_GROUP(vin1_clk),
1650         VIN_DATA_PIN_GROUP(vin2_data, 16),
1651         VIN_DATA_PIN_GROUP(vin2_data, 12),
1652         VIN_DATA_PIN_GROUP(vin2_data, 10),
1653         VIN_DATA_PIN_GROUP(vin2_data, 8),
1654         SH_PFC_PIN_GROUP(vin2_sync),
1655         SH_PFC_PIN_GROUP(vin2_field),
1656         SH_PFC_PIN_GROUP(vin2_clkenb),
1657         SH_PFC_PIN_GROUP(vin2_clk),
1658         VIN_DATA_PIN_GROUP(vin3_data, 16),
1659         VIN_DATA_PIN_GROUP(vin3_data, 12),
1660         VIN_DATA_PIN_GROUP(vin3_data, 10),
1661         VIN_DATA_PIN_GROUP(vin3_data, 8),
1662         SH_PFC_PIN_GROUP(vin3_sync),
1663         SH_PFC_PIN_GROUP(vin3_field),
1664         SH_PFC_PIN_GROUP(vin3_clkenb),
1665         SH_PFC_PIN_GROUP(vin3_clk),
1666         VIN_DATA_PIN_GROUP(vin4_data, 12),
1667         VIN_DATA_PIN_GROUP(vin4_data, 10),
1668         VIN_DATA_PIN_GROUP(vin4_data, 8),
1669         SH_PFC_PIN_GROUP(vin4_sync),
1670         SH_PFC_PIN_GROUP(vin4_field),
1671         SH_PFC_PIN_GROUP(vin4_clkenb),
1672         SH_PFC_PIN_GROUP(vin4_clk),
1673         VIN_DATA_PIN_GROUP(vin5_data, 12),
1674         VIN_DATA_PIN_GROUP(vin5_data, 10),
1675         VIN_DATA_PIN_GROUP(vin5_data, 8),
1676         SH_PFC_PIN_GROUP(vin5_sync),
1677         SH_PFC_PIN_GROUP(vin5_field),
1678         SH_PFC_PIN_GROUP(vin5_clkenb),
1679         SH_PFC_PIN_GROUP(vin5_clk),
1680 };
1681
1682 static const char * const avb_groups[] = {
1683         "avb_link",
1684         "avb_magic",
1685         "avb_phy_int",
1686         "avb_mdio",
1687         "avb_mii",
1688         "avb_gmii",
1689         "avb_avtp_match",
1690 };
1691
1692 static const char * const can0_groups[] = {
1693         "can0_data",
1694         "can_clk",
1695 };
1696
1697 static const char * const can1_groups[] = {
1698         "can1_data",
1699         "can_clk",
1700 };
1701
1702 static const char * const du0_groups[] = {
1703         "du0_rgb666",
1704         "du0_rgb888",
1705         "du0_sync",
1706         "du0_oddf",
1707         "du0_disp",
1708         "du0_cde",
1709 };
1710
1711 static const char * const du1_groups[] = {
1712         "du1_rgb666",
1713         "du1_sync",
1714         "du1_oddf",
1715         "du1_disp",
1716         "du1_cde",
1717 };
1718
1719 static const char * const intc_groups[] = {
1720         "intc_irq0",
1721         "intc_irq1",
1722         "intc_irq2",
1723         "intc_irq3",
1724 };
1725
1726 static const char * const lbsc_groups[] = {
1727         "lbsc_cs0",
1728         "lbsc_cs1",
1729         "lbsc_ex_cs0",
1730         "lbsc_ex_cs1",
1731         "lbsc_ex_cs2",
1732         "lbsc_ex_cs3",
1733         "lbsc_ex_cs4",
1734         "lbsc_ex_cs5",
1735 };
1736
1737 static const char * const qspi_groups[] = {
1738         "qspi_ctrl",
1739         "qspi_data2",
1740         "qspi_data4",
1741 };
1742
1743 static const char * const scif0_groups[] = {
1744         "scif0_data",
1745         "scif0_clk",
1746         "scif0_ctrl",
1747 };
1748
1749 static const char * const scif3_groups[] = {
1750         "scif3_data",
1751         "scif3_clk",
1752 };
1753
1754 static const char * const sdhi0_groups[] = {
1755         "sdhi0_data1",
1756         "sdhi0_data4",
1757         "sdhi0_ctrl",
1758         "sdhi0_cd",
1759         "sdhi0_wp",
1760 };
1761
1762 static const char * const vin0_groups[] = {
1763         "vin0_data24",
1764         "vin0_data20",
1765         "vin0_data18",
1766         "vin0_data16",
1767         "vin0_data12",
1768         "vin0_data10",
1769         "vin0_data8",
1770         "vin0_sync",
1771         "vin0_field",
1772         "vin0_clkenb",
1773         "vin0_clk",
1774 };
1775
1776 static const char * const vin1_groups[] = {
1777         "vin1_data24",
1778         "vin1_data20",
1779         "vin1_data18",
1780         "vin1_data16",
1781         "vin1_data12",
1782         "vin1_data10",
1783         "vin1_data8",
1784         "vin1_data24_b",
1785         "vin1_data20_b",
1786         "vin1_data16_b",
1787         "vin1_sync",
1788         "vin1_field",
1789         "vin1_clkenb",
1790         "vin1_clk",
1791 };
1792
1793 static const char * const vin2_groups[] = {
1794         "vin2_data16",
1795         "vin2_data12",
1796         "vin2_data10",
1797         "vin2_data8",
1798         "vin2_sync",
1799         "vin2_field",
1800         "vin2_clkenb",
1801         "vin2_clk",
1802 };
1803
1804 static const char * const vin3_groups[] = {
1805         "vin3_data16",
1806         "vin3_data12",
1807         "vin3_data10",
1808         "vin3_data8",
1809         "vin3_sync",
1810         "vin3_field",
1811         "vin3_clkenb",
1812         "vin3_clk",
1813 };
1814
1815 static const char * const vin4_groups[] = {
1816         "vin4_data12",
1817         "vin4_data10",
1818         "vin4_data8",
1819         "vin4_sync",
1820         "vin4_field",
1821         "vin4_clkenb",
1822         "vin4_clk",
1823 };
1824
1825 static const char * const vin5_groups[] = {
1826         "vin5_data12",
1827         "vin5_data10",
1828         "vin5_data8",
1829         "vin5_sync",
1830         "vin5_field",
1831         "vin5_clkenb",
1832         "vin5_clk",
1833 };
1834
1835 static const struct sh_pfc_function pinmux_functions[] = {
1836         SH_PFC_FUNCTION(avb),
1837         SH_PFC_FUNCTION(can0),
1838         SH_PFC_FUNCTION(can1),
1839         SH_PFC_FUNCTION(du0),
1840         SH_PFC_FUNCTION(du1),
1841         SH_PFC_FUNCTION(intc),
1842         SH_PFC_FUNCTION(lbsc),
1843         SH_PFC_FUNCTION(qspi),
1844         SH_PFC_FUNCTION(scif0),
1845         SH_PFC_FUNCTION(scif3),
1846         SH_PFC_FUNCTION(sdhi0),
1847         SH_PFC_FUNCTION(vin0),
1848         SH_PFC_FUNCTION(vin1),
1849         SH_PFC_FUNCTION(vin2),
1850         SH_PFC_FUNCTION(vin3),
1851         SH_PFC_FUNCTION(vin4),
1852         SH_PFC_FUNCTION(vin5),
1853 };
1854
1855 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1856         { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
1857                 0, 0,
1858                 0, 0,
1859                 0, 0,
1860                 GP_0_28_FN, FN_IP1_4,
1861                 GP_0_27_FN, FN_IP1_3,
1862                 GP_0_26_FN, FN_IP1_2,
1863                 GP_0_25_FN, FN_IP1_1,
1864                 GP_0_24_FN, FN_IP1_0,
1865                 GP_0_23_FN, FN_IP0_23,
1866                 GP_0_22_FN, FN_IP0_22,
1867                 GP_0_21_FN, FN_IP0_21,
1868                 GP_0_20_FN, FN_IP0_20,
1869                 GP_0_19_FN, FN_IP0_19,
1870                 GP_0_18_FN, FN_IP0_18,
1871                 GP_0_17_FN, FN_IP0_17,
1872                 GP_0_16_FN, FN_IP0_16,
1873                 GP_0_15_FN, FN_IP0_15,
1874                 GP_0_14_FN, FN_IP0_14,
1875                 GP_0_13_FN, FN_IP0_13,
1876                 GP_0_12_FN, FN_IP0_12,
1877                 GP_0_11_FN, FN_IP0_11,
1878                 GP_0_10_FN, FN_IP0_10,
1879                 GP_0_9_FN, FN_IP0_9,
1880                 GP_0_8_FN, FN_IP0_8,
1881                 GP_0_7_FN, FN_IP0_7,
1882                 GP_0_6_FN, FN_IP0_6,
1883                 GP_0_5_FN, FN_IP0_5,
1884                 GP_0_4_FN, FN_IP0_4,
1885                 GP_0_3_FN, FN_IP0_3,
1886                 GP_0_2_FN, FN_IP0_2,
1887                 GP_0_1_FN, FN_IP0_1,
1888                 GP_0_0_FN, FN_IP0_0 }
1889         },
1890         { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
1891                 0, 0,
1892                 0, 0,
1893                 0, 0,
1894                 0, 0,
1895                 0, 0,
1896                 0, 0,
1897                 0, 0,
1898                 0, 0,
1899                 0, 0,
1900                 GP_1_22_FN, FN_DU1_CDE,
1901                 GP_1_21_FN, FN_DU1_DISP,
1902                 GP_1_20_FN, FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,
1903                 GP_1_19_FN, FN_DU1_EXVSYNC_DU1_VSYNC,
1904                 GP_1_18_FN, FN_DU1_EXHSYNC_DU1_HSYNC,
1905                 GP_1_17_FN, FN_DU1_DB7_C5,
1906                 GP_1_16_FN, FN_DU1_DB6_C4,
1907                 GP_1_15_FN, FN_DU1_DB5_C3_DATA15,
1908                 GP_1_14_FN, FN_DU1_DB4_C2_DATA14,
1909                 GP_1_13_FN, FN_DU1_DB3_C1_DATA13,
1910                 GP_1_12_FN, FN_DU1_DB2_C0_DATA12,
1911                 GP_1_11_FN, FN_IP1_16,
1912                 GP_1_10_FN, FN_IP1_15,
1913                 GP_1_9_FN, FN_IP1_14,
1914                 GP_1_8_FN, FN_IP1_13,
1915                 GP_1_7_FN, FN_IP1_12,
1916                 GP_1_6_FN, FN_IP1_11,
1917                 GP_1_5_FN, FN_IP1_10,
1918                 GP_1_4_FN, FN_IP1_9,
1919                 GP_1_3_FN, FN_IP1_8,
1920                 GP_1_2_FN, FN_IP1_7,
1921                 GP_1_1_FN, FN_IP1_6,
1922                 GP_1_0_FN, FN_IP1_5, }
1923         },
1924         { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
1925                 GP_2_31_FN, FN_A15,
1926                 GP_2_30_FN, FN_A14,
1927                 GP_2_29_FN, FN_A13,
1928                 GP_2_28_FN, FN_A12,
1929                 GP_2_27_FN, FN_A11,
1930                 GP_2_26_FN, FN_A10,
1931                 GP_2_25_FN, FN_A9,
1932                 GP_2_24_FN, FN_A8,
1933                 GP_2_23_FN, FN_A7,
1934                 GP_2_22_FN, FN_A6,
1935                 GP_2_21_FN, FN_A5,
1936                 GP_2_20_FN, FN_A4,
1937                 GP_2_19_FN, FN_A3,
1938                 GP_2_18_FN, FN_A2,
1939                 GP_2_17_FN, FN_A1,
1940                 GP_2_16_FN, FN_A0,
1941                 GP_2_15_FN, FN_D15,
1942                 GP_2_14_FN, FN_D14,
1943                 GP_2_13_FN, FN_D13,
1944                 GP_2_12_FN, FN_D12,
1945                 GP_2_11_FN, FN_D11,
1946                 GP_2_10_FN, FN_D10,
1947                 GP_2_9_FN, FN_D9,
1948                 GP_2_8_FN, FN_D8,
1949                 GP_2_7_FN, FN_D7,
1950                 GP_2_6_FN, FN_D6,
1951                 GP_2_5_FN, FN_D5,
1952                 GP_2_4_FN, FN_D4,
1953                 GP_2_3_FN, FN_D3,
1954                 GP_2_2_FN, FN_D2,
1955                 GP_2_1_FN, FN_D1,
1956                 GP_2_0_FN, FN_D0 }
1957         },
1958         { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
1959                 0, 0,
1960                 0, 0,
1961                 0, 0,
1962                 0, 0,
1963                 GP_3_27_FN, FN_CS0_N,
1964                 GP_3_26_FN, FN_IP1_22,
1965                 GP_3_25_FN, FN_IP1_21,
1966                 GP_3_24_FN, FN_IP1_20,
1967                 GP_3_23_FN, FN_IP1_19,
1968                 GP_3_22_FN, FN_IRQ3,
1969                 GP_3_21_FN, FN_IRQ2,
1970                 GP_3_20_FN, FN_IRQ1,
1971                 GP_3_19_FN, FN_IRQ0,
1972                 GP_3_18_FN, FN_EX_WAIT0,
1973                 GP_3_17_FN, FN_WE1_N,
1974                 GP_3_16_FN, FN_WE0_N,
1975                 GP_3_15_FN, FN_RD_WR_N,
1976                 GP_3_14_FN, FN_RD_N,
1977                 GP_3_13_FN, FN_BS_N,
1978                 GP_3_12_FN, FN_EX_CS5_N,
1979                 GP_3_11_FN, FN_EX_CS4_N,
1980                 GP_3_10_FN, FN_EX_CS3_N,
1981                 GP_3_9_FN, FN_EX_CS2_N,
1982                 GP_3_8_FN, FN_EX_CS1_N,
1983                 GP_3_7_FN, FN_EX_CS0_N,
1984                 GP_3_6_FN, FN_CS1_N_A26,
1985                 GP_3_5_FN, FN_IP1_18,
1986                 GP_3_4_FN, FN_IP1_17,
1987                 GP_3_3_FN, FN_A19,
1988                 GP_3_2_FN, FN_A18,
1989                 GP_3_1_FN, FN_A17,
1990                 GP_3_0_FN, FN_A16 }
1991         },
1992         { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
1993                 0, 0,
1994                 0, 0,
1995                 0, 0,
1996                 0, 0,
1997                 0, 0,
1998                 0, 0,
1999                 0, 0,
2000                 0, 0,
2001                 0, 0,
2002                 0, 0,
2003                 0, 0,
2004                 0, 0,
2005                 0, 0,
2006                 0, 0,
2007                 0, 0,
2008                 GP_4_16_FN, FN_VI0_FIELD,
2009                 GP_4_15_FN, FN_VI0_D11_G3_Y3,
2010                 GP_4_14_FN, FN_VI0_D10_G2_Y2,
2011                 GP_4_13_FN, FN_VI0_D9_G1_Y1,
2012                 GP_4_12_FN, FN_VI0_D8_G0_Y0,
2013                 GP_4_11_FN, FN_VI0_D7_B7_C7,
2014                 GP_4_10_FN, FN_VI0_D6_B6_C6,
2015                 GP_4_9_FN, FN_VI0_D5_B5_C5,
2016                 GP_4_8_FN, FN_VI0_D4_B4_C4,
2017                 GP_4_7_FN, FN_VI0_D3_B3_C3,
2018                 GP_4_6_FN, FN_VI0_D2_B2_C2,
2019                 GP_4_5_FN, FN_VI0_D1_B1_C1,
2020                 GP_4_4_FN, FN_VI0_D0_B0_C0,
2021                 GP_4_3_FN, FN_VI0_VSYNC_N,
2022                 GP_4_2_FN, FN_VI0_HSYNC_N,
2023                 GP_4_1_FN, FN_VI0_CLKENB,
2024                 GP_4_0_FN, FN_VI0_CLK }
2025         },
2026         { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
2027                 0, 0,
2028                 0, 0,
2029                 0, 0,
2030                 0, 0,
2031                 0, 0,
2032                 0, 0,
2033                 0, 0,
2034                 0, 0,
2035                 0, 0,
2036                 0, 0,
2037                 0, 0,
2038                 0, 0,
2039                 0, 0,
2040                 0, 0,
2041                 0, 0,
2042                 GP_5_16_FN, FN_VI1_FIELD,
2043                 GP_5_15_FN, FN_VI1_D11_G3_Y3,
2044                 GP_5_14_FN, FN_VI1_D10_G2_Y2,
2045                 GP_5_13_FN, FN_VI1_D9_G1_Y1,
2046                 GP_5_12_FN, FN_VI1_D8_G0_Y0,
2047                 GP_5_11_FN, FN_VI1_D7_B7_C7,
2048                 GP_5_10_FN, FN_VI1_D6_B6_C6,
2049                 GP_5_9_FN, FN_VI1_D5_B5_C5,
2050                 GP_5_8_FN, FN_VI1_D4_B4_C4,
2051                 GP_5_7_FN, FN_VI1_D3_B3_C3,
2052                 GP_5_6_FN, FN_VI1_D2_B2_C2,
2053                 GP_5_5_FN, FN_VI1_D1_B1_C1,
2054                 GP_5_4_FN, FN_VI1_D0_B0_C0,
2055                 GP_5_3_FN, FN_VI1_VSYNC_N,
2056                 GP_5_2_FN, FN_VI1_HSYNC_N,
2057                 GP_5_1_FN, FN_VI1_CLKENB,
2058                 GP_5_0_FN, FN_VI1_CLK }
2059         },
2060         { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) {
2061                 0, 0,
2062                 0, 0,
2063                 0, 0,
2064                 0, 0,
2065                 0, 0,
2066                 0, 0,
2067                 0, 0,
2068                 0, 0,
2069                 0, 0,
2070                 0, 0,
2071                 0, 0,
2072                 0, 0,
2073                 0, 0,
2074                 0, 0,
2075                 0, 0,
2076                 GP_6_16_FN, FN_IP2_16,
2077                 GP_6_15_FN, FN_IP2_15,
2078                 GP_6_14_FN, FN_IP2_14,
2079                 GP_6_13_FN, FN_IP2_13,
2080                 GP_6_12_FN, FN_IP2_12,
2081                 GP_6_11_FN, FN_IP2_11,
2082                 GP_6_10_FN, FN_IP2_10,
2083                 GP_6_9_FN, FN_IP2_9,
2084                 GP_6_8_FN, FN_IP2_8,
2085                 GP_6_7_FN, FN_IP2_7,
2086                 GP_6_6_FN, FN_IP2_6,
2087                 GP_6_5_FN, FN_IP2_5,
2088                 GP_6_4_FN, FN_IP2_4,
2089                 GP_6_3_FN, FN_IP2_3,
2090                 GP_6_2_FN, FN_IP2_2,
2091                 GP_6_1_FN, FN_IP2_1,
2092                 GP_6_0_FN, FN_IP2_0 }
2093         },
2094         { PINMUX_CFG_REG("GPSR7", 0xE6060020, 32, 1) {
2095                 0, 0,
2096                 0, 0,
2097                 0, 0,
2098                 0, 0,
2099                 0, 0,
2100                 0, 0,
2101                 0, 0,
2102                 0, 0,
2103                 0, 0,
2104                 0, 0,
2105                 0, 0,
2106                 0, 0,
2107                 0, 0,
2108                 0, 0,
2109                 0, 0,
2110                 GP_7_16_FN, FN_VI3_FIELD,
2111                 GP_7_15_FN, FN_IP3_14,
2112                 GP_7_14_FN, FN_VI3_D10_Y2,
2113                 GP_7_13_FN, FN_IP3_13,
2114                 GP_7_12_FN, FN_IP3_12,
2115                 GP_7_11_FN, FN_IP3_11,
2116                 GP_7_10_FN, FN_IP3_10,
2117                 GP_7_9_FN, FN_IP3_9,
2118                 GP_7_8_FN, FN_IP3_8,
2119                 GP_7_7_FN, FN_IP3_7,
2120                 GP_7_6_FN, FN_IP3_6,
2121                 GP_7_5_FN, FN_IP3_5,
2122                 GP_7_4_FN, FN_IP3_4,
2123                 GP_7_3_FN, FN_IP3_3,
2124                 GP_7_2_FN, FN_IP3_2,
2125                 GP_7_1_FN, FN_IP3_1,
2126                 GP_7_0_FN, FN_IP3_0 }
2127         },
2128         { PINMUX_CFG_REG("GPSR8", 0xE6060024, 32, 1) {
2129                 0, 0,
2130                 0, 0,
2131                 0, 0,
2132                 0, 0,
2133                 0, 0,
2134                 0, 0,
2135                 0, 0,
2136                 0, 0,
2137                 0, 0,
2138                 0, 0,
2139                 0, 0,
2140                 0, 0,
2141                 0, 0,
2142                 0, 0,
2143                 0, 0,
2144                 GP_8_16_FN, FN_IP4_24,
2145                 GP_8_15_FN, FN_IP4_23,
2146                 GP_8_14_FN, FN_IP4_22,
2147                 GP_8_13_FN, FN_IP4_21,
2148                 GP_8_12_FN, FN_IP4_20_19,
2149                 GP_8_11_FN, FN_IP4_18_17,
2150                 GP_8_10_FN, FN_IP4_16_15,
2151                 GP_8_9_FN, FN_IP4_14_13,
2152                 GP_8_8_FN, FN_IP4_12_11,
2153                 GP_8_7_FN, FN_IP4_10_9,
2154                 GP_8_6_FN, FN_IP4_8_7,
2155                 GP_8_5_FN, FN_IP4_6_5,
2156                 GP_8_4_FN, FN_IP4_4,
2157                 GP_8_3_FN, FN_IP4_3_2,
2158                 GP_8_2_FN, FN_IP4_1,
2159                 GP_8_1_FN, FN_IP4_0,
2160                 GP_8_0_FN, FN_VI4_CLK }
2161         },
2162         { PINMUX_CFG_REG("GPSR9", 0xE6060028, 32, 1) {
2163                 0, 0,
2164                 0, 0,
2165                 0, 0,
2166                 0, 0,
2167                 0, 0,
2168                 0, 0,
2169                 0, 0,
2170                 0, 0,
2171                 0, 0,
2172                 0, 0,
2173                 0, 0,
2174                 0, 0,
2175                 0, 0,
2176                 0, 0,
2177                 0, 0,
2178                 GP_9_16_FN, FN_VI5_FIELD,
2179                 GP_9_15_FN, FN_VI5_D11_Y3,
2180                 GP_9_14_FN, FN_VI5_D10_Y2,
2181                 GP_9_13_FN, FN_VI5_D9_Y1,
2182                 GP_9_12_FN, FN_IP5_11,
2183                 GP_9_11_FN, FN_IP5_10,
2184                 GP_9_10_FN, FN_IP5_9,
2185                 GP_9_9_FN, FN_IP5_8,
2186                 GP_9_8_FN, FN_IP5_7,
2187                 GP_9_7_FN, FN_IP5_6,
2188                 GP_9_6_FN, FN_IP5_5,
2189                 GP_9_5_FN, FN_IP5_4,
2190                 GP_9_4_FN, FN_IP5_3,
2191                 GP_9_3_FN, FN_IP5_2,
2192                 GP_9_2_FN, FN_IP5_1,
2193                 GP_9_1_FN, FN_IP5_0,
2194                 GP_9_0_FN, FN_VI5_CLK }
2195         },
2196         { PINMUX_CFG_REG("GPSR10", 0xE606002C, 32, 1) {
2197                 GP_10_31_FN, FN_CAN1_RX,
2198                 GP_10_30_FN, FN_CAN1_TX,
2199                 GP_10_29_FN, FN_CAN_CLK,
2200                 GP_10_28_FN, FN_CAN0_RX,
2201                 GP_10_27_FN, FN_CAN0_TX,
2202                 GP_10_26_FN, FN_SCIF_CLK,
2203                 GP_10_25_FN, FN_IP6_18_17,
2204                 GP_10_24_FN, FN_IP6_16,
2205                 GP_10_23_FN, FN_IP6_15_14,
2206                 GP_10_22_FN, FN_IP6_13_12,
2207                 GP_10_21_FN, FN_IP6_11_10,
2208                 GP_10_20_FN, FN_IP6_9_8,
2209                 GP_10_19_FN, FN_RX1,
2210                 GP_10_18_FN, FN_TX1,
2211                 GP_10_17_FN, FN_RTS1_N,
2212                 GP_10_16_FN, FN_CTS1_N,
2213                 GP_10_15_FN, FN_SCK1,
2214                 GP_10_14_FN, FN_RX0,
2215                 GP_10_13_FN, FN_TX0,
2216                 GP_10_12_FN, FN_RTS0_N,
2217                 GP_10_11_FN, FN_CTS0_N,
2218                 GP_10_10_FN, FN_SCK0,
2219                 GP_10_9_FN, FN_IP6_7,
2220                 GP_10_8_FN, FN_IP6_6,
2221                 GP_10_7_FN, FN_HCTS1_N,
2222                 GP_10_6_FN, FN_IP6_5,
2223                 GP_10_5_FN, FN_IP6_4,
2224                 GP_10_4_FN, FN_IP6_3,
2225                 GP_10_3_FN, FN_IP6_2,
2226                 GP_10_2_FN, FN_HRTS0_N,
2227                 GP_10_1_FN, FN_IP6_1,
2228                 GP_10_0_FN, FN_IP6_0 }
2229         },
2230         { PINMUX_CFG_REG("GPSR11", 0xE6060030, 32, 1) {
2231                 0, 0,
2232                 0, 0,
2233                 GP_11_29_FN, FN_AVS2,
2234                 GP_11_28_FN, FN_AVS1,
2235                 GP_11_27_FN, FN_ADICHS2,
2236                 GP_11_26_FN, FN_ADICHS1,
2237                 GP_11_25_FN, FN_ADICHS0,
2238                 GP_11_24_FN, FN_ADIDATA,
2239                 GP_11_23_FN, FN_ADICS_SAMP,
2240                 GP_11_22_FN, FN_ADICLK,
2241                 GP_11_21_FN, FN_IP7_20,
2242                 GP_11_20_FN, FN_IP7_19,
2243                 GP_11_19_FN, FN_IP7_18,
2244                 GP_11_18_FN, FN_IP7_17,
2245                 GP_11_17_FN, FN_IP7_16,
2246                 GP_11_16_FN, FN_IP7_15_14,
2247                 GP_11_15_FN, FN_IP7_13_12,
2248                 GP_11_14_FN, FN_IP7_11_10,
2249                 GP_11_13_FN, FN_IP7_9_8,
2250                 GP_11_12_FN, FN_SD0_WP,
2251                 GP_11_11_FN, FN_SD0_CD,
2252                 GP_11_10_FN, FN_SD0_DAT3,
2253                 GP_11_9_FN, FN_SD0_DAT2,
2254                 GP_11_8_FN, FN_SD0_DAT1,
2255                 GP_11_7_FN, FN_SD0_DAT0,
2256                 GP_11_6_FN, FN_SD0_CMD,
2257                 GP_11_5_FN, FN_SD0_CLK,
2258                 GP_11_4_FN, FN_IP7_7,
2259                 GP_11_3_FN, FN_IP7_6,
2260                 GP_11_2_FN, FN_IP7_5_4,
2261                 GP_11_1_FN, FN_IP7_3_2,
2262                 GP_11_0_FN, FN_IP7_1_0 }
2263         },
2264         { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060040, 32,
2265                              4, 4,
2266                              1, 1, 1, 1, 1, 1, 1, 1,
2267                              1, 1, 1, 1, 1, 1, 1, 1,
2268                              1, 1, 1, 1, 1, 1, 1, 1) {
2269                 /* IP0_31_28 [4] */
2270                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2271                 /* IP0_27_24 [4] */
2272                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2273                 /* IP0_23 [1] */
2274                 FN_DU0_DB7_C5, 0,
2275                 /* IP0_22 [1] */
2276                 FN_DU0_DB6_C4, 0,
2277                 /* IP0_21 [1] */
2278                 FN_DU0_DB5_C3, 0,
2279                 /* IP0_20 [1] */
2280                 FN_DU0_DB4_C2, 0,
2281                 /* IP0_19 [1] */
2282                 FN_DU0_DB3_C1, 0,
2283                 /* IP0_18 [1] */
2284                 FN_DU0_DB2_C0, 0,
2285                 /* IP0_17 [1] */
2286                 FN_DU0_DB1, 0,
2287                 /* IP0_16 [1] */
2288                 FN_DU0_DB0, 0,
2289                 /* IP0_15 [1] */
2290                 FN_DU0_DG7_Y3_DATA15, 0,
2291                 /* IP0_14 [1] */
2292                 FN_DU0_DG6_Y2_DATA14, 0,
2293                 /* IP0_13 [1] */
2294                 FN_DU0_DG5_Y1_DATA13, 0,
2295                 /* IP0_12 [1] */
2296                 FN_DU0_DG4_Y0_DATA12, 0,
2297                 /* IP0_11 [1] */
2298                 FN_DU0_DG3_C7_DATA11, 0,
2299                 /* IP0_10 [1] */
2300                 FN_DU0_DG2_C6_DATA10, 0,
2301                 /* IP0_9 [1] */
2302                 FN_DU0_DG1_DATA9, 0,
2303                 /* IP0_8 [1] */
2304                 FN_DU0_DG0_DATA8, 0,
2305                 /* IP0_7 [1] */
2306                 FN_DU0_DR7_Y9_DATA7, 0,
2307                 /* IP0_6 [1] */
2308                 FN_DU0_DR6_Y8_DATA6, 0,
2309                 /* IP0_5 [1] */
2310                 FN_DU0_DR5_Y7_DATA5, 0,
2311                 /* IP0_4 [1] */
2312                 FN_DU0_DR4_Y6_DATA4, 0,
2313                 /* IP0_3 [1] */
2314                 FN_DU0_DR3_Y5_DATA3, 0,
2315                 /* IP0_2 [1] */
2316                 FN_DU0_DR2_Y4_DATA2, 0,
2317                 /* IP0_1 [1] */
2318                 FN_DU0_DR1_DATA1, 0,
2319                 /* IP0_0 [1] */
2320                 FN_DU0_DR0_DATA0, 0 }
2321         },
2322         { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060044, 32,
2323                              4, 4,
2324                              1, 1, 1, 1, 1, 1, 1, 1,
2325                              1, 1, 1, 1, 1, 1, 1, 1,
2326                              1, 1, 1, 1, 1, 1, 1, 1) {
2327                 /* IP1_31_28 [4] */
2328                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2329                 /* IP1_27_24 [4] */
2330                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2331                 /* IP1_23 [1] */
2332                 0, 0,
2333                 /* IP1_22 [1] */
2334                 FN_A25, FN_SSL,
2335                 /* IP1_21 [1] */
2336                 FN_A24, FN_SPCLK,
2337                 /* IP1_20 [1] */
2338                 FN_A23, FN_IO3,
2339                 /* IP1_19 [1] */
2340                 FN_A22, FN_IO2,
2341                 /* IP1_18 [1] */
2342                 FN_A21, FN_MISO_IO1,
2343                 /* IP1_17 [1] */
2344                 FN_A20, FN_MOSI_IO0,
2345                 /* IP1_16 [1] */
2346                 FN_DU1_DG7_Y3_DATA11, 0,
2347                 /* IP1_15 [1] */
2348                 FN_DU1_DG6_Y2_DATA10, 0,
2349                 /* IP1_14 [1] */
2350                 FN_DU1_DG5_Y1_DATA9, 0,
2351                 /* IP1_13 [1] */
2352                 FN_DU1_DG4_Y0_DATA8, 0,
2353                 /* IP1_12 [1] */
2354                 FN_DU1_DG3_C7_DATA7, 0,
2355                 /* IP1_11 [1] */
2356                 FN_DU1_DG2_C6_DATA6, 0,
2357                 /* IP1_10 [1] */
2358                 FN_DU1_DR7_DATA5, 0,
2359                 /* IP1_9 [1] */
2360                 FN_DU1_DR6_DATA4, 0,
2361                 /* IP1_8 [1] */
2362                 FN_DU1_DR5_Y7_DATA3, 0,
2363                 /* IP1_7 [1] */
2364                 FN_DU1_DR4_Y6_DATA2, 0,
2365                 /* IP1_6 [1] */
2366                 FN_DU1_DR3_Y5_DATA1, 0,
2367                 /* IP1_5 [1] */
2368                 FN_DU1_DR2_Y4_DATA0, 0,
2369                 /* IP1_4 [1] */
2370                 FN_DU0_CDE, 0,
2371                 /* IP1_3 [1] */
2372                 FN_DU0_DISP, 0,
2373                 /* IP1_2 [1] */
2374                 FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, 0,
2375                 /* IP1_1 [1] */
2376                 FN_DU0_EXVSYNC_DU0_VSYNC, 0,
2377                 /* IP1_0 [1] */
2378                 FN_DU0_EXHSYNC_DU0_HSYNC, 0 }
2379         },
2380         { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060048, 32,
2381                              4, 4,
2382                              4, 3, 1,
2383                              1, 1, 1, 1, 1, 1, 1, 1,
2384                              1, 1, 1, 1, 1, 1, 1, 1) {
2385                 /* IP2_31_28 [4] */
2386                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2387                 /* IP2_27_24 [4] */
2388                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2389                 /* IP2_23_20 [4] */
2390                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2391                 /* IP2_19_17 [3] */
2392                 0, 0, 0, 0, 0, 0, 0, 0,
2393                 /* IP2_16 [1] */
2394                 FN_VI2_FIELD, FN_AVB_TXD2,
2395                 /* IP2_15 [1] */
2396                 FN_VI2_D11_Y3, FN_AVB_TXD1,
2397                 /* IP2_14 [1] */
2398                 FN_VI2_D10_Y2, FN_AVB_TXD0,
2399                 /* IP2_13 [1] */
2400                 FN_VI2_D9_Y1, FN_AVB_TX_EN,
2401                 /* IP2_12 [1] */
2402                 FN_VI2_D8_Y0, FN_AVB_TXD3,
2403                 /* IP2_11 [1] */
2404                 FN_VI2_D7_C7, FN_AVB_COL,
2405                 /* IP2_10 [1] */
2406                 FN_VI2_D6_C6, FN_AVB_RX_ER,
2407                 /* IP2_9 [1] */
2408                 FN_VI2_D5_C5, FN_AVB_RXD7,
2409                 /* IP2_8 [1] */
2410                 FN_VI2_D4_C4, FN_AVB_RXD6,
2411                 /* IP2_7 [1] */
2412                 FN_VI2_D3_C3, FN_AVB_RXD5,
2413                 /* IP2_6 [1] */
2414                 FN_VI2_D2_C2, FN_AVB_RXD4,
2415                 /* IP2_5 [1] */
2416                 FN_VI2_D1_C1, FN_AVB_RXD3,
2417                 /* IP2_4 [1] */
2418                 FN_VI2_D0_C0, FN_AVB_RXD2,
2419                 /* IP2_3 [1] */
2420                 FN_VI2_VSYNC_N, FN_AVB_RXD1,
2421                 /* IP2_2 [1] */
2422                 FN_VI2_HSYNC_N, FN_AVB_RXD0,
2423                 /* IP2_1 [1] */
2424                 FN_VI2_CLKENB, FN_AVB_RX_DV,
2425                 /* IP2_0 [1] */
2426                 FN_VI2_CLK, FN_AVB_RX_CLK }
2427         },
2428         { PINMUX_CFG_REG_VAR("IPSR3", 0xE606004C, 32,
2429                              4, 4,
2430                              4, 4,
2431                              1, 1, 1, 1, 1, 1, 1, 1,
2432                              1, 1, 1, 1, 1, 1, 1, 1) {
2433                 /* IP3_31_28 [4] */
2434                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2435                 /* IP3_27_24 [4] */
2436                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2437                 /* IP3_23_20 [4] */
2438                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2439                 /* IP3_19_16 [4] */
2440                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2441                 /* IP3_15 [1] */
2442                 0, 0,
2443                 /* IP3_14 [1] */
2444                 FN_VI3_D11_Y3, FN_AVB_AVTP_MATCH,
2445                 /* IP3_13 [1] */
2446                 FN_VI3_D9_Y1, FN_AVB_GTXREFCLK,
2447                 /* IP3_12 [1] */
2448                 FN_VI3_D8_Y0, FN_AVB_CRS,
2449                 /* IP3_11 [1] */
2450                 FN_VI3_D7_C7, FN_AVB_PHY_INT,
2451                 /* IP3_10 [1] */
2452                 FN_VI3_D6_C6, FN_AVB_MAGIC,
2453                 /* IP3_9 [1] */
2454                 FN_VI3_D5_C5, FN_AVB_LINK,
2455                 /* IP3_8 [1] */
2456                 FN_VI3_D4_C4, FN_AVB_MDIO,
2457                 /* IP3_7 [1] */
2458                 FN_VI3_D3_C3, FN_AVB_MDC,
2459                 /* IP3_6 [1] */
2460                 FN_VI3_D2_C2, FN_AVB_GTX_CLK,
2461                 /* IP3_5 [1] */
2462                 FN_VI3_D1_C1, FN_AVB_TX_ER,
2463                 /* IP3_4 [1] */
2464                 FN_VI3_D0_C0, FN_AVB_TXD7,
2465                 /* IP3_3 [1] */
2466                 FN_VI3_VSYNC_N, FN_AVB_TXD6,
2467                 /* IP3_2 [1] */
2468                 FN_VI3_HSYNC_N, FN_AVB_TXD5,
2469                 /* IP3_1 [1] */
2470                 FN_VI3_CLKENB, FN_AVB_TXD4,
2471                 /* IP3_0 [1] */
2472                 FN_VI3_CLK, FN_AVB_TX_CLK }
2473         },
2474         { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060050, 32,
2475                              4, 3, 1,
2476                              1, 1, 1, 2, 2, 2,
2477                              2, 2, 2, 2, 2, 1, 2, 1, 1) {
2478                 /* IP4_31_28 [4] */
2479                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2480                 /* IP4_27_25 [3] */
2481                 0, 0, 0, 0, 0, 0, 0, 0,
2482                 /* IP4_24 [1] */
2483                 FN_VI4_FIELD, FN_VI3_D15_Y7,
2484                 /* IP4_23 [1] */
2485                 FN_VI4_D11_Y3, FN_VI3_D14_Y6,
2486                 /* IP4_22 [1] */
2487                 FN_VI4_D10_Y2, FN_VI3_D13_Y5,
2488                 /* IP4_21 [1] */
2489                 FN_VI4_D9_Y1, FN_VI3_D12_Y4,
2490                 /* IP4_20_19 [2] */
2491                 FN_VI4_D8_Y0, FN_VI0_D23_R7, FN_VI2_D15_Y7, 0,
2492                 /* IP4_18_17 [2] */
2493                 FN_VI4_D7_C7, FN_VI0_D22_R6, FN_VI2_D14_Y6, 0,
2494                 /* IP4_16_15 [2] */
2495                 FN_VI4_D6_C6, FN_VI0_D21_R5, FN_VI2_D13_Y5, 0,
2496                 /* IP4_14_13 [2] */
2497                 FN_VI4_D5_C5, FN_VI0_D20_R4, FN_VI2_D12_Y4, 0,
2498                 /* IP4_12_11 [2] */
2499                 FN_VI4_D4_C4, FN_VI0_D19_R3, FN_VI1_D15_G7_Y7, 0,
2500                 /* IP4_10_9 [2] */
2501                 FN_VI4_D3_C3, FN_VI0_D18_R2, FN_VI1_D14_G6_Y6, 0,
2502                 /* IP4_8_7 [2] */
2503                 FN_VI4_D2_C2, 0, FN_VI0_D17_R1, FN_VI1_D13_G5_Y5,
2504                 /* IP4_6_5 [2] */
2505                 FN_VI4_D1_C1, FN_VI0_D16_R0, FN_VI1_D12_G4_Y4, 0,
2506                 /* IP4_4 [1] */
2507                 FN_VI4_D0_C0, FN_VI0_D15_G7_Y7,
2508                 /* IP4_3_2 [2] */
2509                 FN_VI4_VSYNC_N, FN_VI0_D14_G6_Y6, 0, 0,
2510                 /* IP4_1 [1] */
2511                 FN_VI4_HSYNC_N, FN_VI0_D13_G5_Y5,
2512                 /* IP4_0 [1] */
2513                 FN_VI4_CLKENB, FN_VI0_D12_G4_Y4 }
2514         },
2515         { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060054, 32,
2516                              4, 4,
2517                              4, 4,
2518                              4, 1, 1, 1, 1,
2519                              1, 1, 1, 1, 1, 1, 1, 1) {
2520                 /* IP5_31_28 [4] */
2521                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2522                 /* IP5_27_24 [4] */
2523                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2524                 /* IP5_23_20 [4] */
2525                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2526                 /* IP5_19_16 [4] */
2527                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2528                 /* IP5_15_12 [4] */
2529                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2530                 /* IP5_11 [1] */
2531                 FN_VI5_D8_Y0, FN_VI1_D23_R7,
2532                 /* IP5_10 [1] */
2533                 FN_VI5_D7_C7, FN_VI1_D22_R6,
2534                 /* IP5_9 [1] */
2535                 FN_VI5_D6_C6, FN_VI1_D21_R5,
2536                 /* IP5_8 [1] */
2537                 FN_VI5_D5_C5, FN_VI1_D20_R4,
2538                 /* IP5_7 [1] */
2539                 FN_VI5_D4_C4, FN_VI1_D19_R3,
2540                 /* IP5_6 [1] */
2541                 FN_VI5_D3_C3, FN_VI1_D18_R2,
2542                 /* IP5_5 [1] */
2543                 FN_VI5_D2_C2, FN_VI1_D17_R1,
2544                 /* IP5_4 [1] */
2545                 FN_VI5_D1_C1, FN_VI1_D16_R0,
2546                 /* IP5_3 [1] */
2547                 FN_VI5_D0_C0, FN_VI1_D15_G7_Y7_B,
2548                 /* IP5_2 [1] */
2549                 FN_VI5_VSYNC_N, FN_VI1_D14_G6_Y6_B,
2550                 /* IP5_1 [1] */
2551                 FN_VI5_HSYNC_N, FN_VI1_D13_G5_Y5_B,
2552                 /* IP5_0 [1] */
2553                 FN_VI5_CLKENB, FN_VI1_D12_G4_Y4_B }
2554         },
2555         { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060058, 32,
2556                              4, 4,
2557                              4, 1, 2, 1,
2558                              2, 2, 2, 2,
2559                              1, 1, 1, 1, 1, 1, 1, 1) {
2560                 /* IP6_31_28 [4] */
2561                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2562                 /* IP6_27_24 [4] */
2563                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2564                 /* IP6_23_20 [4] */
2565                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2566                 /* IP6_19 [1] */
2567                 0, 0,
2568                 /* IP6_18_17 [2] */
2569                 FN_DREQ1_N, FN_RX3, 0, 0,
2570                 /* IP6_16 [1] */
2571                 FN_TX3, 0,
2572                 /* IP6_15_14 [2] */
2573                 FN_DACK1, FN_SCK3, 0, 0,
2574                 /* IP6_13_12 [2] */
2575                 FN_DREQ0_N, FN_RX2, 0, 0,
2576                 /* IP6_11_10 [2] */
2577                 FN_DACK0, FN_TX2, 0, 0,
2578                 /* IP6_9_8 [2] */
2579                 FN_DRACK0, FN_SCK2, 0, 0,
2580                 /* IP6_7 [1] */
2581                 FN_MSIOF1_RXD, FN_HRX1,
2582                 /* IP6_6 [1] */
2583                 FN_MSIOF1_TXD, FN_HTX1,
2584                 /* IP6_5 [1] */
2585                 FN_MSIOF1_SYNC, FN_HRTS1_N,
2586                 /* IP6_4 [1] */
2587                 FN_MSIOF1_SCK, FN_HSCK1,
2588                 /* IP6_3 [1] */
2589                 FN_MSIOF0_RXD, FN_HRX0,
2590                 /* IP6_2 [1] */
2591                 FN_MSIOF0_TXD, FN_HTX0,
2592                 /* IP6_1 [1] */
2593                 FN_MSIOF0_SYNC, FN_HCTS0_N,
2594                 /* IP6_0 [1] */
2595                 FN_MSIOF0_SCK, FN_HSCK0 }
2596         },
2597         { PINMUX_CFG_REG_VAR("IPSR7", 0xE606005C, 32,
2598                              4, 4,
2599                              3, 1, 1, 1, 1, 1,
2600                              2, 2, 2, 2,
2601                              1, 1, 2, 2, 2) {
2602                 /* IP7_31_28 [4] */
2603                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2604                 /* IP7_27_24 [4] */
2605                 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2606                 /* IP7_23_21 [3] */
2607                 0, 0, 0, 0, 0, 0, 0, 0,
2608                 /* IP7_20 [1] */
2609                 FN_AUDIO_CLKB, 0,
2610                 /* IP7_19 [1] */
2611                 FN_AUDIO_CLKA, 0,
2612                 /* IP7_18 [1] */
2613                 FN_AUDIO_CLKOUT, 0,
2614                 /* IP7_17 [1] */
2615                 FN_SSI_SDATA4, 0,
2616                 /* IP7_16 [1] */
2617                 FN_SSI_WS4, 0,
2618                 /* IP7_15_14 [2] */
2619                 FN_SSI_SCK4, FN_TPU0TO3, 0, 0,
2620                 /* IP7_13_12 [2] */
2621                 FN_SSI_SDATA3, FN_TPU0TO2, 0, 0,
2622                 /* IP7_11_10 [2] */
2623                 FN_SSI_WS34, FN_TPU0TO1, 0, 0,
2624                 /* IP7_9_8 [2] */
2625                 FN_SSI_SCK34, FN_TPU0TO0, 0, 0,
2626                 /* IP7_7 [1] */
2627                 FN_PWM4, 0,
2628                 /* IP7_6 [1] */
2629                 FN_PWM3, 0,
2630                 /* IP7_5_4 [2] */
2631                 FN_PWM2, FN_TCLK3, FN_FSO_TOE, 0,
2632                 /* IP7_3_2 [2] */
2633                 FN_PWM1, FN_TCLK2, FN_FSO_CFE_1, 0,
2634                 /* IP7_1_0 [2] */
2635                 FN_PWM0, FN_TCLK1, FN_FSO_CFE_0, 0 }
2636         },
2637         { },
2638 };
2639
2640 const struct sh_pfc_soc_info r8a7792_pinmux_info = {
2641         .name = "r8a77920_pfc",
2642         .unlock_reg = 0xe6060000, /* PMMR */
2643
2644         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
2645
2646         .pins = pinmux_pins,
2647         .nr_pins = ARRAY_SIZE(pinmux_pins),
2648         .groups = pinmux_groups,
2649         .nr_groups = ARRAY_SIZE(pinmux_groups),
2650         .functions = pinmux_functions,
2651         .nr_functions = ARRAY_SIZE(pinmux_functions),
2652
2653         .cfg_regs = pinmux_config_regs,
2654
2655         .pinmux_data = pinmux_data,
2656         .pinmux_data_size = ARRAY_SIZE(pinmux_data),
2657 };